diff options
6 files changed, 933 insertions, 0 deletions
diff --git a/config/coreboot/default/patches/0031-mb-dell-Add-OptiPlex-7020-9020-port_cb55232_31.patch b/config/coreboot/default/patches/0031-mb-dell-Add-OptiPlex-7020-9020-port_cb55232_31.patch new file mode 100644 index 00000000..3b4d8004 --- /dev/null +++ b/config/coreboot/default/patches/0031-mb-dell-Add-OptiPlex-7020-9020-port_cb55232_31.patch @@ -0,0 +1,923 @@ +From 38a713eb071dd9c1b7d5092ce686537e5d9266f5 Mon Sep 17 00:00:00 2001 +From: Mate Kukri <kukri.mate@gmail.com> +Date: Mon, 4 Dec 2023 21:34:18 +0000 +Subject: [PATCH 1/1] mb/dell: Add OptiPlex 7020/9020 port +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The OptiPlex 7020 and 9020 use physically identical motherboards. + +Each model comes in the following form factors: +- 7020: SFF, MT +- 9020: USFF (not currently supported), SFF, MT + +(7020 SFF) Boots Linux and Windows 10: +- Tested with an i3-4160 and i5-4460 +- DRAM init works using the MRC (4G, 4G+4G) +- iGPU init works using libgfxinit (VGA, 2x DP) +- PCIe 16x: tested, ok +- PCIe 4x: tested, ok +- All USB2 and USB3 ports work +- SMSC SCH5555 Super I/O: serial works, PS/2 untested +- Audio: back and front output works, internal speaker works, + mic inputs untested +- Ethernet: tested, works + +(9020 MT) +- Tested by Michael Büchler (thanks for the overridetree) + +Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a +Signed-off-by: Mate Kukri <kukri.mate@gmail.com> +--- + src/mainboard/dell/optiplex_9020/Kconfig | 34 +++ + src/mainboard/dell/optiplex_9020/Kconfig.name | 11 + + src/mainboard/dell/optiplex_9020/Makefile.inc | 5 + + src/mainboard/dell/optiplex_9020/acpi/ec.asl | 3 + + .../dell/optiplex_9020/acpi/platform.asl | 11 + + .../dell/optiplex_9020/acpi/superio.asl | 3 + + .../dell/optiplex_9020/board_info.txt | 8 + + src/mainboard/dell/optiplex_9020/bootblock.c | 116 ++++++++++ + src/mainboard/dell/optiplex_9020/cmos.default | 4 + + src/mainboard/dell/optiplex_9020/cmos.layout | 58 +++++ + src/mainboard/dell/optiplex_9020/data.vbt | Bin 0 -> 4409 bytes + .../dell/optiplex_9020/devicetree.cb | 80 +++++++ + src/mainboard/dell/optiplex_9020/dsdt.asl | 25 ++ + .../dell/optiplex_9020/gma-mainboard.ads | 18 ++ + src/mainboard/dell/optiplex_9020/gpio.c | 217 ++++++++++++++++++ + src/mainboard/dell/optiplex_9020/hda_verb.c | 27 +++ + src/mainboard/dell/optiplex_9020/mainboard.c | 15 ++ + .../dell/optiplex_9020/overridetree_mt.cb | 10 + + src/mainboard/dell/optiplex_9020/romstage.c | 53 +++++ + 19 files changed, 698 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig + create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig.name + create mode 100644 src/mainboard/dell/optiplex_9020/Makefile.inc + create mode 100644 src/mainboard/dell/optiplex_9020/acpi/ec.asl + create mode 100644 src/mainboard/dell/optiplex_9020/acpi/platform.asl + create mode 100644 src/mainboard/dell/optiplex_9020/acpi/superio.asl + create mode 100644 src/mainboard/dell/optiplex_9020/board_info.txt + create mode 100644 src/mainboard/dell/optiplex_9020/bootblock.c + create mode 100644 src/mainboard/dell/optiplex_9020/cmos.default + create mode 100644 src/mainboard/dell/optiplex_9020/cmos.layout + create mode 100644 src/mainboard/dell/optiplex_9020/data.vbt + create mode 100644 src/mainboard/dell/optiplex_9020/devicetree.cb + create mode 100644 src/mainboard/dell/optiplex_9020/dsdt.asl + create mode 100644 src/mainboard/dell/optiplex_9020/gma-mainboard.ads + create mode 100644 src/mainboard/dell/optiplex_9020/gpio.c + create mode 100644 src/mainboard/dell/optiplex_9020/hda_verb.c + create mode 100644 src/mainboard/dell/optiplex_9020/mainboard.c + create mode 100644 src/mainboard/dell/optiplex_9020/overridetree_mt.cb + create mode 100644 src/mainboard/dell/optiplex_9020/romstage.c + +diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig +new file mode 100644 +index 0000000000..774a72f161 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/Kconfig +@@ -0,0 +1,34 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++if BOARD_DELL_OPTIPLEX_9020_SFF || BOARD_DELL_OPTIPLEX_9020_MT ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ select BOARD_ROMSIZE_KB_12288 ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_OPTION_TABLE ++ select HAVE_CMOS_DEFAULT ++ select INTEL_GMA_HAVE_VBT ++ select INTEL_INT15 ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select NORTHBRIDGE_INTEL_HASWELL ++ select SERIRQ_CONTINUOUS_MODE ++ select SOUTHBRIDGE_INTEL_LYNXPOINT ++ select SUPERIO_SMSC_SCH555x ++ ++config CBFS_SIZE ++ default 0x600000 ++ ++config MAINBOARD_DIR ++ default "dell/optiplex_9020" ++ ++config MAINBOARD_PART_NUMBER ++ default "OptiPlex 7020/9020 SFF" if BOARD_DELL_OPTIPLEX_9020_SFF ++ default "OptiPlex 7020/9020 MT" if BOARD_DELL_OPTIPLEX_9020_MT ++ ++config OVERRIDE_DEVICETREE ++ default "overridetree_mt.cb" if BOARD_DELL_OPTIPLEX_9020_MT ++ ++endif +diff --git a/src/mainboard/dell/optiplex_9020/Kconfig.name b/src/mainboard/dell/optiplex_9020/Kconfig.name +new file mode 100644 +index 0000000000..c25c330a44 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/Kconfig.name +@@ -0,0 +1,11 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_DELL_OPTIPLEX_9020_SFF ++ bool "OptiPlex 7020/9020 SFF" ++ help ++ The 7020 SFF and 9020 SFF mainboards are physically identical. ++ ++config BOARD_DELL_OPTIPLEX_9020_MT ++ bool "OptiPlex 7020/9020 MT" ++ help ++ The 7020 MT and 9020 MT mainboards are physically identical. +diff --git a/src/mainboard/dell/optiplex_9020/Makefile.inc b/src/mainboard/dell/optiplex_9020/Makefile.inc +new file mode 100644 +index 0000000000..6ca2f2afaa +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/Makefile.inc +@@ -0,0 +1,5 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++romstage-y += gpio.c ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads ++bootblock-y += bootblock.c +diff --git a/src/mainboard/dell/optiplex_9020/acpi/ec.asl b/src/mainboard/dell/optiplex_9020/acpi/ec.asl +new file mode 100644 +index 0000000000..16990d45f4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/acpi/ec.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: CC-PDDC */ ++ ++/* Please update the license if adding licensable material. */ +diff --git a/src/mainboard/dell/optiplex_9020/acpi/platform.asl b/src/mainboard/dell/optiplex_9020/acpi/platform.asl +new file mode 100644 +index 0000000000..cda7682e3e +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/acpi/platform.asl +@@ -0,0 +1,11 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++Method(_WAK, 1) ++{ ++ Return(Package() { 0, 0 }) ++} ++ ++Method(_PTS, 1) ++{ ++ ++} +diff --git a/src/mainboard/dell/optiplex_9020/acpi/superio.asl b/src/mainboard/dell/optiplex_9020/acpi/superio.asl +new file mode 100644 +index 0000000000..16990d45f4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/acpi/superio.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: CC-PDDC */ ++ ++/* Please update the license if adding licensable material. */ +diff --git a/src/mainboard/dell/optiplex_9020/board_info.txt b/src/mainboard/dell/optiplex_9020/board_info.txt +new file mode 100644 +index 0000000000..e30cf9c41f +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/board_info.txt +@@ -0,0 +1,8 @@ ++Vendor name: Dell Inc. ++Board name: OptiPlex 7020/9020 ++Release year: 2014 ++Category: desktop ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y +diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c +new file mode 100644 +index 0000000000..2837cf9cf1 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/bootblock.c +@@ -0,0 +1,116 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <arch/io.h> ++#include <device/pnp_ops.h> ++#include <superio/smsc/sch555x/sch555x.h> ++#include <southbridge/intel/lynxpoint/pch.h> ++ ++static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) ++{ ++ // Clear EC-to-Host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // Send address and value to the EC ++ sch555x_emi_write16(0, (addr1 * 2) | 0x101); ++ sch555x_emi_write32(4, val | (addr2 << 16)); ++ ++ // Wait for acknowledgement message from EC ++ outb(1, SCH555x_EMI_IOBASE); ++ size_t timeout = 0; ++ do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0); ++} ++ ++struct ec_init_entry { ++ uint16_t addr; ++ uint8_t val; ++}; ++ ++static void ec_init(void) ++{ ++ /* ++ * Tables from CORE_PEI ++ */ ++ ++ static const struct ec_init_entry init_table1[] = { ++ {0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10}, ++ {0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10}, ++ {0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12}, ++ {0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12}, ++ {0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10}, ++ {0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11}, ++ }; ++ ++ for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i) ++ ec_write(2, init_table1[i].addr, init_table1[i].val); ++ ++ static const struct ec_init_entry init_table2[] = { ++ {0x0005, 0x33}, {0x0018, 0x2f}, {0x0019, 0x2f}, {0x001a, 0x2f}, ++ {0x0083, 0xbb}, {0x0085, 0xd9}, {0x0086, 0x2c}, {0x008a, 0x34}, ++ {0x008b, 0x60}, {0x0090, 0x5e}, {0x0091, 0x5e}, {0x0092, 0x86}, ++ {0x0096, 0xa4}, {0x0097, 0xa4}, {0x0098, 0xa4}, {0x009b, 0xa4}, ++ {0x00a0, 0x0a}, {0x00a1, 0x0a}, {0x00ae, 0x7c}, {0x00af, 0x7c}, ++ {0x00b0, 0x9e}, {0x00b3, 0x7c}, {0x00b6, 0x08}, {0x00b7, 0x08}, ++ {0x00ea, 0x64}, {0x00ef, 0xff}, {0x00f8, 0x15}, {0x00f9, 0x00}, ++ {0x00f0, 0x30}, {0x00fd, 0x01}, {0x01a1, 0x00}, {0x01a2, 0x00}, ++ {0x01b1, 0x08}, {0x01be, 0x90}, {0x0280, 0x24}, {0x0281, 0x13}, ++ {0x0282, 0x03}, {0x0283, 0x0a}, {0x0284, 0x80}, {0x0285, 0x03}, ++ {0x0288, 0x80}, {0x0289, 0x0c}, {0x028a, 0x03}, {0x028b, 0x0a}, ++ {0x028c, 0x80}, {0x028d, 0x03}, {0x0040, 0x01}, ++ }; ++ ++ for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i) ++ ec_write(1, init_table2[i].addr, init_table2[i].val); ++ ++ /* ++ * Table from PeiHwmInit ++ */ ++ ++ static const struct ec_init_entry hwm_init_table[] = { ++ {0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f}, ++ {0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33}, ++ {0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff}, ++ {0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00}, ++ {0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00}, ++ {0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80}, ++ {0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02}, ++ {0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04}, ++ {0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50}, ++ {0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50}, ++ {0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c}, ++ {0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd}, ++ {0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e}, ++ {0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00}, ++ {0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff}, ++ {0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00}, ++ {0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c}, ++ {0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02}, ++ {0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03}, ++ }; ++ ++ for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i) ++ ec_write(1, hwm_init_table[i].addr, hwm_init_table[i].val); ++} ++ ++#define SCH555x_IOBASE 0x2e ++#define GLOBAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL) ++#define SERIAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1) ++ ++void mainboard_config_superio(void) ++{ ++ // Super I/O early init will map Runtime and EMI registers ++ sch555x_early_init(GLOBAL_DEV); ++ ++ // Changes LED color among a few other things (extracted from Dell's FW) ++ outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS); ++ outb(0x00, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN); ++ outb(0x18, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN1); ++ outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); ++ outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); ++ ++ // Magic EC init ++ ec_init(); ++ ++ // Magic EC init is needed for UART1 initialization to work ++ sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ++} +diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default +new file mode 100644 +index 0000000000..b159660aa8 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/cmos.default +@@ -0,0 +1,4 @@ ++boot_option=Fallback ++debug_level=Debug ++nmi=Disable ++power_on_after_fail=Disable +diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout +new file mode 100644 +index 0000000000..c9ba76c78f +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/cmos.layout +@@ -0,0 +1,58 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 3 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 4 debug_level ++ ++#400 8 r 0 reserved for century byte ++ ++# coreboot config options: southbridge ++408 1 e 1 nmi ++409 2 e 5 power_on_after_fail ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++ ++2 0 Enable ++2 1 Disable ++ ++3 0 Fallback ++3 1 Normal ++ ++4 0 Emergency ++4 1 Alert ++4 2 Critical ++4 3 Error ++4 4 Warning ++4 5 Notice ++4 6 Info ++4 7 Debug ++4 8 Spew ++ ++5 0 Disable ++5 1 Enable ++5 2 Keep ++ ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 415 984 +diff --git a/src/mainboard/dell/optiplex_9020/data.vbt b/src/mainboard/dell/optiplex_9020/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..1779f3b8d1018ba0aae480103b145bd7b6dd6187 +GIT binary patch +literal 4409 +zcmdT{T}&KR6h8B_yR)-1!!lr9XiE<T5h_au1f&hdSy<_UtKG6lH%+yR*`>u$pi5g@ +zP3)>@YHE~+rqQIfO&U!#QHhDMkD3^5qG|e|_!FbV_|P=QG{y&G)b-q%VY>waTYnNg +zlQZY%p84*%_nv!argpGv03)IJ_Pe7|bSMP|Y$`oQ_r=uJyEVQm92yAi>WXgdz6a04 +zD)5&6aRng7aW^T=MoU}o*#7ireSZT+;@h#UsjZ1Q4>q^r@OTD8dxst!AG;&CDL8Oo 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+ +diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb +new file mode 100644 +index 0000000000..c0b17a15ff +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/devicetree.cb +@@ -0,0 +1,80 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++chip northbridge/intel/haswell ++ # This mainboard has VGA ++ register "gpu_ddi_e_connected" = "1" ++ ++ chip cpu/intel/haswell ++ device cpu_cluster 0 on ops haswell_cpu_bus_ops end ++ end ++ ++ device domain 0 on ++ ops haswell_pci_domain_ops ++ ++ subsystemid 0x1028 0x05a5 inherit ++ ++ device pci 00.0 on end # Host bridge ++ device pci 01.0 on end # PCIe graphics ++ device pci 02.0 on end # VGA controller ++ device pci 03.0 on end # Mini-HD audio ++ ++ chip southbridge/intel/lynxpoint ++ register "gen1_dec" = "0x007c0a01" ++ register "gen2_dec" = "0x007c0901" ++ register "gen3_dec" = "0x003c07e1" ++ register "gen4_dec" = "0x001c0901" ++ register "sata_port_map" = "0x33" ++ ++ device pci 14.0 on end # xHCI controller ++ device pci 16.0 on end # Management Engine interface 1 ++ device pci 16.1 off end # Management Engine interface 2 ++ device pci 16.2 off end # Management Engine IDE-R ++ device pci 16.3 on end # Management Engine KT ++ device pci 19.0 on # Intel Gigabit Ethernet ++ subsystemid 0x1028 0x05a4 ++ end ++ device pci 1a.0 on end # EHCI controller #2 ++ device pci 1b.0 on end # HD audio controller ++ device pci 1c.0 off end ++ device pci 1c.1 off end ++ device pci 1c.2 off end ++ device pci 1c.3 off end ++ device pci 1c.4 on end # PCIe 4x slot ++ device pci 1c.5 off end ++ device pci 1c.6 off end ++ device pci 1c.7 off end ++ device pci 1d.0 on end # EHCI controller #1 ++ device pci 1f.0 on # LPC bridge ++ chip superio/smsc/sch555x ++ device pnp 2e.0 on # EMI ++ io 0x60 = 0xa00 ++ end ++ device pnp 2e.1 on # 8042 ++ io 0x60 = 0x60 ++ irq 0x0f = 0 ++ irq 0x70 = 1 ++ irq 0x72 = 12 ++ end ++ device pnp 2e.7 on # UART1 ++ io 0x60 = 0x3f8 ++ irq 0x0f = 2 ++ irq 0x70 = 4 ++ end ++ device pnp 2e.8 off end # UART2 ++ device pnp 2e.c on # LPC interface ++ io 0x60 = 0x2e ++ end ++ device pnp 2e.a on # Runtime registers ++ io 0x60 = 0xa40 ++ end ++ device pnp 2e.b off end # Floppy Controller ++ device pnp 2e.11 off end # Parallel Port ++ end ++ end ++ device pci 1f.2 on end # SATA controller 1 ++ device pci 1f.3 on end # SMBus ++ device pci 1f.5 off end # SATA controller 2 ++ device pci 1f.6 off end # Thermal ++ end ++ end ++end +diff --git a/src/mainboard/dell/optiplex_9020/dsdt.asl b/src/mainboard/dell/optiplex_9020/dsdt.asl +new file mode 100644 +index 0000000000..7ec1e9775a +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/dsdt.asl +@@ -0,0 +1,25 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <acpi/acpi.h> ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20181031 /* OEM Revision */ ++) ++{ ++ #include <acpi/dsdt_top.asl> ++ #include "acpi/platform.asl" ++ #include <southbridge/intel/common/acpi/platform.asl> ++ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> ++ #include <southbridge/intel/common/acpi/sleepstates.asl> ++ #include <cpu/intel/common/acpi/cpu.asl> ++ ++ Device (\_SB.PCI0) ++ { ++ #include <northbridge/intel/haswell/acpi/hostbridge.asl> ++ #include <southbridge/intel/lynxpoint/acpi/pch.asl> ++ } ++} +diff --git a/src/mainboard/dell/optiplex_9020/gma-mainboard.ads b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads +new file mode 100644 +index 0000000000..173f2f1d0d +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads +@@ -0,0 +1,18 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (DP1, ++ DP2, ++ DP3, ++ Analog, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/optiplex_9020/gpio.c b/src/mainboard/dell/optiplex_9020/gpio.c +new file mode 100644 +index 0000000000..48b7707e2c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/gpio.c +@@ -0,0 +1,217 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_GPIO, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_GPIO, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_GPIO, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_NATIVE, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_NATIVE, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_NATIVE, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_GPIO, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_GPIO, ++ .gpio26 = GPIO_MODE_GPIO, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_NATIVE, ++ .gpio30 = GPIO_MODE_NATIVE, ++ .gpio31 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio1 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio5 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio11 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_OUTPUT, ++ .gpio15 = GPIO_DIR_OUTPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_OUTPUT, ++ .gpio23 = GPIO_DIR_OUTPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio25 = GPIO_DIR_OUTPUT, ++ .gpio26 = GPIO_DIR_OUTPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio31 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio13 = GPIO_LEVEL_LOW, ++ .gpio15 = GPIO_LEVEL_HIGH, ++ .gpio22 = GPIO_LEVEL_HIGH, ++ .gpio23 = GPIO_LEVEL_HIGH, ++ .gpio25 = GPIO_LEVEL_HIGH, ++ .gpio26 = GPIO_LEVEL_HIGH, ++ .gpio28 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++ .gpio18 = GPIO_BLINK, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio8 = GPIO_INVERT, ++ .gpio9 = GPIO_INVERT, ++ .gpio11 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++ .gpio26 = GPIO_RESET_RSMRST, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_GPIO, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_NATIVE, ++ .gpio37 = GPIO_MODE_NATIVE, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_GPIO, ++ .gpio45 = GPIO_MODE_GPIO, ++ .gpio46 = GPIO_MODE_GPIO, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_GPIO, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_GPIO, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_GPIO, ++ .gpio56 = GPIO_MODE_NATIVE, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio32 = GPIO_DIR_INPUT, ++ .gpio33 = GPIO_DIR_OUTPUT, ++ .gpio34 = GPIO_DIR_OUTPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio44 = GPIO_DIR_INPUT, ++ .gpio45 = GPIO_DIR_OUTPUT, ++ .gpio46 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_INPUT, ++ .gpio50 = GPIO_DIR_OUTPUT, ++ .gpio51 = GPIO_DIR_OUTPUT, ++ .gpio52 = GPIO_DIR_OUTPUT, ++ .gpio53 = GPIO_DIR_OUTPUT, ++ .gpio54 = GPIO_DIR_OUTPUT, ++ .gpio55 = GPIO_DIR_OUTPUT, ++ .gpio57 = GPIO_DIR_OUTPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio33 = GPIO_LEVEL_HIGH, ++ .gpio34 = GPIO_LEVEL_HIGH, ++ .gpio45 = GPIO_LEVEL_LOW, ++ .gpio50 = GPIO_LEVEL_HIGH, ++ .gpio51 = GPIO_LEVEL_HIGH, ++ .gpio52 = GPIO_LEVEL_HIGH, ++ .gpio53 = GPIO_LEVEL_HIGH, ++ .gpio54 = GPIO_LEVEL_HIGH, ++ .gpio55 = GPIO_LEVEL_HIGH, ++ .gpio57 = GPIO_LEVEL_HIGH, ++ .gpio60 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = {}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_GPIO, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_GPIO, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_GPIO, ++ .gpio69 = GPIO_MODE_GPIO, ++ .gpio70 = GPIO_MODE_NATIVE, ++ .gpio71 = GPIO_MODE_NATIVE, ++ .gpio72 = GPIO_MODE_GPIO, ++ .gpio73 = GPIO_MODE_GPIO, ++ .gpio74 = GPIO_MODE_GPIO, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio64 = GPIO_DIR_OUTPUT, ++ .gpio66 = GPIO_DIR_OUTPUT, ++ .gpio68 = GPIO_DIR_INPUT, ++ .gpio69 = GPIO_DIR_INPUT, ++ .gpio72 = GPIO_DIR_OUTPUT, ++ .gpio73 = GPIO_DIR_INPUT, ++ .gpio74 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++ .gpio64 = GPIO_LEVEL_HIGH, ++ .gpio66 = GPIO_LEVEL_HIGH, ++ .gpio72 = GPIO_LEVEL_HIGH, ++ .gpio74 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = {}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/dell/optiplex_9020/hda_verb.c b/src/mainboard/dell/optiplex_9020/hda_verb.c +new file mode 100644 +index 0000000000..df43ade3e6 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/hda_verb.c +@@ -0,0 +1,27 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <stdint.h> ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ 0x10ec0280, /* Realtek ALC3220 */ ++ 0x102805a5, /* Subsystem ID */ ++ 13, /* Number of entries */ ++ AZALIA_SUBVENDOR(0, 0x102805a5), ++ AZALIA_PIN_CFG(0, 0x12, 0x4008c000), ++ AZALIA_PIN_CFG(0, 0x13, 0x411111f0), ++ AZALIA_PIN_CFG(0, 0x14, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x15, 0x0221401f), ++ AZALIA_PIN_CFG(0, 0x16, 0x411111f0), ++ AZALIA_PIN_CFG(0, 0x17, 0x411111f0), ++ AZALIA_PIN_CFG(0, 0x18, 0x01a13040), ++ AZALIA_PIN_CFG(0, 0x19, 0x411111f0), ++ AZALIA_PIN_CFG(0, 0x1a, 0x02a19030), ++ AZALIA_PIN_CFG(0, 0x1b, 0x01014020), ++ AZALIA_PIN_CFG(0, 0x1d, 0x40400001), ++ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), ++}; ++ ++const u32 pc_beep_verbs[] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c +new file mode 100644 +index 0000000000..c834fea5d3 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/mainboard.c +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/device.h> ++#include <drivers/intel/gma/int15.h> ++ ++static void mainboard_enable(struct device *dev) ++{ ++ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, ++ GMA_INT15_PANEL_FIT_DEFAULT, ++ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); ++} ++ ++struct chip_operations mainboard_ops = { ++ .enable_dev = mainboard_enable, ++}; +diff --git a/src/mainboard/dell/optiplex_9020/overridetree_mt.cb b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb +new file mode 100644 +index 0000000000..90205c2d68 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb +@@ -0,0 +1,10 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++chip northbridge/intel/haswell ++ device domain 0 on ++ chip southbridge/intel/lynxpoint ++ device pci 1c.1 on end # PCI (via XIO2001 bridge) ++ device pci 1c.2 on end # PCIe 1x slot ++ end ++ end ++end +diff --git a/src/mainboard/dell/optiplex_9020/romstage.c b/src/mainboard/dell/optiplex_9020/romstage.c +new file mode 100644 +index 0000000000..2b9cdaa5fd +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/romstage.c +@@ -0,0 +1,53 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <northbridge/intel/haswell/haswell.h> ++#include <northbridge/intel/haswell/raminit.h> ++#include <southbridge/intel/lynxpoint/pch.h> ++ ++void mainboard_config_rcba(void) ++{ ++ RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQC, PIRQD, PIRQA); ++ RCBA16(D29IR) = DIR_ROUTE(PIRQC, PIRQA, PIRQD, PIRQH); ++ RCBA16(D28IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA); ++ RCBA16(D27IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQG); ++ RCBA16(D26IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQF, PIRQA); ++ RCBA16(D25IR) = DIR_ROUTE(PIRQH, PIRQG, PIRQF, PIRQE); ++ RCBA16(D22IR) = DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQA); ++ RCBA16(D20IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA); ++} ++ ++void mb_get_spd_map(struct spd_info *spdi) ++{ ++ spdi->addresses[0] = 0x50; ++ spdi->addresses[1] = 0x51; ++ spdi->addresses[2] = 0x52; ++ spdi->addresses[3] = 0x53; ++} ++ ++const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { ++ /* Length, Enable, OCn#, Location */ ++ {0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP}, ++ {0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP}, ++ {0x0040, 1, 1, USB_PORT_BACK_PANEL}, ++ {0x0040, 1, 2, USB_PORT_BACK_PANEL}, ++ {0x0040, 1, 3, USB_PORT_BACK_PANEL}, ++ {0x0040, 1, 3, USB_PORT_BACK_PANEL}, ++ {0x0040, 1, 0, USB_PORT_BACK_PANEL}, ++ {0x0040, 1, 0, USB_PORT_BACK_PANEL}, ++ {0x0040, 1, 4, USB_PORT_BACK_PANEL}, ++ {0x0040, 1, 4, USB_PORT_BACK_PANEL}, ++ {0x0040, 1, 5, USB_PORT_BACK_PANEL}, ++ {0x0040, 1, 5, USB_PORT_BACK_PANEL}, ++ {0x0040, 1, 6, USB_PORT_BACK_PANEL}, ++ {0x0040, 1, 7, USB_PORT_BACK_PANEL}, ++}; ++ ++const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { ++ /* Enable, OCn# */ ++ {1, 6}, ++ {1, 7}, ++ {0, USB_OC_PIN_SKIP}, ++ {0, USB_OC_PIN_SKIP}, ++ {1, 1}, ++ {1, 2}, ++}; +-- +2.39.2 + diff --git a/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb b/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb index 3254c612..a5ea58fb 100644 --- a/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb @@ -137,6 +137,8 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_E6400 is not set CONFIG_BOARD_DELL_LATITUDE_E6430=y # CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set # CONFIG_BOARD_DELL_PRECISION_T1650 is not set CONFIG_PS2K_EISAID="PNP0303" diff --git a/config/coreboot/e6430_12mb/config/libgfxinit_txtmode b/config/coreboot/e6430_12mb/config/libgfxinit_txtmode index c76f2a2f..5be6c754 100644 --- a/config/coreboot/e6430_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6430_12mb/config/libgfxinit_txtmode @@ -135,6 +135,8 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_E6400 is not set CONFIG_BOARD_DELL_LATITUDE_E6430=y # CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set # CONFIG_BOARD_DELL_PRECISION_T1650 is not set CONFIG_PS2K_EISAID="PNP0303" diff --git a/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb b/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb index 55e49b43..c6bcaa39 100644 --- a/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb @@ -137,6 +137,8 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_E6400 is not set # CONFIG_BOARD_DELL_LATITUDE_E6430 is not set CONFIG_BOARD_DELL_LATITUDE_E6530=y +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set # CONFIG_BOARD_DELL_PRECISION_T1650 is not set CONFIG_PS2K_EISAID="PNP0303" diff --git a/config/coreboot/e6530_12mb/config/libgfxinit_txtmode b/config/coreboot/e6530_12mb/config/libgfxinit_txtmode index f4a09759..05c1ec3a 100644 --- a/config/coreboot/e6530_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6530_12mb/config/libgfxinit_txtmode @@ -135,6 +135,8 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_E6400 is not set # CONFIG_BOARD_DELL_LATITUDE_E6430 is not set CONFIG_BOARD_DELL_LATITUDE_E6530=y +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set # CONFIG_BOARD_DELL_PRECISION_T1650 is not set CONFIG_PS2K_EISAID="PNP0303" diff --git a/config/coreboot/t1650_12mb/config/libgfxinit_txtmode b/config/coreboot/t1650_12mb/config/libgfxinit_txtmode index d980a8c2..ee568972 100644 --- a/config/coreboot/t1650_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t1650_12mb/config/libgfxinit_txtmode @@ -138,6 +138,8 @@ CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_E6400 is not set # CONFIG_BOARD_DELL_LATITUDE_E6430 is not set # CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set CONFIG_BOARD_DELL_PRECISION_T1650=y CONFIG_PS2K_EISAID="PNP0303" |