diff options
| author | Leah Rowe <leah@libreboot.org> | 2022-11-14 00:51:12 +0000 |
|---|---|---|
| committer | Leah Rowe <leah@libreboot.org> | 2022-11-14 00:51:12 +0000 |
| commit | 7af9953463c65fe2f02704e6bce815d830e58d7d (patch) | |
| tree | dce6c19484fd27288c65ac33092040601d8a0622 /resources/coreboot/ga-g41m-es2l | |
| parent | b5c25efed46f0a9121023997c6758eda5c3f5017 (diff) | |
pragmatic system distribution guideline compliancepsdg
osboot is now part of libreboot, and will soon shut down.
libreboot now conforms to osboot policy.
Diffstat (limited to 'resources/coreboot/ga-g41m-es2l')
| -rw-r--r-- | resources/coreboot/ga-g41m-es2l/board.cfg | 2 | ||||
| -rw-r--r-- | resources/coreboot/ga-g41m-es2l/config/libgfxinit_txtmode | 13 |
2 files changed, 11 insertions, 4 deletions
diff --git a/resources/coreboot/ga-g41m-es2l/board.cfg b/resources/coreboot/ga-g41m-es2l/board.cfg index 2690fd2c..242f8913 100644 --- a/resources/coreboot/ga-g41m-es2l/board.cfg +++ b/resources/coreboot/ga-g41m-es2l/board.cfg @@ -2,6 +2,6 @@ cbtree="default" romtype="normal" arch="x86_64" payload_grub="y" -payload_grub_withseabios="y" +payload_grub_withseabios="n" payload_seabios="y" grub_scan_disk="ata" diff --git a/resources/coreboot/ga-g41m-es2l/config/libgfxinit_txtmode b/resources/coreboot/ga-g41m-es2l/config/libgfxinit_txtmode index b52295a4..ee2277ad 100644 --- a/resources/coreboot/ga-g41m-es2l/config/libgfxinit_txtmode +++ b/resources/coreboot/ga-g41m-es2l/config/libgfxinit_txtmode @@ -146,6 +146,9 @@ CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y # CONFIG_BOARD_GIGABYTE_GA_H61MA_D3V is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="GA-G41M-ES2L" +CONFIG_PCIEXP_HOTPLUG_BUSES=32 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 CONFIG_PS2K_EISAID="PNP0303" CONFIG_PS2M_EISAID="PNP0F13" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" @@ -247,10 +250,11 @@ CONFIG_SMP=y CONFIG_MMX=y CONFIG_SSE=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y -# CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS is not set +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set -CONFIG_CPU_MICROCODE_CBFS_NONE=y +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set # # Northbridge @@ -262,7 +266,7 @@ CONFIG_NORTHBRIDGE_INTEL_X4X=y # Southbridge # CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -348,6 +352,9 @@ CONFIG_ECAM_MMCONF_LENGTH=0x10000000 CONFIG_PCI_ALLOW_BUS_MASTER=y CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 |