diff options
author | Leah Rowe <leah@libreboot.org> | 2022-11-19 03:33:38 +0000 |
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committer | Leah Rowe <leah@libreboot.org> | 2022-11-19 03:33:38 +0000 |
commit | 60793c552fa0eb1066adcf5e8eec3d5a4bcb7efd (patch) | |
tree | 3867f9fff8b6e298d66d7c411296bb58c76a8bcb /resources/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch | |
parent | 6114c34988d9f5768aac0b56cc4137ebaad81fd4 (diff) |
fix gnat build issue on coreboot repositories
backported from newer coreboot revisions, see patch
coreboot/default/patches/0014-coreboot-default-fix-crossgcc-build.patch
Diffstat (limited to 'resources/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch')
-rw-r--r-- | resources/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/resources/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch b/resources/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch new file mode 100644 index 00000000..bf41150d --- /dev/null +++ b/resources/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch @@ -0,0 +1,34 @@ +From 1c3812ccecef2b22379e4999666de95cd7f38acf Mon Sep 17 00:00:00 2001 +From: persmule <persmule@gmail.com> +Date: Sun, 31 Oct 2021 23:33:26 +0000 +Subject: [PATCH 09/14] lenovo/t400: Enable all SATA ports + +There are 2 SATA ports on the chassis of t400(s), but at least one dock for +t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its +chassis, and another one on its dock. + +They have to be unmasked via device tree to use. + +This patch unmasked all SATA ports found within t400s with factory firmware. +--- + src/mainboard/lenovo/t400/devicetree.cb | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb +index 670b4883f3..1fc60d9b24 100644 +--- a/src/mainboard/lenovo/t400/devicetree.cb ++++ b/src/mainboard/lenovo/t400/devicetree.cb +@@ -59,8 +59,8 @@ chip northbridge/intel/gm45 + register "gpe0_en" = "0x01000000" + register "gpi1_routing" = "2" + +- # Set AHCI mode, enable ports 1 and 2. +- register "sata_port_map" = "0x03" ++ # Set AHCI mode, enable ports 1, 2, 5 and 6. ++ register "sata_port_map" = "0x33" + register "sata_clock_request" = "0" + register "sata_traffic_monitor" = "0" + +-- +2.25.1 + |