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authorLeah Rowe <leah@libreboot.org>2024-01-25 15:58:29 +0000
committerLeah Rowe <leah@libreboot.org>2024-01-25 16:09:19 +0000
commit614c5efa6550a0c1935965848a2b86382bf6c67a (patch)
treef095be3e14704c5271c45c9209d0279bd42857be /config
parent4a6dc5553f2a15542f730ca735fb8bf95fb8f49b (diff)
update coreboot/dell to same rev as default
re-use the same patches, and drop the same patches. this tree uses hell's special ddr2 fix, which we apply for the dell latitude e6400. Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config')
-rw-r--r--config/coreboot/dell/patches/0001-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch (renamed from config/coreboot/dell/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch)140
-rw-r--r--config/coreboot/dell/patches/0002-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch (renamed from config/coreboot/dell/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch)4
-rw-r--r--config/coreboot/dell/patches/0003-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch (renamed from config/coreboot/dell/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch)4
-rw-r--r--config/coreboot/dell/patches/0004-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch (renamed from config/coreboot/dell/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch)6
-rw-r--r--config/coreboot/dell/patches/0005-Remove-warning-for-coreboot-images-built-without-a-p.patch (renamed from config/coreboot/dell/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch)16
-rw-r--r--config/coreboot/dell/patches/0006-don-t-use-github-for-the-acpica-download.patch (renamed from config/coreboot/dell/patches/0024-don-t-use-github-for-the-acpica-download.patch)6
-rw-r--r--config/coreboot/dell/patches/0007-use-mirrorservice.org-for-gcc-downloads.patch (renamed from config/coreboot/dell/patches/0029-use-mirrorservice.org-for-gcc-downloads.patch)6
-rw-r--r--config/coreboot/dell/patches/0008-nb-intel-gm45-Make-DDR2-raminit-work.patch (renamed from config/coreboot/dell/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch)35
-rw-r--r--config/coreboot/dell/patches/0009-dell-e6400-crank-up-vram-to-256MB-max.patch (renamed from config/coreboot/dell/patches/0028-dell-e6400-crank-up-vram-to-256MB-max.patch)4
-rw-r--r--config/coreboot/dell/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch61
-rw-r--r--config/coreboot/dell/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch37
-rw-r--r--config/coreboot/dell/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch341
-rw-r--r--config/coreboot/dell/target.cfg2
-rw-r--r--config/coreboot/e6400_4mb/config/libgfxinit_corebootfb27
-rw-r--r--config/coreboot/e6400_4mb/config/libgfxinit_txtmode27
-rw-r--r--config/coreboot/e6400nvidia_4mb/config/normal23
16 files changed, 170 insertions, 569 deletions
diff --git a/config/coreboot/dell/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/dell/patches/0001-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
index 6a293287..cb1effa7 100644
--- a/config/coreboot/dell/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
+++ b/config/coreboot/dell/patches/0001-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
@@ -1,7 +1,7 @@
-From 38c76afbea4abfed2976bfbe10977e41f21665b0 Mon Sep 17 00:00:00 2001
+From 4fbd327df271d613d4a56a36eafd88d9d642ec6b Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 19 Feb 2023 18:21:43 +0000
-Subject: [PATCH 15/22] util/ifdtool: add --nuke flag (all 0xFF on region)
+Subject: [PATCH 1/9] util/ifdtool: add --nuke flag (all 0xFF on region)
When this option is used, the region's contents are overwritten
with all ones (0xFF).
@@ -16,91 +16,91 @@ Rebased since the last revision update in lbmk.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
- 1 file changed, 83 insertions(+), 31 deletions(-)
+ util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------
+ 1 file changed, 81 insertions(+), 31 deletions(-)
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
-index ddbc0fb91b..7af9235ae3 100644
+index 191b3216de..38132b4a28 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
-@@ -1847,6 +1847,7 @@ static void print_usage(const char *name)
+@@ -1942,6 +1942,7 @@ static void print_usage(const char *name)
+ " tgl - Tiger Lake\n"
" wbg - Wellsburg\n"
" -S | --setpchstrap Write a PCH strap\n"
- " -V | --newvalue The new value to write into PCH strap specified by -S\n"
+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
+ " -V | --newvalue The new value to write into PCH strap specified by -S\n"
" -v | --version: print the version\n"
" -h | --help: print this help\n\n"
- "<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, "
-@@ -1854,6 +1855,60 @@ static void print_usage(const char *name)
+@@ -1950,6 +1951,60 @@ static void print_usage(const char *name)
"\n");
}
+static int
+get_region_type_string(const char *region_type_string)
+{
-+ if (!strcasecmp("Descriptor", region_type_string))
-+ return 0;
-+ else if (!strcasecmp("BIOS", region_type_string))
-+ return 1;
-+ else if (!strcasecmp("ME", region_type_string))
-+ return 2;
-+ else if (!strcasecmp("GbE", region_type_string))
-+ return 3;
-+ else if (!strcasecmp("Platform Data", region_type_string))
-+ return 4;
-+ else if (!strcasecmp("Device Exp1", region_type_string))
-+ return 5;
-+ else if (!strcasecmp("Secondary BIOS", region_type_string))
-+ return 6;
-+ else if (!strcasecmp("Reserved", region_type_string))
-+ return 7;
-+ else if (!strcasecmp("EC", region_type_string))
-+ return 8;
-+ else if (!strcasecmp("Device Exp2", region_type_string))
-+ return 9;
-+ else if (!strcasecmp("IE", region_type_string))
-+ return 10;
-+ else if (!strcasecmp("10GbE_0", region_type_string))
-+ return 11;
-+ else if (!strcasecmp("10GbE_1", region_type_string))
-+ return 12;
-+ else if (!strcasecmp("PTT", region_type_string))
-+ return 15;
-+ return -1;
++ if (!strcasecmp("Descriptor", region_type_string))
++ return 0;
++ else if (!strcasecmp("BIOS", region_type_string))
++ return 1;
++ else if (!strcasecmp("ME", region_type_string))
++ return 2;
++ else if (!strcasecmp("GbE", region_type_string))
++ return 3;
++ else if (!strcasecmp("Platform Data", region_type_string))
++ return 4;
++ else if (!strcasecmp("Device Exp1", region_type_string))
++ return 5;
++ else if (!strcasecmp("Secondary BIOS", region_type_string))
++ return 6;
++ else if (!strcasecmp("Reserved", region_type_string))
++ return 7;
++ else if (!strcasecmp("EC", region_type_string))
++ return 8;
++ else if (!strcasecmp("Device Exp2", region_type_string))
++ return 9;
++ else if (!strcasecmp("IE", region_type_string))
++ return 10;
++ else if (!strcasecmp("10GbE_0", region_type_string))
++ return 11;
++ else if (!strcasecmp("10GbE_1", region_type_string))
++ return 12;
++ else if (!strcasecmp("PTT", region_type_string))
++ return 15;
++ return -1;
+}
+
+static void
+nuke(const char *filename, char *image, int size, int region_type)
+{
-+ int i;
-+ struct region region;
-+ const struct frba *frba = find_frba(image, size);
-+ if (!frba)
-+ exit(EXIT_FAILURE);
++ int i;
++ struct region region;
++ const struct frba *frba = find_frba(image, size);
++ if (!frba)
++ exit(EXIT_FAILURE);
+
-+ region = get_region(frba, region_type);
-+ if (region.size > 0) {
-+ for (i = region.base; i <= region.limit; i++) {
-+ if ((i + 1) > (size))
-+ break;
-+ image[i] = 0xFF;
-+ }
-+ write_image(filename, image, size);
-+ }
++ region = get_region(frba, region_type);
++ if (region.size > 0) {
++ for (i = region.base; i <= region.limit; i++) {
++ if ((i + 1) > (size))
++ break;
++ image[i] = 0xFF;
++ }
++ write_image(filename, image, size);
++ }
+}
+
int main(int argc, char *argv[])
{
int opt, option_index = 0;
-@@ -1861,6 +1916,7 @@ int main(int argc, char *argv[])
+@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[])
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
+ int mode_nuke = 0;
+ int mode_gpr0_disable = 0;
char *region_type_string = NULL, *region_fname = NULL;
const char *layout_fname = NULL;
- char *new_filename = NULL;
-@@ -1892,6 +1948,7 @@ int main(int argc, char *argv[])
+@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[])
{"validate", 0, NULL, 't'},
{"setpchstrap", 1, NULL, 'S'},
{"newvalue", 1, NULL, 'V'},
@@ -108,7 +108,7 @@ index ddbc0fb91b..7af9235ae3 100644
{0, 0, 0, 0}
};
-@@ -1941,35 +1998,8 @@ int main(int argc, char *argv[])
+@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[])
region_fname++;
// Descriptor, BIOS, ME, GbE, Platform
// valid type?
@@ -141,12 +141,12 @@ index ddbc0fb91b..7af9235ae3 100644
- else if (!strcasecmp("PTT", region_type_string))
- region_type = 15;
- if (region_type == -1) {
-+ if ((region_type =
-+ get_region_type_string(region_type_string)) == -1) {
++ if ((region_type =
++ get_region_type_string(region_type_string)) == -1) {
fprintf(stderr, "No such region type: '%s'\n\n",
region_type_string);
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
-@@ -2135,6 +2165,22 @@ int main(int argc, char *argv[])
+@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[])
case 't':
mode_validate = 1;
break;
@@ -169,31 +169,29 @@ index ddbc0fb91b..7af9235ae3 100644
case 'v':
print_version();
exit(EXIT_SUCCESS);
-@@ -2150,7 +2196,8 @@ int main(int argc, char *argv[])
-
+@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
-- mode_unlocked | mode_locked) + mode_altmedisable + mode_validate) > 1) {
-+ mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
-+ mode_nuke) > 1) {
+ mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
+- mode_gpr0_disable) > 1) {
++ mode_gpr0_disable + mode_nuke) > 1) {
fprintf(stderr, "You may not specify more than one mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
-@@ -2158,7 +2205,8 @@ int main(int argc, char *argv[])
-
+@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
-- mode_locked + mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) {
-+ mode_locked + mode_unlocked + mode_density + mode_altmedisable +
-+ mode_validate + mode_nuke) == 0) {
+ mode_locked + mode_unlocked + mode_density + mode_altmedisable +
+- mode_validate + mode_gpr0_disable) == 0) {
++ mode_validate + mode_gpr0_disable + mode_nuke) == 0) {
fprintf(stderr, "You need to specify a mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
-@@ -2262,6 +2310,10 @@ int main(int argc, char *argv[])
+@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[])
write_image(new_filename, image, size);
}
-+ if (mode_nuke) {
++ if (mode_nuke) {
+ nuke(new_filename, image, size, region_type);
+ }
+
diff --git a/config/coreboot/dell/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch b/config/coreboot/dell/patches/0002-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
index 0f9b192d..b0ac4e67 100644
--- a/config/coreboot/dell/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
+++ b/config/coreboot/dell/patches/0002-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
@@ -1,7 +1,7 @@
-From 3ec06fa2393995b87af1dbc0387c5d3255d5c0db Mon Sep 17 00:00:00 2001
+From 362e86f89b3980699e7e794df9b98018397fe2d8 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Dec 2021 02:53:00 +0000
-Subject: [PATCH 16/22] fix speedstep on x200/t400: Revert
+Subject: [PATCH 2/9] fix speedstep on x200/t400: Revert
"cpu/intel/model_1067x: enable PECI"
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
diff --git a/config/coreboot/dell/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch b/config/coreboot/dell/patches/0003-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
index 4d7b3421..3193ed97 100644
--- a/config/coreboot/dell/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
+++ b/config/coreboot/dell/patches/0003-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
@@ -1,7 +1,7 @@
-From fdde15b69bd5c8bf54339adf3581a32fa992a503 Mon Sep 17 00:00:00 2001
+From 883455573f07551eaf2b12ab80bedcd2b4904a17 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 17 Apr 2023 15:49:57 +0100
-Subject: [PATCH 17/22] GM45-type CPUs: don't enable alternative SMRR
+Subject: [PATCH 3/9] GM45-type CPUs: don't enable alternative SMRR
This reverts the changes in coreboot revision:
df7aecd92643d207feaf7fd840f8835097346644
diff --git a/config/coreboot/dell/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/dell/patches/0004-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
index 04f3bd63..c9b41c79 100644
--- a/config/coreboot/dell/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
+++ b/config/coreboot/dell/patches/0004-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
@@ -1,8 +1,8 @@
-From a65797a9e7e610b1c916cb4d275b72848622c218 Mon Sep 17 00:00:00 2001
+From 458fe39e9cd2536cfa8671427e6f557396143339 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 6 May 2023 15:53:41 -0600
-Subject: [PATCH 18/22] mb/dell/e6400: Enable 01.0 device in devicetree for
- dGPU models
+Subject: [PATCH 4/9] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU
+ models
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
diff --git a/config/coreboot/dell/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/dell/patches/0005-Remove-warning-for-coreboot-images-built-without-a-p.patch
index 3f21ad02..546bad7f 100644
--- a/config/coreboot/dell/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch
+++ b/config/coreboot/dell/patches/0005-Remove-warning-for-coreboot-images-built-without-a-p.patch
@@ -1,7 +1,7 @@
-From 7d5452bc3358cf82eea48fde312494bcb4ca8101 Mon Sep 17 00:00:00 2001
+From de4eeaf6d44cb05c60c0b0d54b43cdb88686b998 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 19/22] Remove warning for coreboot images built without a
+Subject: [PATCH 5/9] Remove warning for coreboot images built without a
payload
I added this in upstream to prevent people from accidentally flashing
@@ -9,19 +9,19 @@ roms without a payload resulting in a no boot situation, but in
libreboot lbmk handles the payload and thus this warning always comes
up. This has caused confusion and concern so just patch it out.
---
- payloads/Makefile.inc | 13 +------------
+ payloads/Makefile.mk | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
-diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
-index e735443a76..4f1692a873 100644
---- a/payloads/Makefile.inc
-+++ b/payloads/Makefile.inc
+diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
+index a2336aa876..4f1692a873 100644
+--- a/payloads/Makefile.mk
++++ b/payloads/Makefile.mk
@@ -49,16 +49,5 @@ distclean-payloads:
print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
-ifeq ($(CONFIG_PAYLOAD_NONE),y)
--files_added:: warn_no_payload
+-show_notices:: warn_no_payload
-endif
-
-warn_no_payload:
diff --git a/config/coreboot/dell/patches/0024-don-t-use-github-for-the-acpica-download.patch b/config/coreboot/dell/patches/0006-don-t-use-github-for-the-acpica-download.patch
index 2c4c9e5f..3ee38c29 100644
--- a/config/coreboot/dell/patches/0024-don-t-use-github-for-the-acpica-download.patch
+++ b/config/coreboot/dell/patches/0006-don-t-use-github-for-the-acpica-download.patch
@@ -1,7 +1,7 @@
-From cddb709fd01e3e93a7879488d0d4024360e1e3d9 Mon Sep 17 00:00:00 2001
+From 261454e47783b973b088e9dbea47bda02758dcb4 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 22 Oct 2023 15:02:25 +0100
-Subject: [PATCH 1/1] don't use github for the acpica download
+Subject: [PATCH 6/9] don't use github for the acpica download
i have the tarball from a previous download, and i placed
it on libreboot rsync, which then got mirrored to princeton.
@@ -22,7 +22,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index ebc9fcb49a..a857110b4b 100755
+index 23a5caf2bb..36565a906c 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
diff --git a/config/coreboot/dell/patches/0029-use-mirrorservice.org-for-gcc-downloads.patch b/config/coreboot/dell/patches/0007-use-mirrorservice.org-for-gcc-downloads.patch
index 2e653f83..ff481081 100644
--- a/config/coreboot/dell/patches/0029-use-mirrorservice.org-for-gcc-downloads.patch
+++ b/config/coreboot/dell/patches/0007-use-mirrorservice.org-for-gcc-downloads.patch
@@ -1,7 +1,7 @@
-From 89c47fad6e97fc6a7113ebbdedfcc42ae2b6fc7f Mon Sep 17 00:00:00 2001
+From 622daa7c46de01530de60a7be32c8b9e48b356fd Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 22:57:08 +0000
-Subject: [PATCH 1/1] use mirrorservice.org for gcc downloads
+Subject: [PATCH 7/9] use mirrorservice.org for gcc downloads
the gnu.org 302 redirect often fails
@@ -11,7 +11,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index 87f80ba7f6..b3aad5df7d 100755
+index 36565a906c..4d4ca06113 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
diff --git a/config/coreboot/dell/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/dell/patches/0008-nb-intel-gm45-Make-DDR2-raminit-work.patch
index 454e3e7b..8de8060f 100644
--- a/config/coreboot/dell/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch
+++ b/config/coreboot/dell/patches/0008-nb-intel-gm45-Make-DDR2-raminit-work.patch
@@ -1,7 +1,7 @@
-From e047dc3c95063f27517cd6754e9cbe496ac9313d Mon Sep 17 00:00:00 2001
+From f26df5dff7be4b0c9d8dced1cf6ed07472a174c7 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 10 May 2021 22:40:59 +0200
-Subject: [PATCH] [NOT FOR MERGE] nb/intel/gm45: Make DDR2 raminit work
+Subject: [PATCH 8/9] nb/intel/gm45: Make DDR2 raminit work
List of changes:
- Update some timing and ODT values
@@ -14,12 +14,16 @@ Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs.
Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
+ src/northbridge/intel/gm45/gm45.h | 2 +-
+ src/northbridge/intel/gm45/raminit.c | 90 +++++++++++++++++--
+ .../intel/gm45/raminit_rcomp_calibration.c | 27 ++++--
+ 3 files changed, 106 insertions(+), 13 deletions(-)
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
-index f28c6d1..bdf0432 100644
+index d929533d92..997f8a0e5a 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
-@@ -419,7 +419,7 @@
+@@ -419,7 +419,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
int raminit_read_vco_index(void);
u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
@@ -29,10 +33,10 @@ index f28c6d1..bdf0432 100644
void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *);
void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
-index ecada7b..2b8c44e 100644
+index b7e013959a..df8f46fbbc 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
-@@ -1049,7 +1049,7 @@
+@@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping,
}
/* Perform RCOMP calibration for DDR3. */
@@ -41,7 +45,7 @@ index ecada7b..2b8c44e 100644
/* Run initial RCOMP. */
mchbar_setbits32(0x418, 1 << 17);
-@@ -1119,7 +1119,7 @@
+@@ -1117,7 +1117,7 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
reg = (reg & ~(0xf << 10)) | (2 << 10);
else
reg = (reg & ~(0xf << 10)) | (3 << 10);
@@ -50,7 +54,7 @@ index ecada7b..2b8c44e 100644
} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
-@@ -1288,11 +1288,11 @@
+@@ -1286,11 +1286,11 @@ static void ddr2_odt_setup(const timings_t *const timings, const int sff)
reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32));
reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32));
if (timings->mem_clock == MEM_CLOCK_667MT) {
@@ -66,7 +70,7 @@ index ecada7b..2b8c44e 100644
}
mchbar_write32(CxODT_HIGH(ch), reg);
-@@ -2217,6 +2217,84 @@
+@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
raminit_write_training(timings->mem_clock, dimms, s3resume);
}
@@ -152,10 +156,10 @@ index ecada7b..2b8c44e 100644
/* Program final memory map (with real values). */
diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-index aef863f..b74765f 100644
+index aef863f05a..b74765fd9c 100644
--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-@@ -161,11 +161,13 @@
+@@ -161,11 +161,13 @@ static void lookup_and_write(const int a1step,
mchbar += 4;
}
}
@@ -170,7 +174,7 @@ index aef863f..b74765f 100644
enum {
PULL_UP = 0,
PULL_DOWN = 1,
-@@ -196,6 +198,10 @@
+@@ -196,6 +198,10 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
reg = mchbar_read32(0x518);
lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
@@ -181,7 +185,7 @@ index aef863f..b74765f 100644
}
/* Cleanup? */
mchbar_setbits32(0x400, 1 << 3);
-@@ -216,13 +222,19 @@
+@@ -216,13 +222,19 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
for (channel = 0; channel < 2; ++channel) {
for (group = 0; group < 6; ++group) {
for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) {
@@ -206,7 +210,7 @@ index aef863f..b74765f 100644
mchbar += 0x0010;
/* Channel B knows only the first two groups. */
if ((1 == channel) && (1 == group))
-@@ -230,4 +242,7 @@
+@@ -230,4 +242,7 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
}
mchbar += 0x0040;
}
@@ -214,3 +218,6 @@ index aef863f..b74765f 100644
+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
}
+--
+2.39.2
+
diff --git a/config/coreboot/dell/patches/0028-dell-e6400-crank-up-vram-to-256MB-max.patch b/config/coreboot/dell/patches/0009-dell-e6400-crank-up-vram-to-256MB-max.patch
index 2c23ab0b..8d48bfd9 100644
--- a/config/coreboot/dell/patches/0028-dell-e6400-crank-up-vram-to-256MB-max.patch
+++ b/config/coreboot/dell/patches/0009-dell-e6400-crank-up-vram-to-256MB-max.patch
@@ -1,7 +1,7 @@
-From 1116145917035a92cc92a34e6a914a9506d17680 Mon Sep 17 00:00:00 2001
+From f318da0563ecb2386ac368e04bad88a8aacbc83d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Nov 2023 16:33:11 +0000
-Subject: [PATCH 1/1] dell/e6400: crank up vram to 256MB (max)
+Subject: [PATCH 9/9] dell/e6400: crank up vram to 256MB (max)
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
diff --git a/config/coreboot/dell/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch b/config/coreboot/dell/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch
deleted file mode 100644
index 2f2cddfe..00000000
--- a/config/coreboot/dell/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From f0db13a15c76c2947eec8919fd121450048914ce Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sun, 27 Aug 2023 17:36:36 -0600
-Subject: [PATCH 20/22] ec/dell/mec5035: Add command to enable/disable radios
-
-These were determined by sniffing the LPC bus while toggling the
-hardware wireless switch on the Latitude E6400. To differentiate devices
-options in the vendor BIOS to change which radios the switch controlled
-were used.
-
-Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/ec/dell/mec5035/mec5035.c | 9 +++++++++
- src/ec/dell/mec5035/mec5035.h | 8 ++++++++
- 2 files changed, 17 insertions(+)
-
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index 8da11e5b1c..e0335a4635 100644
---- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -84,6 +84,15 @@ u8 mec5035_mouse_touchpad(u8 setting)
- return buf[0];
- }
-
-+void mec5035_radio_enable(enum mec5035_radio_dev dev, u8 on)
-+{
-+ /* From LPC traces and userspace testing with other values,
-+ the second byte has to be 2 for an unknown reason. */
-+ u8 buf[3] = {dev, 2, on};
-+ write_mailbox_regs(buf, 2, 3);
-+ ec_command(CMD_RADIO_EN);
-+}
-+
- void mec5035_early_init(void)
- {
- /* If this isn't sent the EC shuts down the system after about 15
-diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
-index e7a05b64d4..16512e2cc2 100644
---- a/src/ec/dell/mec5035/mec5035.h
-+++ b/src/ec/dell/mec5035/mec5035.h
-@@ -16,8 +16,16 @@
-
- #define CMD_CPU_OK 0xc2
-
-+#define CMD_RADIO_EN 0x2b
-+enum mec5035_radio_dev {
-+ RADIO_WLAN = 0,
-+ RADIO_WWAN = 1,
-+ RADIO_WPAN = 2,
-+};
-+
- u8 mec5035_mouse_touchpad(u8 setting);
- void mec5035_cpu_ok(void);
- void mec5035_early_init(void);
-+void mec5035_radio_enable(enum mec5035_radio_dev device, u8 on);
-
- #endif /* _EC_DELL_MEC5035_H_ */
---
-2.39.2
-
diff --git a/config/coreboot/dell/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch b/config/coreboot/dell/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch
deleted file mode 100644
index d02ad724..00000000
--- a/config/coreboot/dell/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 4537c365dae010645404fdb5d2d4e5f478dede67 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sun, 27 Aug 2023 19:15:37 -0600
-Subject: [PATCH 21/22] ec/dell/mec5035: Hook up radio enables to option API
-
-Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/ec/dell/mec5035/mec5035.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index e0335a4635..20a33cc0ad 100644
---- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -4,6 +4,7 @@
- #include <console/console.h>
- #include <device/device.h>
- #include <device/pnp.h>
-+#include <option.h>
- #include <pc80/keyboard.h>
- #include <stdint.h>
- #include "mec5035.h"
-@@ -108,6 +109,10 @@ static void mec5035_init(struct device *dev)
- mec5035_mouse_touchpad(TP_PS2_MOUSE);
-
- pc_keyboard_init(NO_AUX_DEVICE);
-+
-+ mec5035_radio_enable(RADIO_WLAN, get_uint_option("wlan", 1));
-+ mec5035_radio_enable(RADIO_WWAN, get_uint_option("wwan", 1));
-+ mec5035_radio_enable(RADIO_WPAN, get_uint_option("bluetooth", 1));
- }
-
- static struct device_operations ops = {
---
-2.39.2
-
diff --git a/config/coreboot/dell/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch b/config/coreboot/dell/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch
deleted file mode 100644
index cca8901f..00000000
--- a/config/coreboot/dell/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch
+++ /dev/null
@@ -1,341 +0,0 @@
-From f1b5b0051718139cf59ad047d42d1360b8452ec5 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 29 Oct 2023 01:18:50 +0000
-Subject: [PATCH 1/1] Revert "Kconfig: Bring HEAP_SIZE to a common, large
- value"
-
-This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6.
-
-NOTE:
-
-this is done instead of merging:
-https://review.coreboot.org/c/coreboot/+/78623
-
-which is still under review for now
-
-the patch i'm reverting is this one:
-https://review.coreboot.org/c/coreboot/+/78270
-
-this was actually only merged the day before i
-updated coreboot revs in lbmk to the 12 october rev,
-so there's no harm in quickly reverting this for now
-
-however, later on, we will rely on the other patch
----
- src/Kconfig | 3 ++-
- src/cpu/qemu-x86/Kconfig | 3 +++
- src/mainboard/sifive/hifive-unleashed/Kconfig | 3 +++
- src/northbridge/amd/pi/Kconfig | 4 ++++
- src/soc/amd/picasso/Kconfig | 4 ++++
- src/soc/amd/stoneyridge/Kconfig | 4 ++++
- src/soc/cavium/cn81xx/Kconfig | 3 +++
- src/soc/intel/alderlake/Kconfig | 5 +++++
- src/soc/intel/apollolake/Kconfig | 4 ++++
- src/soc/intel/cannonlake/Kconfig | 4 ++++
- src/soc/intel/elkhartlake/Kconfig | 4 ++++
- src/soc/intel/jasperlake/Kconfig | 4 ++++
- src/soc/intel/meteorlake/Kconfig | 5 +++++
- src/soc/intel/skylake/Kconfig | 4 ++++
- src/soc/intel/tigerlake/Kconfig | 4 ++++
- src/soc/intel/xeon_sp/Kconfig | 4 ++++
- src/soc/intel/xeon_sp/cpx/Kconfig | 4 ++++
- src/soc/intel/xeon_sp/skx/Kconfig | 4 ++++
- src/soc/intel/xeon_sp/spr/Kconfig | 4 ++++
- src/soc/qualcomm/ipq40xx/Kconfig | 4 ++++
- 20 files changed, 77 insertions(+), 1 deletion(-)
-
-diff --git a/src/Kconfig b/src/Kconfig
-index ae8024089e..1549719dd0 100644
---- a/src/Kconfig
-+++ b/src/Kconfig
-@@ -751,7 +751,8 @@ config RTC
-
- config HEAP_SIZE
- hex
-- default 0x100000
-+ default 0x100000 if FLATTENED_DEVICE_TREE
-+ default 0x4000
-
- config STACK_SIZE
- hex
-diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
-index 0fa999e1ac..f3e2c4cea9 100644
---- a/src/cpu/qemu-x86/Kconfig
-+++ b/src/cpu/qemu-x86/Kconfig
-@@ -35,4 +35,7 @@ config MAX_CPUS
- default 32 if SMM_TSEG
- default 4
-
-+config HEAP_SIZE
-+ default 0x8000
-+
- endif
-diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig
-index 7bc3b0bcbb..7f9300f2a7 100644
---- a/src/mainboard/sifive/hifive-unleashed/Kconfig
-+++ b/src/mainboard/sifive/hifive-unleashed/Kconfig
-@@ -10,6 +10,9 @@ config BOARD_SPECIFIC_OPTIONS
- select FLATTENED_DEVICE_TREE
- select SPI_SDCARD
-
-+config HEAP_SIZE
-+ default 0x10000
-+
- config MAINBOARD_DIR
- default "sifive/hifive-unleashed"
-
-diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
-index 4ffe82a15f..4518db149b 100644
---- a/src/northbridge/amd/pi/Kconfig
-+++ b/src/northbridge/amd/pi/Kconfig
-@@ -29,4 +29,8 @@ config HW_MEM_HOLE_SIZEK
- hex
- default 0x200000
-
-+config HEAP_SIZE
-+ hex
-+ default 0xc0000
-+
- endif # NORTHBRIDGE_AMD_PI
-diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
-index c33f287067..796fe4eb13 100644
---- a/src/soc/amd/picasso/Kconfig
-+++ b/src/soc/amd/picasso/Kconfig
-@@ -264,6 +264,10 @@ config S3_VGA_ROM_RUN
- bool
- default n
-
-+config HEAP_SIZE
-+ hex
-+ default 0xc0000
-+
- config SERIRQ_CONTINUOUS_MODE
- bool
- default n
-diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
-index 6ff135e6a8..9af7455bae 100644
---- a/src/soc/amd/stoneyridge/Kconfig
-+++ b/src/soc/amd/stoneyridge/Kconfig
-@@ -152,6 +152,10 @@ config S3_VGA_ROM_RUN
- bool
- default n
-
-+config HEAP_SIZE
-+ hex
-+ default 0xc0000
-+
- config EHCI_BAR
- hex
- default 0xfef00000
-diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig
-index 77ca97202b..368581f8f1 100644
---- a/src/soc/cavium/cn81xx/Kconfig
-+++ b/src/soc/cavium/cn81xx/Kconfig
-@@ -30,6 +30,9 @@ config ARCH_ARMV8_EXTENSION
- int
- default 1
-
-+config HEAP_SIZE
-+ default 0x10000
-+
- config STACK_SIZE
- default 0x2000
-
-diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
-index 4b960c1d22..82ec8f263e 100644
---- a/src/soc/intel/alderlake/Kconfig
-+++ b/src/soc/intel/alderlake/Kconfig
-@@ -215,6 +215,11 @@ config IED_REGION_SIZE
- hex
- default 0x400000
-
-+config HEAP_SIZE
-+ hex
-+ default 0x80000 if BMP_LOGO
-+ default 0x10000
-+
- config GFX_GMA_DEFAULT_MMIO
- default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT
-
-diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
-index 78ec2987ce..bce935d800 100644
---- a/src/soc/intel/apollolake/Kconfig
-+++ b/src/soc/intel/apollolake/Kconfig
-@@ -252,6 +252,10 @@ config IFWI_FILE_NAME
- help
- Name of file to store in the IFWI region.
-
-+config HEAP_SIZE
-+ hex
-+ default 0x8000
-+
- config MAX_ROOT_PORTS
- int
- default 6
-diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
-index a42a3c365b..80237f9810 100644
---- a/src/soc/intel/cannonlake/Kconfig
-+++ b/src/soc/intel/cannonlake/Kconfig
-@@ -160,6 +160,10 @@ config IED_REGION_SIZE
- hex
- default 0x400000
-
-+config HEAP_SIZE
-+ hex
-+ default 0x8000
-+
- config NHLT_DMIC_1CH_16B
- bool
- depends on ACPI_NHLT
-diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
-index 3361c0ddb9..7f1c767379 100644
---- a/src/soc/intel/elkhartlake/Kconfig
-+++ b/src/soc/intel/elkhartlake/Kconfig
-@@ -104,6 +104,10 @@ config IED_REGION_SIZE
- hex
- default 0x0
-
-+config HEAP_SIZE
-+ hex
-+ default 0x8000
-+
- config MAX_ROOT_PORTS
- int
- default 7
-diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
-index 3d84991e09..ff5def3263 100644
---- a/src/soc/intel/jasperlake/Kconfig
-+++ b/src/soc/intel/jasperlake/Kconfig
-@@ -106,6 +106,10 @@ config IED_REGION_SIZE
- hex
- default 0x400000
-
-+config HEAP_SIZE
-+ hex
-+ default 0x8000
-+
- config MAX_ROOT_PORTS
- int
- default 8
-diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
-index 590e8b80e1..48030a1911 100644
---- a/src/soc/intel/meteorlake/Kconfig
-+++ b/src/soc/intel/meteorlake/Kconfig
-@@ -197,6 +197,11 @@ config IED_REGION_SIZE
- hex
- default 0x400000
-
-+config HEAP_SIZE
-+ hex
-+ default 0x80000 if BMP_LOGO
-+ default 0x10000
-+
- # Intel recommends reserving the PCIe TBT root port resources as below:
- # - 42 buses
- # - 194 MiB Non-prefetchable memory
-diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
-index e0df501460..d6a11363ee 100644
---- a/src/soc/intel/skylake/Kconfig
-+++ b/src/soc/intel/skylake/Kconfig
-@@ -151,6 +151,10 @@ config EXCLUDE_NATIVE_SD_INTERFACE
- help
- If you set this option to n, will not use native SD controller.
-
-+config HEAP_SIZE
-+ hex
-+ default 0x80000
-+
- config IED_REGION_SIZE
- hex
- default 0x400000
-diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
-index c07a0d8365..0a4b7bfdb8 100644
---- a/src/soc/intel/tigerlake/Kconfig
-+++ b/src/soc/intel/tigerlake/Kconfig
-@@ -152,6 +152,10 @@ config IED_REGION_SIZE
- config INTEL_TME
- default n
-
-+config HEAP_SIZE
-+ hex
-+ default 0x10000
-+
- config MAX_ROOT_PORTS
- int
- default 24 if SOC_INTEL_TIGERLAKE_PCH_H
-diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
-index e63bee5451..63ced01067 100644
---- a/src/soc/intel/xeon_sp/Kconfig
-+++ b/src/soc/intel/xeon_sp/Kconfig
-@@ -91,6 +91,10 @@ config ECAM_MMCONF_BASE_ADDRESS
- config ECAM_MMCONF_BUS_NUMBER
- default 256
-
-+config HEAP_SIZE
-+ hex
-+ default 0x80000
-+
- config HPET_MIN_TICKS
- hex
- default 0x80
-diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
-index ac166c3038..f54f7716b6 100644
---- a/src/soc/intel/xeon_sp/cpx/Kconfig
-+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
-@@ -71,6 +71,10 @@ config CPU_MICROCODE_CBFS_LEN
- hex
- default 0x7C00
-
-+config HEAP_SIZE
-+ hex
-+ default 0x80000
-+
- config STACK_SIZE
- hex
- default 0x4000
-diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig
-index 5d843878e1..c2c3d4e2e8 100644
---- a/src/soc/intel/xeon_sp/skx/Kconfig
-+++ b/src/soc/intel/xeon_sp/skx/Kconfig
-@@ -55,6 +55,10 @@ config CPU_MICROCODE_CBFS_LEN
- hex
- default 0x7C00
-
-+config HEAP_SIZE
-+ hex
-+ default 0x80000
-+
- config IED_REGION_SIZE
- hex
- default 0x400000
-diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
-index 43b87ade14..b1c4c783b7 100644
---- a/src/soc/intel/xeon_sp/spr/Kconfig
-+++ b/src/soc/intel/xeon_sp/spr/Kconfig
-@@ -79,6 +79,10 @@ config CPU_MICROCODE_CBFS_LEN
- hex
- default 0x8c00
-
-+config HEAP_SIZE
-+ hex
-+ default 0x80000
-+
- config STACK_SIZE
- hex
- default 0x4000
-diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig
-index 0ce92731c0..0eabb00752 100644
---- a/src/soc/qualcomm/ipq40xx/Kconfig
-+++ b/src/soc/qualcomm/ipq40xx/Kconfig
-@@ -57,4 +57,8 @@ config SBL_UTIL_PATH
- help
- Path for utils to combine SBL_ELF and bootblock
-
-+config HEAP_SIZE
-+ hex
-+ default 0x8000
-+
- endif
---
-2.39.2
-
diff --git a/config/coreboot/dell/target.cfg b/config/coreboot/dell/target.cfg
index 8b2e2277..45176407 100644
--- a/config/coreboot/dell/target.cfg
+++ b/config/coreboot/dell/target.cfg
@@ -1,4 +1,4 @@
tree="dell"
tree_depend="default"
xtree="default"
-rev="d862695f5f432b5c78dada5f16c293a4c3f9fce6"
+rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"
diff --git a/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb b/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb
index b961aef0..fcdde6b2 100644
--- a/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb
@@ -22,6 +22,7 @@ CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -150,7 +151,6 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_VGA_BIOS_FILE="../../../pciroms/pci10de,06eb.rom"
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
@@ -170,7 +170,6 @@ CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_4096=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -184,6 +183,7 @@ CONFIG_COREBOOT_ROMSIZE_KB_4096=y
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=4096
@@ -213,6 +213,7 @@ CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
# CONFIG_VGA_BIOS_SECOND is not set
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@@ -221,14 +222,15 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
+CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
@@ -327,6 +329,8 @@ CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
@@ -363,7 +367,7 @@ CONFIG_LINEAR_FRAMEBUFFER=y
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -374,8 +378,6 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -406,6 +408,7 @@ CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_ISSI=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
CONFIG_HAVE_USBDEBUG_OPTIONS=y
@@ -421,6 +424,10 @@ CONFIG_INTEL_EDID=y
CONFIG_INTEL_INT15=y
CONFIG_INTEL_GMA_ACPI=y
CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
+CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
+# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
+# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
+CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
CONFIG_GFX_GMA=y
CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
CONFIG_GFX_GMA_DYN_CPU=y
@@ -459,6 +466,7 @@ CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
@@ -486,6 +494,7 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
#
# Console
@@ -550,6 +559,10 @@ CONFIG_PAYLOAD_NONE=y
# CONFIG_DISPLAY_MTRRS is not set
#
+# Vendorcode Debug Settings
+#
+
+#
# BLOB Debug Settings
#
diff --git a/config/coreboot/e6400_4mb/config/libgfxinit_txtmode b/config/coreboot/e6400_4mb/config/libgfxinit_txtmode
index 7f2b9822..e253feb0 100644
--- a/config/coreboot/e6400_4mb/config/libgfxinit_txtmode
+++ b/config/coreboot/e6400_4mb/config/libgfxinit_txtmode
@@ -22,6 +22,7 @@ CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -148,7 +149,6 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_VGA_BIOS_FILE="../../../pciroms/pci10de,06eb.rom"
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
@@ -168,7 +168,6 @@ CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_4096=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -182,6 +181,7 @@ CONFIG_COREBOOT_ROMSIZE_KB_4096=y
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=4096
@@ -211,6 +211,7 @@ CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
# CONFIG_VGA_BIOS_SECOND is not set
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@@ -219,14 +220,15 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
+CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
@@ -325,6 +327,8 @@ CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
@@ -359,7 +363,7 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -370,8 +374,6 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -402,6 +404,7 @@ CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_ISSI=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
CONFIG_HAVE_USBDEBUG_OPTIONS=y
@@ -417,6 +420,10 @@ CONFIG_INTEL_EDID=y
CONFIG_INTEL_INT15=y
CONFIG_INTEL_GMA_ACPI=y
CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
+CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
+# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
+# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
+CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
CONFIG_GFX_GMA=y
CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
CONFIG_GFX_GMA_DYN_CPU=y
@@ -455,6 +462,7 @@ CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
@@ -482,6 +490,7 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
#
# Console
@@ -546,6 +555,10 @@ CONFIG_PAYLOAD_NONE=y
# CONFIG_DISPLAY_MTRRS is not set
#
+# Vendorcode Debug Settings
+#
+
+#
# BLOB Debug Settings
#
diff --git a/config/coreboot/e6400nvidia_4mb/config/normal b/config/coreboot/e6400nvidia_4mb/config/normal
index 2743c787..4593f32a 100644
--- a/config/coreboot/e6400nvidia_4mb/config/normal
+++ b/config/coreboot/e6400nvidia_4mb/config/normal
@@ -22,6 +22,7 @@ CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -147,7 +148,6 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_VGA_BIOS_FILE="../../../pciroms/pci10de,06eb.rom"
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
@@ -166,7 +166,6 @@ CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_4096=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -180,6 +179,7 @@ CONFIG_COREBOOT_ROMSIZE_KB_4096=y
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=4096
@@ -209,6 +209,7 @@ CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
# CONFIG_VGA_BIOS_SECOND is not set
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@@ -217,14 +218,15 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
+CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
@@ -323,6 +325,8 @@ CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
@@ -347,7 +351,7 @@ CONFIG_NO_EARLY_GFX_INIT=y
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -358,8 +362,6 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -390,6 +392,7 @@ CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_ISSI=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
CONFIG_HAVE_USBDEBUG_OPTIONS=y
@@ -437,6 +440,7 @@ CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
@@ -464,6 +468,7 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
#
# Console
@@ -528,6 +533,10 @@ CONFIG_PAYLOAD_NONE=y
# CONFIG_DISPLAY_MTRRS is not set
#
+# Vendorcode Debug Settings
+#
+
+#
# BLOB Debug Settings
#