diff options
| author | Leah Rowe <vimuser@noreply.codeberg.org> | 2024-07-11 22:03:18 +0000 |
|---|---|---|
| committer | Leah Rowe <vimuser@noreply.codeberg.org> | 2024-07-11 22:03:18 +0000 |
| commit | 12c3956f5986645afd17e2b72bfdae9771c89240 (patch) | |
| tree | 61bfed2a4295575221e8de8a314f28024bcef436 /config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch | |
| parent | 090cf7ad541d181385d1b1a80c669af68ff22c8b (diff) | |
| parent | 708fc14c605b4d95a80e2476485387551a62d095 (diff) | |
Merge pull request 'Update U-Boot to v2024.07' (#225) from alpernebbi/lbmk:uboot-v2024.07 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/225
Diffstat (limited to 'config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch')
| -rw-r--r-- | config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch b/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch index 4a3e8687..4ceeac59 100644 --- a/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch +++ b/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch @@ -1,4 +1,4 @@ -From 27d49512277677afb7f71e093b007b3e2022b83e Mon Sep 17 00:00:00 2001 +From f98475a64fcfe6ef710acb29391c33c17903e580 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak <alpernebiyasak@gmail.com> Date: Fri, 8 Oct 2021 17:33:22 +0300 Subject: [PATCH] clk: rockchip: rk3399: Set hardcoded clock rates same as @@ -60,7 +60,7 @@ index d941a129f3e5..54035c0df1f3 100644 #define PWM_CLOCK_HZ PMU_PCLK_HZ diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c -index f748fb5189e0..33f02c2d633c 100644 +index 67b2c05ec9ed..754b35c23197 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -54,10 +54,11 @@ struct pll_div { @@ -87,7 +87,7 @@ index f748fb5189e0..33f02c2d633c 100644 void *aclkreg_addr, *dclkreg_addr; u32 div; -@@ -1336,6 +1337,7 @@ static void rkclk_init(struct rockchip_cru *cru) +@@ -1395,6 +1396,7 @@ static void rkclk_init(struct rockchip_cru *cru) /* configure gpll cpll */ rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg); @@ -96,5 +96,5 @@ index f748fb5189e0..33f02c2d633c 100644 /* configure perihp aclk, hclk, pclk */ aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; -- -2.42.0 +2.45.2 |