diff options
| author | Leah Rowe <leah@libreboot.org> | 2024-08-06 01:43:57 +0100 |
|---|---|---|
| committer | Leah Rowe <leah@libreboot.org> | 2024-08-09 20:55:42 +0100 |
| commit | a15347ef1e677ca711ce706877db2416ddfd451a (patch) | |
| tree | 7ddea08641383688c22f3105eb9ef95fe2e6f7a7 /config/submodule/coreboot/default/libgfxinit | |
| parent | dbe24b039d381365b62c02802016f108c3efe8eb (diff) | |
coreboot/dell: merge into coreboot/default
The libgfxinit patch and other patches e.g. DDR2 fix, are
now provided in coreboot/default. The Latitude E6400 is now
using the newer coreboot revision from late July 2024.
Some other configs had to change because of this, relating to
the new way that Nicholas handles timing on LVDS displays
with the E6400 port; a default 96MHz clock is still used for
pixel reference clock, overridden with a value of 100MHz on
other GM45 machines, where 96MHz was previously hardcoded.
Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/submodule/coreboot/default/libgfxinit')
| -rw-r--r-- | config/submodule/coreboot/default/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/config/submodule/coreboot/default/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch b/config/submodule/coreboot/default/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch new file mode 100644 index 00000000..2d248941 --- /dev/null +++ b/config/submodule/coreboot/default/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch @@ -0,0 +1,42 @@ +From ba078864500de99c26b6ea7e3fdcef19bca582a7 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Mon, 20 May 2024 10:10:03 -0600 +Subject: [PATCH 1/1] g45/hw-gfx-gma-plls.adb: Make reference clock frequency + configurable + +Instead of assuming a 96 MHz reference clock frequency, use the value +specified by the new INTEL_GMA_DPLL_REF_FREQ Kconfig. This defaults to +96 MHz to preserve the existing behavior. An example of where this is +needed is the DPLL_REF_SSCLK input, which will typically be 100 MHz +to support LVDS spread spectrum clocking. + +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + common/g45/hw-gfx-gma-plls.adb | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/common/g45/hw-gfx-gma-plls.adb b/common/g45/hw-gfx-gma-plls.adb +index 67242f2..5e970d7 100644 +--- a/common/g45/hw-gfx-gma-plls.adb ++++ b/common/g45/hw-gfx-gma-plls.adb +@@ -12,6 +12,8 @@ + -- GNU General Public License for more details. + -- + ++with CB.Config; ++ + with HW.Time; + with HW.GFX.GMA.Config; + with HW.GFX.GMA.Registers; +@@ -460,7 +462,7 @@ is + (Display => Port_Cfg.Display, + Target_Dotclock => Target_Clock, + -- should be, but doesn't has to be always the same: +- Reference_Clock => 96_000_000, ++ Reference_Clock => CB.Config.INTEL_GMA_DPLL_REF_FREQ, + Best_Clock => Clk, + Valid => Success); + else +-- +2.39.2 + |