i945: switch boards to 20230625 coreboot revision

On T60 with Libreboot 20231106 and the GRUB payload, a user
reported this error in GRUB when a battery was connected:

"alloc magic is broken at 0x7b1aedf0: 0"

This error disappears when a battery is not connected, or
when using Libreboot 20230625. The issue has persisted
through to LIbreboot 20240225 and after, and I believe the
issue will be somewhere in coreboot, not in GRUB itself.

For now, switch i945 laptops (X60, T60, Macbook2,1) back to
the February 2023 coreboot revision used in Libreboot 20230625.

A bisect can be done before the next Libreboot release, ETA
May 2024, if time permits. Otherwise, this revert should solve
the problem for now, at least so far as Libreboot is concerned.

The following coreboot patches have been backported:

    commit 29030d0f3dad2ec6b86000dfe2c8e951ae80bf94
    Author: Bill Xie <persmule@hardenedlinux.org>
    Date:   Sat Oct 7 01:32:51 2023 +0800

        drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume

    Further patches from upstream:

    commit 432e92688eca0e85cbaebca3232f65936b305a98
    Author: Bill Xie <persmule@hardenedlinux.org>
    Date:   Fri Nov 3 12:34:01 2023 +0800

        drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum

These patches fixed S3 on GM45 machines, though it will be useful on
the i945 machines aswell.

The reason I'm doing it this way it is because I don't have a battery
for my X60 or T60, and my T60 isn't in a very good state either,
so I can't reproduce the error myself yet.

Signed-off-by: Leah Rowe <leah@libreboot.org>

9 files changed, 317 insertions, 0 deletions

diff --git a/config/coreboot/i945/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch b/config/coreboot/i945/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch
new file mode 100644
index 00000000..a06a5058
--- /dev/null
+++ b/config/coreboot/i945/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch
@@ -0,0 +1,23 @@
+From 4c5971a6fcf7e948f7df4d0ce2ab0751060cb2ca Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@retroboot.org>
+Date: Fri, 19 Mar 2021 05:54:58 +0000
+Subject: [PATCH 01/18] apple/macbook21: Set default VRAM to 64MiB instead of
+ 8MiB
+
+---
+ src/mainboard/apple/macbook21/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
+index cf1bc4566e..dc0df3b6d6 100644
+--- a/src/mainboard/apple/macbook21/cmos.default
++++ b/src/mainboard/apple/macbook21/cmos.default
+@@ -5,4 +5,4 @@ boot_devices=''
+ boot_default=0x40
+ cmos_defaults_loaded=Yes
+ lpt=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+-- 
+2.39.2
+
diff --git a/config/coreboot/i945/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/i945/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch
new file mode 100644
index 00000000..57c32ec7
--- /dev/null
+++ b/config/coreboot/i945/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch
@@ -0,0 +1,68 @@
+From ff523fd40649b72512b0f1253701509d83ca4a8d Mon Sep 17 00:00:00 2001
+From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
+Date: Wed, 27 Oct 2021 13:36:01 +0200
+Subject: [PATCH 02/18] add c3 and clockgen to apple/macbook21
+
+---
+ src/mainboard/apple/macbook21/Kconfig       |  1 +
+ src/mainboard/apple/macbook21/cstates.c     | 13 +++++++++++++
+ src/mainboard/apple/macbook21/devicetree.cb |  6 ++++++
+ 3 files changed, 20 insertions(+)
+
+diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
+index 5f5ffde588..27377b737c 100644
+--- a/src/mainboard/apple/macbook21/Kconfig
++++ b/src/mainboard/apple/macbook21/Kconfig
+@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select HAVE_ACPI_TABLES
+ 	select HAVE_ACPI_RESUME
+ 	select I945_LVDS
++	select DRIVERS_I2C_CK505
+ 
+ config MAINBOARD_DIR
+ 	default "apple/macbook21"
+diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c
+index 13d06f0839..88b8669c61 100644
+--- a/src/mainboard/apple/macbook21/cstates.c
++++ b/src/mainboard/apple/macbook21/cstates.c
+@@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = {
+ 			.addrh = 0,
+ 		}
+ 	},
++	{
++		.ctype = 3,
++		.latency = 17,
++		.power = 250,
++		.resource = {
++			.space_id = ACPI_ADDRESS_SPACE_FIXED,
++			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
++			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
++			.access_size = ACPI_ACCESS_SIZE_UNDEFINED,
++			.addrl = 0x20,
++			.addrh = 0,
++		}
++	},
+ };
+ 
+ int get_cst_entries(const acpi_cstate_t **entries)
+diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
+index dd701da7ed..5587c48d1f 100644
+--- a/src/mainboard/apple/macbook21/devicetree.cb
++++ b/src/mainboard/apple/macbook21/devicetree.cb
+@@ -100,7 +100,13 @@ chip northbridge/intel/i945
+ 			end
+ 			device pci 1f.3 on # SMBUS
+ 				subsystemid 0x8086 0x7270
++				chip drivers/i2c/ck505
++					register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }"
++					register "regs" = "{ 0x77, 0x77, 0x2d, 0x00, 0x21, 0x10, 0x3b, 0x06, 0x07, 0x0f, 0xf0, 0x01, 0x1e, 0x7f, 0x80, 0x80, 0x10, 0x08, 0x04, 0x01 }"
++					device i2c 69 on end
++				end
+ 			end
++
+ 		end
+ 	end
+ end
+-- 
+2.39.2
+
diff --git a/config/coreboot/i945/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch b/config/coreboot/i945/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch
new file mode 100644
index 00000000..d8ca5b1f
--- /dev/null
+++ b/config/coreboot/i945/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch
@@ -0,0 +1,23 @@
+From fe79712702002bf2044227d6c3cef7ae022e3539 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@osboot.org>
+Date: Sun, 3 Jan 2021 03:34:01 +0000
+Subject: [PATCH 03/18] lenovo/x60: 64MiB Video RAM changed to default
+ (previously it was 8MiB)
+
+---
+ src/mainboard/lenovo/x60/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
+index 5c3576d1f3..88170a1aab 100644
+--- a/src/mainboard/lenovo/x60/cmos.default
++++ b/src/mainboard/lenovo/x60/cmos.default
+@@ -15,4 +15,4 @@ trackpoint=Enable
+ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+-- 
+2.39.2
+
diff --git a/config/coreboot/i945/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch b/config/coreboot/i945/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch
new file mode 100644
index 00000000..630e68a6
--- /dev/null
+++ b/config/coreboot/i945/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch
@@ -0,0 +1,22 @@
+From 79440902866bdafeec651476a5a0e51d42b43b21 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@osboot.org>
+Date: Mon, 22 Feb 2021 22:16:59 +0000
+Subject: [PATCH 04/18] lenovo/t60: make 64MiB VRAM the default in cmos.default
+
+---
+ src/mainboard/lenovo/t60/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
+index af865f16da..7f03157df7 100644
+--- a/src/mainboard/lenovo/t60/cmos.default
++++ b/src/mainboard/lenovo/t60/cmos.default
+@@ -15,4 +15,4 @@ trackpoint=Enable
+ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+-- 
+2.39.2
+
diff --git a/config/coreboot/i945/patches/0005-buildgcc-use-mirrorservice-for-gnu-toolchains.patch b/config/coreboot/i945/patches/0005-buildgcc-use-mirrorservice-for-gnu-toolchains.patch
new file mode 100644
index 00000000..dcb28780
--- /dev/null
+++ b/config/coreboot/i945/patches/0005-buildgcc-use-mirrorservice-for-gnu-toolchains.patch
@@ -0,0 +1,34 @@
+From 5d8fc92948782e9837b26ee8cdfaa88f41fce174 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Fri, 26 Apr 2024 09:16:57 +0100
+Subject: [PATCH 1/1] buildgcc: use mirrorservice for gnu toolchains
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ util/crossgcc/buildgcc | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 0de27ed6e8..0faea86894 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -66,11 +66,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
+ # to the jenkins build as well, or the builder won't download it.
+ 
+ # GCC toolchain archive locations
+-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
+-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
++GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
++MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
++MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
++GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
++BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
+ IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+-- 
+2.39.2
+
diff --git a/config/coreboot/i945/patches/0006-drivers-pc80-rtc-option.c-Stop-resetting-CMOS-during.patch b/config/coreboot/i945/patches/0006-drivers-pc80-rtc-option.c-Stop-resetting-CMOS-during.patch
new file mode 100644
index 00000000..e11e33da
--- /dev/null
+++ b/config/coreboot/i945/patches/0006-drivers-pc80-rtc-option.c-Stop-resetting-CMOS-during.patch
@@ -0,0 +1,56 @@
+From 412f1d68c610f69384b156f09f0b326af984b7cc Mon Sep 17 00:00:00 2001
+From: Bill XIE <persmule@hardenedlinux.org>
+Date: Sat, 7 Oct 2023 01:32:51 +0800
+Subject: [PATCH 1/2] drivers/pc80/rtc/option.c: Stop resetting CMOS during s3
+ resume
+
+After commit e12b313844da ("drivers/pc80/rtc/option.c: Allow CMOS
+defaults to extend to bank 1"), Thinkpad X200 with
+CONFIG(STATIC_OPTION_TABLE) can no longer resume from s3 (detected via
+bisect).
+
+Further inspection shows that DRAM training result of GM45 is stored
+in CMOS above 128 bytes in raminit_read_write_training.c, for s3 resume
+to restore, but it will be erased by sanitize_cmos(), which now clears
+both bank 0 and bank 1, leaving only "untrained" result restored, so s3
+resume will fail.
+
+However, resetting CMOS seems unnecessary during s3 resume. Now,
+cmos_need_reset will be negated when acpi_is_wakeup_s3() returns true.
+
+Tested: Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from
+	s3 again with these changes.
+
+Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b
+Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/78288
+Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+---
+ src/drivers/pc80/rtc/option.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c
+index e8e2345133..e6cfa175ad 100644
+--- a/src/drivers/pc80/rtc/option.c
++++ b/src/drivers/pc80/rtc/option.c
+@@ -1,5 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0-only */
+ 
++#include <acpi/acpi.h>
+ #include <console/console.h>
+ #include <string.h>
+ #include <cbfs.h>
+@@ -200,7 +201,8 @@ void sanitize_cmos(void)
+ {
+ 	const unsigned char *cmos_default;
+ 	const bool cmos_need_reset =
+-		CONFIG(STATIC_OPTION_TABLE) || cmos_error() || !cmos_lb_cks_valid();
++		(CONFIG(STATIC_OPTION_TABLE) || cmos_error() || !cmos_lb_cks_valid())
++		&& !acpi_is_wakeup_s3();
+ 	size_t length = 128;
+ 	size_t i;
+ 
+-- 
+2.39.2
+
diff --git a/config/coreboot/i945/patches/0007-drivers-pc80-rtc-option.c-Reset-only-CMOS-range-cove.patch b/config/coreboot/i945/patches/0007-drivers-pc80-rtc-option.c-Reset-only-CMOS-range-cove.patch
new file mode 100644
index 00000000..1a614db7
--- /dev/null
+++ b/config/coreboot/i945/patches/0007-drivers-pc80-rtc-option.c-Reset-only-CMOS-range-cove.patch
@@ -0,0 +1,51 @@
+From 0bc5a67f926e193a429cce4028fb382c49fa08f8 Mon Sep 17 00:00:00 2001
+From: Bill XIE <persmule@hardenedlinux.org>
+Date: Fri, 3 Nov 2023 12:34:01 +0800
+Subject: [PATCH 2/2] drivers/pc80/rtc/option.c: Reset only CMOS range covered
+ by checksum
+
+Proposed in the comment of commit 29030d0f3dad
+("drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume"),
+during sanitize_cmos(), only reset CMOS range covered by checksum and
+the checksum itself from the file cmos.default in CBFS, in order to
+prevent other runtime data in CMOS (e.g. the DRAM training data on
+GM45 platforms for s3 resume) being erased.
+
+Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig:
+	Bring HEAP_SIZE to a common, large value"), which is already
+	before my commit 29030d0f3dad , Thinkpad X200 with
+	CONFIG(STATIC_OPTION_TABLE) can resume from s3 again,
+	indicating that DRAM training data are no longer erased.
+
+Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
+Co-authored-by: Jonathon Hall <jonathon.hall@puri.sm>
+Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/78906
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+Reviewed-by: Nico Huber <nico.h@gmx.de>
+Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
+---
+ src/drivers/pc80/rtc/option.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c
+index e6cfa175ad..cb18e14ae9 100644
+--- a/src/drivers/pc80/rtc/option.c
++++ b/src/drivers/pc80/rtc/option.c
+@@ -213,8 +213,12 @@ void sanitize_cmos(void)
+ 			return;
+ 
+ 		u8 control_state = cmos_disable_rtc();
+-		for (i = 14; i < MIN(128, length); i++)
++		/* Copy checked range and the checksum from the default */
++		for (i = LB_CKS_RANGE_START; i < MIN(LB_CKS_RANGE_END + 1, length); i++)
+ 			cmos_write_inner(cmos_default[i], i);
++		/* CMOS checksum takes 2 bytes */
++		cmos_write_inner(cmos_default[LB_CKS_LOC], LB_CKS_LOC);
++		cmos_write_inner(cmos_default[LB_CKS_LOC + 1], LB_CKS_LOC + 1);
+ 		cmos_restore_rtc(control_state);
+ 	}
+ }
+-- 
+2.39.2
+
diff --git a/config/coreboot/i945/patches/0022-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/i945/patches/0022-Remove-warning-for-coreboot-images-built-without-a-p.patch
new file mode 100644
index 00000000..547c6392
--- /dev/null
+++ b/config/coreboot/i945/patches/0022-Remove-warning-for-coreboot-images-built-without-a-p.patch
@@ -0,0 +1,38 @@
+From 1ce4f118b024a6367382b46016781f30fe622e3e Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Fri, 12 May 2023 19:55:15 -0600
+Subject: [PATCH] Remove warning for coreboot images built without a payload
+
+I added this in upstream to prevent people from accidentally flashing
+roms without a payload resulting in a no boot situation, but in
+libreboot lbmk handles the payload and thus this warning always comes
+up. This has caused confusion and concern so just patch it out.
+---
+ payloads/Makefile.inc | 13 +------------
+ 1 file changed, 1 insertion(+), 12 deletions(-)
+
+diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
+index e735443a76..4f1692a873 100644
+--- a/payloads/Makefile.inc
++++ b/payloads/Makefile.inc
+@@ -49,16 +49,5 @@ distclean-payloads:
+ print-repo-info-payloads:
+ 	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
+ 
+-ifeq ($(CONFIG_PAYLOAD_NONE),y)
+-files_added:: warn_no_payload
+-endif
+-
+-warn_no_payload:
+-	printf "\n\t** WARNING **\n"
+-	printf "coreboot has been built without a payload. Writing\n"
+-	printf "a coreboot image without a payload to your board's\n"
+-	printf "flash chip will result in a non-booting system. You\n"
+-	printf "can use cbfstool to add a payload to the image.\n\n"
+-
+ .PHONY: force-payload coreinfo nvramcui
+-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
++.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
+-- 
+2.40.1
+
diff --git a/config/coreboot/i945/target.cfg b/config/coreboot/i945/target.cfg
new file mode 100644
index 00000000..16a4de7d
--- /dev/null
+++ b/config/coreboot/i945/target.cfg
@@ -0,0 +1,2 @@
+tree="i945"
+rev="e70bc423f9a2e1d13827f2703efe1f9c72549f20"