i945: switch boards to 20230625 coreboot revision

On T60 with Libreboot 20231106 and the GRUB payload, a user
reported this error in GRUB when a battery was connected:

"alloc magic is broken at 0x7b1aedf0: 0"

This error disappears when a battery is not connected, or
when using Libreboot 20230625. The issue has persisted
through to LIbreboot 20240225 and after, and I believe the
issue will be somewhere in coreboot, not in GRUB itself.

For now, switch i945 laptops (X60, T60, Macbook2,1) back to
the February 2023 coreboot revision used in Libreboot 20230625.

A bisect can be done before the next Libreboot release, ETA
May 2024, if time permits. Otherwise, this revert should solve
the problem for now, at least so far as Libreboot is concerned.

The following coreboot patches have been backported:

    commit 29030d0f3dad2ec6b86000dfe2c8e951ae80bf94
    Author: Bill Xie <persmule@hardenedlinux.org>
    Date:   Sat Oct 7 01:32:51 2023 +0800

        drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume

    Further patches from upstream:

    commit 432e92688eca0e85cbaebca3232f65936b305a98
    Author: Bill Xie <persmule@hardenedlinux.org>
    Date:   Fri Nov 3 12:34:01 2023 +0800

        drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum

These patches fixed S3 on GM45 machines, though it will be useful on
the i945 machines aswell.

The reason I'm doing it this way it is because I don't have a battery
for my X60 or T60, and my T60 isn't in a very good state either,
so I can't reproduce the error myself yet.

Signed-off-by: Leah Rowe <leah@libreboot.org>

1 files changed, 51 insertions, 0 deletions

diff --git a/config/coreboot/i945/patches/0007-drivers-pc80-rtc-option.c-Reset-only-CMOS-range-cove.patch b/config/coreboot/i945/patches/0007-drivers-pc80-rtc-option.c-Reset-only-CMOS-range-cove.patch
new file mode 100644
index 00000000..1a614db7
--- /dev/null
+++ b/config/coreboot/i945/patches/0007-drivers-pc80-rtc-option.c-Reset-only-CMOS-range-cove.patch
@@ -0,0 +1,51 @@
+From 0bc5a67f926e193a429cce4028fb382c49fa08f8 Mon Sep 17 00:00:00 2001
+From: Bill XIE <persmule@hardenedlinux.org>
+Date: Fri, 3 Nov 2023 12:34:01 +0800
+Subject: [PATCH 2/2] drivers/pc80/rtc/option.c: Reset only CMOS range covered
+ by checksum
+
+Proposed in the comment of commit 29030d0f3dad
+("drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume"),
+during sanitize_cmos(), only reset CMOS range covered by checksum and
+the checksum itself from the file cmos.default in CBFS, in order to
+prevent other runtime data in CMOS (e.g. the DRAM training data on
+GM45 platforms for s3 resume) being erased.
+
+Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig:
+	Bring HEAP_SIZE to a common, large value"), which is already
+	before my commit 29030d0f3dad , Thinkpad X200 with
+	CONFIG(STATIC_OPTION_TABLE) can resume from s3 again,
+	indicating that DRAM training data are no longer erased.
+
+Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
+Co-authored-by: Jonathon Hall <jonathon.hall@puri.sm>
+Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/78906
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+Reviewed-by: Nico Huber <nico.h@gmx.de>
+Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
+---
+ src/drivers/pc80/rtc/option.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c
+index e6cfa175ad..cb18e14ae9 100644
+--- a/src/drivers/pc80/rtc/option.c
++++ b/src/drivers/pc80/rtc/option.c
+@@ -213,8 +213,12 @@ void sanitize_cmos(void)
+ 			return;
+ 
+ 		u8 control_state = cmos_disable_rtc();
+-		for (i = 14; i < MIN(128, length); i++)
++		/* Copy checked range and the checksum from the default */
++		for (i = LB_CKS_RANGE_START; i < MIN(LB_CKS_RANGE_END + 1, length); i++)
+ 			cmos_write_inner(cmos_default[i], i);
++		/* CMOS checksum takes 2 bytes */
++		cmos_write_inner(cmos_default[LB_CKS_LOC], LB_CKS_LOC);
++		cmos_write_inner(cmos_default[LB_CKS_LOC + 1], LB_CKS_LOC + 1);
+ 		cmos_restore_rtc(control_state);
+ 	}
+ }
+-- 
+2.39.2
+