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author | Leah Rowe <leah@libreboot.org> | 2023-09-09 20:05:11 +0100 |
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committer | Leah Rowe <leah@libreboot.org> | 2023-09-09 20:11:11 +0100 |
commit | 20be007f5b7042196647eabc5b6ec9d0d84ac108 (patch) | |
tree | 781edcb4441a57b0fe957cd876234b4e897f5796 /config/coreboot/haswell/patches/0017-haswell-NRI-Add-pre-training-steps.patch | |
parent | f989d5b434f8fe3c6c5baafb8b35ec8e6cfcdbb1 (diff) |
blobs/inject: fix checksum validation if no-ucode
on e6400_4mb, the release build scripts remove nvidia's vga
rom which is used on dgpu models. however, microcode is also
removed in separately copied rom images
the inject script was inserting vgaroms directly into these
no-microcode roms, but the microcode blob is bigger than the
vga rom, and cbfstool inserts into the first available free
spot within cbfs, so it was inserting into the spot where
cpu microcode went. this caused the rom checksum to not match
what was generated during build/release/roms being executed
the only real fix is to guarantee offsets within cbfs for all
files, by recording what offsets were used and then calculating
that during insertion
so this patch is a workaround, but fixes the issue. the workaround
is: don't insert blobs directly on no-microcode roms, instead
insert only on microcode-based roms, then re-copy those roms
and remove microcode in aptly named copies
it's a bit more convoluted, but works perfectly fine.
Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/haswell/patches/0017-haswell-NRI-Add-pre-training-steps.patch')
0 files changed, 0 insertions, 0 deletions