diff options
author | Leah Rowe <leah@libreboot.org> | 2023-09-04 02:36:41 +0100 |
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committer | Leah Rowe <leah@libreboot.org> | 2023-09-04 02:47:25 +0100 |
commit | da3c9bb3c5c3b1f2e6e67a3695ce39b17bf68d5b (patch) | |
tree | b81cdd418a4906c846800a8c5094b312e74f57df /config/coreboot/fam15h_udimm/patches/0001-Revert-Revert-nb-amd-mct_ddr3-Fix-RDIMM-training-fai.patch | |
parent | a05010503f9a748943033d1fc40e36625e72dcbb (diff) |
merge config/ and resources/
Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/fam15h_udimm/patches/0001-Revert-Revert-nb-amd-mct_ddr3-Fix-RDIMM-training-fai.patch')
-rw-r--r-- | config/coreboot/fam15h_udimm/patches/0001-Revert-Revert-nb-amd-mct_ddr3-Fix-RDIMM-training-fai.patch | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/config/coreboot/fam15h_udimm/patches/0001-Revert-Revert-nb-amd-mct_ddr3-Fix-RDIMM-training-fai.patch b/config/coreboot/fam15h_udimm/patches/0001-Revert-Revert-nb-amd-mct_ddr3-Fix-RDIMM-training-fai.patch new file mode 100644 index 00000000..3c131a86 --- /dev/null +++ b/config/coreboot/fam15h_udimm/patches/0001-Revert-Revert-nb-amd-mct_ddr3-Fix-RDIMM-training-fai.patch @@ -0,0 +1,31 @@ +From 8f2988cba4fffef1bd4f65e123c76bf4b7a18672 Mon Sep 17 00:00:00 2001 +From: "D.d.P.F. Lombard" <lombard@lombards.xyz> +Date: Sun, 7 Feb 2021 15:29:40 +0100 +Subject: [PATCH 1/6] Revert "Revert "nb/amd/mct_ddr3: Fix RDIMM training + failure on Fam15h" (fixes a bug that prevent certain RAM modules from + booting) + +This reverts commit 610d1c67b2298a9840681c2b4492b6d3fdf44a46. + +After 610d1c67b2298a9840681c2b4492b6d3fdf44a46 many RAM modules wouldn't work and you couldn't even see any output on the screen. +--- + src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c +index ddaaaab8d5..3b07786b91 100644 +--- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c ++++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c +@@ -71,6 +71,9 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, + misc2 |= ((cs_mux_67 & 0x1) << 27); + misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */ + misc2 |= ((cs_mux_45 & 0x1) << 26); ++ ++ if (pDCTstat->Status & (1 << SB_Registered)) ++ misc2 |= 1 << SubMemclkRegDly; + } else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) { + if (pDCTstat->Status & (1 << SB_Registered)) { + misc2 |= 1 << SubMemclkRegDly; +-- +2.25.1 + |