diff options
| author | Nicholas Chin <nic.c3.14@gmail.com> | 2024-05-20 10:46:25 -0600 |
|---|---|---|
| committer | Nicholas Chin <nic.c3.14@gmail.com> | 2024-05-20 10:46:25 -0600 |
| commit | 8629873a6043067affc137be275b7aa69cb1f10c (patch) | |
| tree | 687ef4477eebc28c40c35e987325a72fb1f82b0a /config/coreboot/e6400nvidia_4mb | |
| parent | 1e54db29897786ff49b8ff228ed0b2fbdd8b70dc (diff) | |
Fix E6400 display issue with 1440 x 900 panel
The E6400 uses a 100 MHz reference clock on DPLL_REF_SSCLK, whereas
libgfxinit assumed that the reference was always 96 MHz. The frequency
difference caused by a 100 MHz reference with PLL config values
calculated assuming a 96 MHz reference were not significant enough to
cause noticable issues with the more common 1280 x 800 panels, but are
enough to matter for the 1440 x 900 panels which use a higher pixel
clock. This only affected the pre-OS graphics environment provided by
libgfxinit, as Linux drivers would determine the reference clock
frequency based on data in the VBT.
Fix this by making the reference clock frequency in libgfxinit
configurable for GM45 based on a new coreboot Kconfig, which is set to
100 MHz for the E6400.
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Diffstat (limited to 'config/coreboot/e6400nvidia_4mb')
| -rw-r--r-- | config/coreboot/e6400nvidia_4mb/config/normal | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/config/coreboot/e6400nvidia_4mb/config/normal b/config/coreboot/e6400nvidia_4mb/config/normal index 4593f32a..8cf79154 100644 --- a/config/coreboot/e6400nvidia_4mb/config/normal +++ b/config/coreboot/e6400nvidia_4mb/config/normal @@ -133,6 +133,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 CONFIG_BOARD_DELL_E6400=y # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set # CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" |