diff options
| author | Leah Rowe <leah@libreboot.org> | 2023-10-29 01:26:54 +0000 |
|---|---|---|
| committer | Leah Rowe <leah@libreboot.org> | 2023-10-29 01:29:38 +0000 |
| commit | 93458de74a2e403bdd7e7a25d6fdead41d8fa718 (patch) | |
| tree | 6e49b277faea817ee46b19ae1ba83f4af04099ea /config/coreboot/e6400_4mb | |
| parent | 83bf23766040d5e1642b8c80d975953c1c34f876 (diff) | |
revert coreboot heap size patch
the patch:
https://review.coreboot.org/c/coreboot/+/78270
this has been reverted, because it caused s3 resume
issues on most intel laptops in libreboot.
i was going to merge this instead:
https://review.coreboot.org/c/coreboot/+/78623
however, it's under review, and this doesn't change
to the old behaviour; it keeps the new universal
config, but changes the default
we know the old logic works, so keep that for now.
in fact, the offending patch was only merged to
main in coreboot, one day before i recently
updated coreboot revs in coreboot/default - i used
a 12 october revision, the patch above is 11 october
i then ran "./update trees -u coreboot" which updated
the heap sizes back to the old defaults. this should
fix s3 suspend/resume where it was broken, in the
libreboot 20231021 release - a point release with this
and a few other fixes is planned soon.
Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/e6400_4mb')
| -rw-r--r-- | config/coreboot/e6400_4mb/config/libgfxinit_corebootfb | 2 | ||||
| -rw-r--r-- | config/coreboot/e6400_4mb/config/libgfxinit_txtmode | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb b/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb index 54d627a2..ca0b6f8d 100644 --- a/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb @@ -171,6 +171,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -486,7 +487,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/e6400_4mb/config/libgfxinit_txtmode b/config/coreboot/e6400_4mb/config/libgfxinit_txtmode index 15a9719c..b2ee3e81 100644 --- a/config/coreboot/e6400_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6400_4mb/config/libgfxinit_txtmode @@ -169,6 +169,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -482,7 +483,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console |