diff options
| author | Leah Rowe <leah@libreboot.org> | 2024-07-31 12:26:25 +0100 |
|---|---|---|
| committer | Leah Rowe <leah@libreboot.org> | 2024-08-09 20:50:37 +0100 |
| commit | dbe24b039d381365b62c02802016f108c3efe8eb (patch) | |
| tree | 435214dc54b53a560e2d2a9fff3dfe5864943dc6 /config/coreboot/default | |
| parent | 1b55fc790c1eebc8db16dab0611f08df36acd793 (diff) | |
coreboot/default: Update to 97bc693ab (2024-07-29)
Several patches are now merged upstream and no longer needed
in lbmk, such as the HP EliteBook 8560w patch, and related
patches. Some patches were changed, for example the Dell Latitude
ivb/snb laptops are now variants in coreboot, instead of being
individual ports; now they re-use the same base code.
This this, the corresponding files under config/submodules
have changed, for things like 3rdparty submodules e.g. libgfxinit,
and tarballs e.g. crossgcc.
This is long overdue, and will enable more boards to be added.
This newer revision will be used in the next release, and some
follow-up patches will merge these trees into default:
* coreboot/haswell
* coreboot/dell
Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/default')
59 files changed, 4645 insertions, 9408 deletions
diff --git a/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch b/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch index d2bae2e4..8bbffb53 100644 --- a/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch +++ b/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch @@ -1,7 +1,7 @@ -From 1195c954a3b6822e5e843067251c0c80c9520eab Mon Sep 17 00:00:00 2001 +From 2d9f38a12b883e1ddcdae5de107f204e522146e2 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@retroboot.org> Date: Fri, 19 Mar 2021 05:54:58 +0000 -Subject: [PATCH 01/30] apple/macbook21: Set default VRAM to 64MiB instead of +Subject: [PATCH 01/39] apple/macbook21: Set default VRAM to 64MiB instead of 8MiB --- @@ -9,10 +9,10 @@ Subject: [PATCH 01/30] apple/macbook21: Set default VRAM to 64MiB instead of 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default -index cf1bc4566e..dc0df3b6d6 100644 +index b744b11cda..9749e26547 100644 --- a/src/mainboard/apple/macbook21/cmos.default +++ b/src/mainboard/apple/macbook21/cmos.default -@@ -5,4 +5,4 @@ boot_devices='' +@@ -7,4 +7,4 @@ boot_devices='' boot_default=0x40 cmos_defaults_loaded=Yes lpt=Enable diff --git a/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch index 8cd272ec..b163d5d2 100644 --- a/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch +++ b/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch @@ -1,7 +1,7 @@ -From 50a52cea2b43e6e407b456c082e908c7d29e090b Mon Sep 17 00:00:00 2001 +From e60ec1c7304e3f167fd2bf762f28b7eacd0b169a Mon Sep 17 00:00:00 2001 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> Date: Wed, 27 Oct 2021 13:36:01 +0200 -Subject: [PATCH 02/30] add c3 and clockgen to apple/macbook21 +Subject: [PATCH 02/39] add c3 and clockgen to apple/macbook21 --- src/mainboard/apple/macbook21/Kconfig | 1 + @@ -10,10 +10,10 @@ Subject: [PATCH 02/30] add c3 and clockgen to apple/macbook21 3 files changed, 20 insertions(+) diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig -index 5f5ffde588..27377b737c 100644 +index 330d8efae2..cf10343554 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig -@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS +@@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select I945_LVDS diff --git a/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch b/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch index 34e12a6b..8bf9a049 100644 --- a/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch +++ b/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch @@ -1,7 +1,7 @@ -From ca4cd66f411247395a323e5ea1abf09e83057827 Mon Sep 17 00:00:00 2001 +From 9a0157b1459365cf52f90e66b78dd6b60a259587 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@osboot.org> Date: Sun, 3 Jan 2021 03:34:01 +0000 -Subject: [PATCH 03/30] lenovo/x60: 64MiB Video RAM changed to default +Subject: [PATCH 03/39] lenovo/x60: 64MiB Video RAM changed to default (previously it was 8MiB) --- @@ -9,10 +9,10 @@ Subject: [PATCH 03/30] lenovo/x60: 64MiB Video RAM changed to default 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default -index 5c3576d1f3..88170a1aab 100644 +index 58825c8a36..8e0aaf427d 100644 --- a/src/mainboard/lenovo/x60/cmos.default +++ b/src/mainboard/lenovo/x60/cmos.default -@@ -15,4 +15,4 @@ trackpoint=Enable +@@ -17,4 +17,4 @@ trackpoint=Enable sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable diff --git a/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch b/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch index ee90dd63..80f3023d 100644 --- a/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch +++ b/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch @@ -1,17 +1,17 @@ -From eca0f4a3a4d6907e92b948547a362ca0ac3fc382 Mon Sep 17 00:00:00 2001 +From 5b2a26e72bce37f7b0a92f1ed93fd607cea8de9b Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@osboot.org> Date: Mon, 22 Feb 2021 22:16:59 +0000 -Subject: [PATCH 04/30] lenovo/t60: make 64MiB VRAM the default in cmos.default +Subject: [PATCH 04/39] lenovo/t60: make 64MiB VRAM the default in cmos.default --- src/mainboard/lenovo/t60/cmos.default | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default -index af865f16da..7f03157df7 100644 +index 283a5747ee..91f6c0e6e2 100644 --- a/src/mainboard/lenovo/t60/cmos.default +++ b/src/mainboard/lenovo/t60/cmos.default -@@ -15,4 +15,4 @@ trackpoint=Enable +@@ -17,4 +17,4 @@ trackpoint=Enable sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable diff --git a/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch b/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch index 35d74c75..2140071d 100644 --- a/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch +++ b/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch @@ -1,7 +1,7 @@ -From 2eae87815675aebd472b6042777fe51279be4550 Mon Sep 17 00:00:00 2001 +From 945d84782e706e8f3effab57edca68d9463d21fc Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 14 May 2021 13:10:33 +0100 -Subject: [PATCH 05/30] lenovo/t400: set VRAM to 256MiB VRAM by default +Subject: [PATCH 05/39] lenovo/t400: set VRAM to 256MiB VRAM by default Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -9,10 +9,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default -index a326e315b1..b907a3e2df 100644 +index a16d386dd1..e7bb32306c 100644 --- a/src/mainboard/lenovo/t400/cmos.default +++ b/src/mainboard/lenovo/t400/cmos.default -@@ -13,4 +13,4 @@ power_management_beeps=Enable +@@ -15,4 +15,4 @@ power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI hybrid_graphics_mode=Integrated Only diff --git a/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch index cc6abb00..07434470 100644 --- a/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch +++ b/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch @@ -1,7 +1,7 @@ -From f6b4913a5eca619b745d5ccea9af022a54fb185b Mon Sep 17 00:00:00 2001 +From 112470b4f7b046ec2656699336211ba63ff448fa Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 14 May 2021 13:11:59 +0100 -Subject: [PATCH 06/30] lenovo/x200: set VRAM to 256MiB by default +Subject: [PATCH 06/39] lenovo/x200: set VRAM to 256MiB by default Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -9,10 +9,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default -index bb4323836e..458b3f19c5 100644 +index 434af5d227..443ef54e41 100644 --- a/src/mainboard/lenovo/x200/cmos.default +++ b/src/mainboard/lenovo/x200/cmos.default -@@ -12,4 +12,4 @@ sticky_fn=Disable +@@ -14,4 +14,4 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI diff --git a/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch index c4840ecc..ad619606 100644 --- a/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch +++ b/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch @@ -1,7 +1,7 @@ -From a3a0969075163be413f968b03671aa5d8662672a Mon Sep 17 00:00:00 2001 +From 37418629a56cb740cae2870317458ea52daad8c9 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 14 May 2021 13:18:26 +0100 -Subject: [PATCH 07/30] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default +Subject: [PATCH 07/39] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -9,10 +9,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default -index 8372032119..bedad54d2a 100644 +index fe79c83570..4a1f97a9d8 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default -@@ -2,4 +2,4 @@ boot_option=Fallback +@@ -4,4 +4,4 @@ boot_option=Fallback debug_level=Debug power_on_after_fail=Enable nmi=Enable diff --git a/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch index 19977870..e0ac6cf1 100644 --- a/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch +++ b/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch @@ -1,7 +1,7 @@ -From 223ac17617b3a0c08925abbbe42d0d003e144a28 Mon Sep 17 00:00:00 2001 +From e785387dffe382a02d4c0cb006cced48c235484c Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 14 May 2021 13:21:39 +0100 -Subject: [PATCH 08/30] acer/g43t-am3: set VRAM to 256MiB by default +Subject: [PATCH 08/39] acer/g43t-am3: set VRAM to 256MiB by default Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -9,10 +9,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default -index 706f5dd551..e8b45ea22c 100644 +index 23f0e55f3e..8d6c4db1ce 100644 --- a/src/mainboard/acer/g43t-am3/cmos.default +++ b/src/mainboard/acer/g43t-am3/cmos.default -@@ -3,4 +3,4 @@ debug_level=Debug +@@ -5,4 +5,4 @@ debug_level=Debug power_on_after_fail=Disable nmi=Enable sata_mode=AHCI diff --git a/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch index 332b870e..f655f93c 100644 --- a/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch +++ b/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch @@ -1,7 +1,7 @@ -From 80ebbfef42454ea0911e5fc3858103d905987ed8 Mon Sep 17 00:00:00 2001 +From 3659aec797baa40e4336e88361a705295fb72b0f Mon Sep 17 00:00:00 2001 From: persmule <persmule@gmail.com> Date: Sun, 31 Oct 2021 23:33:26 +0000 -Subject: [PATCH 09/30] lenovo/t400: Enable all SATA ports +Subject: [PATCH 09/39] lenovo/t400: Enable all SATA ports There are 2 SATA ports on the chassis of t400(s), but at least one dock for t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its diff --git a/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch b/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch index 12917ed8..db6d64f8 100644 --- a/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch +++ b/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch @@ -1,7 +1,7 @@ -From 318a97c284f8d5030100476a32516ddc9e51603d Mon Sep 17 00:00:00 2001 +From 820c2d64a7415f7159fd7cdac4746049c91f89a2 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 20 Dec 2021 01:29:31 +0000 -Subject: [PATCH 10/30] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by +Subject: [PATCH 10/39] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by default --- @@ -9,10 +9,10 @@ Subject: [PATCH 10/30] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default -index 7314066c2b..2e315d4521 100644 +index 732e214b32..3bb78960b9 100644 --- a/src/mainboard/lenovo/x230/cmos.default +++ b/src/mainboard/lenovo/x230/cmos.default -@@ -16,3 +16,4 @@ backlight=Both +@@ -18,3 +18,4 @@ backlight=Both usb_always_on=Disable f1_to_f12_as_primary=Enable me_state=Normal diff --git a/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch index dc3a33ca..868b65d5 100644 --- a/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch +++ b/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -1,7 +1,7 @@ -From 47afbe8b94edd1ff58c1daf0bda020e6afac35f4 Mon Sep 17 00:00:00 2001 +From 6bc13399517009917538cd4ddb426c4b1550bfad Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 3 Jan 2022 19:06:22 +0000 -Subject: [PATCH 11/30] lenovo/x230: set me_state=Disabled in cmos.default +Subject: [PATCH 11/39] lenovo/x230: set me_state=Disabled in cmos.default I only recently found out about this. It's possible to use me_cleaner to do the same thing, but some people might just flash coreboot and not do @@ -23,10 +23,10 @@ Date: Thu Nov 21 21:47:31 2019 +0300 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default -index 2e315d4521..3585cbd58b 100644 +index 3bb78960b9..ae47202aac 100644 --- a/src/mainboard/lenovo/x230/cmos.default +++ b/src/mainboard/lenovo/x230/cmos.default -@@ -15,5 +15,5 @@ trackpoint=Enable +@@ -17,5 +17,5 @@ trackpoint=Enable backlight=Both usb_always_on=Disable f1_to_f12_as_primary=Enable diff --git a/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch index 49f4db9b..09981df8 100644 --- a/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch +++ b/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -1,7 +1,7 @@ -From 531ef34ece796f38cb8a13a54856e46e79842e29 Mon Sep 17 00:00:00 2001 +From 72c9e1403fb93c025be75536f5520e2ef9d4da9e Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Wed, 2 Mar 2022 21:50:01 +0000 -Subject: [PATCH 12/30] set me_state=Disabled on all cmos.default files! +Subject: [PATCH 12/39] set me_state=Disabled on all cmos.default files! yeah. why the hell isn't this the default @@ -20,99 +20,101 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default -index 681c40e78b..57cdcf9162 100644 +index be08e0a342..b8970efa46 100644 --- a/src/mainboard/lenovo/l520/cmos.default +++ b/src/mainboard/lenovo/l520/cmos.default -@@ -14,4 +14,4 @@ sticky_fn=Disable +@@ -16,4 +16,4 @@ sticky_fn=Disable trackpoint=Enable backlight=Both usb_always_on=Disable -me_state=Normal +me_state=Disabled diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default -index 8244071b8a..c011867916 100644 +index 6fd26c5fe3..27a62d07b3 100644 --- a/src/mainboard/lenovo/t420/cmos.default +++ b/src/mainboard/lenovo/t420/cmos.default -@@ -14,4 +14,4 @@ sticky_fn=Disable +@@ -16,4 +16,4 @@ sticky_fn=Disable trackpoint=Enable hybrid_graphics_mode=Integrated Only usb_always_on=Disable -me_state=Normal +me_state=Disabled diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default -index 8244071b8a..c011867916 100644 +index 6fd26c5fe3..27a62d07b3 100644 --- a/src/mainboard/lenovo/t420s/cmos.default +++ b/src/mainboard/lenovo/t420s/cmos.default -@@ -14,4 +14,4 @@ sticky_fn=Disable +@@ -16,4 +16,4 @@ sticky_fn=Disable trackpoint=Enable hybrid_graphics_mode=Integrated Only usb_always_on=Disable -me_state=Normal +me_state=Disabled diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default -index 26795fe5cf..55e1e6c04e 100644 +index c896eadec1..6d1e172056 100644 --- a/src/mainboard/lenovo/t430/cmos.default +++ b/src/mainboard/lenovo/t430/cmos.default -@@ -15,4 +15,4 @@ trackpoint=Enable +@@ -17,4 +17,4 @@ trackpoint=Enable backlight=Both usb_always_on=Disable hybrid_graphics_mode=Integrated Only -me_state=Normal +me_state=Disabled diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default -index 52dbf70377..b16800ca9e 100644 +index 286fb0ae8c..5a05c73721 100644 --- a/src/mainboard/lenovo/t430s/cmos.default +++ b/src/mainboard/lenovo/t430s/cmos.default -@@ -16,4 +16,4 @@ backlight=Both +@@ -18,4 +18,4 @@ backlight=Both enable_dual_graphics=Disable usb_always_on=Disable f1_to_f12_as_primary=Enable -me_state=Normal +me_state=Disabled diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default -index cf79b391e2..b66f7034dc 100644 +index 4857f92f67..ab1be1a678 100644 --- a/src/mainboard/lenovo/t520/cmos.default +++ b/src/mainboard/lenovo/t520/cmos.default -@@ -15,4 +15,4 @@ trackpoint=Enable +@@ -17,4 +17,4 @@ trackpoint=Enable backlight=Both hybrid_graphics_mode=Integrated Only usb_always_on=Disable -me_state=Normal +me_state=Disabled diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default -index cf79b391e2..b66f7034dc 100644 +index 4857f92f67..ab1be1a678 100644 --- a/src/mainboard/lenovo/t530/cmos.default +++ b/src/mainboard/lenovo/t530/cmos.default -@@ -15,4 +15,4 @@ trackpoint=Enable +@@ -17,4 +17,4 @@ trackpoint=Enable backlight=Both hybrid_graphics_mode=Integrated Only usb_always_on=Disable -me_state=Normal +me_state=Disabled diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default -index 6d1d57a795..52f303dfdb 100644 +index ef706c1303..b318ab9772 100644 --- a/src/mainboard/lenovo/x220/cmos.default +++ b/src/mainboard/lenovo/x220/cmos.default -@@ -13,4 +13,4 @@ usb_always_on=Disable +@@ -15,4 +15,4 @@ usb_always_on=Disable fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable -me_state=Normal +me_state=Disabled diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default -index 62715bc6ba..129b5fd121 100644 +index d61046df6b..8c793fd1c3 100644 --- a/src/mainboard/protectli/vault_cml/cmos.default +++ b/src/mainboard/protectli/vault_cml/cmos.default -@@ -1,3 +1,3 @@ +@@ -2,4 +2,4 @@ + boot_option=Fallback debug_level=Debug -me_state=Enable +me_state=Disabled diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default -index 62715bc6ba..129b5fd121 100644 +index d61046df6b..8c793fd1c3 100644 --- a/src/mainboard/system76/tgl-u/cmos.default +++ b/src/mainboard/system76/tgl-u/cmos.default -@@ -1,3 +1,3 @@ +@@ -2,4 +2,4 @@ + boot_option=Fallback debug_level=Debug -me_state=Enable diff --git a/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0013-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch index a71324db..9d4270e7 100644 --- a/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ b/config/coreboot/default/patches/0013-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -1,7 +1,7 @@ -From 158b79e6057e071d039619f617c112d31fb13f64 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> +From 70cf6905b54d39285025373dae1c897c9c727f83 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 15/30] util/ifdtool: add --nuke flag (all 0xFF on region) +Subject: [PATCH 13/39] util/ifdtool: add --nuke flag (all 0xFF on region) When this option is used, the region's contents are overwritten with all ones (0xFF). @@ -16,14 +16,14 @@ Rebased since the last revision update in lbmk. Signed-off-by: Leah Rowe <leah@libreboot.org> --- - util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------ - 1 file changed, 81 insertions(+), 31 deletions(-) + util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++----------- + 1 file changed, 83 insertions(+), 31 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index 191b3216de..38132b4a28 100644 +index 32b2081d93..1473cf058b 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c -@@ -1942,6 +1942,7 @@ static void print_usage(const char *name) +@@ -2204,6 +2204,7 @@ static void print_usage(const char *name) " tgl - Tiger Lake\n" " wbg - Wellsburg\n" " -S | --setpchstrap Write a PCH strap\n" @@ -31,7 +31,7 @@ index 191b3216de..38132b4a28 100644 " -V | --newvalue The new value to write into PCH strap specified by -S\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" -@@ -1950,6 +1951,60 @@ static void print_usage(const char *name) +@@ -2212,6 +2213,60 @@ static void print_usage(const char *name) "\n"); } @@ -92,15 +92,15 @@ index 191b3216de..38132b4a28 100644 int main(int argc, char *argv[]) { int opt, option_index = 0; -@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[]) +@@ -2219,6 +2274,7 @@ int main(int argc, char *argv[]) int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; + int mode_nuke = 0; - int mode_gpr0_disable = 0; + int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0; char *region_type_string = NULL, *region_fname = NULL; const char *layout_fname = NULL; -@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[]) +@@ -2254,6 +2310,7 @@ int main(int argc, char *argv[]) {"validate", 0, NULL, 't'}, {"setpchstrap", 1, NULL, 'S'}, {"newvalue", 1, NULL, 'V'}, @@ -108,7 +108,7 @@ index 191b3216de..38132b4a28 100644 {0, 0, 0, 0} }; -@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[]) +@@ -2303,35 +2360,8 @@ int main(int argc, char *argv[]) region_fname++; // Descriptor, BIOS, ME, GbE, Platform // valid type? @@ -141,12 +141,12 @@ index 191b3216de..38132b4a28 100644 - else if (!strcasecmp("PTT", region_type_string)) - region_type = 15; - if (region_type == -1) { -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { ++ if ((region_type = ++ get_region_type_string(region_type_string)) == -1) { fprintf(stderr, "No such region type: '%s'\n\n", region_type_string); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); -@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[]) +@@ -2508,6 +2538,22 @@ int main(int argc, char *argv[]) case 't': mode_validate = 1; break; @@ -169,31 +169,33 @@ index 191b3216de..38132b4a28 100644 case 'v': print_version(); exit(EXIT_SUCCESS); -@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[]) +@@ -2524,7 +2570,8 @@ int main(int argc, char *argv[]) if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 | mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + -- mode_gpr0_disable) > 1) { -+ mode_gpr0_disable + mode_nuke) > 1) { +- (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) { ++ (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status + ++ mode_nuke) > 1) { fprintf(stderr, "You may not specify more than one mode.\n\n"); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); exit(EXIT_FAILURE); -@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[]) +@@ -2533,7 +2580,8 @@ int main(int argc, char *argv[]) if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 + mode_locked + mode_unlocked + mode_density + mode_altmedisable + -- mode_validate + mode_gpr0_disable) == 0) { -+ mode_validate + mode_gpr0_disable + mode_nuke) == 0) { +- mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) { ++ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status + ++ mode_nuke) == 0) { fprintf(stderr, "You need to specify a mode.\n\n"); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); exit(EXIT_FAILURE); -@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[]) +@@ -2646,6 +2694,10 @@ int main(int argc, char *argv[]) write_image(new_filename, image, size); } -+ if (mode_nuke) { -+ nuke(new_filename, image, size, region_type); -+ } ++ if (mode_nuke) { ++ nuke(new_filename, image, size, region_type); ++ } + if (mode_altmedisable) { struct fpsba *fpsba = find_fpsba(image, size); diff --git a/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch b/config/coreboot/default/patches/0014-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch index 279fdad1..bfcc486a 100644 --- a/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch +++ b/config/coreboot/default/patches/0014-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch @@ -1,7 +1,7 @@ -From bb83e857a2e7b6ecb7cb476ba65019b14e68dc34 Mon Sep 17 00:00:00 2001 +From c53e5035b612710595abc93f0b4c3c65ca61ebad Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Wed, 1 Dec 2021 02:53:00 +0000 -Subject: [PATCH 16/30] fix speedstep on x200/t400: Revert +Subject: [PATCH 14/39] fix speedstep on x200/t400: Revert "cpu/intel/model_1067x: enable PECI" This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f. @@ -16,7 +16,7 @@ maintain this revert patch in Libreboot, from now on. 1 file changed, 9 deletions(-) diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c -index 315e7c36fc..1423fd72bc 100644 +index d051e8915b..30ba2bf0c6 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -141,8 +141,6 @@ static void configure_emttm_tables(void) diff --git a/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch b/config/coreboot/default/patches/0015-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch index 4e5f5089..4e0c8172 100644 --- a/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch +++ b/config/coreboot/default/patches/0015-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch @@ -1,7 +1,7 @@ -From 8a94f38398b8fa554fa4ae53ecb88a372df634fd Mon Sep 17 00:00:00 2001 +From dabe942b006082f6e592a26f1d0f13a2586b53d6 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 17 Apr 2023 15:49:57 +0100 -Subject: [PATCH 17/30] GM45-type CPUs: don't enable alternative SMRR +Subject: [PATCH 15/39] GM45-type CPUs: don't enable alternative SMRR This reverts the changes in coreboot revision: df7aecd92643d207feaf7fd840f8835097346644 @@ -42,7 +42,7 @@ Pragmatism is a good thing. I recommend it. 5 files changed, 16 insertions(+), 26 deletions(-) diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c -index 1423fd72bc..d1f98ca43a 100644 +index 30ba2bf0c6..312046901a 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -8,6 +8,7 @@ diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0016-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch index bfc9231a..9ebeffa2 100644 --- a/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ b/config/coreboot/default/patches/0016-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -1,7 +1,7 @@ -From 2b899f40ce5d728faa7c1da23c3348435b7ac9cb Mon Sep 17 00:00:00 2001 +From 6426e07c7da50d588ee1ca30e0911040d89e4c96 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 18/30] mb/dell/e6400: Enable 01.0 device in devicetree for +Subject: [PATCH 16/39] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU models Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed diff --git a/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0017-Remove-warning-for-coreboot-images-built-without-a-p.patch index 090f2629..b575453c 100644 --- a/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/default/patches/0017-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,7 +1,7 @@ -From 2ccd3e71730004c3ffbed178087cb778c170079e Mon Sep 17 00:00:00 2001 +From 29a654eaaa7bf924f9681a2520dbabfe12619269 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 19/30] Remove warning for coreboot images built without a +Subject: [PATCH 17/39] Remove warning for coreboot images built without a payload I added this in upstream to prevent people from accidentally flashing @@ -13,10 +13,10 @@ up. This has caused confusion and concern so just patch it out. 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk -index a2336aa876..4f1692a873 100644 +index 5f988dac1b..516133880f 100644 --- a/payloads/Makefile.mk +++ b/payloads/Makefile.mk -@@ -49,16 +49,5 @@ distclean-payloads: +@@ -50,16 +50,5 @@ distclean-payloads: print-repo-info-payloads: -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) diff --git a/config/coreboot/default/patches/0018-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch b/config/coreboot/default/patches/0018-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch new file mode 100644 index 00000000..bfcdb6cf --- /dev/null +++ b/config/coreboot/default/patches/0018-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch @@ -0,0 +1,430 @@ +From 892b6244c27590cbf1d82125340c57273e42b911 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Sat, 19 Aug 2023 16:19:10 -0600 +Subject: [PATCH 18/39] mb/dell: Add Latitude E6530 (Ivy Bridge) + +Mainboard is QALA0/LA-7761P (UMA). The version with a Nvidia dGPU was +not tested. I do not physically have this system; someone with physical +access to one sent me the output of autoport which I then modified to +produce this port. + +I was also sent the vbios obtained using intel_bios_dumper while running +version A22 of the vendor firmware, which I then processed using +`intelvbttool --inoprom vbios.bin --outvbt data.vbt` to obtain data.vbt. + +This was originally tested and found to be working as a standalone board +port in Libreboot, though this variant based port in upstream coreboot +has not been tested. + +This can be internally flashed by sending a command to the EC, which +causes the EC to pull the FDO pin low and the firmware to skip setting +up any chipset based write protections [1]. The EC is the SMSC MEC5055, +which seems to be compatible with the existing MEC5035 code. + +[1] https://gitlab.com/nic3-14159/dell-flash-unlock + +Change-Id: I9fcd73416018574f8934962f92c8222d0101cb71 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/snb_ivb_latitude/Kconfig | 8 + + .../dell/snb_ivb_latitude/Kconfig.name | 3 + + .../snb_ivb_latitude/variants/e6530/data.vbt | Bin 0 -> 4280 bytes + .../variants/e6530/early_init.c | 14 ++ + .../snb_ivb_latitude/variants/e6530/gpio.c | 192 ++++++++++++++++++ + .../variants/e6530/hda_verb.c | 32 +++ + .../variants/e6530/overridetree.cb | 37 ++++ + 7 files changed, 286 insertions(+) + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/data.vbt + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb + +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig +index be9ac37845..03377275f0 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig +@@ -23,6 +23,12 @@ config BOARD_DELL_LATITUDE_E6430 + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_C216 + ++config BOARD_DELL_LATITUDE_E6530 ++ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON ++ select BOARD_ROMSIZE_KB_12288 ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select SOUTHBRIDGE_INTEL_C216 ++ + if BOARD_DELL_SNB_IVB_LATITUDE_COMMON + + config DRAM_RESET_GATE_GPIO +@@ -33,6 +39,7 @@ config MAINBOARD_DIR + + config MAINBOARD_PART_NUMBER + default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430 ++ default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530 + + config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" +@@ -42,6 +49,7 @@ config USBDEBUG_HCD_INDEX + + config VARIANT_DIR + default "e6430" if BOARD_DELL_LATITUDE_E6430 ++ default "e6530" if BOARD_DELL_LATITUDE_E6530 + + config VGA_BIOS_ID + default "8086,0166" +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +index 183252630a..d89185d670 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +@@ -2,3 +2,6 @@ + + config BOARD_DELL_LATITUDE_E6430 + bool "Latitude E6430" ++ ++config BOARD_DELL_LATITUDE_E6530 ++ bool "Latitude E6530" +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..af64a913d521fe240ce30e114e90fe75d3841bbc +GIT binary patch +literal 4280 +zcmdT{U2GiH75-*te`aTAcGqJQY$rA+e`ZbWcy_TDH@NC}cbl$*NjAn^RtPm->J7GV +zY_m3jN`RN*h9FvG3Do9+qP$c^s1;PLB3@br9>Ag%La5?TLP`-2DDaR65U2_)=g!QU +zIJ+cPr4+cc-@WIad+wQY&YW{+c1J!nPPgn&^^N3Hy*D37jg0=7CSl@*=mXr>x75gi +zTMlK0$A=H4Mh~QKqCa92jz_;d3rtFqp(o-4gCnzxrJ2}Rw@^!haWp<ahv&+aDb5_3 +zE0-vq=pkms7Ves!pD#^PA#PF^_wjBTO=oC(ayR{asyKURiBdh3?x76Ll#Z5WXklvl +z@M5XFK#OxUXqrdzedca+l4WK~_tG8Hv&HgsX`$Za3pnYy`CpW$@0?nsSh|}MrfK#j +z%y^t^lPNt{p5INwGcz<MWEN<wv`{J^Eluv$Rb2&6%ZgV5Bp(6~Lz2Eoz~@C!!B)bs +z1x-OrK~}*8L07Po(5+xZL6I<}phTEf5QRsVJYHa{f^AXPFaoSsnJ0feXUdB=CJ>Fv +zr&_=Q6YubieL}zoiJ0a+c+(bGwFN5g1pz;^rGP1sM+lHB@UAPM2&F=RB&yv@$caXF +ze~Io&3CQe=cMHr!e{yiokd?~p&F&k`jg99Ex7}WO=$8*Kx8wXv4eSa_CJqKVkyRr& +zCdcqs*@M5!gD84e@fW{|5B#mDGTH;JFw`h^stQcTjf@V3pNe8&f$=NG?-+klRGea* +zX1vOHi}4@EM~qJyfuM>e#%9J&Mjzt`j5OnB#;uGZ<1WTMj3vgSj3*esXZY{I`KqUa +zfbB~~a>piTMAVDNyHR<{<v-=}gXhE(15|emxueb8Kv%5>0{F7}8pool{7_h6u?7yg +zlyNm>-Eq_&WjW{0$9ZHq6x?~W8l2#1g0CyrtN#R-nbWG(?>iNG1zRiZgj;Lm_%rVe +zwZ6i{g#sR5xudpbj~5H9TNIQ3gMikIG@l(Z4IR@^2|Vu|LZteLF5@$KH5`Pr&3_vn +z^!Fn27&z6hSPR+*;D*&lm-)OE=ZgjK*(X&XdBq7RDUd7>|Lou?UMNg6lVCB;TPz{Z +zN4-~p*Rr=uq8OYdlAy38{}dt5%2}aUax{}zWzDRgmsn2|!)=Bp)U35;Ld3H+Ye=*_ +z4S&0{5*TVI!OU-SWz$XUwrrnb%9?NHau^uhn>&;%&X#8O7mt)SIJr8D$u?NS=rUW6 +zCmnxV&FgUDAWX}gZ+1AH&-C4Q=3sl5RX9=OWPfCtcRZi4tkX44YYfRH*@?H7T=Kz= +zG*i-wU2jbJMK%ChTMTXZFJEm~k;KCj*D60g=j!2ns8Q`g%jSRK^?=IwL^|I5-K2zH +z8*A0-mL%Q`R#xatM^u^E=IrX+2&bc;3rv!NipS^G*6zlIRAV(JJDU($OBHuptd&1( +zoNu>t*Q}|siS8#MYavR6j7&(~AEL#OaV(^+gy>YrSPiLfgy{2-p=xT2Mtd}4R8#XB +z-LDysYw8J&{-GJKYwEiif07x7u5QsOr5oeA`ZJxDb>p|XdQzvCb>nSaeP1UfY_x~f +z9bwuRHf|5Ahr{&iu<>+QeI`t=g^e>|^=z1;5o23K?TP5uo%2>aXQWCKr#dH;Qr0*j +z3LecKKarw5`Xblzd$&H4oP%y&l3egyUc<=<Azs)*u}X^*n$F~s2O<-paSF?q*HB+n +zqBfj5;J|x@hM`M(QD20jrkwi8`y3l;8qO;#l8A#CMI8Kg9E{ERsT>TGXaGC^5Cz)J +z4?eb?Kub*nWYdmhV-4?j<o}k#pt-{wK;b3U(B^+`s7-`HYOZOxv<+RG^LulAxKL|9 +z3NH#9{Lg*7U1&gy<zHSG$;LMHby+V=ENlGFVLKjt%kkph7kP1M8|vebT=K5)*E>JW +zjd{Tu*o*CE*QO)}{_J>haU5zn+1QJ^eBg|d5n5-%|DwS@1+<Mtvat=iZ3BF??pZXh +zth4PnnWL*s%}k43fbe34>yaZ_2@Kj<UGt)`2G5>K>)nIBR-xB@+1PQ2*c$lV?Z13o +zbX%CHpm`!1Z4$d28~9k{rfu-0w@xg6{q!u2{)Dm_))4RK$?#7P*t7V+g_9d<V!MD` +zaj`t-?uy6zsjzp<-IdM6g(XhQX2iF<+p?Kmw6?a+f^VMex*PuetNfqf+4_FpD%8TW +eZvUbDHC^NLu5~gtzg|!EqSkX2ep9pg!tpEeo1jDh + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c +new file mode 100644 +index 0000000000..ff83db095b +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <bootblock_common.h> ++#include <device/pci_ops.h> ++#include <ec/dell/mec5035/mec5035.h> ++#include <southbridge/intel/bd82x6x/pch.h> ++ ++void bootblock_mainboard_early_init(void) ++{ ++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN ++ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN ++ | COMB_LPC_EN | COMA_LPC_EN); ++ mec5035_early_init(); ++} +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c +new file mode 100644 +index 0000000000..777570765a +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c +@@ -0,0 +1,192 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_GPIO, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_NATIVE, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio1 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio28 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++ .gpio30 = GPIO_RESET_RSMRST, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio0 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++ .gpio13 = GPIO_INVERT, ++ .gpio14 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_GPIO, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_NATIVE, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_OUTPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio45 = GPIO_DIR_OUTPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_INPUT, ++ .gpio51 = GPIO_DIR_INPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio34 = GPIO_LEVEL_HIGH, ++ .gpio45 = GPIO_LEVEL_LOW, ++ .gpio60 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_GPIO, ++ .gpio69 = GPIO_MODE_GPIO, ++ .gpio70 = GPIO_MODE_GPIO, ++ .gpio71 = GPIO_MODE_GPIO, ++ .gpio72 = GPIO_MODE_NATIVE, ++ .gpio73 = GPIO_MODE_NATIVE, ++ .gpio74 = GPIO_MODE_NATIVE, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio68 = GPIO_DIR_INPUT, ++ .gpio69 = GPIO_DIR_INPUT, ++ .gpio70 = GPIO_DIR_INPUT, ++ .gpio71 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c +new file mode 100644 +index 0000000000..3ebccff81d +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ 0x111d76df, /* Codec Vendor / Device ID: IDT */ ++ 0x10280535, /* Subsystem ID */ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x10280535), ++ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), ++ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), ++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), ++ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), ++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), ++ ++ 0x80862806, /* Codec Vendor / Device ID: Intel */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(3, 0x80860101), ++ AZALIA_PIN_CFG(3, 0x05, 0x18560010), ++ AZALIA_PIN_CFG(3, 0x06, 0x18560020), ++ AZALIA_PIN_CFG(3, 0x07, 0x18560030), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb +new file mode 100644 +index 0000000000..8b9c82fba4 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb +@@ -0,0 +1,37 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/sandybridge ++ device domain 0 on ++ subsystemid 0x1028 0x0535 inherit ++ ++ device ref igd on ++ register "gpu_cpu_backlight" = "0x00000251" ++ register "gpu_pch_backlight" = "0x13121312" ++ end ++ ++ chip southbridge/intel/bd82x6x ++ register "usb_port_config" = "{ ++ { 1, 1, 0 }, ++ { 1, 1, 0 }, ++ { 1, 1, 1 }, ++ { 1, 1, 1 }, ++ { 1, 1, 2 }, ++ { 1, 1, 2 }, ++ { 1, 0, 3 }, ++ { 1, 1, 3 }, ++ { 1, 1, 4 }, ++ { 1, 1, 4 }, ++ { 1, 1, 5 }, ++ { 1, 1, 5 }, ++ { 1, 2, 6 }, ++ { 1, 2, 6 }, ++ }" ++ ++ device ref xhci on ++ register "superspeed_capable_ports" = "0x0000000f" ++ register "xhci_overcurrent_mapping" = "0x00000c03" ++ register "xhci_switchable_ports" = "0x0000000f" ++ end ++ end ++ end ++end +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0019-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch b/config/coreboot/default/patches/0019-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch new file mode 100644 index 00000000..97055b7c --- /dev/null +++ b/config/coreboot/default/patches/0019-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch @@ -0,0 +1,430 @@ +From 9b0766b86ac010b7edfe27d1f7edbb3f27dc742e Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Wed, 31 Jan 2024 22:57:07 -0700 +Subject: [PATCH 19/39] mb/dell: Add Latitude E5530 (Ivy Bridge) + +Mainboard is QXW10/LA-7902P (UMA). I do not physically have this board; +someone with physical access to one sent me the output of autoport which +I then modified to produce this port. I was also sent the VBT binary, +which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running +version A21 of the vendor firmware. + +This was originally tested and found to be working as a standalone board +port in Libreboot, but this variant based port in upstream coreboot has +not been tested. + +This can be internally flashed by sending a command to the EC, which +causes the EC to pull the FDO pin low and the firmware to skip setting +up any chipset based write protections [1]. The EC is the SMSC MEC5055, +which seems to be compatible with the existing MEC5035 code. + +Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/snb_ivb_latitude/Kconfig | 7 + + .../dell/snb_ivb_latitude/Kconfig.name | 3 + + .../snb_ivb_latitude/variants/e5530/data.vbt | Bin 0 -> 6144 bytes + .../variants/e5530/early_init.c | 14 ++ + .../snb_ivb_latitude/variants/e5530/gpio.c | 194 ++++++++++++++++++ + .../variants/e5530/hda_verb.c | 32 +++ + .../variants/e5530/overridetree.cb | 39 ++++ + 7 files changed, 289 insertions(+) + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb + +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig +index 03377275f0..183a67bec3 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig +@@ -17,6 +17,11 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + ++config BOARD_DELL_LATITUDE_E5530 ++ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON ++ select BOARD_ROMSIZE_KB_12288 ++ select SOUTHBRIDGE_INTEL_C216 ++ + config BOARD_DELL_LATITUDE_E6430 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_12288 +@@ -38,6 +43,7 @@ config MAINBOARD_DIR + default "dell/snb_ivb_latitude" + + config MAINBOARD_PART_NUMBER ++ default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530 + default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430 + default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530 + +@@ -48,6 +54,7 @@ config USBDEBUG_HCD_INDEX + default 2 + + config VARIANT_DIR ++ default "e5530" if BOARD_DELL_LATITUDE_E5530 + default "e6430" if BOARD_DELL_LATITUDE_E6430 + default "e6530" if BOARD_DELL_LATITUDE_E6530 + +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +index d89185d670..c15ef4028f 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +@@ -1,5 +1,8 @@ + ## SPDX-License-Identifier: GPL-2.0-only + ++config BOARD_DELL_LATITUDE_E5530 ++ bool "Latitude E5530" ++ + config BOARD_DELL_LATITUDE_E6430 + bool "Latitude E6430" + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..3c54b70be7856a6420d001112d7f17f8bab46ed3 +GIT binary patch +literal 6144 +zcmeHKU2Gdg5dO}0w$JA~+qs02q)iz56C9e5vuQ#oL0l3O+%|395Q2peO{y4(2uX0t +zuMja1N)bPb1cE+5)fYsCK!89MFQAGChyWpk5PuR<K|G+sLmxmOR4}u5=Rg`mj70g7 +zvgdDic6N4dW^QKhynd)>kS^cR)3#-(r*-?zo-O^C(kLvv8XM<+Y3tdt^YY!P?!oTe +zJ^ed-x6w0Lh5fN#jsv5TWE#mtd*_yky}9xDK(kOwLt+C7_AQAd#iwr=o0`gvQZ`{x +z6ZeT`x^^;8+a~jSa^o~PF@8J6N5;o#dhCwebaM;!_oisw1#O9K={qQM<@Oeu$lXeN +z#wJGcW4Y<2)-A{Bot(NoKX%>qdnw-AOi9bKT9Z~HL5|7PJDHz4kGlEx143q+26EH6 +z{4KfB^9;?<fTOaiNPy%=@LovL&q<^d1Qdi+Xex9SvIM^ZLq%9cP{A1rE>#dw(WfA; +zBCR3@pCS1a;A|CZW1h7H*l#mW{%y{bf)9ofiz!EHzyiac@{RpMzz>O-<~{hx5tw%b +z3ZJWD4_g-`iF`tUJb}+Vfe;XI1T2Y4_Y!iVk<<T4ce(^PWKh<?N^a`t+}vgNr25iZ +z`!fTBL)ojYF5G?3y|eW=`9>MLB9et&!A7LDDE7&5ye#|hn%s#IWgagDEPNHHMUhb- +ztc9t?uz{bD#kh#kpsE;AO-wWHV?4olPStRPag^~k<737bjBgm<GlC%vRgBe)4U9I% +zg^XUtcE**A5ylOSn;A2V2N;hso?--U#>t|ufS}_`LGs2bcSKCVBh4s0>G7ZR_@NWx +zkph}GhP}~YR?roT!61GqzQ?gBsuv3jY}UXbmr|alv^VxUqbz5<`5=!hhpaa*7DK~4 +zP4ad6dhH!>nYpc4{J&G-w{UiWo$zXnTz{tAq0|?c_`QJ7pKmCwIpe7Uix$P?9}v*1 +z(aVR6OkMkQ6oM}*UC@j78!~>7=OZCVYXeu|u0SiI4}w$uw6&0P09LF%Hp}O&IA3gl +z4@ap0NfAe+q(ZVm{Bwe*Do~kbCc$Q!x7b3Sk9tLgVmsR<Q4H=9Nl;mmf2xpY<*d*- +z`yI_BR#`La=Oxxt#qgS`3pER^nh^CZ%*qlq2N9@uSAtz-C7AhduB_U|{>#oOrY`tq +z%|?L!zRd2-$V6^@$H<Mj3MXf#F<J+^8%<X2{tnmQTI*aK*ageBrm9^|<Ked3j_s;% +zva<(Dob)BOwdcj8Z67UhYUAjbk==Of9W#D7k!DJobLx$$fXD_wuZyD&Kk-$EIY~S` +zan1ANbFUW8hZ0pUw5)y??*}!;chdgq|0X5;s;m`@YdY{zs4z#z8e;13T6b4tC7gy$ +zTwszEQhk0!U$`3=Qi)ZbY^*|bAyvF>@ml^iaX;uzoVB3JA(|h9tcNKXHdA43N0|18 +z&3$2QE=)(l=6qQDAWT1oO-<KoblR+&{kk@!)1A8ch^`&b>2=+FU)Mg<35IDJ+8Tp; +z40F)Xt}$rVFdsLxLk7KRn4cKhmj<a3vp%A&kI>eLd38j)HbM_Y%!3i_aD?8An8za8 +z@d(AD=Gv&%5;e{}p%i?_q(T*^IwzEx*Eu1wKHV9=lVUvjqv!B@cWER!2fe%`IqO?q +z!=Wf4kzGUaLX8`m#*P^uL?%M#6qc9Qu(YT|ZMb#7UzCc_(DkQYEG<G&Q*QkX`CS`I +z8cwQnl8A#CMH~W79L&{2*Jof_MD5t{bPTAszWUa20yPzD=*wW8)wHSu?avDhffu^! +zL>Q#%k_O0@^DN5S@MXi$D;acJ>#cTV-(U@Offv4ACp4hO4$Ll!WO)s3P4=t9vpWBC +zSckhlcD?xUuX=Gx96Dx{IsQ23r&;o1*+^Cp2RA3nd$A-RIHP2Q7uitC>c67FIR*5} +zB3a%B!?6K=TJ$W+SJv@*9Lms{mTvWmU4Zanj_Z*lSqOGISzYp?yawOqLhVhRt#-E6 +zd)YW~h&meh-5prIE}Cr&7f?MMi&cqTt_^%Fa?>k(=`9jVoIf@}{g+WX#TpWuc+!2v +zPG^>A|NZ2GlGsKdGqN{7>Fr7+Hc_^3z}uBhC4?nzOQ*!QyVugGjkK_~$bvtfY`h79 +z9rOI3;Mt}9)_G{zXTAPw`8T@6=Ut0r9R5;0#Zy|#8F;v4^UAmqft3iXL|`QXD-l?U +Jz~2*rUjdP?m;3+# + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c +new file mode 100644 +index 0000000000..ff83db095b +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <bootblock_common.h> ++#include <device/pci_ops.h> ++#include <ec/dell/mec5035/mec5035.h> ++#include <southbridge/intel/bd82x6x/pch.h> ++ ++void bootblock_mainboard_early_init(void) ++{ ++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN ++ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN ++ | COMB_LPC_EN | COMA_LPC_EN); ++ mec5035_early_init(); ++} +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c +new file mode 100644 +index 0000000000..0599f13921 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c +@@ -0,0 +1,194 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_GPIO, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_GPIO, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_NATIVE, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio1 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio12 = GPIO_DIR_OUTPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio12 = GPIO_LEVEL_HIGH, ++ .gpio28 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++ .gpio30 = GPIO_RESET_RSMRST, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio0 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++ .gpio13 = GPIO_INVERT, ++ .gpio14 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_GPIO, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_GPIO, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_NATIVE, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio45 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_INPUT, ++ .gpio51 = GPIO_DIR_INPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio53 = GPIO_DIR_INPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio60 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_GPIO, ++ .gpio69 = GPIO_MODE_GPIO, ++ .gpio70 = GPIO_MODE_GPIO, ++ .gpio71 = GPIO_MODE_GPIO, ++ .gpio72 = GPIO_MODE_NATIVE, ++ .gpio73 = GPIO_MODE_NATIVE, ++ .gpio74 = GPIO_MODE_GPIO, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio68 = GPIO_DIR_INPUT, ++ .gpio69 = GPIO_DIR_INPUT, ++ .gpio70 = GPIO_DIR_INPUT, ++ .gpio71 = GPIO_DIR_INPUT, ++ .gpio74 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c +new file mode 100644 +index 0000000000..3e89a6d75f +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ 0x111d76df, /* Codec Vendor / Device ID: IDT */ ++ 0x1028053d, /* Subsystem ID */ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x1028053d), ++ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), ++ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), ++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), ++ AZALIA_PIN_CFG(0, 0x11, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x20, 0xd5a301a0), ++ ++ 0x80862806, /* Codec Vendor / Device ID: Intel */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(3, 0x80860101), ++ AZALIA_PIN_CFG(3, 0x05, 0x18560010), ++ AZALIA_PIN_CFG(3, 0x06, 0x18560020), ++ AZALIA_PIN_CFG(3, 0x07, 0x18560030), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb +new file mode 100644 +index 0000000000..85c448d010 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb +@@ -0,0 +1,39 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/sandybridge ++ device domain 0 on ++ subsystemid 0x1028 0x053d inherit ++ ++ device ref igd on ++ register "gpu_cpu_backlight" = "0x00000000" ++ register "gpu_pch_backlight" = "0x03d003d0" ++ end ++ ++ chip southbridge/intel/bd82x6x ++ register "usb_port_config" = "{ ++ { 1, 1, 0 }, ++ { 1, 1, 0 }, ++ { 1, 1, 1 }, ++ { 1, 1, 1 }, ++ { 1, 1, 2 }, ++ { 1, 1, 2 }, ++ { 1, 1, 3 }, ++ { 1, 0, 3 }, ++ { 1, 2, 4 }, ++ { 1, 1, 4 }, ++ { 1, 1, 5 }, ++ { 1, 1, 5 }, ++ { 1, 0, 6 }, ++ { 1, 1, 6 }, ++ }" ++ ++ device ref xhci on ++ register "superspeed_capable_ports" = "0x0000000f" ++ register "xhci_overcurrent_mapping" = "0x00000c03" ++ register "xhci_switchable_ports" = "0x0000000f" ++ end ++ device ref gbe off end ++ device ref pcie_rp7 on end # BCM5761 Ethernet ++ end ++ end ++end +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch b/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch new file mode 100644 index 00000000..2f6629b2 --- /dev/null +++ b/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch @@ -0,0 +1,435 @@ +From 5d8a651a71d19918130f58c637700539dd320789 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Sun, 26 Nov 2023 17:08:52 -0700 +Subject: [PATCH 20/39] mb/dell: Add Latitude E6420 (Sandy Bridge) + +Mainboard is PAL50/LA-6591P (UMA). The version with an Nvidia dGPU was +not tested. I do not physically have this system; someone with physical +access to one sent me the output of autoport which I then modified to +produce this port. I was also sent the VBT binary, which was obtained +from `/sys/kernel/debug/dri/0/i915_vbt` while running version A25 of the +vendor firmware. + +This was originally tested and found to be working as a standalone board +port in Libreboot, but this variant based port in upstream coreboot has +not been tested. + +This can be internally flashed by sending a command to the EC, which +causes the EC to pull the FDO pin low and the firmware to skip setting +up any chipset based write protections [1]. The EC is the SMSC MEC5055, +which seems to be compatible with the existing MEC5035 code. + +[1] https://gitlab.com/nic3-14159/dell-flash-unlock + +Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/snb_ivb_latitude/Kconfig | 13 +- + .../dell/snb_ivb_latitude/Kconfig.name | 3 + + .../snb_ivb_latitude/variants/e6420/data.vbt | Bin 0 -> 6144 bytes + .../variants/e6420/early_init.c | 14 ++ + .../snb_ivb_latitude/variants/e6420/gpio.c | 191 ++++++++++++++++++ + .../variants/e6420/hda_verb.c | 32 +++ + .../variants/e6420/overridetree.cb | 35 ++++ + 7 files changed, 287 insertions(+), 1 deletion(-) + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb + +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig +index 183a67bec3..d2786970ee 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig +@@ -17,6 +17,12 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + ++config BOARD_DELL_LATITUDE_E6420 ++ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON ++ select BOARD_ROMSIZE_KB_10240 ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select SOUTHBRIDGE_INTEL_BD82X6X ++ + config BOARD_DELL_LATITUDE_E5530 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_12288 +@@ -43,6 +49,7 @@ config MAINBOARD_DIR + default "dell/snb_ivb_latitude" + + config MAINBOARD_PART_NUMBER ++ default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 + default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530 + default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430 + default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530 +@@ -54,11 +61,15 @@ config USBDEBUG_HCD_INDEX + default 2 + + config VARIANT_DIR ++ default "e6420" if BOARD_DELL_LATITUDE_E6420 + default "e5530" if BOARD_DELL_LATITUDE_E5530 + default "e6430" if BOARD_DELL_LATITUDE_E6430 + default "e6530" if BOARD_DELL_LATITUDE_E6530 + + config VGA_BIOS_ID +- default "8086,0166" ++ default "8086,0166" if BOARD_DELL_LATITUDE_E5530 ++ default "8086,0126" if BOARD_DELL_LATITUDE_E6420 ++ default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \ ++ || BOARD_DELL_LATITUDE_E6530 + + endif +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +index c15ef4028f..257d428a70 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +@@ -1,5 +1,8 @@ + ## SPDX-License-Identifier: GPL-2.0-only + ++config BOARD_DELL_LATITUDE_E6420 ++ bool "Latitude E6420" ++ + config BOARD_DELL_LATITUDE_E5530 + bool "Latitude E5530" + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..d3662eea1bc78b60be6d0bd2cc38bb46b654afbd +GIT binary patch +literal 6144 +zcmeHKeQZ-z6hE);wSBvNZ|mO1=*HLC2BQN8uVX6{N9eY)75ORymb$R8!YYuAZEgeE +zKk|S@Fen*n41W-viAF;r%)~^EkpLz-B{2q##)LmGAtoY;7*Qhv_1yPbw$TC$2}G0K +z=6Ao&x#ym9?z!i_&TOh(kLzky2cN8MTpny#R<;VU4Rkn?rBIz(YL~BBw<%b&zGhSH +z$~AQ>@D0d=Xx6RE0BwSxspWdrW9y<FZGD@&x3_JL;p$p!;!BVdcKLkht0=-%(Jj&T +z_GkyztZ%>#t7^)^(T-R<7W?O6ZTI%A+j=`<Jw3Q%dk6N!da<_?7oyiU3)^<~_TiSk +zE$y+=RK3PGQ`gzmXYPRBx>C|f*UP9{h|4>ANrAe~?ymV*)83AaT#FuTjP=C2cg5P~ +zt4w78r$t#300cWY_k)mevmAmFI3&oBfytoAAPQiYK$XEIgHwV@5-gJ-Q-*p8yfTDj +zaDz=1Y!X1B3`OpQ&Ik}bM|0xHn0gYNZw0rT=7AXS2in-q8K^?)0|el+Z6geW7i7MM +zv~!|>HqL-|Fk}EYOa@)R<X)VQ7c}d8R1b@RTn5rq(90|QRg0?wwZZz(6Dz}w>zg9Y +z8;!mD_V*XSjT33~$`o`s>zEGBq8AQ`HaH?y!Fh2QiX1v@aCo4LaENf&DZ_cE2A2qb +z5@cC}X)=S^1RvpXLWs~v*hqMau$!=t@B-mg!XV)|;eEm>!Z6`H;R4|&!d1d`f|S7^ +zli+B98*!TfPE&6~NVM5j3v{N3OTjpnm_L@BPh(}esd(J!gj?~iJP?n|OZZOiTqlql +zg<NWR@g&-*W-E%A7|*1Z_`sVO$K&iAP+VIj9{<1hT%SXsK}IBk8!daftR`6-)EUiS +zvv*HR(#-ZwhA~7wcmxbe4%E?Y7P0y{1q|nqR1L29UR8v@#No^g5MH)7!>{%-$T|cR +zZx5|xm>Fl>;@$m};P{0WC>O~<Nl1`*PLgPN_hP2a^h+L$ls&SYrkDYr+&l*%%S?^Q +ziPSdtHE<LNEnr7cs=ihL-C>-p>*$9CpHRLgN|POkqD^UP4nw|4nf0bc8MOBk<;%js +zfpCAWNzqSPlz@X%j9CGrwZDKUl@K{g6pzqiIIARDQ)#@^RW&0pmNG;XZ?!SlHB?L# +zKRAMgq(R;aQd%@Gy38-LS@ix)fR**(P3B9wI=Uk^&cWmmwB<vf21<0#LBA!;qtAh( +zYe5g_T{+gw^mi8QzPPraBoH~8oCz%r=$nVi1A)`Y8IKqIdqm6MihqxtpFaTggaPxu +zQP07nf#&kPkPp}Cmk$F1g7q7QK;kz~80i&oDN}~wYbPUI6AtG5H+$T!@f5FzUhp21 +z^XiPT3rb%B@sA9g!n88R7BOsLS|?+D3}0v3dyIX|@JFWo&e%<c#V)PV#g@7-=F*;V +zvAr&Q+ogTvVxPM3XP5Smi`f;Nt7uCU)}Y`HMcbpW=M_AuXlE35PQl+4O{7m66&I@7 +zGL@}Sai^*sP}va`KTx$VRQ8REf2*1+lTFH0=UkNx+eN|1rVyipl)Du=h=@%w+iQZG +zT6@-PdW^oyFb44AG`HMZWEnP{&OQ+jC`N4emoS)x;EPN}uaSFOf-Mn8JRRO<WJc +zn6%=L94~PR)%Ua_HTZcfTXD<p{%8p|<N<;Efw$Zb4$}{m8@7c((~<7^thaau&@Wx# +zVGNL)lmH@{o=h*{muXGc!;nXrVgpp3;1V1stMj=4AtxyzX+?SoB~zN}!*r?9Qvs1P +zmV_(CTmt0sY&6=F=_M>E34GYvuh1uQF+BUdWyQC5SaEM1QvKlHBMs13C}n{0SwRxW +ziekMa&kvRFruRcKCevGy5)TxUBDlur@E{TtQ^NQ>nO+Cgl)&Ga(PxqVW?e3TLH-UY +zdL3T{z^xdd`$(STFUb8R*cKa}r>n{Wk+MXRH~o-hN}#9OF*>T#>rfhiRs(Wc-R^9@ +z%F=<}dn(E}ADc03zJ>JvZe;_8f+WFLL4%qNYs`_aa`a$Pl5H;iO^Wt*cP3W(d=(g} +zZ%nKT1$|r-tAv8($u2-BI2Uiz#%OT&!Q3b~Ru2P2j;Gem!@wfPsTR%J>W{8z)oq^J +k^Qm&?O@bFkw4CTocwoW<6CRlGz=Q`TJTT#bN9KWl0rH4|j{pDw + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c +new file mode 100644 +index 0000000000..ff83db095b +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <bootblock_common.h> ++#include <device/pci_ops.h> ++#include <ec/dell/mec5035/mec5035.h> ++#include <southbridge/intel/bd82x6x/pch.h> ++ ++void bootblock_mainboard_early_init(void) ++{ ++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN ++ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN ++ | COMB_LPC_EN | COMA_LPC_EN); ++ mec5035_early_init(); ++} +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c +new file mode 100644 +index 0000000000..943c743f48 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c +@@ -0,0 +1,191 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_NATIVE, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_INPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_OUTPUT, ++ .gpio31 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio30 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio0 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++ .gpio14 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_GPIO, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_NATIVE, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_OUTPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio45 = GPIO_DIR_OUTPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio51 = GPIO_DIR_INPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio34 = GPIO_LEVEL_HIGH, ++ .gpio45 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_LOW, ++ .gpio60 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_GPIO, ++ .gpio69 = GPIO_MODE_GPIO, ++ .gpio70 = GPIO_MODE_GPIO, ++ .gpio71 = GPIO_MODE_GPIO, ++ .gpio72 = GPIO_MODE_NATIVE, ++ .gpio73 = GPIO_MODE_NATIVE, ++ .gpio74 = GPIO_MODE_NATIVE, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio68 = GPIO_DIR_INPUT, ++ .gpio69 = GPIO_DIR_INPUT, ++ .gpio70 = GPIO_DIR_INPUT, ++ .gpio71 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c +new file mode 100644 +index 0000000000..ede8445aaf +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ 0x111d76e7, /* Codec Vendor / Device ID: IDT */ ++ 0x10280493, /* Subsystem ID */ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x10280493), ++ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), ++ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), ++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), ++ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), ++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), ++ ++ 0x80862805, /* Codec Vendor / Device ID: Intel */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(3, 0x80860101), ++ AZALIA_PIN_CFG(3, 0x05, 0x18560010), ++ AZALIA_PIN_CFG(3, 0x06, 0x18560020), ++ AZALIA_PIN_CFG(3, 0x07, 0x18560030), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb +new file mode 100644 +index 0000000000..3012a3177f +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb +@@ -0,0 +1,35 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/sandybridge ++ device domain 0 on ++ subsystemid 0x1028 0x0493 inherit ++ ++ device ref igd on ++ register "gpu_cpu_backlight" = "0x0000054f" ++ register "gpu_pch_backlight" = "0x13121312" ++ end ++ ++ chip southbridge/intel/bd82x6x ++ register "usb_port_config" = "{ ++ { 1, 1, 0 }, ++ { 1, 1, 0 }, ++ { 1, 1, 1 }, ++ { 1, 1, 1 }, ++ { 1, 0, 2 }, ++ { 1, 1, 2 }, ++ { 1, 1, 3 }, ++ { 1, 1, 3 }, ++ { 1, 1, 5 }, ++ { 1, 1, 5 }, ++ { 1, 1, 7 }, ++ { 1, 1, 6 }, ++ { 1, 0, 6 }, ++ { 1, 0, 7 }, ++ }" ++ ++ device ref sata1 on ++ register "sata_port_map" = "0x3b" ++ end ++ end ++ end ++end +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch b/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch deleted file mode 100644 index fecaf88a..00000000 --- a/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch +++ /dev/null @@ -1,826 +0,0 @@ -From a49df0307455d6d8b7a9efb9f4639b72be1b64d4 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Sat, 19 Aug 2023 16:19:10 -0600 -Subject: [PATCH 20/30] mb/dell: Add Latitude E6430 (Ivy Bridge) - -Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested. This -is based on the autoport output with some manual tweaks. The flash is -8MiB + 4MiB, and is fairly easily accessed by removing the keyboard. It -can also be internally flashed by sending a command to the EC, which -causes the EC to pull the FDO pin low and the firmware to skip setting -up any chipset based write protections [1]. The EC is the SMSC MEC5055, -which seems to be compatible with the existing MEC5035 code. - -Working: -- Libgfxinit -- USB EHCI debug (left side usb port is HCD index 2, middle port on the - right side is HCD index 1) -- Keyboard -- Touchpad/trackpoint -- ExpressCard -- Audio -- Ethernet -- SD card reader -- mPCIe WiFi -- SeaBIOS 1.16.2 -- edk2 (MrChromebox' fork, uefipayload_202306) -- Internal flashing using dell-flash-unlock - -Not working: -- S3 suspend: Possibly EC related -- Physical wireless switch - this triggers an SMI handler in the vendor - firmware which sends commands to the EC to enable/disable wireless - devices -- Battery reporting - needs ACPI code for the EC -- Brightness hotkeys - probably EC related - -Unknown/untested: -- Dock -- eSATA -- TPM -- dGPU on non-UMA model -- Bluetooth module (not included on my system) - -[1] https://gitlab.com/nic3-14159/dell-flash-unlock - -Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 -Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> ---- - src/mainboard/dell/e6430/Kconfig | 44 +++++ - src/mainboard/dell/e6430/Kconfig.name | 2 + - src/mainboard/dell/e6430/Makefile.inc | 6 + - src/mainboard/dell/e6430/acpi/ec.asl | 9 + - src/mainboard/dell/e6430/acpi/platform.asl | 12 ++ - src/mainboard/dell/e6430/acpi/superio.asl | 3 + - src/mainboard/dell/e6430/acpi_tables.c | 16 ++ - src/mainboard/dell/e6430/board_info.txt | 6 + - src/mainboard/dell/e6430/cmos.default | 9 + - src/mainboard/dell/e6430/cmos.layout | 88 ++++++++++ - src/mainboard/dell/e6430/data.vbt | Bin 0 -> 6144 bytes - src/mainboard/dell/e6430/devicetree.cb | 70 ++++++++ - src/mainboard/dell/e6430/dsdt.asl | 30 ++++ - src/mainboard/dell/e6430/early_init.c | 32 ++++ - src/mainboard/dell/e6430/gma-mainboard.ads | 20 +++ - src/mainboard/dell/e6430/gpio.c | 192 +++++++++++++++++++++ - src/mainboard/dell/e6430/hda_verb.c | 33 ++++ - src/mainboard/dell/e6430/mainboard.c | 21 +++ - 18 files changed, 593 insertions(+) - create mode 100644 src/mainboard/dell/e6430/Kconfig - create mode 100644 src/mainboard/dell/e6430/Kconfig.name - create mode 100644 src/mainboard/dell/e6430/Makefile.inc - create mode 100644 src/mainboard/dell/e6430/acpi/ec.asl - create mode 100644 src/mainboard/dell/e6430/acpi/platform.asl - create mode 100644 src/mainboard/dell/e6430/acpi/superio.asl - create mode 100644 src/mainboard/dell/e6430/acpi_tables.c - create mode 100644 src/mainboard/dell/e6430/board_info.txt - create mode 100644 src/mainboard/dell/e6430/cmos.default - create mode 100644 src/mainboard/dell/e6430/cmos.layout - create mode 100644 src/mainboard/dell/e6430/data.vbt - create mode 100644 src/mainboard/dell/e6430/devicetree.cb - create mode 100644 src/mainboard/dell/e6430/dsdt.asl - create mode 100644 src/mainboard/dell/e6430/early_init.c - create mode 100644 src/mainboard/dell/e6430/gma-mainboard.ads - create mode 100644 src/mainboard/dell/e6430/gpio.c - create mode 100644 src/mainboard/dell/e6430/hda_verb.c - create mode 100644 src/mainboard/dell/e6430/mainboard.c - -diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig -new file mode 100644 -index 0000000000..e4c799803e ---- /dev/null -+++ b/src/mainboard/dell/e6430/Kconfig -@@ -0,0 +1,44 @@ -+if BOARD_DELL_LATITUDE_E6430 -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ select BOARD_ROMSIZE_KB_12288 -+ select EC_ACPI -+ select EC_DELL_MEC5035 -+ select GFX_GMA_PANEL_1_ON_LVDS -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ select INTEL_GMA_HAVE_VBT -+ select INTEL_INT15 -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_USES_IFD_GBE_REGION -+ select NORTHBRIDGE_INTEL_SANDYBRIDGE -+ select SERIRQ_CONTINUOUS_MODE -+ select SOUTHBRIDGE_INTEL_C216 -+ select SYSTEM_TYPE_LAPTOP -+ select USE_NATIVE_RAMINIT -+ -+config DRAM_RESET_GATE_GPIO -+ default 60 -+ -+config MAINBOARD_DIR -+ default "dell/e6430" -+ -+config MAINBOARD_PART_NUMBER -+ default "Latitude E6430" -+ -+config PS2K_EISAID -+ default "PNP0303" -+ -+config PS2M_EISAID -+ default "PNP0F13" -+ -+config USBDEBUG_HCD_INDEX -+ default 2 -+ -+config VGA_BIOS_ID -+ default "8086,0166" -+ -+endif -diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name -new file mode 100644 -index 0000000000..f866b03585 ---- /dev/null -+++ b/src/mainboard/dell/e6430/Kconfig.name -@@ -0,0 +1,2 @@ -+config BOARD_DELL_LATITUDE_E6430 -+ bool "Latitude E6430" -diff --git a/src/mainboard/dell/e6430/Makefile.inc b/src/mainboard/dell/e6430/Makefile.inc -new file mode 100644 -index 0000000000..ba64e93eb8 ---- /dev/null -+++ b/src/mainboard/dell/e6430/Makefile.inc -@@ -0,0 +1,6 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+bootblock-y += early_init.c -+bootblock-y += gpio.c -+romstage-y += early_init.c -+romstage-y += gpio.c -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -diff --git a/src/mainboard/dell/e6430/acpi/ec.asl b/src/mainboard/dell/e6430/acpi/ec.asl -new file mode 100644 -index 0000000000..0d429410a9 ---- /dev/null -+++ b/src/mainboard/dell/e6430/acpi/ec.asl -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Device(EC) -+{ -+ Name (_HID, EISAID("PNP0C09")) -+ Name (_UID, 0) -+ Name (_GPE, 16) -+/* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e6430/acpi/platform.asl b/src/mainboard/dell/e6430/acpi/platform.asl -new file mode 100644 -index 0000000000..2d24bbd9b9 ---- /dev/null -+++ b/src/mainboard/dell/e6430/acpi/platform.asl -@@ -0,0 +1,12 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Method(_WAK, 1) -+{ -+ /* FIXME: EC support */ -+ Return(Package() {0, 0}) -+} -+ -+Method(_PTS,1) -+{ -+ /* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e6430/acpi/superio.asl b/src/mainboard/dell/e6430/acpi/superio.asl -new file mode 100644 -index 0000000000..55b1db5b11 ---- /dev/null -+++ b/src/mainboard/dell/e6430/acpi/superio.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <drivers/pc80/pc/ps2_controller.asl> -diff --git a/src/mainboard/dell/e6430/acpi_tables.c b/src/mainboard/dell/e6430/acpi_tables.c -new file mode 100644 -index 0000000000..e2759659bf ---- /dev/null -+++ b/src/mainboard/dell/e6430/acpi_tables.c -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <acpi/acpi_gnvs.h> -+#include <soc/nvs.h> -+ -+/* FIXME: check this function. */ -+void mainboard_fill_gnvs(struct global_nvs *gnvs) -+{ -+ /* The lid is open by default. */ -+ gnvs->lids = 1; -+ -+ /* Temperature at which OS will shutdown */ -+ gnvs->tcrt = 100; -+ /* Temperature at which OS will throttle CPU */ -+ gnvs->tpsv = 90; -+} -diff --git a/src/mainboard/dell/e6430/board_info.txt b/src/mainboard/dell/e6430/board_info.txt -new file mode 100644 -index 0000000000..4601a4aaba ---- /dev/null -+++ b/src/mainboard/dell/e6430/board_info.txt -@@ -0,0 +1,6 @@ -+Category: laptop -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2012 -diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default -new file mode 100644 -index 0000000000..2a5b30f2b7 ---- /dev/null -+++ b/src/mainboard/dell/e6430/cmos.default -@@ -0,0 +1,9 @@ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -+nmi=Enable -+bluetooth=Enable -+wwan=Enable -+wlan=Enable -+sata_mode=AHCI -+me_state=Normal -diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout -new file mode 100644 -index 0000000000..1aa7e77bce ---- /dev/null -+++ b/src/mainboard/dell/e6430/cmos.layout -@@ -0,0 +1,88 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+#400 8 r 0 reserved for century byte -+ -+# coreboot config options: southbridge -+408 1 e 1 nmi -+409 2 e 7 power_on_after_fail -+411 1 e 9 sata_mode -+ -+# coreboot config options: EC -+412 1 e 1 bluetooth -+413 1 e 1 wwan -+414 1 e 1 wlan -+ -+# coreboot config options: ME -+424 1 e 14 me_state -+425 2 h 0 me_state_prev -+ -+# coreboot config options: northbridge -+432 3 e 11 gfx_uma_size -+435 2 e 12 hybrid_graphics_mode -+440 8 h 0 volume -+ -+# VBOOT -+448 128 r 0 vbnv -+ -+# SandyBridge MRC Scrambler Seed values -+896 32 r 0 mrc_scrambler_seed -+928 32 r 0 mrc_scrambler_seed_s3 -+960 16 r 0 mrc_scrambler_seed_chk -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+2 0 Enable -+2 1 Disable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+9 0 AHCI -+9 1 Compatible -+11 0 32M -+11 1 64M -+11 2 96M -+11 3 128M -+11 4 160M -+11 5 192M -+11 6 224M -+14 0 Normal -+14 1 Disabled -+ -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 447 984 -diff --git a/src/mainboard/dell/e6430/data.vbt b/src/mainboard/dell/e6430/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..08952c26ab82933ebb5cc5b9c7e2265963a87b2d -GIT binary patch -literal 6144 -zcmeHKU2Gdw7XHRFw#VZc+nI!tq)j-qG$b@>#vu)%WW~fb!7ZV6LkJc^+qlG~(WXgp -zLU)l?#Jhyj)dGqHf<6H13kV^8g;enZDm*~=5kd&@Cn1Fu52*0a2hgri!F%q^IFQ;) -zjkMh#DR=zcpL5Use9xJ4?#x^=mKdcQb|t!Zj3v6R-<{Yod<{*&!ppI%xUMXT9lLMX -zn;IM)+?yEQoxF~o#5x>}{dfwPkR;RSiC=!jj_JAlRQpJWpd}$VY+XtFX9|?cO&y#m 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-qS<b6g={WLAp3+&R^8(yo-t$_!=7BX2ta)I~18W{w^T5By1OEis_@J`@ - -literal 0 -HcmV?d00001 - -diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb -new file mode 100644 -index 0000000000..054b01c5ac ---- /dev/null -+++ b/src/mainboard/dell/e6430/devicetree.cb -@@ -0,0 +1,70 @@ -+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. -+ register "gfx" = "GMA_STATIC_DISPLAYS(1)" -+ register "gpu_cpu_backlight" = "0x00001312" -+ register "gpu_dp_b_hotplug" = "4" -+ register "gpu_dp_c_hotplug" = "4" -+ register "gpu_dp_d_hotplug" = "4" -+ register "gpu_panel_port_select" = "0" -+ register "gpu_panel_power_backlight_off_delay" = "2300" -+ register "gpu_panel_power_backlight_on_delay" = "2300" -+ register "gpu_panel_power_cycle_delay" = "6" -+ register "gpu_panel_power_down_delay" = "400" -+ register "gpu_panel_power_up_delay" = "400" -+ register "gpu_pch_backlight" = "0x13121312" -+ -+ register "spd_addresses" = "{0x50, 0, 0x52, 0}" -+ -+ device domain 0x0 on -+ subsystemid 0x1028 0x0534 inherit -+ -+ device ref host_bridge on end -+ device ref peg10 off end -+ device ref igd on end -+ -+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH -+ register "docking_supported" = "1" -+ register "gen1_dec" = "0x007c0681" -+ register "gen2_dec" = "0x005c0921" -+ register "gen3_dec" = "0x003c07e1" -+ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC -+ register "gpi0_routing" = "2" -+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }" -+ register "pcie_port_coalesce" = "1" -+ register "sata_interface_speed_support" = "0x3" -+ register "sata_port_map" = "0x33" -+ register "spi_lvscc" = "0x2005" -+ register "spi_uvscc" = "0x2005" -+ register "superspeed_capable_ports" = "0x0000000f" -+ register "xhci_overcurrent_mapping" = "0x00000c03" -+ register "xhci_switchable_ports" = "0x0000000f" -+ -+ device ref xhci on end -+ device ref mei1 on end -+ device ref mei2 off end -+ device ref me_ide_r off end -+ device ref me_kt on end -+ device ref gbe on end -+ device ref ehci2 on end -+ device ref hda on end -+ device ref pcie_rp1 on end # WWAN Slot -+ device ref pcie_rp2 on end # SLAN Slot -+ device ref pcie_rp3 on end # ExpressCard -+ device ref pcie_rp4 on end # E-Module (optical bay) -+ device ref pcie_rp5 on end # Extra Half Mini PCIe slot -+ device ref pcie_rp6 on end # SD/MMC Card Reader -+ device ref pcie_rp7 off end -+ device ref pcie_rp8 off end -+ device ref ehci1 on end -+ device ref pci_bridge off end -+ device ref lpc on -+ chip ec/dell/mec5035 -+ device pnp ff.0 on end -+ end -+ end -+ device ref sata1 on end -+ device ref smbus on end -+ device ref sata2 off end -+ device ref thermal off end -+ end -+ end -+end -diff --git a/src/mainboard/dell/e6430/dsdt.asl b/src/mainboard/dell/e6430/dsdt.asl -new file mode 100644 -index 0000000000..7d13c55b08 ---- /dev/null -+++ b/src/mainboard/dell/e6430/dsdt.asl -@@ -0,0 +1,30 @@ -+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+ -+#include <acpi/acpi.h> -+ -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20141018 /* OEM revision */ -+) -+{ -+ #include <acpi/dsdt_top.asl> -+ #include "acpi/platform.asl" -+ #include <cpu/intel/common/acpi/cpu.asl> -+ #include <southbridge/intel/common/acpi/platform.asl> -+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> -+ #include <southbridge/intel/common/acpi/sleepstates.asl> -+ -+ Device (\_SB.PCI0) -+ { -+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> -+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl> -+ #include <southbridge/intel/bd82x6x/acpi/pch.asl> -+ } -+} -diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c -new file mode 100644 -index 0000000000..d882c3d78b ---- /dev/null -+++ b/src/mainboard/dell/e6430/early_init.c -@@ -0,0 +1,32 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+ -+#include <bootblock_common.h> -+#include <device/pci_ops.h> -+#include <ec/dell/mec5035/mec5035.h> -+#include <southbridge/intel/bd82x6x/pch.h> -+ -+const struct southbridge_usb_port mainboard_usb_ports[] = { -+ { 1, 1, 0 }, -+ { 1, 1, 0 }, -+ { 1, 1, 1 }, -+ { 1, 1, 1 }, -+ { 1, 0, 2 }, -+ { 1, 1, 2 }, -+ { 1, 1, 3 }, -+ { 1, 1, 3 }, -+ { 1, 1, 4 }, -+ { 1, 1, 4 }, -+ { 1, 1, 5 }, -+ { 1, 1, 5 }, -+ { 1, 2, 6 }, -+ { 1, 2, 6 }, -+}; -+ -+void bootblock_mainboard_early_init(void) -+{ -+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN -+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN -+ | COMB_LPC_EN | COMA_LPC_EN); -+ mec5035_early_init(); -+} -diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads -new file mode 100644 -index 0000000000..1310830c8e ---- /dev/null -+++ b/src/mainboard/dell/e6430/gma-mainboard.ads -@@ -0,0 +1,20 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ ( -+ HDMI1, -- mainboard HDMI -+ DP2, -- dock DP -+ DP3, -- dock DP -+ Analog, --mainboard VGA -+ LVDS, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/e6430/gpio.c b/src/mainboard/dell/e6430/gpio.c -new file mode 100644 -index 0000000000..777570765a ---- /dev/null -+++ b/src/mainboard/dell/e6430/gpio.c -@@ -0,0 +1,192 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <southbridge/intel/common/gpio.h> -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_GPIO, -+ .gpio1 = GPIO_MODE_GPIO, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_NATIVE, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_GPIO, -+ .gpio8 = GPIO_MODE_GPIO, -+ .gpio9 = GPIO_MODE_NATIVE, -+ .gpio10 = GPIO_MODE_NATIVE, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_GPIO, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_GPIO, -+ .gpio18 = GPIO_MODE_NATIVE, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_NATIVE, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_NATIVE, -+ .gpio31 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio0 = GPIO_DIR_INPUT, -+ .gpio1 = GPIO_DIR_INPUT, -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio7 = GPIO_DIR_INPUT, -+ .gpio8 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio15 = GPIO_DIR_INPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio17 = GPIO_DIR_INPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_OUTPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio28 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_reset = { -+ .gpio30 = GPIO_RESET_RSMRST, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio0 = GPIO_INVERT, -+ .gpio8 = GPIO_INVERT, -+ .gpio13 = GPIO_INVERT, -+ .gpio14 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_NATIVE, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_GPIO, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_GPIO, -+ .gpio52 = GPIO_MODE_GPIO, -+ .gpio53 = GPIO_MODE_NATIVE, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_NATIVE, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_OUTPUT, -+ .gpio35 = GPIO_DIR_INPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio45 = GPIO_DIR_OUTPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_INPUT, -+ .gpio51 = GPIO_DIR_INPUT, -+ .gpio52 = GPIO_DIR_INPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio34 = GPIO_LEVEL_HIGH, -+ .gpio45 = GPIO_LEVEL_LOW, -+ .gpio60 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_reset = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_NATIVE, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_NATIVE, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_GPIO, -+ .gpio69 = GPIO_MODE_GPIO, -+ .gpio70 = GPIO_MODE_GPIO, -+ .gpio71 = GPIO_MODE_GPIO, -+ .gpio72 = GPIO_MODE_NATIVE, -+ .gpio73 = GPIO_MODE_NATIVE, -+ .gpio74 = GPIO_MODE_NATIVE, -+ .gpio75 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio68 = GPIO_DIR_INPUT, -+ .gpio69 = GPIO_DIR_INPUT, -+ .gpio70 = GPIO_DIR_INPUT, -+ .gpio71 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_reset = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ .reset = &pch_gpio_set1_reset, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ .reset = &pch_gpio_set2_reset, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ .reset = &pch_gpio_set3_reset, -+ }, -+}; -diff --git a/src/mainboard/dell/e6430/hda_verb.c b/src/mainboard/dell/e6430/hda_verb.c -new file mode 100644 -index 0000000000..56ada95c58 ---- /dev/null -+++ b/src/mainboard/dell/e6430/hda_verb.c -@@ -0,0 +1,33 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/azalia_device.h> -+ -+const u32 cim_verb_data[] = { -+ 0x111d76df, /* Codec Vendor / Device ID: IDT */ -+ 0x10280534, /* Subsystem ID */ -+ 11, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(0, 0x10280534), -+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), -+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), -+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), -+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), -+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), -+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), -+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), -+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), -+ -+ 0x80862806, /* Codec Vendor / Device ID: Intel */ -+ 0x80860101, /* Subsystem ID */ -+ 4, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(3, 0x80860101), -+ AZALIA_PIN_CFG(3, 0x05, 0x18560010), -+ AZALIA_PIN_CFG(3, 0x06, 0x18560020), -+ AZALIA_PIN_CFG(3, 0x07, 0x18560030), -+ -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/e6430/mainboard.c b/src/mainboard/dell/e6430/mainboard.c -new file mode 100644 -index 0000000000..31e49802fc ---- /dev/null -+++ b/src/mainboard/dell/e6430/mainboard.c -@@ -0,0 +1,21 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/device.h> -+#include <drivers/intel/gma/int15.h> -+#include <southbridge/intel/bd82x6x/pch.h> -+#include <ec/acpi/ec.h> -+#include <console/console.h> -+#include <pc80/keyboard.h> -+ -+static void mainboard_enable(struct device *dev) -+{ -+ -+ /* FIXME: fix these values. */ -+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, -+ GMA_INT15_PANEL_FIT_DEFAULT, -+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -+} -+ -+struct chip_operations mainboard_ops = { -+ .enable_dev = mainboard_enable, -+}; --- -2.39.2 - diff --git a/config/coreboot/default/patches/0021-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch b/config/coreboot/default/patches/0021-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch new file mode 100644 index 00000000..5d4139e8 --- /dev/null +++ b/config/coreboot/default/patches/0021-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch @@ -0,0 +1,449 @@ +From 1111dcab65ca83f175f1bb9c0496cae24fbfb7c2 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Wed, 31 Jan 2024 22:07:25 -0700 +Subject: [PATCH 21/39] mb/dell: Add Latitude E6520 (Sandy Bridge) + +Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was +not tested. I do not physically have this system; someone with physical +access to one sent me the output of autoport which I then modified to +produce this port. I was also sent the VBT binary, which was obtained +from `/sys/kernel/debug/dri/0/i915_vbt` while running version A08 of the +vendor firmware. + +This was originally tested and found to be working as a standalone board +port in Libreboot, but this variant based port in upstream coreboot has +not been tested. + +This can be internally flashed by sending a command to the EC, which +causes the EC to pull the FDO pin low and the firmware to skip setting +up any chipset based write protections [1]. The EC is the SMSC MEC5055, +which seems to be compatible with the existing MEC5035 code. + +[1] https://gitlab.com/nic3-14159/dell-flash-unlock + +Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/snb_ivb_latitude/Kconfig | 9 + + .../dell/snb_ivb_latitude/Kconfig.name | 3 + + .../snb_ivb_latitude/variants/e6520/data.vbt | Bin 0 -> 6144 bytes + .../variants/e6520/early_init.c | 31 +++ + .../snb_ivb_latitude/variants/e6520/gpio.c | 190 ++++++++++++++++++ + .../variants/e6520/hda_verb.c | 32 +++ + .../variants/e6520/overridetree.cb | 35 ++++ + 7 files changed, 300 insertions(+) + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb + +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig +index d2786970ee..72bdc96c0a 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig +@@ -23,6 +23,12 @@ config BOARD_DELL_LATITUDE_E6420 + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_BD82X6X + ++config BOARD_DELL_LATITUDE_E6520 ++ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON ++ select BOARD_ROMSIZE_KB_10240 ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select SOUTHBRIDGE_INTEL_BD82X6X ++ + config BOARD_DELL_LATITUDE_E5530 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_12288 +@@ -50,6 +56,7 @@ config MAINBOARD_DIR + + config MAINBOARD_PART_NUMBER + default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 ++ default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520 + default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530 + default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430 + default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530 +@@ -62,11 +69,13 @@ config USBDEBUG_HCD_INDEX + + config VARIANT_DIR + default "e6420" if BOARD_DELL_LATITUDE_E6420 ++ default "e6520" if BOARD_DELL_LATITUDE_E6520 + default "e5530" if BOARD_DELL_LATITUDE_E5530 + default "e6430" if BOARD_DELL_LATITUDE_E6430 + default "e6530" if BOARD_DELL_LATITUDE_E6530 + + config VGA_BIOS_ID ++ default "8086,0116" if BOARD_DELL_LATITUDE_E6520 + default "8086,0166" if BOARD_DELL_LATITUDE_E5530 + default "8086,0126" if BOARD_DELL_LATITUDE_E6420 + default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \ +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +index 257d428a70..c7665ac263 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +@@ -3,6 +3,9 @@ + config BOARD_DELL_LATITUDE_E6420 + bool "Latitude E6420" + ++config BOARD_DELL_LATITUDE_E6520 ++ bool "Latitude E6520" ++ + config BOARD_DELL_LATITUDE_E5530 + bool "Latitude E5530" + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..0ef16ee7cb482d2cb91ea80c3f419759355f7ba0 +GIT binary patch +literal 6144 +zcmeHKZ){Ul6hE);wSB#PZ|mL$bQ^!}HW(eF@H)0JafGfbqsZ9G21{L7Sg{or$5uN) +z_QgG55e!O(8p8*oBhhF`l$n^QF%rN;rzFNqqcPzFCd5QSB1Y7RKt1=pmTk1aFo9^Y +z+x+gi_nvdlJ@?#m&wZWW=G#bH>ze$J`&!oe*Q|E0r!)d89LYY8b$aowZEoG-uiIF+ +z#n;$ezm6V<nGnvtc?lrGaf)1_);!W0?uqnojdw-1MQM|dwy`OcF?M@A)KgVV*N2}7 +zcXx+--0R}IwzW3-+`f2k?^Av5V7MpRO-q(9rn_R1@Xlz2Ztdy`$Gf6^w6~|bKi!!7 +z9;xq*^~bxmZQn^<^<`+2s=BdSM%VW2#FguN<FO^QuDhGIFquBu677q|cSj>jWFixQ +z)4V8f0Gt`D`+>9Fr~tnJ76EJ`5D_F1cn-`0$RgN9unI6kfYkzIiO?W`ON4+34lv1_ +zNdPDkq1cf$p8^EW;TS*O$CdzNo#1fbIG_Oi0T(ti0jwyt0le_p_HlvX^CFvr)>$b> +zO-z8^CSU`w=mIK7Q)@9fR;XUzrFu{T=rRyygIZBpU9+Or>+?4R9%~G?Y-|g)Z`Sti +z+do(U*Wb-xR~DzjS<75#=Us4sH^C9U2FCbND7L7u$>M|<;t=AnRfI9C0v8c~AVg7t +zIU<3D2oK^>L;%r(*o=4*u?Mja@dDyi#4zFn;(f#^#3*76aUSs#;tJv#La-6YLRdQB +zdcvfERkvH?k~GJlfM<HR476j(@nfm+47<!Ult@^ua5M3h6A}q=C0ognX9aX4mxq)U +zXOhm=DbLene?C%_16Q)2NRV@Yacz`D;{V>Ve-1?&ZXy}n)YwnVAgNlz#zX;=IX)-F +z)9LL3lbEdY5Co)LsK?vP)7s}G(5xduE!Y!#Wgh<IN3(3ey=-oWU(9aEJ_HzV53Jbq +zj5B5RjzLUt>_T&xi$uUA#0e}X3D~`J(bHz;DgTa@GrpW6=>eZwJeNYYo*GjF=``;( +zuoQ3|V5YoKd$j=KK{`uSX*DeU1oJg=+RT6)rLe6%2>Ci^!5ao=*gS}wFN=nUf`fTF +zM?Gb5ycWjM7I?MJ!2;w|LFg=UoLq-ytr2iemG)AsW}bI4X9PK}T5UKsQi7anu=tD6 +zf|={kXkNeQBD>6bQ3taC8XJOJ^e40_ydyfr&a41L^1)jNrK<B_wV}+ZE`p;QK=rDz +zTw`SJ+e`Oc*icaF4INF51Xg*~ts@m)@9ETt(*@N7yy0)Ddce%i9{^k2kbd8=Wns~P +zWBD$~himxDharxF@f!ti^0$~9Zxt{tg`@Dbl_0Ki2Xp_MEw-<z6qgep;XYmR%Dl-F +z%3cBfcN;Avikpz-gmw_6mymu!Unk0YgnUfsk3{*6kQ;=S*p(_fS!JhDyYh^k?6uRk +z?8--W@~NHvY*+ra6SG9iC1s^V)<|@Rqzp*pd5NBslrs`JC(&Oeg~v}CnJ$x+)iP<8 +z=`LA0Ad@39{XkZ}kjXbP{YzHtS!70*yy%LcnJ#cz4u%*Wq!^d*AVMZdr&l=#Qgik~ +ze2l)cX+!kF9EaFhY;0^Uo_#VNC?7K2Tf=ZR1y5);b!mCGG?<cc#M0rtHKYeKi%BE? +z@Y6|P8fx#li}c`Uv24UGyZaM0To;Ep<_AWZA1t~bFgI)uf}&Eq=L_Cs89=>wnT0Vx +z-jp>o1ffJNommZ4?=TIPlePIw0hgQ706f*tBC`#pg>9&zRHe>J2%RxBTrOc6Adh9E +ziJr`?VQH!N!_GkoKaoq|+3$^Ae0#sUxXlmM1Huq~g<=Ls?ILv+nQcH%PQedGOlH=Q +z77rMcJlH4Mkc#U2(IDv>rsm1aHpsdL_RdT^i_ACcQUMIJcSus}*(?CIiy^#^=t=g1 +z+*^Zbh30&^#_bKclSy9pL$<B~pK8m*sLpIdnHM@W$nA7Ea@Z`x27K?aNK<@lCW(2L +zb@kB3H8kKy4W3Hu)NN|kd!DL^o#iR9a{QYV-Wl&r&hmIFX{ezkIV<4zFiVUQ@K>ao +z00DnFy~Uek!JRwhVX!of0)$Sa*X^S~LMQH0<E(UUx}L=|;Kgw(r(4q=nD)T52c|tR +O?SW|zOncy=dEg(6JAK&z + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c +new file mode 100644 +index 0000000000..b6415a428b +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c +@@ -0,0 +1,31 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <bootblock_common.h> ++#include <device/pci_ops.h> ++#include <ec/dell/mec5035/mec5035.h> ++#include <southbridge/intel/bd82x6x/pch.h> ++ ++const struct southbridge_usb_port mainboard_usb_ports[] = { ++ { 1, 1, 0 }, ++ { 1, 1, 0 }, ++ { 1, 1, 1 }, ++ { 1, 1, 1 }, ++ { 1, 0, 2 }, ++ { 1, 1, 2 }, ++ { 1, 0, 3 }, ++ { 1, 0, 3 }, ++ { 1, 1, 5 }, ++ { 1, 1, 5 }, ++ { 1, 1, 7 }, ++ { 1, 1, 6 }, ++ { 1, 0, 6 }, ++ { 1, 0, 7 }, ++}; ++ ++void bootblock_mainboard_early_init(void) ++{ ++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN ++ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN ++ | COMB_LPC_EN | COMA_LPC_EN); ++ mec5035_early_init(); ++} +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c +new file mode 100644 +index 0000000000..61f01816c4 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c +@@ -0,0 +1,190 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_NATIVE, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_INPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio30 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio0 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++ .gpio14 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_GPIO, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_NATIVE, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_OUTPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio45 = GPIO_DIR_OUTPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio51 = GPIO_DIR_INPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio34 = GPIO_LEVEL_HIGH, ++ .gpio45 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_LOW, ++ .gpio60 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_GPIO, ++ .gpio69 = GPIO_MODE_GPIO, ++ .gpio70 = GPIO_MODE_GPIO, ++ .gpio71 = GPIO_MODE_GPIO, ++ .gpio72 = GPIO_MODE_NATIVE, ++ .gpio73 = GPIO_MODE_NATIVE, ++ .gpio74 = GPIO_MODE_NATIVE, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio68 = GPIO_DIR_INPUT, ++ .gpio69 = GPIO_DIR_INPUT, ++ .gpio70 = GPIO_DIR_INPUT, ++ .gpio71 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c +new file mode 100644 +index 0000000000..ae376691e7 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ 0x111d76e7, /* Codec Vendor / Device ID: IDT */ ++ 0x10280494, /* Subsystem ID */ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x10280494), ++ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), ++ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), ++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), ++ AZALIA_PIN_CFG(0, 0x11, 0x400000f2), ++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), ++ ++ 0x80862805, /* Codec Vendor / Device ID: Intel */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(3, 0x80860101), ++ AZALIA_PIN_CFG(3, 0x05, 0x18560010), ++ AZALIA_PIN_CFG(3, 0x06, 0x18560020), ++ AZALIA_PIN_CFG(3, 0x07, 0x18560030), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb +new file mode 100644 +index 0000000000..f90f2dee1f +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb +@@ -0,0 +1,35 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/sandybridge ++ device domain 0 on ++ subsystemid 0x1028 0x0494 inherit ++ ++ device ref igd on ++ register "gpu_cpu_backlight" = "0x00001312" ++ register "gpu_pch_backlight" = "0x13121312" ++ end ++ ++ chip southbridge/intel/bd82x6x ++ register "usb_port_config" = "{ ++ { 1, 1, 0 }, ++ { 1, 1, 0 }, ++ { 1, 1, 1 }, ++ { 1, 1, 1 }, ++ { 1, 0, 2 }, ++ { 1, 1, 2 }, ++ { 1, 1, 3 }, ++ { 1, 1, 3 }, ++ { 1, 1, 5 }, ++ { 1, 1, 5 }, ++ { 1, 1, 7 }, ++ { 1, 1, 6 }, ++ { 1, 0, 6 }, ++ { 1, 0, 7 }, ++ }" ++ ++ device ref sata1 on ++ register "sata_port_map" = "0x3b" ++ end ++ end ++ end ++end +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0022-don-t-use-github-for-the-acpica-download.patch b/config/coreboot/default/patches/0022-don-t-use-github-for-the-acpica-download.patch deleted file mode 100644 index f66909c6..00000000 --- a/config/coreboot/default/patches/0022-don-t-use-github-for-the-acpica-download.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 536a1dd349f590cbefccac7e7364cafcdaec9600 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Sun, 22 Oct 2023 15:02:25 +0100 -Subject: [PATCH 22/30] don't use github for the acpica download - -i have the tarball from a previous download, and i placed -it on libreboot rsync, which then got mirrored to princeton. - -today, github's ssl cert was b0rking the hell out and i really -really wanted to finish a build, and didn't want to wait for -github to fix their httpd. - -so i'm now hosting this specific acpica tarball on rsync. - -this patch makes that URL be used, instead of the github one. - -that's the 2nd time i've had to patch coreboot's acpica download! - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - util/crossgcc/buildgcc | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index 23a5caf2bb..36565a906c 100755 ---- a/util/crossgcc/buildgcc -+++ b/util/crossgcc/buildgcc -@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" - MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" - GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" - BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" --IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags" -+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica" - # CLANG toolchain archive locations - LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" - CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" --- -2.39.2 - diff --git a/config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E5520-Sandy-Bridge.patch b/config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E5520-Sandy-Bridge.patch new file mode 100644 index 00000000..cec59dbe --- /dev/null +++ b/config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E5520-Sandy-Bridge.patch @@ -0,0 +1,442 @@ +From 39dcb2dcada8821c49a3a042d9e70a6cda81a4ab Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Wed, 7 Feb 2024 10:23:38 -0700 +Subject: [PATCH 22/39] mb/dell: Add Latitude E5520 (Sandy Bridge) + +Mainboard is Krug 15". I do not physically have this system; someone +with physical access to one sent me the output of autoport which I then +modified to produce this port. I was also sent the VBT binary, which was +obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version +A14 of the vendor firmware. + +This was originally tested and found to be working as a standalone +board port in Libreboot, but this variant based port in upstream +coreboot has not been tested. + +This can be internally flashed by sending a command to the EC, which +causes the EC to pull the FDO pin low and the firmware to skip setting +up any chipset based write protections [1]. The EC is the SMSC MEC5055, +which seems to be compatible with the existing MEC5035 code. + +[1] https://gitlab.com/nic3-14159/dell-flash-unlock + +Change-Id: Ic9bfc028d4b8ae01ccc019157bb53e7764671134 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/snb_ivb_latitude/Kconfig | 10 +- + .../dell/snb_ivb_latitude/Kconfig.name | 3 + + .../snb_ivb_latitude/variants/e5520/data.vbt | Bin 0 -> 6144 bytes + .../variants/e5520/early_init.c | 14 ++ + .../snb_ivb_latitude/variants/e5520/gpio.c | 195 ++++++++++++++++++ + .../variants/e5520/hda_verb.c | 32 +++ + .../variants/e5520/overridetree.cb | 39 ++++ + 7 files changed, 292 insertions(+), 1 deletion(-) + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb + +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig +index 72bdc96c0a..4e94a7ef80 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig +@@ -17,6 +17,11 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + ++config BOARD_DELL_LATITUDE_E5520 ++ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON ++ select BOARD_ROMSIZE_KB_6144 ++ select SOUTHBRIDGE_INTEL_BD82X6X ++ + config BOARD_DELL_LATITUDE_E6420 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_10240 +@@ -55,6 +60,7 @@ config MAINBOARD_DIR + default "dell/snb_ivb_latitude" + + config MAINBOARD_PART_NUMBER ++ default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520 + default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 + default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520 + default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530 +@@ -68,6 +74,7 @@ config USBDEBUG_HCD_INDEX + default 2 + + config VARIANT_DIR ++ default "e5520" if BOARD_DELL_LATITUDE_E5520 + default "e6420" if BOARD_DELL_LATITUDE_E6420 + default "e6520" if BOARD_DELL_LATITUDE_E6520 + default "e5530" if BOARD_DELL_LATITUDE_E5530 +@@ -77,7 +84,8 @@ config VARIANT_DIR + config VGA_BIOS_ID + default "8086,0116" if BOARD_DELL_LATITUDE_E6520 + default "8086,0166" if BOARD_DELL_LATITUDE_E5530 +- default "8086,0126" if BOARD_DELL_LATITUDE_E6420 ++ default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \ ++ || BOARD_DELL_LATITUDE_E5520 + default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \ + || BOARD_DELL_LATITUDE_E6530 + +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +index c7665ac263..7976691f21 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +@@ -1,5 +1,8 @@ + ## SPDX-License-Identifier: GPL-2.0-only + ++config BOARD_DELL_LATITUDE_E5520 ++ bool "Latitude E5520" ++ + config BOARD_DELL_LATITUDE_E6420 + bool "Latitude E6420" + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..b511e75262e37fa123d674e9a7b21a8dfe427729 +GIT binary patch +literal 6144 +zcmeHKZ){Ul6hE);wSBvNZ|mL$bmQOM2BTvXUI!}^N9ejTij1vnu+)Wx6<c9(Y_%K6 +zzOV-@f<ehpWB5RHBpMBgG7}RuMuM2=l*E{6G$wq&gqTQ3#E2RZsOP@dvW*rP7>Fjj +z&F`Lj?>YC}bI(2Z+}C+6zKyiGrosQXuW7A+&1%<rN+Y1ck(}dLrx)Ma#^x>lnvFGE +zeD#gB>*#Tq4&j^|7Xcz1r^pp*)g#T}u1Me3ct>Pgls5Qi3!6e2W0%`a-Ic|3efWuR +zXJ@#}wJyGMTXTcY<%@TBKh@(3hP$Gjv}E}rx-%9D_eLXhYe!c&-VyDg-Cdo1>Biji +zNNsnlFW#|jdoOj?mZ43m>cVO%UE9@*E7x|%V~c4`XD4l9GCi~@+7pfMibfX8L?!^I +zc~Rg1I5SxH1DAEZ0{jA41jrJBh#-l;b6^%g7QrThRe)&%tQH_!ggOD7A_PRRgGuI0 +z0zi=n#rCB66d-sO$M~^6wgeb$2fH1|0R`v}xUiWCU`4SF;Dyh&j|mK&6WJWJ&Pq9I +zVgmFQfh+)vE}(KWwHA|Oh3fSkss|;2E(2i}s1?gRRV%8!K7U={vHD=s#+Fd)W^M1j +z{R4$??VSvEWpgT=vCM&1-U$bI6CB~IV3Z$$Vv7o!EDnev4j~R(MHsazZ~^fLLKGF4 +zEfQFOa3dZ?1Q1P#&4?!vyAk^k&m&$z3?WV+-b0*1j37o4=MX<3E+eiYge(Ht2umAW +zOPDmU>UL{flI9u|@JtVvfp#o8ek?VfVV9YP5(%pnZX~{PKq4WoWGmV8t$=Ri@{zLQ +zNYYt4<$0Ry&qIoG;7s-t333)Nu8opN{NG!)&!I@eO(cVx8vBVEBvotJ7%yNl$7iQ_ +zI=xk30+V$ff`F6<wRoF(TK%j9nsr#H23umU%)_7jNOl%*FPU567qbg;4gtp711nj2 +z#+kHw`v4|5cA+`UMIvAl;slnH1nl0v=xH<al>1}ljxDE1dcda^&!do|r^eJkI?aC- +zEQMSfm?<w*Unzumkj_w5>VYL6W4=aCiy4rk%xq~5LV?bi|GL2$G7li<%c7yd;6T34 +zQBN5huZ3~6`ChGkpb$Bg5ITb#2iK-qs|1`=sl6Dhn(Lj&8Agt?S{sTDmmtRj7Jm_1 +zFnt{w&FdFkWS3bl>OeL?eO+*i{)9G!cSI-InGt|U0eEYmRCOHm7|I;#LO8ksRIeJ# +zGe+jTwPg4C4TYuN(9zULV3k+hI$YuPo=%N8oZ#u_4S!3Xelt6N0BmuC`hCNeg+&97 +z6*!>)uHvr%2004GZv?!_-y&|TRmil=9D%Q`1aXBsnD^gov3*UZI34&1_vn(B=T4kZ +z_A>ClXVIBNaS^hd&^DrU6VgZMYeadMkdFxcktn|ra-Gl;n^I{bt86rCQ=YMry*B!$ +zP5ID9KDE)GZOY#^VwPyRq^y+48j0?ZlzxdkC()CV@`*&wO7vGr;qjA3rb}gIwM-gi +zx>HsT$mEDj-<OpyWb%zn|B@A3Hkp<!FT5;hrt_SZiy?*wDaIu{h>%Ir=@rh7)SR;b +zAEWQGv_X1)wq0y5Ha0c~&psIsln<Hiu3;#Lf;%*eI<@?p8cfMJV(IYi8q$NA#iS8` +z_~|4t4b^wtMSAeFST^F8-Tm<zu8D&j^8=&I4;I}Im>aeSK~X8*^Z9SE44_`P#KIUL +zf6^N2f>5HCPWM3N+f0MyWOV^kz~!-wVc4MRXOY>4Jsxd1RyBKEMzNf{RKhesKFdbq +zJ(*d<l2Y#n?E?~iBA39P?~Pr2d#}5=#Sfl-VGzGUF$4U2KcqCIVlwkC(&7PQk_X!a +z8}3Jgq-&U*Co|h1>l)ZQGyW_x->i#;FvQ*=Nv&nG0N5@D@jjv_Q}K}6MP?1A6`JGe +zDwj9pN+x;T4>`I9e5x(uqdK#OGB31ikk@Xv=dxLb4fx(;ktX@rOb~M~?dYQQYiPia +z8r;jUQ?sd2@3||-cb2Eb%JFYfxHsONoaJ^eqoKN{<g9?-%`7oWz+aJS0tEc!^d@hD +z1-I{%hr!Y?0uVZpUbl__37xn@jkD6Z>3SATgBQlEoN7&ZV9Eni9+>jLln16fFy(=V +H=7E0zE^L4Z + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c +new file mode 100644 +index 0000000000..ff83db095b +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <bootblock_common.h> ++#include <device/pci_ops.h> ++#include <ec/dell/mec5035/mec5035.h> ++#include <southbridge/intel/bd82x6x/pch.h> ++ ++void bootblock_mainboard_early_init(void) ++{ ++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN ++ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN ++ | COMB_LPC_EN | COMA_LPC_EN); ++ mec5035_early_init(); ++} +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c +new file mode 100644 +index 0000000000..f76b93d9f0 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c +@@ -0,0 +1,195 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_GPIO, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_NATIVE, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio12 = GPIO_DIR_OUTPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_INPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio12 = GPIO_LEVEL_HIGH, ++ .gpio30 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio0 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++ .gpio14 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_GPIO, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_NATIVE, ++ .gpio50 = GPIO_MODE_GPIO, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_GPIO, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_GPIO, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_OUTPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_OUTPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio46 = GPIO_DIR_OUTPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio50 = GPIO_DIR_OUTPUT, ++ .gpio51 = GPIO_DIR_OUTPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio53 = GPIO_DIR_INPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio55 = GPIO_DIR_OUTPUT, ++ .gpio56 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio34 = GPIO_LEVEL_LOW, ++ .gpio37 = GPIO_LEVEL_LOW, ++ .gpio46 = GPIO_LEVEL_HIGH, ++ .gpio50 = GPIO_LEVEL_HIGH, ++ .gpio51 = GPIO_LEVEL_LOW, ++ .gpio55 = GPIO_LEVEL_LOW, ++ .gpio60 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_NATIVE, ++ .gpio69 = GPIO_MODE_NATIVE, ++ .gpio70 = GPIO_MODE_NATIVE, ++ .gpio71 = GPIO_MODE_NATIVE, ++ .gpio72 = GPIO_MODE_NATIVE, ++ .gpio73 = GPIO_MODE_NATIVE, ++ .gpio74 = GPIO_MODE_GPIO, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio74 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c +new file mode 100644 +index 0000000000..1373975352 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ 0x111d76e7, /* Codec Vendor / Device ID: IDT */ ++ 0x1028049a, /* Subsystem ID */ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x1028049a), ++ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), ++ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), ++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), ++ AZALIA_PIN_CFG(0, 0x11, 0xd5a301a0), ++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), ++ ++ 0x80862805, /* Codec Vendor / Device ID: Intel */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(3, 0x80860101), ++ AZALIA_PIN_CFG(3, 0x05, 0x18560010), ++ AZALIA_PIN_CFG(3, 0x06, 0x18560020), ++ AZALIA_PIN_CFG(3, 0x07, 0x18560030), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb +new file mode 100644 +index 0000000000..479d1b696e +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb +@@ -0,0 +1,39 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/sandybridge ++ device domain 0 on ++ subsystemid 0x1028 0x049a inherit ++ ++ device ref igd on ++ register "gpu_cpu_backlight" = "0x00000218" ++ register "gpu_pch_backlight" = "0x13121312" ++ end ++ ++ chip southbridge/intel/bd82x6x ++ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }" ++ register "usb_port_config" = "{ ++ { 1, 1, 0 }, ++ { 1, 1, 0 }, ++ { 1, 1, 1 }, ++ { 1, 1, 1 }, ++ { 1, 1, 2 }, ++ { 1, 1, 2 }, ++ { 1, 1, 3 }, ++ { 1, 1, 3 }, ++ { 1, 1, 5 }, ++ { 1, 1, 5 }, ++ { 1, 1, 7 }, ++ { 1, 1, 6 }, ++ { 1, 1, 6 }, ++ { 1, 1, 7 }, ++ }" ++ ++ device ref gbe off end ++ device ref pcie_rp4 off end ++ device ref pcie_rp7 on end # Broadcom BCM5761 Gigabit Ethernet ++ device ref sata1 on ++ register "sata_port_map" = "0x3b" ++ end ++ end ++ end ++end +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch b/config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch new file mode 100644 index 00000000..dda8313a --- /dev/null +++ b/config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch @@ -0,0 +1,442 @@ +From 948221e226340c1c5852a73d005ada18120de393 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Mon, 4 Mar 2024 18:05:43 -0700 +Subject: [PATCH 23/39] mb/dell: Add Latitude E5420 (Sandy Bridge) + +Mainboard is Krug 14". I do not physically have this system; someone +with physical access to one sent me the output of autoport which I then +modified to produce this port. I was also sent the VBT binary, which was +obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version +A02 of the vendor firmware. + +This was originally tested and found to be working as a standalone board +port in Libreboot, but this variant based port in upstream coreboot has +not been tested. + +This can be internally flashed by sending a command to the EC, which +causes the EC to pull the FDO pin low and the firmware to skip setting +up any chipset based write protections [1]. The EC is the SMSC MEC5055, +which seems to be compatible with the existing MEC5035 code. + +[1] https://gitlab.com/nic3-14159/dell-flash-unlock + +Change-Id: I0283653156083768e1fd451bcf539b4e028589f4 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/snb_ivb_latitude/Kconfig | 10 +- + .../dell/snb_ivb_latitude/Kconfig.name | 3 + + .../snb_ivb_latitude/variants/e5420/data.vbt | Bin 0 -> 6144 bytes + .../variants/e5420/early_init.c | 14 ++ + .../snb_ivb_latitude/variants/e5420/gpio.c | 195 ++++++++++++++++++ + .../variants/e5420/hda_verb.c | 32 +++ + .../variants/e5420/overridetree.cb | 39 ++++ + 7 files changed, 292 insertions(+), 1 deletion(-) + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb + +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig +index 4e94a7ef80..e6a21ffb99 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig +@@ -17,6 +17,11 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + ++config BOARD_DELL_LATITUDE_E5420 ++ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON ++ select BOARD_ROMSIZE_KB_6144 ++ select SOUTHBRIDGE_INTEL_BD82X6X ++ + config BOARD_DELL_LATITUDE_E5520 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_6144 +@@ -60,6 +65,7 @@ config MAINBOARD_DIR + default "dell/snb_ivb_latitude" + + config MAINBOARD_PART_NUMBER ++ default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420 + default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520 + default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 + default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520 +@@ -74,6 +80,7 @@ config USBDEBUG_HCD_INDEX + default 2 + + config VARIANT_DIR ++ default "e5420" if BOARD_DELL_LATITUDE_E5420 + default "e5520" if BOARD_DELL_LATITUDE_E5520 + default "e6420" if BOARD_DELL_LATITUDE_E6420 + default "e6520" if BOARD_DELL_LATITUDE_E6520 +@@ -82,7 +89,8 @@ config VARIANT_DIR + default "e6530" if BOARD_DELL_LATITUDE_E6530 + + config VGA_BIOS_ID +- default "8086,0116" if BOARD_DELL_LATITUDE_E6520 ++ default "8086,0116" if BOARD_DELL_LATITUDE_E6520 \ ++ || BOARD_DELL_LATITUDE_E5420 + default "8086,0166" if BOARD_DELL_LATITUDE_E5530 + default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \ + || BOARD_DELL_LATITUDE_E5520 +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +index 7976691f21..a3fa2b1837 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +@@ -1,5 +1,8 @@ + ## SPDX-License-Identifier: GPL-2.0-only + ++config BOARD_DELL_LATITUDE_E5420 ++ bool "Latitude E5420" ++ + config BOARD_DELL_LATITUDE_E5520 + bool "Latitude E5520" + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..98b82fe6110fd295b5749041ec7f8c084ace5f57 +GIT binary patch +literal 6144 +zcmeHKeQZ-z6hE);wSBvNZ!2$ObQ^;MgV6zl*Rhp}BXnCCMZU^_r7jRwT!kfLo8?3H +zk9)u(7?cb(hChhTM57@QFfmbMB!G!dNsO6BW5OSp5EGF^jHnTTdhUBI+h`e+1ft1q +z^SfW?+;h)4_uO+|XEfEV$91)<gOArWE)OnSTD}Ug6?8a~vz+SmQn!4~y3N7b^|hPp +zR<5aEfv-b8M00Lk251!oO|8(YA6XaeXzkt-Z)@Ee!_{@z#Fro^?DqN4SGjRIu8KYp +zZEufuU@5MM@7jv%h;75FS}ezKv?JDzCH}d%tE)A-GuDb*+B%}~w%88r>}c;!*XQ5O +z)OU7u$J@4U+lk)#GSW%c%c)v`%R6?`w)LIyu6bD7-j0o&X9qUMcEsYlW3BU4rZRvt +zqAUpjf*qXuLCCsU0YM2I5@gB1WKd)f1+Yt?%HWd0DZxYumP(K<LxTif8A39+!KMl} +z31FHG)7?qk5g>e?=ER{f^&}W<0k@mxff(?6+Stw+s6y%k1mM$cLk#^FWWI*9bE1GY +z&VY9?WC1u#23^3^UYw5?H0x2S2gN`x18Fko6_x(#MKyuCU_<D!mEp$qO_An}#@>DV +zdkf*li41yW3p$*0Oo3+63kO6S91*KwP#l2i4jnc)JkUirL^$k}VbH0;CBh#BS=OLf +zW-yE3BRon75gG{_2~QIC5cUzCC%i)FCmbidM>tIwAPf>N5Pl?FC0r*+Sq!oXj!keQ +zVKcyK>TL+gc7oLco$28+FpeeXkEP}_Sea=mk#IWUR^m$!BogvszLPu83FJm0k6K<l +z$#$~YiXtY*GpHp#@FvHJ1UnBD*H%d+{_j24XE4nmBa*?5mOWiold28s3}>*}<HaeO +z+1|-8g2)FCfkDZIdb-Ub);z0#;XEbPfGe?A72!{DAUg|$m+Z~(i@h9j4gtm611ni( +z#u>ACcP}M4exU`*MKVwl5+t6JBpTkmm}xWflKUe~7}`!#%z#gAo{NxUrpDAndYktu +zI0}VLU`J7^xmF1AFiz5S^uzp*DPI$%$qq!(ikh0kP+(GKzF|@N?Y%_#Vp@M+xHr$F +z=%+18z`-fT%z)9-TS$~Dh@2yeN7!UIt0h`fWxUu`JvA_ra*8P48l%7KR0&c1;0R75 +z4f0oz(xQ3MWqz5>qW5M4tZWExHs8<H(e1G@4km@5wEzOOP^x<l`YmA|eKs6j3wl8B +z%C%;uygh%<#kGZ{fymL+OlV0!-*T!V5IB>X@p!@CBU=7e{5^Jl{s7by`po-AJqM2l +znk(=^0bHkF0rUw7)^7j;$=_UIs8`6P6b-;vPDZ#U9L)W1_PAYRDP9k~;5$stt5ZiV +zD0>;i-?OlYY2}P9WVnfGos4xee2r=EGWHR}ADH$VV>cO=xU?!4TjIi)OMBYI_PX#b +zm-eBHed5BOT-x6*W>;{IqAga~G6lCQT93k>Q}CpsomJR*1%FjEkv?fuT%c-8RklXO +zU8;6KWk*zeU)4TW+1D!mrE0EhHZfbBeN{4S7X@Pig%};A99QTdA~wZruL*8y?K!jP +zG5R*k=);S}Zn<T;W!Mxt`(!+z7_r@3LVpf|FESauM&4}+wqzXfba-zG>A}on(uzNF +zyu>BcjA})C@bg%<;+Eh2;Sz4heFFCbZ@C{FrXMIbYzu>?Bi-|vZ}JSFU%JA>7$7et +z0Yo%CnOVZm#ZA}4kWZOn15};h5*#OM3b+6vHzgruMP>=5MNJK1y42{YgveP-!j%#( +z0rGe@8t%!=66Ti%K4|Gx=o7gFp83wQ;+s3H7+r^SKlpp3KKcr!3@|n;NCH_=qL=3T +zq3WH?en`b+W-HR-fnrhw*9aZ%M}lHX7@H?E>!6wv_&YQFEHdA$%Z1R--yub>=c@p? +z6@7Fc$&>sAxwiz{BE$1kb$K9Co=ozlA973y^i(^BM|EZ$$^y`0KyHiMJ%O*XbfEX1 +ziZaH>W(1pWL0bo|T!x__N$^$DpmxI=bL6WUK3JGyn?rw-qC4ZA$yGjIB}N(=ldD2O +zAJ@bxp<qR-3lIv<!P~SE8r*#_Ckl?$0|1fZ>2>n}u*mUIYFd>}O_wuwBD^r9<#=!0 +X1LGbT_rSOZ#yv3ZfpHH!G!Og(1Xg~J + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c +new file mode 100644 +index 0000000000..ff83db095b +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <bootblock_common.h> ++#include <device/pci_ops.h> ++#include <ec/dell/mec5035/mec5035.h> ++#include <southbridge/intel/bd82x6x/pch.h> ++ ++void bootblock_mainboard_early_init(void) ++{ ++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN ++ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN ++ | COMB_LPC_EN | COMA_LPC_EN); ++ mec5035_early_init(); ++} +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c +new file mode 100644 +index 0000000000..f76b93d9f0 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c +@@ -0,0 +1,195 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_GPIO, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_NATIVE, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio12 = GPIO_DIR_OUTPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_INPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio12 = GPIO_LEVEL_HIGH, ++ .gpio30 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio0 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++ .gpio14 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_GPIO, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_NATIVE, ++ .gpio50 = GPIO_MODE_GPIO, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_GPIO, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_GPIO, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_OUTPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_OUTPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio46 = GPIO_DIR_OUTPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio50 = GPIO_DIR_OUTPUT, ++ .gpio51 = GPIO_DIR_OUTPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio53 = GPIO_DIR_INPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio55 = GPIO_DIR_OUTPUT, ++ .gpio56 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio34 = GPIO_LEVEL_LOW, ++ .gpio37 = GPIO_LEVEL_LOW, ++ .gpio46 = GPIO_LEVEL_HIGH, ++ .gpio50 = GPIO_LEVEL_HIGH, ++ .gpio51 = GPIO_LEVEL_LOW, ++ .gpio55 = GPIO_LEVEL_LOW, ++ .gpio60 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_NATIVE, ++ .gpio69 = GPIO_MODE_NATIVE, ++ .gpio70 = GPIO_MODE_NATIVE, ++ .gpio71 = GPIO_MODE_NATIVE, ++ .gpio72 = GPIO_MODE_NATIVE, ++ .gpio73 = GPIO_MODE_NATIVE, ++ .gpio74 = GPIO_MODE_GPIO, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio74 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c +new file mode 100644 +index 0000000000..0bc6c35a63 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ 0x111d76e7, /* Codec Vendor / Device ID: IDT */ ++ 0x1028049b, /* Subsystem ID */ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x1028049b), ++ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), ++ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), ++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), ++ AZALIA_PIN_CFG(0, 0x11, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x20, 0xd5a30130), ++ ++ 0x80862805, /* Codec Vendor / Device ID: Intel */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(3, 0x80860101), ++ AZALIA_PIN_CFG(3, 0x05, 0x18560010), ++ AZALIA_PIN_CFG(3, 0x06, 0x18560020), ++ AZALIA_PIN_CFG(3, 0x07, 0x18560030), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb +new file mode 100644 +index 0000000000..3f55bfd49d +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb +@@ -0,0 +1,39 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/sandybridge ++ device domain 0 on ++ subsystemid 0x1028 0x049b inherit ++ ++ device ref igd on ++ register "gpu_cpu_backlight" = "0x00000c31" ++ register "gpu_pch_backlight" = "0x13121312" ++ end ++ ++ chip southbridge/intel/bd82x6x ++ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }" ++ register "usb_port_config" = "{ ++ { 1, 1, 0 }, ++ { 1, 1, 0 }, ++ { 1, 1, 1 }, ++ { 1, 1, 1 }, ++ { 1, 1, 2 }, ++ { 1, 1, 2 }, ++ { 1, 1, 3 }, ++ { 1, 1, 3 }, ++ { 1, 1, 5 }, ++ { 1, 1, 5 }, ++ { 1, 1, 7 }, ++ { 1, 1, 6 }, ++ { 1, 1, 6 }, ++ { 1, 1, 7 }, ++ }" ++ ++ device ref gbe off end ++ device ref pcie_rp4 off end ++ device ref pcie_rp7 on end # Broadcom BCM5761 Gigabit Ethernet ++ device ref sata1 on ++ register "sata_port_map" = "0x3b" ++ end ++ end ++ end ++end +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0024-mb-dell-Add-Latitude-E6320-Sandy-Bridge.patch b/config/coreboot/default/patches/0024-mb-dell-Add-Latitude-E6320-Sandy-Bridge.patch new file mode 100644 index 00000000..0b731f5a --- /dev/null +++ b/config/coreboot/default/patches/0024-mb-dell-Add-Latitude-E6320-Sandy-Bridge.patch @@ -0,0 +1,435 @@ +From 5ebb21be501cf43d41d1690c29d047bd98fbc942 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Wed, 7 Feb 2024 15:23:46 -0700 +Subject: [PATCH 24/39] mb/dell: Add Latitude E6320 (Sandy Bridge) + +Mainboard is PAL70/LA-6611P. I do not physically have this system; +someone with physical access to one sent me the output of autoport which +I then modified to produce this port. I was also sent the VBT binary, +which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running +version A22 of the vendor firmware. This port has not been tested. + +The EC is the SMSC MEC5055, which seems to be compatible with the +existing MEC5035 code. As with the other Dell systems with this EC, this +board is assumed to be internally flashable using an EC command that +tells it to pull the FDO pin low on the next boot, which also tells the +vendor firmware to disable all write protections to the flash [1]. + +[1] https://gitlab.com/nic3-14159/dell-flash-unlock + +Change-Id: I5905f8c6a8dbad56e03bdeedc2179600d0c4ba46 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/snb_ivb_latitude/Kconfig | 11 +- + .../dell/snb_ivb_latitude/Kconfig.name | 3 + + .../snb_ivb_latitude/variants/e6320/data.vbt | Bin 0 -> 6144 bytes + .../variants/e6320/early_init.c | 17 ++ + .../snb_ivb_latitude/variants/e6320/gpio.c | 190 ++++++++++++++++++ + .../variants/e6320/hda_verb.c | 32 +++ + .../variants/e6320/overridetree.cb | 35 ++++ + 7 files changed, 287 insertions(+), 1 deletion(-) + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb + +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig +index e6a21ffb99..84ffe1d33a 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig +@@ -27,6 +27,12 @@ config BOARD_DELL_LATITUDE_E5520 + select BOARD_ROMSIZE_KB_6144 + select SOUTHBRIDGE_INTEL_BD82X6X + ++config BOARD_DELL_LATITUDE_E6320 ++ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON ++ select BOARD_ROMSIZE_KB_10240 ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select SOUTHBRIDGE_INTEL_BD82X6X ++ + config BOARD_DELL_LATITUDE_E6420 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_10240 +@@ -67,6 +73,7 @@ config MAINBOARD_DIR + config MAINBOARD_PART_NUMBER + default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420 + default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520 ++ default "Latitude E6320" if BOARD_DELL_LATITUDE_E6320 + default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 + default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520 + default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530 +@@ -82,6 +89,7 @@ config USBDEBUG_HCD_INDEX + config VARIANT_DIR + default "e5420" if BOARD_DELL_LATITUDE_E5420 + default "e5520" if BOARD_DELL_LATITUDE_E5520 ++ default "e6320" if BOARD_DELL_LATITUDE_E6320 + default "e6420" if BOARD_DELL_LATITUDE_E6420 + default "e6520" if BOARD_DELL_LATITUDE_E6520 + default "e5530" if BOARD_DELL_LATITUDE_E5530 +@@ -93,7 +101,8 @@ config VGA_BIOS_ID + || BOARD_DELL_LATITUDE_E5420 + default "8086,0166" if BOARD_DELL_LATITUDE_E5530 + default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \ +- || BOARD_DELL_LATITUDE_E5520 ++ || BOARD_DELL_LATITUDE_E5520 \ ++ || BOARD_DELL_LATITUDE_E6320 + default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \ + || BOARD_DELL_LATITUDE_E6530 + +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +index a3fa2b1837..ef6a1329a9 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +@@ -6,6 +6,9 @@ config BOARD_DELL_LATITUDE_E5420 + config BOARD_DELL_LATITUDE_E5520 + bool "Latitude E5520" + ++config BOARD_DELL_LATITUDE_E6320 ++ bool "Latitude E6320" ++ + config BOARD_DELL_LATITUDE_E6420 + bool "Latitude E6420" + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..471a9e29da639dd496f3ecebd5d0754a9045c00b +GIT binary patch +literal 6144 +zcmeHKeP|p-6#wn*-rZ(yH@R-odPzTgZEU>S#_pv}j2iKhT+^%8_DtJw21|4GP8*0x +zyw;EYW49Xozz<Rt@ek1mic(N32r8oZ0U9lcR8a)~s33wLV8yCftLK~DJJWb)8w-j; +z=J?H<nfK<+n>TOX?48xuwV5_`Zb)3w)w?dSc1`nTL|NF_SMw&<<)v%g#!cH2otrzi +zb*<mneJMSLdC1iK_7#v-6w7R}+t1&W8P4wBo*&F!lcNn?)F-EqWZV#oQEb%`x-4^5 +zW@sogOik1`n9Wc#r82|0A!=-0LD!FFGrMwG+CDg($q(js(#Y`8?s79ubEJD@ba#I6 +znjO0++P#czvh8NBR?)iQUA%txNPhHO>Kq!PUMaJadUHE-`5SWCb4_6i;5Aj(6hQGK +zcq^2uUt5sS5YSMiL+CJcs0#cVOdTN|K@D>?tkF=dqenwjM^Z-^K2z~&z+xRs!o^Jx +zkUGd?>QtXw8V(I09OiMb0DZy>`=tO^#BCssw{}bkOnj=#Ic!~!6!J*{`jbEv5O4)- +zg-UBlIa$c9Pg4C;0_-wq3t+dbZfn1wBi@zhNnWx()w{Vb-G8OC_m*478gTrX3U*a1 +zHr@y<Lcbct?Wzy^)OH+FC$S`8V@n`{QN~@2dxJU-1ucBe_>rOO78dFPXES1q3mHj9 +zFXKwa)r^}Mw=nKzJjj?}>}NdBc$G29IK=pr@de`u;}}D$5~yYbw&Hlf=OF0X?I=Y$ +z$D`mgy>}U$hl}G6m&PmXveHnY5DenC!g~=E3i?HIrEpyk>_(-IsVtEqUEoqxrDFdq +zrYwhOv0o^NgW$OKN}=$7Z-w5*Vuv?T3~uuFGwP92?Qr8n0iQp=u*7rep9Q8dW#?ZI +zFly1ww^^l*+YC6t16l_{g}tVVpVZ0fDk%5+`|+*688vr-<Lw_SRc^+avHI{BCpdYb +z70yLEI0-45%t;z||GKzov+|VFW6hab&NAG9FD+h6sBu$cX`r0eJ%T`kvK4+(wT`0= +z$fxKG+om?Ge1-EhbNc*Xjy1opKZSaiv-EL~GvOa&&bx~z##3W;F2{b=<HQ4!<1CFk +z17i)$X+`=C=0udOPOx3$IjzopqwQzLr*jT4C)(jmj2>uYP8$M=#caX6OWA1Ez395U +z%x<yAs)6-Ascr5<x*>CIZibyRlE~I0-ianVaz~q|EMlL7hc1U5w?}Kekws6fyy@`e +z4NdX%L#2`A#c_N4ftGmuwbDo=incwf=WnBJk6)fYz%6Cmy>HwK$Y|iP`Y7sgjDPhQ +zR|wv367k}1g)-G@kXq(X;{Bjt998b9{cpD9zGhOQ5%$4OSMtc2(<dx@0O}7_G+$WF +zLYyaPtFT6d*e&Q$VLd0r%Yr@=*7rjEDyT7JwT8sSA<BiU8$)7mh@K2tFNMULA^I|8 +z{Sp#>gO(fCMTS^w(6xrO#}IcK^sHgMZis^heP>uIf6|z=%Cy#)Vxvjdo7U~7*k{rU +zruB{~J}~KL(+X9Kxz*-5M>NNGSaIfXi19({d4mrk?K50@R0%Wn*PP9d(MMIzI2~RX +z)(4h&8(YL@UyKJ*)4o${n5ZGd(hDf+)cv8sSBxWen|f*u<-sgt(u+U-bkd}Tj+5@9 +zJosfSdvPo8zGnluemJg=E7A{=N<Rc#KYYEg?^p`+_?~aU(kEmFus{DshA~iA(onLY +zvIfpBJt;KWP4n8&`n1##c($WnDo|=?rlHBz&}36&HPWwp8op_i8c-**(TSd{Y{SZ? +z_=^K$27e+q;^vRNU3~a=cd;V{%O=iuo*&xwXyg19${Ap0yO@a|N-<e^7iIClF{vUn +z&4$y_V7MA)=E=%7n63u!J9FY$RK8hXHDE%%Lx$ZgX902-<9r|4lkx>QwFch>PUO1w +z=6JffnB-kQ)VLb>sSZdDrI@U2!?HLA9Mlek!*k>;&jx<)xfnBiY^I6DRt*l*`n8ly +zu!h)b?sRV1==Nf*Cw9&&i7n^9Nts>wk>adaY&E5OdW*A?iI}v+E6GGlsR<+#%jpl^ +zGz<Q^vpj>qhDjj3zr60Bgh=l{NzJp$x#fCR%*8!ZR?fC&JuvHmSr5#5VAcb(9+>sO +IzvhA80TAzedH?_b + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c +new file mode 100644 +index 0000000000..b0c4638858 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c +@@ -0,0 +1,17 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <bootblock_common.h> ++#include <device/pci_ops.h> ++#include <ec/dell/mec5035/mec5035.h> ++#include <southbridge/intel/bd82x6x/pch.h> ++ ++const struct southbridge_usb_port mainboard_usb_ports[] = { ++}; ++ ++void bootblock_mainboard_early_init(void) ++{ ++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN ++ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN ++ | COMB_LPC_EN | COMA_LPC_EN); ++ mec5035_early_init(); ++} +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c +new file mode 100644 +index 0000000000..61f01816c4 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c +@@ -0,0 +1,190 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_NATIVE, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_INPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio30 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio0 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++ .gpio14 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_GPIO, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_NATIVE, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_OUTPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio45 = GPIO_DIR_OUTPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio51 = GPIO_DIR_INPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio34 = GPIO_LEVEL_HIGH, ++ .gpio45 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_LOW, ++ .gpio60 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_GPIO, ++ .gpio69 = GPIO_MODE_GPIO, ++ .gpio70 = GPIO_MODE_GPIO, ++ .gpio71 = GPIO_MODE_GPIO, ++ .gpio72 = GPIO_MODE_NATIVE, ++ .gpio73 = GPIO_MODE_NATIVE, ++ .gpio74 = GPIO_MODE_NATIVE, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio68 = GPIO_DIR_INPUT, ++ .gpio69 = GPIO_DIR_INPUT, ++ .gpio70 = GPIO_DIR_INPUT, ++ .gpio71 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c +new file mode 100644 +index 0000000000..2e3f7fa697 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ 0x111d76e7, /* Codec Vendor / Device ID: IDT */ ++ 0x10280492, /* Subsystem ID */ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x10280492), ++ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), ++ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), ++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), ++ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), ++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), ++ ++ 0x80862805, /* Codec Vendor / Device ID: Intel */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(3, 0x80860101), ++ AZALIA_PIN_CFG(3, 0x05, 0x18560010), ++ AZALIA_PIN_CFG(3, 0x06, 0x18560020), ++ AZALIA_PIN_CFG(3, 0x07, 0x18560030), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb +new file mode 100644 +index 0000000000..3bfe6b57ed +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb +@@ -0,0 +1,35 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/sandybridge ++ device domain 0 on ++ subsystemid 0x1028 0x0492 inherit ++ ++ device ref igd on ++ register "gpu_cpu_backlight" = "0x00000622" ++ register "gpu_pch_backlight" = "0x13121312" ++ end ++ ++ chip southbridge/intel/bd82x6x ++ register "usb_port_config" = "{ ++ { 1, 1, 0 }, ++ { 1, 0, 0 }, ++ { 1, 1, 1 }, ++ { 1, 0, 1 }, ++ { 1, 1, 2 }, ++ { 1, 1, 2 }, ++ { 1, 1, 3 }, ++ { 1, 1, 3 }, ++ { 1, 0, 5 }, ++ { 1, 0, 5 }, ++ { 1, 1, 7 }, ++ { 1, 1, 6 }, ++ { 1, 0, 6 }, ++ { 1, 0, 7 }, ++ }" ++ ++ device ref sata1 on ++ register "sata_port_map" = "0x3b" ++ end ++ end ++ end ++end +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0025-mb-dell-Add-Latitude-E6220-Sandy-Bridge.patch b/config/coreboot/default/patches/0025-mb-dell-Add-Latitude-E6220-Sandy-Bridge.patch new file mode 100644 index 00000000..0df0a822 --- /dev/null +++ b/config/coreboot/default/patches/0025-mb-dell-Add-Latitude-E6220-Sandy-Bridge.patch @@ -0,0 +1,438 @@ +From fbe48205a55b4a03082affe9f66e81ee509d5f44 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Fri, 8 Mar 2024 09:27:36 -0700 +Subject: [PATCH 25/39] mb/dell: Add Latitude E6220 (Sandy Bridge) + +Mainboard is codenamed Vida. I do not physically have this system; +someone with physical access to one sent me the output of autoport which +I then modified to produce this port. The VBT was obtained using +intelvbttool while running version A14 (latest available version) of the +vendor firmware. + +Tested and found to boot as part of a libreboot build based on upstream +coreboot commit b7341da191 with additional patches, though these do not +appear to affect SNB/IVB. The base E6430 patch was tested against +coreboot main. + +The EC is the SMSC MEC5055, which seems to be compatible with the +existing MEC5035 code. As with the other Dell systems with this EC, this +board is assumed to be internally flashable using an EC command that +tells it to pull the FDO pin low on the next boot, which also tells the +vendor firmware to disable all write protections to the flash [1]. + +[1] https://gitlab.com/nic3-14159/dell-flash-unlock + +Change-Id: I570023b0837521b75aac6d5652c74030c06b8a4c +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/snb_ivb_latitude/Kconfig | 9 + + .../dell/snb_ivb_latitude/Kconfig.name | 3 + + .../snb_ivb_latitude/variants/e6220/data.vbt | Bin 0 -> 3985 bytes + .../variants/e6220/early_init.c | 14 ++ + .../snb_ivb_latitude/variants/e6220/gpio.c | 192 ++++++++++++++++++ + .../variants/e6220/hda_verb.c | 32 +++ + .../variants/e6220/overridetree.cb | 37 ++++ + 7 files changed, 287 insertions(+) + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb + +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig +index 84ffe1d33a..baa83baa41 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig +@@ -27,6 +27,12 @@ config BOARD_DELL_LATITUDE_E5520 + select BOARD_ROMSIZE_KB_6144 + select SOUTHBRIDGE_INTEL_BD82X6X + ++config BOARD_DELL_LATITUDE_E6220 ++ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON ++ select BOARD_ROMSIZE_KB_10240 ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select SOUTHBRIDGE_INTEL_BD82X6X ++ + config BOARD_DELL_LATITUDE_E6320 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_10240 +@@ -73,6 +79,7 @@ config MAINBOARD_DIR + config MAINBOARD_PART_NUMBER + default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420 + default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520 ++ default "Latitude E6220" if BOARD_DELL_LATITUDE_E6220 + default "Latitude E6320" if BOARD_DELL_LATITUDE_E6320 + default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 + default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520 +@@ -89,6 +96,7 @@ config USBDEBUG_HCD_INDEX + config VARIANT_DIR + default "e5420" if BOARD_DELL_LATITUDE_E5420 + default "e5520" if BOARD_DELL_LATITUDE_E5520 ++ default "e6220" if BOARD_DELL_LATITUDE_E6220 + default "e6320" if BOARD_DELL_LATITUDE_E6320 + default "e6420" if BOARD_DELL_LATITUDE_E6420 + default "e6520" if BOARD_DELL_LATITUDE_E6520 +@@ -102,6 +110,7 @@ config VGA_BIOS_ID + default "8086,0166" if BOARD_DELL_LATITUDE_E5530 + default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \ + || BOARD_DELL_LATITUDE_E5520 \ ++ || BOARD_DELL_LATITUDE_E6220 \ + || BOARD_DELL_LATITUDE_E6320 + default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \ + || BOARD_DELL_LATITUDE_E6530 +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +index ef6a1329a9..349ee7f79e 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +@@ -6,6 +6,9 @@ config BOARD_DELL_LATITUDE_E5420 + config BOARD_DELL_LATITUDE_E5520 + bool "Latitude E5520" + ++config BOARD_DELL_LATITUDE_E6220 ++ bool "Latitude E6220" ++ + config BOARD_DELL_LATITUDE_E6320 + bool "Latitude E6320" + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..548075a74500b5d159108089ee29cff802d07db7 +GIT binary patch +literal 3985 +zcmdT{eP|p-6#wn*-rZ(yH@R-odPzTgZQ6LXjonL|7&YQ0xu#d`$C=h}21|4GP8*0x +zyjE@hv0Dv(P?c0g{G(_DMJZ@22r8oZ0U9lcR8a)~s33wOSg|T<^?b8?XBzL?#)6`A +z{N~Nfd-LYan>TOv7WZ{+rcIq264!S1u1&02-MpSC3mf}u-r~BvbgkXEX=|c$bLZBs +zbsM{{q9-s1nVR3f2C|A`nJsqvC7UwC+1=angV`H%w4sao<P?&OTVpYbtz1OwGuLN^ +zhBCv{M16zV3^h|KGn^Zu#@6L@%V;*UGnb`pgTtBpU~UJE3=i!tH{%>fx<^KL=Lc`x +zzLTQeOW7vdZsuwwtsUOU>vxajM=zqzp&{y(GCQa@w<DLoHJ81}6s7=PS9MJR6hDG@ +zLaF+#1qlrS4OKdX4nv2kz^}p75z-OVFk8cF4b?h&G(>eIb%fzF6`uwy)UhaB+ynus +zBRr-~^|__t=m5fD9tR81r@XLV3UEc-2I6>o`;@@MXS$rj)&)r+pA?|K2vh+9SHM=N +zw3d{Uh1~iK)juV`E`v4?cFU@^_DehBU5TFLmFrTyoBPuJ*ExIdxO1!lC!eceSG8i} +z&A<Zmt5Mvo`mkSZ$5C|>ivl*T2}Cf;*vEJvsN-nR!WWDm8M<y^zAkV9BgVLlk!18T +zu4CN5*u}VmaUbIm#suRa;|0cRj7i2(#%GK#8OIsFFtjRxYDQoSP8NI)g09_;Qlzsy +z3O>^Zmcltu96wMRudvHXLxn;xh~EqEM^Gr}m&=vHbwRKjl{%)fM2d8tOI4MM{l!dK +z4$)%2P!LDJaqX2t;s4$Wy@Q1gZ=x97<n3qFBc<Bm#;F26e|~<6=hD9lOk>K<zaU`L +zqML8CN*#9@aDs=m4ulGOO%*?>lhsvF9`g6&TYocZ_JQN=A1hUE#+kAD@E9jJd7%}~ +zMLIYMDVoel8h1}$+_YJF%DJ&-O)X~`ZoroouO-yDsj)OrPU{{+ph4LJKdD;Bi3a3T +zbe?Tf8&<r^`I<R>elW+H+t;5$y~|nhq{o@?k1^-Hg%jhcu{xJyzvgk`0m*Te#GQe$ +z2IjOP{U&oF$`&WsuJN2!=fTnT^W)PwhnW-Ya3)3%H!`OUfy6?#V9r%+wCY}TU0!Cl +z*kjeex}MZl_aWVoxhXfp&Ur~>>k;onlO4II%~KY!FT|r)!;agdwcf~rXIAVwc6CEj +zJpE{CBzZ;L-gdYp9)G<w5{aU1kLvl`XxrnL=MQj88F%j+w*oR6c&t8(di=t_dW<Us +z?>C8f@wZ%=YBfkLb0_gZP%us?_tgG3TXJ7BDbWb~V23Mt{QT(?mOc#ihbo#YtY#rD +z7PLiJBSP#J^tiB|7vdE`p9|}IA$}9o7_wSJ;))RELe^~|u{T6dhpd-F;;j&U6|#N} +z3BN(h4C``3tTE^&!`fqrdks2dSZ^5Oh(X^Omdc+rCapBB)uz~J(k-TSw<-3U^rC6K +zYl;s|`q{KX)nazFdEs%*@f}l~SsY?~kb2(WgGl=fm!43<O#L+%@MH9Gl`~Gq=7;rx +zMc&31@YxsRfz-6`>>4I&2(k1$iaK?FYVZ}~h~1{1T|;>=%b4`yk3XF>siEVHyC@HS +z8OvVW%DeB`K&~H7>f?&^gQU_A0oM<l8+N5oZ4)iV>;p0b*k61j!x*S5X(-unS`9rZ +zG}=vb+R*x})DSq-Q7;uJwKLPuG`Ej6G}#nch4dSqhHo0B2Gq%HbgCyS+pwZ3{?fph +z!Jo*Dxcw7v7a#rIU2IRmVn4KE$x~88+a7J4zd|_!%xo9z$+P;Q6qA*AQ5FvzlPW^f +zY&aJUhO1#_o~&$x>1qJKGpC+K<(u_&1197<WZ2zu79e*q&i9c$DPNGYYw%s_L~d?x +zj;EW8N#6BCjjMs5>VVWxipk10ERAEpLG3^|JWI~<Y~c5vi!sB;W|~-R<=`-_TSLhN +zYlyAlPUkfn-CnHq)Xv2vv1R->DYG*_Qk)fwt)g^KZ*f*K5tEj9C7Ea`HGyPe8U4wd +nX2Iz@%Q6UTm;}-X%j^D0i1fiT)I6)4TdrsMY}`L(<y7krryzQ} + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c +new file mode 100644 +index 0000000000..ff83db095b +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <bootblock_common.h> ++#include <device/pci_ops.h> ++#include <ec/dell/mec5035/mec5035.h> ++#include <southbridge/intel/bd82x6x/pch.h> ++ ++void bootblock_mainboard_early_init(void) ++{ ++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN ++ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN ++ | COMB_LPC_EN | COMA_LPC_EN); ++ mec5035_early_init(); ++} +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c +new file mode 100644 +index 0000000000..2306e4cf0a +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c +@@ -0,0 +1,192 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_GPIO, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_NATIVE, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio1 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_INPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio30 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio0 = GPIO_INVERT, ++ .gpio1 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++ .gpio14 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_GPIO, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_NATIVE, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_OUTPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio45 = GPIO_DIR_OUTPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio51 = GPIO_DIR_INPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio34 = GPIO_LEVEL_HIGH, ++ .gpio45 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_LOW, ++ .gpio60 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_GPIO, ++ .gpio69 = GPIO_MODE_GPIO, ++ .gpio70 = GPIO_MODE_GPIO, ++ .gpio71 = GPIO_MODE_GPIO, ++ .gpio72 = GPIO_MODE_NATIVE, ++ .gpio73 = GPIO_MODE_NATIVE, ++ .gpio74 = GPIO_MODE_NATIVE, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio68 = GPIO_DIR_INPUT, ++ .gpio69 = GPIO_DIR_INPUT, ++ .gpio70 = GPIO_DIR_INPUT, ++ .gpio71 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c +new file mode 100644 +index 0000000000..0c69f0bd0e +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ 0x111d76e7, /* Codec Vendor / Device ID: IDT */ ++ 0x102804a9, /* Subsystem ID */ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x102804a9), ++ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), ++ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), ++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), ++ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), ++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), ++ ++ 0x80862805, /* Codec Vendor / Device ID: Intel */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(3, 0x80860101), ++ AZALIA_PIN_CFG(3, 0x05, 0x18560010), ++ AZALIA_PIN_CFG(3, 0x06, 0x18560020), ++ AZALIA_PIN_CFG(3, 0x07, 0x18560030), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb +new file mode 100644 +index 0000000000..9faf27e27b +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb +@@ -0,0 +1,37 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/sandybridge ++ device domain 0 on ++ subsystemid 0x1028 0x04a9 inherit ++ ++ device ref igd on ++ register "gpu_cpu_backlight" = "0x0000046a" ++ register "gpu_pch_backlight" = "0x13121312" ++ end ++ ++ chip southbridge/intel/bd82x6x ++ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" ++ register "usb_port_config" = "{ ++ { 1, 1, 0 }, ++ { 1, 0, 0 }, ++ { 1, 1, 1 }, ++ { 1, 0, 1 }, ++ { 1, 1, 2 }, ++ { 1, 1, 2 }, ++ { 1, 1, 3 }, ++ { 1, 1, 3 }, ++ { 1, 0, 5 }, ++ { 1, 0, 5 }, ++ { 1, 1, 7 }, ++ { 1, 1, 6 }, ++ { 1, 0, 6 }, ++ { 1, 0, 7 }, ++ }" ++ ++ device ref pcie_rp4 off end ++ device ref sata1 on ++ register "sata_port_map" = "0x3b" ++ end ++ end ++ end ++end +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6330-Ivy-Bridge.patch b/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6330-Ivy-Bridge.patch new file mode 100644 index 00000000..c542ef86 --- /dev/null +++ b/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6330-Ivy-Bridge.patch @@ -0,0 +1,436 @@ +From 87e6f8bf38c5dcb4075d0df32507bf9151338b92 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Fri, 8 Mar 2024 09:33:03 -0700 +Subject: [PATCH 26/39] mb/dell: Add Latitude E6330 (Ivy Bridge) + +Mainboard is QAL70/LA-7741P. I do not physically have this system; +someone with physical access to one sent me the output of autoport which +I then modified to produce this port. I was also sent the VBT binary, +which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running +version A21 of the vendor firmware. This port has not been tested. + +The EC is the SMSC MEC5055, which seems to be compatible with the +existing MEC5035 code. As with the other Dell systems with this EC, this +board is assumed to be internally flashable using an EC command that +tells it to pull the FDO pin low on the next boot, which also tells the +vendor firmware to disable all write protections to the flash [1]. + +[1] https://gitlab.com/nic3-14159/dell-flash-unlock + +Change-Id: I827826e9ff8a9a534c50250458b399104478e06c +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/snb_ivb_latitude/Kconfig | 11 +- + .../dell/snb_ivb_latitude/Kconfig.name | 3 + + .../snb_ivb_latitude/variants/e6330/data.vbt | Bin 0 -> 6144 bytes + .../variants/e6330/early_init.c | 14 ++ + .../snb_ivb_latitude/variants/e6330/gpio.c | 192 ++++++++++++++++++ + .../variants/e6330/hda_verb.c | 32 +++ + .../variants/e6330/overridetree.cb | 37 ++++ + 7 files changed, 288 insertions(+), 1 deletion(-) + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb + +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig +index baa83baa41..49bf225fe2 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig +@@ -56,6 +56,12 @@ config BOARD_DELL_LATITUDE_E5530 + select BOARD_ROMSIZE_KB_12288 + select SOUTHBRIDGE_INTEL_C216 + ++config BOARD_DELL_LATITUDE_E6330 ++ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON ++ select BOARD_ROMSIZE_KB_12288 ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select SOUTHBRIDGE_INTEL_C216 ++ + config BOARD_DELL_LATITUDE_E6430 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_12288 +@@ -84,6 +90,7 @@ config MAINBOARD_PART_NUMBER + default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 + default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520 + default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530 ++ default "Latitude E6330" if BOARD_DELL_LATITUDE_E6330 + default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430 + default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530 + +@@ -101,13 +108,15 @@ config VARIANT_DIR + default "e6420" if BOARD_DELL_LATITUDE_E6420 + default "e6520" if BOARD_DELL_LATITUDE_E6520 + default "e5530" if BOARD_DELL_LATITUDE_E5530 ++ default "e6330" if BOARD_DELL_LATITUDE_E6330 + default "e6430" if BOARD_DELL_LATITUDE_E6430 + default "e6530" if BOARD_DELL_LATITUDE_E6530 + + config VGA_BIOS_ID + default "8086,0116" if BOARD_DELL_LATITUDE_E6520 \ + || BOARD_DELL_LATITUDE_E5420 +- default "8086,0166" if BOARD_DELL_LATITUDE_E5530 ++ default "8086,0166" if BOARD_DELL_LATITUDE_E5530 \ ++ || BOARD_DELL_LATITUDE_E6330 + default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \ + || BOARD_DELL_LATITUDE_E5520 \ + || BOARD_DELL_LATITUDE_E6220 \ +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +index 349ee7f79e..d6fc8eb224 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +@@ -21,6 +21,9 @@ config BOARD_DELL_LATITUDE_E6520 + config BOARD_DELL_LATITUDE_E5530 + bool "Latitude E5530" + ++config BOARD_DELL_LATITUDE_E6330 ++ bool "Latitude E6330" ++ + config BOARD_DELL_LATITUDE_E6430 + bool "Latitude E6430" + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..18856746656058651c571ecbb3708e0543b19d62 +GIT binary patch +literal 6144 +zcmeHKU2GiH75-*tc6WAmW_LYygMSkDB*E^Q*zv5f7dLg)@$NQV2a{}!yImnfyvQ4D +z;n-$v0!RpNi<_o@ktI-@2a590stC0zRi%iRR%stvi&hAs3R<K}X~hFddB_6@s8W`5 +zXJ!q~E{TOme<a`8@BW;7?l<?GIp@yo&H2<M-FZ0GKbBAR-Ekx}HvVOrhK1*2?{QsU +zQe#K%JeC=q96gpAKa#$keu^D99ee*0FfB=@F_0J<9-Ch-&BZ5r1T6`{$;1%Fm+qfk +zTr5pfAz@KB*NGlFzEGx2aqh%IxkQOuX*`{wy~+KQo+-}XSE7aaxko77OBtFgoh;4K +z(#-7f<x+WxmKSK)vQFgtt^L+?s+Z<V57E7|^TqOPX{mn0n<VLl#Yf7s_suL*Jl#VB +zmSyz~ScwEVTc-3vd2v6D&dt$;&{?91(o(5>vNXNl&<qW@AghW5NPYw#ha~-b0Dc7_ +z6}t(eHgpwn6<HNi1Vcp^p-07-iXve~MTs!0A_ku!`4nKciajxJYXsOYuuT4N%smA! +zPazgl&bNRSrvAz|_6r3+B;r1=!7D;RUUw8Ke+vNt7E3`(BA-woPvJFBK^3Gzfh4Nk +zOX!J0PJNB)Mk&Z_i?S2ez+iItz=)m79LydX&rM9`3wPaJ`T92=Uv0;g-!<4*M6z%+ +z*omwb#VI+CU&%iFS{_DGS;sE}7G4juqRMCww!+k6=+abJj4v>Dsr*z_6HAP5GJeST +znX2JD;{xLa#;c6KGychVn-L6YXkv6Qx)}Y8&ok1DI~ZSM6dCt39%QUAzRh@o@gqjy +zL0qZ&DhN8ZR3xu$a$Cd{oasU3DNp{CCl6f~PYlq!Hte;Ia0^wn8Vut7>Wl1)s`^E- +z1DhGx<x<9D%6jd%)5>zr8&7h}dMJ3~YBe;)!vVf-T&?{PoMvvRR{!67;Xhz^g^loX +zja+*c-KJJoxbsm3pTE4THs`cgD{Pt+ga3en-i$P#9Wsra(oqRMr;H$4{gxr)9eF(x +zg0v@a7aj}rA^Kf#sNb*>at^>P)5li%ycOq*4e;3~RUj$i1e8=rHi&<Y^Hc>Y_gP4= +zxz9^%q0dLXqC&Bq<&sDScZwvatjRxB=rcJJiYb?w#4Iy2KTk1F6T>T}E@(DNGa>5R +z7&Yv)JdHrRI};pfsKLVj=FE=U*=*T4#ncVktknoGelT||SDY`+9WI_IZE<i@7SnC8 +zN6~Gyo=&><wpzE~>`_>@wb<-RI-lu(_~Oy_Zo6={Cdq!uw(fmyz_u^cB&~5IS7g`U +zdUC}N$J5-C)|`CfUO+?xptr@*hJW$ZhBZk%JaMh_<8!ZGj)z*WU9fcg2`>dT##_?q +z=Ksx}uxo3jTHTq%E1}97UECE@r}nt3I=3R(HOL7jNg>teSM-g$aU#`3jk}#qh;D?6 +zw=CYuA2#mS+vU%0P&u8RCn4)$8VH-2uy#01%VG0WSX&Fz`LMYj)?N<NyJ1t)wHBQY +z=;pYt<#l>gH_zzWS)G2Pn=k3wYdU|DnWmxbG$>`5lZJMWL92%O14BD!(C-cNFNXFH +zgVc!G9?@=&(4mNVcSJiLq3=b^rz6@k5qdFVUW{m$A{2|7d!kxz)VSrcQt@4sDoq^f +z98hXm=YS~qbf<kwigD|YevaR}^`7Jy^x~4_g75ka=c0r}VJF2aEv{=ilPf-mNQBNI +zEMK3YKB+`*xOu>iR|LbzHLa*mLXlH${^b4c9%>9%)HO-?LA1gT0mlz!M}8&;(;^x| +z*H2<VyY>2;juB|7F+k?y(_2~3@STqQ@f^sqD2c8g3x>ciM%siMq~;pKwfE57kw2K@ +z!-ZN0QTVOP@aA5@fEGKjy2+D`t?2KzpPyRQ`JcmHJoc(<#h<UT;@W$t_d{|;S>vyF +zewtgef*II~y;k>*B!+(8*blXsY-~kcJa9zG2yfcMCt+|-0ex$pY`h1<*#rEv=~*<+ +ztV``Um!q33-Aap9fUshX^N~GS2@X3^U9+MwgYQ74^?~6&yU^#oY#cvC9R_}P2d<wN +zJvOE)Xr7A2n#3x14}2_g(YN^0+oYDbb#|V{ze3pzGb9FiF#6Ra&L}bT(ZOvswS7RY +zxLjWFRwWXHR5&={t;%K+Vkd6NX2iF<SF)LXv@y472OmG!_W%Ni*ZDuev-S0%b!dfW +wz4{IL!+uT9t2XI4@_L@?Ri*bc_<n8A+wHaowmq=zfo%_LdtloGpN<DU00~N<ApigX + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c +new file mode 100644 +index 0000000000..ff83db095b +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <bootblock_common.h> ++#include <device/pci_ops.h> ++#include <ec/dell/mec5035/mec5035.h> ++#include <southbridge/intel/bd82x6x/pch.h> ++ ++void bootblock_mainboard_early_init(void) ++{ ++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN ++ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN ++ | COMB_LPC_EN | COMA_LPC_EN); ++ mec5035_early_init(); ++} +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c +new file mode 100644 +index 0000000000..777570765a +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c +@@ -0,0 +1,192 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_GPIO, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_NATIVE, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio1 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio28 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++ .gpio30 = GPIO_RESET_RSMRST, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio0 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++ .gpio13 = GPIO_INVERT, ++ .gpio14 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_GPIO, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_NATIVE, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_OUTPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio45 = GPIO_DIR_OUTPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_INPUT, ++ .gpio51 = GPIO_DIR_INPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio34 = GPIO_LEVEL_HIGH, ++ .gpio45 = GPIO_LEVEL_LOW, ++ .gpio60 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_GPIO, ++ .gpio69 = GPIO_MODE_GPIO, ++ .gpio70 = GPIO_MODE_GPIO, ++ .gpio71 = GPIO_MODE_GPIO, ++ .gpio72 = GPIO_MODE_NATIVE, ++ .gpio73 = GPIO_MODE_NATIVE, ++ .gpio74 = GPIO_MODE_NATIVE, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio68 = GPIO_DIR_INPUT, ++ .gpio69 = GPIO_DIR_INPUT, ++ .gpio70 = GPIO_DIR_INPUT, ++ .gpio71 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c +new file mode 100644 +index 0000000000..804733b172 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ 0x111d76df, /* Codec Vendor / Device ID: IDT */ ++ 0x10280533, /* Subsystem ID */ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x10280533), ++ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), ++ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), ++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), ++ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), ++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), ++ ++ 0x80862806, /* Codec Vendor / Device ID: Intel */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(3, 0x80860101), ++ AZALIA_PIN_CFG(3, 0x05, 0x18560010), ++ AZALIA_PIN_CFG(3, 0x06, 0x18560020), ++ AZALIA_PIN_CFG(3, 0x07, 0x18560030), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb +new file mode 100644 +index 0000000000..4125159367 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb +@@ -0,0 +1,37 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/sandybridge ++ device domain 0 on ++ subsystemid 0x1028 0x0533 inherit ++ ++ device ref igd on ++ register "gpu_cpu_backlight" = "0x00001312" ++ register "gpu_pch_backlight" = "0x13121312" ++ end ++ ++ chip southbridge/intel/bd82x6x ++ register "usb_port_config" = "{ ++ { 1, 2, 0 }, ++ { 1, 0, 0 }, ++ { 1, 0, 1 }, ++ { 1, 1, 1 }, ++ { 1, 1, 2 }, ++ { 1, 1, 2 }, ++ { 1, 2, 3 }, ++ { 1, 2, 3 }, ++ { 1, 2, 4 }, ++ { 1, 1, 4 }, ++ { 1, 1, 5 }, ++ { 1, 1, 5 }, ++ { 1, 2, 6 }, ++ { 1, 0, 6 }, ++ }" ++ ++ device ref xhci on ++ register "superspeed_capable_ports" = "0x0000000f" ++ register "xhci_overcurrent_mapping" = "0x00000c03" ++ register "xhci_switchable_ports" = "0x0000000f" ++ end ++ end ++ end ++end +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch b/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch deleted file mode 100644 index 33d743f1..00000000 --- a/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch +++ /dev/null @@ -1,792 +0,0 @@ -From 973783a989cdcb7b77029e369156c81eefe8cc67 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Sat, 19 Aug 2023 16:19:10 -0600 -Subject: [PATCH 26/30] mb/dell: Add Latitude E6530 (Ivy Bridge) - -Mainboard is QALA0/LA-7761P (UMA). The dGPU model was not tested. This -is based on the autoport output with some manual tweaks. The flash is -8MiB + 4MiB. It can be internally flashed by sending a command to the -EC, which causes the EC to pull the FDO pin low and the firmware to skip -setting up any chipset based write protections. [1] The EC is the SMSC -MEC5055, which seems to be compatible with the existing MEC5035 code. - -[1] https://gitlab.com/nic3-14159/dell-flash-unlock - -Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 -Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> ---- - src/mainboard/dell/e6530/Kconfig | 37 ++++ - src/mainboard/dell/e6530/Kconfig.name | 2 + - src/mainboard/dell/e6530/Makefile.inc | 6 + - src/mainboard/dell/e6530/acpi/ec.asl | 9 + - src/mainboard/dell/e6530/acpi/platform.asl | 12 ++ - src/mainboard/dell/e6530/acpi/superio.asl | 3 + - src/mainboard/dell/e6530/acpi_tables.c | 16 ++ - src/mainboard/dell/e6530/board_info.txt | 6 + - src/mainboard/dell/e6530/cmos.default | 9 + - src/mainboard/dell/e6530/cmos.layout | 88 ++++++++++ - src/mainboard/dell/e6530/data.vbt | Bin 0 -> 4280 bytes - src/mainboard/dell/e6530/devicetree.cb | 68 ++++++++ - src/mainboard/dell/e6530/dsdt.asl | 30 ++++ - src/mainboard/dell/e6530/early_init.c | 38 ++++ - src/mainboard/dell/e6530/gma-mainboard.ads | 20 +++ - src/mainboard/dell/e6530/gpio.c | 192 +++++++++++++++++++++ - src/mainboard/dell/e6530/hda_verb.c | 33 ++++ - src/mainboard/dell/e6530/mainboard.c | 21 +++ - 18 files changed, 590 insertions(+) - create mode 100644 src/mainboard/dell/e6530/Kconfig - create mode 100644 src/mainboard/dell/e6530/Kconfig.name - create mode 100644 src/mainboard/dell/e6530/Makefile.inc - create mode 100644 src/mainboard/dell/e6530/acpi/ec.asl - create mode 100644 src/mainboard/dell/e6530/acpi/platform.asl - create mode 100644 src/mainboard/dell/e6530/acpi/superio.asl - create mode 100644 src/mainboard/dell/e6530/acpi_tables.c - create mode 100644 src/mainboard/dell/e6530/board_info.txt - create mode 100644 src/mainboard/dell/e6530/cmos.default - create mode 100644 src/mainboard/dell/e6530/cmos.layout - create mode 100644 src/mainboard/dell/e6530/data.vbt - create mode 100644 src/mainboard/dell/e6530/devicetree.cb - create mode 100644 src/mainboard/dell/e6530/dsdt.asl - create mode 100644 src/mainboard/dell/e6530/early_init.c - create mode 100644 src/mainboard/dell/e6530/gma-mainboard.ads - create mode 100644 src/mainboard/dell/e6530/gpio.c - create mode 100644 src/mainboard/dell/e6530/hda_verb.c - create mode 100644 src/mainboard/dell/e6530/mainboard.c - -diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig -new file mode 100644 -index 0000000000..582adddbd4 ---- /dev/null -+++ b/src/mainboard/dell/e6530/Kconfig -@@ -0,0 +1,37 @@ -+if BOARD_DELL_LATITUDE_E6530 -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ select BOARD_ROMSIZE_KB_12288 -+ select EC_ACPI -+ select EC_DELL_MEC5035 -+ select GFX_GMA_PANEL_1_ON_LVDS -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ select INTEL_GMA_HAVE_VBT -+ select INTEL_INT15 -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_USES_IFD_GBE_REGION -+ select NORTHBRIDGE_INTEL_SANDYBRIDGE -+ select SERIRQ_CONTINUOUS_MODE -+ select SOUTHBRIDGE_INTEL_C216 -+ select SYSTEM_TYPE_LAPTOP -+ select USE_NATIVE_RAMINIT -+ -+config MAINBOARD_DIR -+ default "dell/e6530" -+ -+config MAINBOARD_PART_NUMBER -+ default "Latitude E6530" -+ -+config VGA_BIOS_ID -+ default "8086,0166" -+ -+config DRAM_RESET_GATE_GPIO -+ default 60 -+ -+config USBDEBUG_HCD_INDEX -+ default 2 -+endif -diff --git a/src/mainboard/dell/e6530/Kconfig.name b/src/mainboard/dell/e6530/Kconfig.name -new file mode 100644 -index 0000000000..01ed76d107 ---- /dev/null -+++ b/src/mainboard/dell/e6530/Kconfig.name -@@ -0,0 +1,2 @@ -+config BOARD_DELL_LATITUDE_E6530 -+ bool "Latitude E6530" -diff --git a/src/mainboard/dell/e6530/Makefile.inc b/src/mainboard/dell/e6530/Makefile.inc -new file mode 100644 -index 0000000000..ba64e93eb8 ---- /dev/null -+++ b/src/mainboard/dell/e6530/Makefile.inc -@@ -0,0 +1,6 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+bootblock-y += early_init.c -+bootblock-y += gpio.c -+romstage-y += early_init.c -+romstage-y += gpio.c -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -diff --git a/src/mainboard/dell/e6530/acpi/ec.asl b/src/mainboard/dell/e6530/acpi/ec.asl -new file mode 100644 -index 0000000000..0d429410a9 ---- /dev/null -+++ b/src/mainboard/dell/e6530/acpi/ec.asl -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Device(EC) -+{ -+ Name (_HID, EISAID("PNP0C09")) -+ Name (_UID, 0) -+ Name (_GPE, 16) -+/* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e6530/acpi/platform.asl b/src/mainboard/dell/e6530/acpi/platform.asl -new file mode 100644 -index 0000000000..2d24bbd9b9 ---- /dev/null -+++ b/src/mainboard/dell/e6530/acpi/platform.asl -@@ -0,0 +1,12 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Method(_WAK, 1) -+{ -+ /* FIXME: EC support */ -+ Return(Package() {0, 0}) -+} -+ -+Method(_PTS,1) -+{ -+ /* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e6530/acpi/superio.asl b/src/mainboard/dell/e6530/acpi/superio.asl -new file mode 100644 -index 0000000000..55b1db5b11 ---- /dev/null -+++ b/src/mainboard/dell/e6530/acpi/superio.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <drivers/pc80/pc/ps2_controller.asl> -diff --git a/src/mainboard/dell/e6530/acpi_tables.c b/src/mainboard/dell/e6530/acpi_tables.c -new file mode 100644 -index 0000000000..e2759659bf ---- /dev/null -+++ b/src/mainboard/dell/e6530/acpi_tables.c -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <acpi/acpi_gnvs.h> -+#include <soc/nvs.h> -+ -+/* FIXME: check this function. */ -+void mainboard_fill_gnvs(struct global_nvs *gnvs) -+{ -+ /* The lid is open by default. */ -+ gnvs->lids = 1; -+ -+ /* Temperature at which OS will shutdown */ -+ gnvs->tcrt = 100; -+ /* Temperature at which OS will throttle CPU */ -+ gnvs->tpsv = 90; -+} -diff --git a/src/mainboard/dell/e6530/board_info.txt b/src/mainboard/dell/e6530/board_info.txt -new file mode 100644 -index 0000000000..4601a4aaba ---- /dev/null -+++ b/src/mainboard/dell/e6530/board_info.txt -@@ -0,0 +1,6 @@ -+Category: laptop -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2012 -diff --git a/src/mainboard/dell/e6530/cmos.default b/src/mainboard/dell/e6530/cmos.default -new file mode 100644 -index 0000000000..279415dfd1 ---- /dev/null -+++ b/src/mainboard/dell/e6530/cmos.default -@@ -0,0 +1,9 @@ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -+nmi=Enable -+bluetooth=Enable -+wwan=Enable -+wlan=Enable -+sata_mode=AHCI -+me_state=Disabled -diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout -new file mode 100644 -index 0000000000..e85ea4c661 ---- /dev/null -+++ b/src/mainboard/dell/e6530/cmos.layout -@@ -0,0 +1,88 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+#400 8 r 0 reserved for century byte -+ -+# coreboot config options: southbridge -+408 1 e 1 nmi -+409 2 e 7 power_on_after_fail -+411 1 e 9 sata_mode -+ -+# coreboot config options: EC -+412 1 e 1 bluetooth -+413 1 e 1 wwan -+415 1 e 1 wlan -+ -+# coreboot config options: ME -+424 1 e 14 me_state -+425 2 h 0 me_state_prev -+ -+# coreboot config options: northbridge -+432 3 e 11 gfx_uma_size -+435 2 e 12 hybrid_graphics_mode -+440 8 h 0 volume -+ -+# VBOOT -+448 128 r 0 vbnv -+ -+# SandyBridge MRC Scrambler Seed values -+896 32 r 0 mrc_scrambler_seed -+928 32 r 0 mrc_scrambler_seed_s3 -+960 16 r 0 mrc_scrambler_seed_chk -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+2 0 Enable -+2 1 Disable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+9 0 AHCI -+9 1 Compatible -+11 0 32M -+11 1 64M -+11 2 96M -+11 3 128M -+11 4 160M -+11 5 192M -+11 6 224M -+14 0 Normal -+14 1 Disabled -+ -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 447 984 -diff --git a/src/mainboard/dell/e6530/data.vbt b/src/mainboard/dell/e6530/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..af64a913d521fe240ce30e114e90fe75d3841bbc -GIT binary patch -literal 4280 -zcmdT{U2GiH75-*te`aTAcGqJQY$rA+e`ZbWcy_TDH@NC}cbl$*NjAn^RtPm->J7GV -zY_m3jN`RN*h9FvG3Do9+qP$c^s1;PLB3@br9>Ag%La5?TLP`-2DDaR65U2_)=g!QU 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-zbX%CHpm`!1Z4$d28~9k{rfu-0w@xg6{q!u2{)Dm_))4RK$?#7P*t7V+g_9d<V!MD` -zaj`t-?uy6zsjzp<-IdM6g(XhQX2iF<+p?Kmw6?a+f^VMex*PuetNfqf+4_FpD%8TW -eZvUbDHC^NLu5~gtzg|!EqSkX2ep9pg!tpEeo1jDh - -literal 0 -HcmV?d00001 - -diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb -new file mode 100644 -index 0000000000..96eed178c5 ---- /dev/null -+++ b/src/mainboard/dell/e6530/devicetree.cb -@@ -0,0 +1,68 @@ -+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. -+ register "gfx" = "GMA_STATIC_DISPLAYS(1)" -+ register "gpu_cpu_backlight" = "0x00000251" -+ register "gpu_dp_b_hotplug" = "4" -+ register "gpu_dp_c_hotplug" = "4" -+ register "gpu_dp_d_hotplug" = "4" -+ register "gpu_panel_port_select" = "0" -+ register "gpu_panel_power_backlight_off_delay" = "2300" -+ register "gpu_panel_power_backlight_on_delay" = "2300" -+ register "gpu_panel_power_cycle_delay" = "6" -+ register "gpu_panel_power_down_delay" = "400" -+ register "gpu_panel_power_up_delay" = "400" -+ register "gpu_pch_backlight" = "0x13121312" -+ -+ device domain 0x0 on -+ subsystemid 0x1028 0x0535 inherit -+ -+ device ref host_bridge on end # Host bridge -+ device ref peg10 off end # PEG -+ device ref igd on end # iGPU -+ -+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH -+ register "docking_supported" = "1" -+ register "gen1_dec" = "0x007c0681" -+ register "gen2_dec" = "0x005c0921" -+ register "gen3_dec" = "0x003c07e1" -+ register "gen4_dec" = "0x007c0901" -+ register "gpi0_routing" = "2" -+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }" -+ register "pcie_port_coalesce" = "1" -+ register "sata_interface_speed_support" = "0x3" -+ register "sata_port_map" = "0x33" -+ register "spi_lvscc" = "0x2005" -+ register "spi_uvscc" = "0x2005" -+ register "superspeed_capable_ports" = "0x0000000f" -+ register "xhci_overcurrent_mapping" = "0x00000c03" -+ register "xhci_switchable_ports" = "0x0000000f" -+ -+ device ref xhci on end # USB 3.0 Controller -+ device ref mei1 off end # Management Engine Interface 1 -+ device ref mei2 off end # Management Engine Interface 2 -+ device ref me_ide_r off end # Management Engine IDE-R -+ device ref me_kt on end # Management Engine KT -+ device ref gbe on end # Intel Gigabit Ethernet -+ device ref ehci2 on end # USB2 EHCI #2 -+ device ref hda on end # High Definition Audio -+ device ref pcie_rp1 on end # PCIe Port #1 -+ device ref pcie_rp2 on end # PCIe Port #2 -+ device ref pcie_rp3 on end # PCIe Port #3 -+ device ref pcie_rp4 on end # PCIe Port #4 -+ device ref pcie_rp5 off end # PCIe Port #5 -+ device ref pcie_rp6 on end # PCIe Port #6 -+ device ref pcie_rp7 off end # PCIe Port #7 -+ device ref pcie_rp8 off end # PCIe Port #8 -+ device ref ehci1 on end # USB2 EHCI #1 -+ device ref pci_bridge off end # PCI bridge -+ device ref lpc on # LPC bridge -+ chip ec/dell/mec5035 -+ device pnp ff.0 on end -+ end -+ end -+ device ref sata1 on end # SATA Controller 1 -+ device ref smbus on end # SMBus -+ device ref sata2 off end # SATA Controller 2 -+ device ref thermal off end # Thermal -+ end -+ end -+end -diff --git a/src/mainboard/dell/e6530/dsdt.asl b/src/mainboard/dell/e6530/dsdt.asl -new file mode 100644 -index 0000000000..7d13c55b08 ---- /dev/null -+++ b/src/mainboard/dell/e6530/dsdt.asl -@@ -0,0 +1,30 @@ -+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+ -+#include <acpi/acpi.h> -+ -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20141018 /* OEM revision */ -+) -+{ -+ #include <acpi/dsdt_top.asl> -+ #include "acpi/platform.asl" -+ #include <cpu/intel/common/acpi/cpu.asl> -+ #include <southbridge/intel/common/acpi/platform.asl> -+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> -+ #include <southbridge/intel/common/acpi/sleepstates.asl> -+ -+ Device (\_SB.PCI0) -+ { -+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> -+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl> -+ #include <southbridge/intel/bd82x6x/acpi/pch.asl> -+ } -+} -diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c -new file mode 100644 -index 0000000000..d57f48e7f1 ---- /dev/null -+++ b/src/mainboard/dell/e6530/early_init.c -@@ -0,0 +1,38 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+ -+#include <bootblock_common.h> -+#include <device/pci_ops.h> -+#include <ec/dell/mec5035/mec5035.h> -+#include <northbridge/intel/sandybridge/raminit_native.h> -+#include <southbridge/intel/bd82x6x/pch.h> -+ -+const struct southbridge_usb_port mainboard_usb_ports[] = { -+ { 1, 1, 0 }, -+ { 1, 1, 0 }, -+ { 1, 1, 1 }, -+ { 1, 1, 1 }, -+ { 1, 1, 2 }, -+ { 1, 1, 2 }, -+ { 1, 0, 3 }, -+ { 1, 1, 3 }, -+ { 1, 1, 4 }, -+ { 1, 1, 4 }, -+ { 1, 1, 5 }, -+ { 1, 1, 5 }, -+ { 1, 2, 6 }, -+ { 1, 2, 6 }, -+}; -+ -+void bootblock_mainboard_early_init(void) -+{ -+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f); -+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); -+ mec5035_early_init(); -+} -+ -+void mainboard_get_spd(spd_raw_data *spd, bool id_only) -+{ -+ read_spd(&spd[0], 0x50, id_only); -+ read_spd(&spd[2], 0x52, id_only); -+} -diff --git a/src/mainboard/dell/e6530/gma-mainboard.ads b/src/mainboard/dell/e6530/gma-mainboard.ads -new file mode 100644 -index 0000000000..1310830c8e ---- /dev/null -+++ b/src/mainboard/dell/e6530/gma-mainboard.ads -@@ -0,0 +1,20 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ ( -+ HDMI1, -- mainboard HDMI -+ DP2, -- dock DP -+ DP3, -- dock DP -+ Analog, --mainboard VGA -+ LVDS, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/e6530/gpio.c b/src/mainboard/dell/e6530/gpio.c -new file mode 100644 -index 0000000000..777570765a ---- /dev/null -+++ b/src/mainboard/dell/e6530/gpio.c -@@ -0,0 +1,192 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <southbridge/intel/common/gpio.h> -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_GPIO, -+ .gpio1 = GPIO_MODE_GPIO, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_NATIVE, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_GPIO, -+ .gpio8 = GPIO_MODE_GPIO, -+ .gpio9 = GPIO_MODE_NATIVE, -+ .gpio10 = GPIO_MODE_NATIVE, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_GPIO, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_GPIO, -+ .gpio18 = GPIO_MODE_NATIVE, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_NATIVE, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_NATIVE, -+ .gpio31 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio0 = GPIO_DIR_INPUT, -+ .gpio1 = GPIO_DIR_INPUT, -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio7 = GPIO_DIR_INPUT, -+ .gpio8 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio15 = GPIO_DIR_INPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio17 = GPIO_DIR_INPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_OUTPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio28 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_reset = { -+ .gpio30 = GPIO_RESET_RSMRST, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio0 = GPIO_INVERT, -+ .gpio8 = GPIO_INVERT, -+ .gpio13 = GPIO_INVERT, -+ .gpio14 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_NATIVE, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_GPIO, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_GPIO, -+ .gpio52 = GPIO_MODE_GPIO, -+ .gpio53 = GPIO_MODE_NATIVE, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_NATIVE, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_OUTPUT, -+ .gpio35 = GPIO_DIR_INPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio45 = GPIO_DIR_OUTPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_INPUT, -+ .gpio51 = GPIO_DIR_INPUT, -+ .gpio52 = GPIO_DIR_INPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio34 = GPIO_LEVEL_HIGH, -+ .gpio45 = GPIO_LEVEL_LOW, -+ .gpio60 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_reset = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_NATIVE, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_NATIVE, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_GPIO, -+ .gpio69 = GPIO_MODE_GPIO, -+ .gpio70 = GPIO_MODE_GPIO, -+ .gpio71 = GPIO_MODE_GPIO, -+ .gpio72 = GPIO_MODE_NATIVE, -+ .gpio73 = GPIO_MODE_NATIVE, -+ .gpio74 = GPIO_MODE_NATIVE, -+ .gpio75 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio68 = GPIO_DIR_INPUT, -+ .gpio69 = GPIO_DIR_INPUT, -+ .gpio70 = GPIO_DIR_INPUT, -+ .gpio71 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_reset = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ .reset = &pch_gpio_set1_reset, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ .reset = &pch_gpio_set2_reset, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ .reset = &pch_gpio_set3_reset, -+ }, -+}; -diff --git a/src/mainboard/dell/e6530/hda_verb.c b/src/mainboard/dell/e6530/hda_verb.c -new file mode 100644 -index 0000000000..9de7e34311 ---- /dev/null -+++ b/src/mainboard/dell/e6530/hda_verb.c -@@ -0,0 +1,33 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/azalia_device.h> -+ -+const u32 cim_verb_data[] = { -+ 0x111d76df, /* Codec Vendor / Device ID: IDT */ -+ 0x10280535, /* Subsystem ID */ -+ 11, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(0, 0x10280535), -+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), -+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), -+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), -+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), -+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), -+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), -+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), -+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), -+ -+ 0x80862806, /* Codec Vendor / Device ID: Intel */ -+ 0x80860101, /* Subsystem ID */ -+ 4, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(3, 0x80860101), -+ AZALIA_PIN_CFG(3, 0x05, 0x18560010), -+ AZALIA_PIN_CFG(3, 0x06, 0x18560020), -+ AZALIA_PIN_CFG(3, 0x07, 0x18560030), -+ -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/e6530/mainboard.c b/src/mainboard/dell/e6530/mainboard.c -new file mode 100644 -index 0000000000..31e49802fc ---- /dev/null -+++ b/src/mainboard/dell/e6530/mainboard.c -@@ -0,0 +1,21 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/device.h> -+#include <drivers/intel/gma/int15.h> -+#include <southbridge/intel/bd82x6x/pch.h> -+#include <ec/acpi/ec.h> -+#include <console/console.h> -+#include <pc80/keyboard.h> -+ -+static void mainboard_enable(struct device *dev) -+{ -+ -+ /* FIXME: fix these values. */ -+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, -+ GMA_INT15_PANEL_FIT_DEFAULT, -+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -+} -+ -+struct chip_operations mainboard_ops = { -+ .enable_dev = mainboard_enable, -+}; --- -2.39.2 - diff --git a/config/coreboot/default/patches/0027-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch b/config/coreboot/default/patches/0027-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch new file mode 100644 index 00000000..6e49c8c2 --- /dev/null +++ b/config/coreboot/default/patches/0027-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch @@ -0,0 +1,440 @@ +From 611b5b3b4794eeda7ffb0a1876e1033705c50545 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Thu, 26 Oct 2017 21:26:43 +0800 +Subject: [PATCH 27/39] mb/dell: Add Latitude E6230 (Ivy Bridge) + +This was adapted from CB:22693 from Iru Cai, which was based on +autoport. I do not physically have this system. Someone with physical +access to an E6230 running version A11 of the vendor firmware sent me +the VBT after running the command `intelvbttool --inlegacy --outvbt +data.vbt`. This new version of the port has not yet been tested. + +The EC is the SMSC MEC5055, which seems to be compatible with the +existing MEC5035 code. As with the other Dell systems with this EC, this +board is assumed to be internally flashable using an EC command that +tells it to pull the FDO pin low on the next boot, which also tells the +vendor firmware to disable all write protections to the flash [1]. + +[1] https://gitlab.com/nic3-14159/dell-flash-unlock + +Original-Change-Id: I8cdc01e902e670310628809416290045c2102340 +Change-Id: I32927beea7c29b96a851ab77ed15b0160f16d369 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/snb_ivb_latitude/Kconfig | 11 +- + .../dell/snb_ivb_latitude/Kconfig.name | 3 + + .../snb_ivb_latitude/variants/e6230/data.vbt | Bin 0 -> 4280 bytes + .../variants/e6230/early_init.c | 12 ++ + .../snb_ivb_latitude/variants/e6230/gpio.c | 193 ++++++++++++++++++ + .../variants/e6230/hda_verb.c | 32 +++ + .../variants/e6230/overridetree.cb | 40 ++++ + 7 files changed, 290 insertions(+), 1 deletion(-) + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb + +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig +index 49bf225fe2..f6e097930b 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig +@@ -56,6 +56,12 @@ config BOARD_DELL_LATITUDE_E5530 + select BOARD_ROMSIZE_KB_12288 + select SOUTHBRIDGE_INTEL_C216 + ++config BOARD_DELL_LATITUDE_E6230 ++ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON ++ select BOARD_ROMSIZE_KB_12288 ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select SOUTHBRIDGE_INTEL_C216 ++ + config BOARD_DELL_LATITUDE_E6330 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_12288 +@@ -90,6 +96,7 @@ config MAINBOARD_PART_NUMBER + default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 + default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520 + default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530 ++ default "Latitude E6230" if BOARD_DELL_LATITUDE_E6230 + default "Latitude E6330" if BOARD_DELL_LATITUDE_E6330 + default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430 + default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530 +@@ -108,6 +115,7 @@ config VARIANT_DIR + default "e6420" if BOARD_DELL_LATITUDE_E6420 + default "e6520" if BOARD_DELL_LATITUDE_E6520 + default "e5530" if BOARD_DELL_LATITUDE_E5530 ++ default "e6230" if BOARD_DELL_LATITUDE_E6230 + default "e6330" if BOARD_DELL_LATITUDE_E6330 + default "e6430" if BOARD_DELL_LATITUDE_E6430 + default "e6530" if BOARD_DELL_LATITUDE_E6530 +@@ -121,7 +129,8 @@ config VGA_BIOS_ID + || BOARD_DELL_LATITUDE_E5520 \ + || BOARD_DELL_LATITUDE_E6220 \ + || BOARD_DELL_LATITUDE_E6320 +- default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \ ++ default "8086,0166" if BOARD_DELL_LATITUDE_E6230 \ ++ || BOARD_DELL_LATITUDE_E6430 \ + || BOARD_DELL_LATITUDE_E6530 + + endif +diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +index d6fc8eb224..cb7bbd5cdb 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name ++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +@@ -21,6 +21,9 @@ config BOARD_DELL_LATITUDE_E6520 + config BOARD_DELL_LATITUDE_E5530 + bool "Latitude E5530" + ++config BOARD_DELL_LATITUDE_E6230 ++ bool "Latitude E6230" ++ + config BOARD_DELL_LATITUDE_E6330 + bool "Latitude E6330" + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..45ce8f435eea647a0bddaab3fd1e9282c87afc66 +GIT binary patch +literal 4280 +zcmdT{Yiu0V75-*tAG5PFyX&zDekA7P<*tbx&o1`j23L%CmvkLWvN7(mLa6alZ?J`9 +zo3#m4YVlG`2;w12Ajppt<qra(R;8*G@uw*8gIcsg2vxi!q_pBkmGUD$s9IGi+jD1T +zO`Kg43n@JA>~|mMp8L%`XU@4ZyCa_(r`z|Z`bP4p-rEkOMn-R;Ntk#o`b)0sOKRl6 +z?T0eM<HLtiqX*Kr(o5Kc<Iyk90h5ws=!y8i;K=M^X(l$-Eoeyyj>ZS*@LZWP#hD{> +z<r2jcJ;b8e!oAb;^QB2D#7*krI^IpA=?ra8?xvqj6=&}$QL2a1J(QuD($UfkElf=x +zUM!UtXmO4PP4h^;&)jWJvd(Pj0lIs7wpgAnE!1!MB1w8~{^#ZCd!`mCmhPs6X_~zW +zGae^<%aoog&+n$;nHd@rItw&bS}2u|mL_-Ws;&ZOWW_51k`IALAW8pAz~@C!!B)bs +z1x-OrK~}*8L07Po(5+xZL6I<}phTEf5QRsVJYHa{f^AWEV+2@lvrPVS%snsOn?N)w +zpKbvwOnk&Q_6Y?aB;r1=!TYwts;yA@BnbFfECo!7JVJq7g^yhYMUV;wlBjksp(hI2 +z^<}E7r698{-pw!*{mH>SLslxYH@j~%H#VLx+<8~!;a@$n+>Q%xHrQ8KGI21_iL4sI +zF*$}m$R7Mr9z@Z*ir@Q9eClsSmC+t(g`q~VQ&nIxZenav_^Buc78s8*o@e|<QE{4a +zhVeGz1IFJN|784&5eTYiVstQeGWr-lWTY9lG45a#8TT^oXDl%uXFS9BHN$^DE>t}g +z1Z-O>lG`>pEuvmL-HpmgSANo!2hWQq2B>Zua$8%tfvQ>!1n@=m9ri_4`H|Rx#SH9n +zDdRF_-FDP&WjW`L$GK%a6x?yO8l2!^g0HJrtA7TknNzCO?|U!wCv2^-5pJ%LW6!+P +z)anX%E>`gP%3Er4c6+J9x=Atk1{Abrr1|WSY3P`SO5j!R5F*vbbQ%AaSHnR_+x&Op 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+zt*M!5u?i4YtZ+WECo6$LJF06|G-mMZskGiV*lQJf-ItB+hltI<?{5E<^P=0rL<P+g +z(P)!c<?MlvMK0O~UwZ4*;x|ms(&&#Vn_-4{KM#g~a=;$N2QD7mSX0{t<cf>sId@e& +z-cN<SWA3VKCN6g3lx#+PySpWu*+pw}>vr(fgI)K*zkikg6TDJi?^}ghc*U*%A%EGg +Y$$8Z}9a~<{Q@y10T!W`-d%n2+Kj)*Kg#Z8m + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c +new file mode 100644 +index 0000000000..24c1b32467 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c +@@ -0,0 +1,12 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <bootblock_common.h> ++#include <device/pci_ops.h> ++#include <ec/dell/mec5035/mec5035.h> ++#include <southbridge/intel/bd82x6x/pch.h> ++ ++void bootblock_mainboard_early_init(void) ++{ ++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); ++ mec5035_early_init(); ++} +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c +new file mode 100644 +index 0000000000..c07e4b1c56 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c +@@ -0,0 +1,193 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_GPIO, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_NATIVE, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio1 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_OUTPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio17 = GPIO_LEVEL_HIGH, ++ .gpio28 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++ .gpio30 = GPIO_RESET_RSMRST, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio0 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++ .gpio13 = GPIO_INVERT, ++ .gpio14 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_GPIO, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_NATIVE, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_OUTPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio45 = GPIO_DIR_OUTPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_INPUT, ++ .gpio51 = GPIO_DIR_INPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio34 = GPIO_LEVEL_HIGH, ++ .gpio45 = GPIO_LEVEL_LOW, ++ .gpio60 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_GPIO, ++ .gpio69 = GPIO_MODE_GPIO, ++ .gpio70 = GPIO_MODE_GPIO, ++ .gpio71 = GPIO_MODE_GPIO, ++ .gpio72 = GPIO_MODE_NATIVE, ++ .gpio73 = GPIO_MODE_NATIVE, ++ .gpio74 = GPIO_MODE_NATIVE, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio68 = GPIO_DIR_INPUT, ++ .gpio69 = GPIO_DIR_INPUT, ++ .gpio70 = GPIO_DIR_INPUT, ++ .gpio71 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c +new file mode 100644 +index 0000000000..f6876f9e09 +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ 0x111d76df, /* Codec Vendor / Device ID: IDT */ ++ 0x10280532, /* Subsystem ID */ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x10280532), ++ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), ++ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), ++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), ++ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), ++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), ++ ++ 0x80862806, /* Codec Vendor / Device ID: Intel */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(3, 0x80860101), ++ AZALIA_PIN_CFG(3, 0x05, 0x18560010), ++ AZALIA_PIN_CFG(3, 0x06, 0x18560020), ++ AZALIA_PIN_CFG(3, 0x07, 0x18560030), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb +new file mode 100644 +index 0000000000..3a0fa720da +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb +@@ -0,0 +1,40 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/sandybridge ++ device domain 0 on ++ subsystemid 0x1028 0x0532 inherit ++ ++ device ref igd on ++ register "gpu_cpu_backlight" = "0x000009e9" ++ register "gpu_pch_backlight" = "0x13121312" ++ end ++ ++ chip southbridge/intel/bd82x6x ++ register "usb_port_config" = "{ ++ { 1, 1, 0 }, ++ { 1, 1, 0 }, ++ { 1, 0, 1 }, ++ { 1, 2, 1 }, ++ { 1, 0, 2 }, ++ { 1, 0, 2 }, ++ { 1, 0, 3 }, ++ { 1, 1, 3 }, ++ { 1, 2, 4 }, ++ { 1, 1, 4 }, ++ { 1, 1, 5 }, ++ { 1, 1, 5 }, ++ { 1, 2, 6 }, ++ { 1, 0, 6 }, ++ }" ++ ++ device ref xhci on ++ register "superspeed_capable_ports" = "0x0000000f" ++ register "xhci_overcurrent_mapping" = "0x00000c03" ++ register "xhci_switchable_ports" = "0x0000000f" ++ end ++ device ref sata1 on ++ register "sata_port_map" = "0x31" ++ end ++ end ++ end ++end +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0027-rebase-dell-e6530-to-newer-coreboot-code.patch b/config/coreboot/default/patches/0027-rebase-dell-e6530-to-newer-coreboot-code.patch deleted file mode 100644 index 130984fb..00000000 --- a/config/coreboot/default/patches/0027-rebase-dell-e6530-to-newer-coreboot-code.patch +++ /dev/null @@ -1,145 +0,0 @@ -From 88652afd52b0a8e0fc8bb1656e59d8ae4796d847 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Thu, 25 Jan 2024 14:30:03 +0000 -Subject: [PATCH 27/30] rebase dell/e6530 to newer coreboot code - -i diffed nicholas's current e6430 patch, versus the old one, -prior to this revision update in lbmk, also cross referencing -the original e6430 and e6530 patches, diffing them, and the -result in this patch. most notably, spd data is now defined in -the devicetree, instead of early_init.c as per: - -commit 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da -Author: Keith Hui <buurin@gmail.com> -Date: Sat Jul 22 12:49:05 2023 -0400 - mb/*: Update SPD mapping for sandybridge boards - -This should work fine. Will test after this builds. - -Signed-off-by: Leah Rowe <info@minifree.org> ---- - src/mainboard/dell/e6530/Kconfig | 15 +++++++++++---- - src/mainboard/dell/e6530/cmos.layout | 2 +- - src/mainboard/dell/e6530/devicetree.cb | 8 +++++--- - src/mainboard/dell/e6530/early_init.c | 12 +++--------- - 4 files changed, 20 insertions(+), 17 deletions(-) - -diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig -index 582adddbd4..a104566890 100644 ---- a/src/mainboard/dell/e6530/Kconfig -+++ b/src/mainboard/dell/e6530/Kconfig -@@ -20,18 +20,25 @@ config BOARD_SPECIFIC_OPTIONS - select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT - -+config DRAM_RESET_GATE_GPIO -+ default 60 -+ - config MAINBOARD_DIR - default "dell/e6530" - - config MAINBOARD_PART_NUMBER - default "Latitude E6530" - --config VGA_BIOS_ID -- default "8086,0166" -+config PS2K_EISAID -+ default "PNP0303" - --config DRAM_RESET_GATE_GPIO -- default 60 -+config PS2M_EISAID -+ default "PNP0F13" - - config USBDEBUG_HCD_INDEX - default 2 -+ -+config VGA_BIOS_ID -+ default "8086,0166" -+ - endif -diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout -index e85ea4c661..1aa7e77bce 100644 ---- a/src/mainboard/dell/e6530/cmos.layout -+++ b/src/mainboard/dell/e6530/cmos.layout -@@ -25,7 +25,7 @@ entries - # coreboot config options: EC - 412 1 e 1 bluetooth - 413 1 e 1 wwan --415 1 e 1 wlan -+414 1 e 1 wlan - - # coreboot config options: ME - 424 1 e 14 me_state -diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb -index 96eed178c5..37135bcf0f 100644 ---- a/src/mainboard/dell/e6530/devicetree.cb -+++ b/src/mainboard/dell/e6530/devicetree.cb -@@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. - register "gpu_panel_power_up_delay" = "400" - register "gpu_pch_backlight" = "0x13121312" - -+ register "spd_addresses" = "{0x50, 0, 0x52, 0}" -+ - device domain 0x0 on - subsystemid 0x1028 0x0535 inherit - -@@ -24,7 +26,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. - register "gen1_dec" = "0x007c0681" - register "gen2_dec" = "0x005c0921" - register "gen3_dec" = "0x003c07e1" -- register "gen4_dec" = "0x007c0901" -+ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC - register "gpi0_routing" = "2" - register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" -@@ -37,7 +39,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. - register "xhci_switchable_ports" = "0x0000000f" - - device ref xhci on end # USB 3.0 Controller -- device ref mei1 off end # Management Engine Interface 1 -+ device ref mei1 on end # Management Engine Interface 1 - device ref mei2 off end # Management Engine Interface 2 - device ref me_ide_r off end # Management Engine IDE-R - device ref me_kt on end # Management Engine KT -@@ -48,7 +50,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. - device ref pcie_rp2 on end # PCIe Port #2 - device ref pcie_rp3 on end # PCIe Port #3 - device ref pcie_rp4 on end # PCIe Port #4 -- device ref pcie_rp5 off end # PCIe Port #5 -+ device ref pcie_rp5 on end # PCIe Port #5 - device ref pcie_rp6 on end # PCIe Port #6 - device ref pcie_rp7 off end # PCIe Port #7 - device ref pcie_rp8 off end # PCIe Port #8 -diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c -index d57f48e7f1..2b40f6963f 100644 ---- a/src/mainboard/dell/e6530/early_init.c -+++ b/src/mainboard/dell/e6530/early_init.c -@@ -4,7 +4,6 @@ - #include <bootblock_common.h> - #include <device/pci_ops.h> - #include <ec/dell/mec5035/mec5035.h> --#include <northbridge/intel/sandybridge/raminit_native.h> - #include <southbridge/intel/bd82x6x/pch.h> - - const struct southbridge_usb_port mainboard_usb_ports[] = { -@@ -26,13 +25,8 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { - - void bootblock_mainboard_early_init(void) - { -- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f); -- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); -+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN -+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN -+ | COMB_LPC_EN | COMA_LPC_EN); - mec5035_early_init(); - } -- --void mainboard_get_spd(spd_raw_data *spd, bool id_only) --{ -- read_spd(&spd[0], 0x50, id_only); -- read_spd(&spd[2], 0x52, id_only); --} --- -2.39.2 - diff --git a/config/coreboot/default/patches/0021-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0028-HACK-Disable-coreboot-related-BL31-features.patch index 40e1ccee..04e4c6d0 100644 --- a/config/coreboot/default/patches/0021-HACK-Disable-coreboot-related-BL31-features.patch +++ b/config/coreboot/default/patches/0028-HACK-Disable-coreboot-related-BL31-features.patch @@ -1,7 +1,7 @@ -From 70262a5f4bf801814d68f8778ea89b5cd8ef8f9a Mon Sep 17 00:00:00 2001 +From ea6e8749112dee4f458e9cf591e13e9097d56bab Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak <alpernebiyasak@gmail.com> Date: Thu, 22 Jun 2023 16:44:27 +0300 -Subject: [PATCH 21/30] HACK: Disable coreboot related BL31 features +Subject: [PATCH 28/39] HACK: Disable coreboot related BL31 features I don't know why, but removing this BL31 make argument lets gru-kevin power off properly when shut down from Linux. Needs investigation. @@ -10,10 +10,10 @@ power off properly when shut down from Linux. Needs investigation. 1 file changed, 3 deletions(-) diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk -index 538d254ace..18e451d63c 100644 +index cb43897efd..a9e5ff399a 100644 --- a/src/arch/arm64/Makefile.mk +++ b/src/arch/arm64/Makefile.mk -@@ -159,9 +159,6 @@ BL31_MAKEARGS += LOG_LEVEL=40 +@@ -173,9 +173,6 @@ BL31_MAKEARGS += LOG_LEVEL=40 # Always enable crash reporting, even on a release build BL31_MAKEARGS += CRASH_REPORTING=1 diff --git a/config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch b/config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch deleted file mode 100644 index fa7ab40d..00000000 --- a/config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 8705b719573d2159adde10af9c6a4d8806b7d27b Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Thu, 25 Jan 2024 14:37:30 +0000 -Subject: [PATCH 28/30] dell/e6*30: disable the ME device in devicetree - -we neuter anyway. disabling it in devicetree will prevent linux -from ever trying to use it or load a driver for it, and thus -might prevent benign error messages from appearing in dmesg. - -this change was suggested by nicholas when asked on irc. - -Signed-off-by: Leah Rowe <info@minifree.org> ---- - src/mainboard/dell/e6430/devicetree.cb | 4 ++-- - src/mainboard/dell/e6530/devicetree.cb | 4 ++-- - 2 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb -index 054b01c5ac..2b8574c984 100644 ---- a/src/mainboard/dell/e6430/devicetree.cb -+++ b/src/mainboard/dell/e6430/devicetree.cb -@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. - register "xhci_switchable_ports" = "0x0000000f" - - device ref xhci on end -- device ref mei1 on end -+ device ref mei1 off end - device ref mei2 off end - device ref me_ide_r off end -- device ref me_kt on end -+ device ref me_kt off end - device ref gbe on end - device ref ehci2 on end - device ref hda on end -diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb -index 37135bcf0f..010200bb6d 100644 ---- a/src/mainboard/dell/e6530/devicetree.cb -+++ b/src/mainboard/dell/e6530/devicetree.cb -@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. - register "xhci_switchable_ports" = "0x0000000f" - - device ref xhci on end # USB 3.0 Controller -- device ref mei1 on end # Management Engine Interface 1 -+ device ref mei1 off end # Management Engine Interface 1 - device ref mei2 off end # Management Engine Interface 2 - device ref me_ide_r off end # Management Engine IDE-R -- device ref me_kt on end # Management Engine KT -+ device ref me_kt off end # Management Engine KT - device ref gbe on end # Intel Gigabit Ethernet - device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio --- -2.39.2 - diff --git a/config/coreboot/default/patches/0029-use-own-mirror-for-acpica-files.patch b/config/coreboot/default/patches/0029-use-own-mirror-for-acpica-files.patch new file mode 100644 index 00000000..a06a5d23 --- /dev/null +++ b/config/coreboot/default/patches/0029-use-own-mirror-for-acpica-files.patch @@ -0,0 +1,29 @@ +From 5c385ef4b4424ed8c37e549a00866edda960563f Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Wed, 31 Jul 2024 00:03:02 +0100 +Subject: [PATCH 29/39] use own mirror for acpica files + +intel likes to break links for no reason, +so we host our own backups of acpica. + +Signed-off-by: Leah Rowe <info@minifree.org> +--- + util/crossgcc/buildgcc | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc +index ad756652ed..5faff337b4 100755 +--- a/util/crossgcc/buildgcc ++++ b/util/crossgcc/buildgcc +@@ -74,7 +74,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" + MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" + GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" + BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" +-IASL_BASE_URL="https://downloadmirror.intel.com/783534" ++IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica" + # CLANG toolchain archive locations + LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" + CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0023-crank-up-vram-allocation-on-more-intel-boards.patch b/config/coreboot/default/patches/0030-crank-up-vram-allocation-on-more-intel-boards.patch index 7701babf..55c95022 100644 --- a/config/coreboot/default/patches/0023-crank-up-vram-allocation-on-more-intel-boards.patch +++ b/config/coreboot/default/patches/0030-crank-up-vram-allocation-on-more-intel-boards.patch @@ -1,7 +1,7 @@ -From ad812d008d570c1655bff13a9026f39a9efdcbc9 Mon Sep 17 00:00:00 2001 +From c1065a638f2af40d8ef2c8586074bb82b96c02db Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 31 Oct 2023 18:24:39 +0000 -Subject: [PATCH 23/30] crank up vram allocation on more intel boards +Subject: [PATCH 30/39] crank up vram allocation on more intel boards these were added to libreboot, and it's a policy of libreboot to max out the vram settings. this was @@ -24,20 +24,20 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 12 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default -index eeb6f47364..25dfa38cb5 100644 +index 744a599708..6b8d478f06 100644 --- a/src/mainboard/dell/e6400/cmos.default +++ b/src/mainboard/dell/e6400/cmos.default -@@ -2,4 +2,4 @@ boot_option=Fallback +@@ -4,4 +4,4 @@ boot_option=Fallback debug_level=Debug power_on_after_fail=Disable sata_mode=AHCI -gfx_uma_size=32M +gfx_uma_size=256M diff --git a/src/mainboard/dell/snb_ivb_workstations/cmos.default b/src/mainboard/dell/snb_ivb_workstations/cmos.default -index ccc7e64625..7c97b84baf 100644 +index 76c16e6a8d..19364aae6e 100644 --- a/src/mainboard/dell/snb_ivb_workstations/cmos.default +++ b/src/mainboard/dell/snb_ivb_workstations/cmos.default -@@ -3,5 +3,5 @@ debug_level=Debug +@@ -5,5 +5,5 @@ debug_level=Debug power_on_after_fail=Disable nmi=Enable sata_mode=AHCI @@ -45,10 +45,10 @@ index ccc7e64625..7c97b84baf 100644 +gfx_uma_size=224M fan_full_speed=Disable diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default -index 6d27a79c66..4517ffc7c2 100644 +index 497ae92e1f..64d43a07f7 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default +++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default -@@ -3,5 +3,5 @@ debug_level=Debug +@@ -5,5 +5,5 @@ debug_level=Debug power_on_after_fail=Enable nmi=Enable sata_mode=AHCI @@ -56,83 +56,83 @@ index 6d27a79c66..4517ffc7c2 100644 +gfx_uma_size=224M psu_fan_lvl=3 diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default -index 6f3cec735e..9fc4db2990 100644 +index f3dad88670..b60f28447b 100644 --- a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default +++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default -@@ -3,4 +3,4 @@ debug_level=Debug +@@ -5,4 +5,4 @@ debug_level=Debug power_on_after_fail=Enable nmi=Enable sata_mode=AHCI -gfx_uma_size=32M +gfx_uma_size=224M diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default -index ad822d5043..89418a4cfc 100644 +index e6042c0c27..a04026b70c 100644 --- a/src/mainboard/hp/snb_ivb_laptops/cmos.default +++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default -@@ -3,3 +3,4 @@ debug_level=Debug +@@ -5,3 +5,4 @@ debug_level=Debug power_on_after_fail=Disable nmi=Enable sata_mode=AHCI +gfx_uma_size=224M diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default -index c011867916..83f590d39d 100644 +index 27a62d07b3..d1c9fcaaaf 100644 --- a/src/mainboard/lenovo/t420/cmos.default +++ b/src/mainboard/lenovo/t420/cmos.default -@@ -15,3 +15,4 @@ trackpoint=Enable +@@ -17,3 +17,4 @@ trackpoint=Enable hybrid_graphics_mode=Integrated Only usb_always_on=Disable me_state=Disabled +gfx_uma_size=224M diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default -index c011867916..83f590d39d 100644 +index 27a62d07b3..d1c9fcaaaf 100644 --- a/src/mainboard/lenovo/t420s/cmos.default +++ b/src/mainboard/lenovo/t420s/cmos.default -@@ -15,3 +15,4 @@ trackpoint=Enable +@@ -17,3 +17,4 @@ trackpoint=Enable hybrid_graphics_mode=Integrated Only usb_always_on=Disable me_state=Disabled +gfx_uma_size=224M diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default -index 55e1e6c04e..a72108f47e 100644 +index 6d1e172056..c00b358314 100644 --- a/src/mainboard/lenovo/t430/cmos.default +++ b/src/mainboard/lenovo/t430/cmos.default -@@ -16,3 +16,4 @@ backlight=Both +@@ -18,3 +18,4 @@ backlight=Both usb_always_on=Disable hybrid_graphics_mode=Integrated Only me_state=Disabled +gfx_uma_size=224M diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default -index b66f7034dc..a73ea6e9ee 100644 +index ab1be1a678..c7ee9564f3 100644 --- a/src/mainboard/lenovo/t520/cmos.default +++ b/src/mainboard/lenovo/t520/cmos.default -@@ -16,3 +16,4 @@ backlight=Both +@@ -18,3 +18,4 @@ backlight=Both hybrid_graphics_mode=Integrated Only usb_always_on=Disable me_state=Disabled +gfx_uma_size=224M diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default -index b66f7034dc..a73ea6e9ee 100644 +index ab1be1a678..c7ee9564f3 100644 --- a/src/mainboard/lenovo/t530/cmos.default +++ b/src/mainboard/lenovo/t530/cmos.default -@@ -16,3 +16,4 @@ backlight=Both +@@ -18,3 +18,4 @@ backlight=Both hybrid_graphics_mode=Integrated Only usb_always_on=Disable me_state=Disabled +gfx_uma_size=224M diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default -index 2cf484fd5a..46294d91ca 100644 +index 94f8e08a75..a1f2eacf11 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default -@@ -15,3 +15,4 @@ power_management_beeps=Enable +@@ -17,3 +17,4 @@ power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI usb_always_on=Disable +gfx_uma_size=128M diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default -index 52f303dfdb..92a2026542 100644 +index b318ab9772..82292ea5d6 100644 --- a/src/mainboard/lenovo/x220/cmos.default +++ b/src/mainboard/lenovo/x220/cmos.default -@@ -14,3 +14,4 @@ fn_ctrl_swap=Disable +@@ -16,3 +16,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable me_state=Disabled diff --git a/config/coreboot/default/patches/0024-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0031-dell-e6430-use-ME-Soft-Temporary-Disable.patch index 79ee4b6c..50fa15f2 100644 --- a/config/coreboot/default/patches/0024-dell-e6430-use-ME-Soft-Temporary-Disable.patch +++ b/config/coreboot/default/patches/0031-dell-e6430-use-ME-Soft-Temporary-Disable.patch @@ -1,7 +1,7 @@ -From a9ab864aee1be7a03926443ddc94e4c5012719ba Mon Sep 17 00:00:00 2001 +From dc02595f99566f71513ee16f1883e315b725241a Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 5 Nov 2023 11:41:41 +0000 -Subject: [PATCH 24/30] dell/e6430: use ME Soft Temporary Disable +Subject: [PATCH 31/39] dell/e6430: use ME Soft Temporary Disable i overlooked this. it's set on other boards. @@ -12,13 +12,13 @@ disablement, to absolutely ensure Intel ME is not alive Signed-off-by: Leah Rowe <leah@libreboot.org> --- - src/mainboard/dell/e6430/cmos.default | 2 +- + src/mainboard/dell/snb_ivb_latitude/cmos.default | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default +diff --git a/src/mainboard/dell/snb_ivb_latitude/cmos.default b/src/mainboard/dell/snb_ivb_latitude/cmos.default index 2a5b30f2b7..279415dfd1 100644 ---- a/src/mainboard/dell/e6430/cmos.default -+++ b/src/mainboard/dell/e6430/cmos.default +--- a/src/mainboard/dell/snb_ivb_latitude/cmos.default ++++ b/src/mainboard/dell/snb_ivb_latitude/cmos.default @@ -6,4 +6,4 @@ bluetooth=Enable wwan=Enable wlan=Enable diff --git a/config/coreboot/default/patches/0031-mb-dell-Add-OptiPlex-7020-9020-port_cb55232_31.patch b/config/coreboot/default/patches/0031-mb-dell-Add-OptiPlex-7020-9020-port_cb55232_31.patch deleted file mode 100644 index 3b4d8004..00000000 --- a/config/coreboot/default/patches/0031-mb-dell-Add-OptiPlex-7020-9020-port_cb55232_31.patch +++ /dev/null @@ -1,923 +0,0 @@ -From 38a713eb071dd9c1b7d5092ce686537e5d9266f5 Mon Sep 17 00:00:00 2001 -From: Mate Kukri <kukri.mate@gmail.com> -Date: Mon, 4 Dec 2023 21:34:18 +0000 -Subject: [PATCH 1/1] mb/dell: Add OptiPlex 7020/9020 port -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The OptiPlex 7020 and 9020 use physically identical motherboards. - -Each model comes in the following form factors: -- 7020: SFF, MT -- 9020: USFF (not currently supported), SFF, MT - -(7020 SFF) Boots Linux and Windows 10: -- Tested with an i3-4160 and i5-4460 -- DRAM init works using the MRC (4G, 4G+4G) -- iGPU init works using libgfxinit (VGA, 2x DP) -- PCIe 16x: tested, ok -- PCIe 4x: tested, ok -- All USB2 and USB3 ports work -- SMSC SCH5555 Super I/O: serial works, PS/2 untested -- Audio: back and front output works, internal speaker works, - mic inputs untested -- Ethernet: tested, works - -(9020 MT) -- Tested by Michael Büchler (thanks for the overridetree) - -Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a -Signed-off-by: Mate Kukri <kukri.mate@gmail.com> ---- - src/mainboard/dell/optiplex_9020/Kconfig | 34 +++ - src/mainboard/dell/optiplex_9020/Kconfig.name | 11 + - src/mainboard/dell/optiplex_9020/Makefile.inc | 5 + - src/mainboard/dell/optiplex_9020/acpi/ec.asl | 3 + - .../dell/optiplex_9020/acpi/platform.asl | 11 + - .../dell/optiplex_9020/acpi/superio.asl | 3 + - .../dell/optiplex_9020/board_info.txt | 8 + - src/mainboard/dell/optiplex_9020/bootblock.c | 116 ++++++++++ - src/mainboard/dell/optiplex_9020/cmos.default | 4 + - src/mainboard/dell/optiplex_9020/cmos.layout | 58 +++++ - src/mainboard/dell/optiplex_9020/data.vbt | Bin 0 -> 4409 bytes - .../dell/optiplex_9020/devicetree.cb | 80 +++++++ - src/mainboard/dell/optiplex_9020/dsdt.asl | 25 ++ - .../dell/optiplex_9020/gma-mainboard.ads | 18 ++ - src/mainboard/dell/optiplex_9020/gpio.c | 217 ++++++++++++++++++ - src/mainboard/dell/optiplex_9020/hda_verb.c | 27 +++ - src/mainboard/dell/optiplex_9020/mainboard.c | 15 ++ - .../dell/optiplex_9020/overridetree_mt.cb | 10 + - src/mainboard/dell/optiplex_9020/romstage.c | 53 +++++ - 19 files changed, 698 insertions(+) - create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig - create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig.name - create mode 100644 src/mainboard/dell/optiplex_9020/Makefile.inc - create mode 100644 src/mainboard/dell/optiplex_9020/acpi/ec.asl - create mode 100644 src/mainboard/dell/optiplex_9020/acpi/platform.asl - create mode 100644 src/mainboard/dell/optiplex_9020/acpi/superio.asl - create mode 100644 src/mainboard/dell/optiplex_9020/board_info.txt - create mode 100644 src/mainboard/dell/optiplex_9020/bootblock.c - create mode 100644 src/mainboard/dell/optiplex_9020/cmos.default - create mode 100644 src/mainboard/dell/optiplex_9020/cmos.layout - create mode 100644 src/mainboard/dell/optiplex_9020/data.vbt - create mode 100644 src/mainboard/dell/optiplex_9020/devicetree.cb - create mode 100644 src/mainboard/dell/optiplex_9020/dsdt.asl - create mode 100644 src/mainboard/dell/optiplex_9020/gma-mainboard.ads - create mode 100644 src/mainboard/dell/optiplex_9020/gpio.c - create mode 100644 src/mainboard/dell/optiplex_9020/hda_verb.c - create mode 100644 src/mainboard/dell/optiplex_9020/mainboard.c - create mode 100644 src/mainboard/dell/optiplex_9020/overridetree_mt.cb - create mode 100644 src/mainboard/dell/optiplex_9020/romstage.c - -diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig -new file mode 100644 -index 0000000000..774a72f161 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/Kconfig -@@ -0,0 +1,34 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+if BOARD_DELL_OPTIPLEX_9020_SFF || BOARD_DELL_OPTIPLEX_9020_MT -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ select BOARD_ROMSIZE_KB_12288 -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_OPTION_TABLE -+ select HAVE_CMOS_DEFAULT -+ select INTEL_GMA_HAVE_VBT -+ select INTEL_INT15 -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_USES_IFD_GBE_REGION -+ select NORTHBRIDGE_INTEL_HASWELL -+ select SERIRQ_CONTINUOUS_MODE -+ select SOUTHBRIDGE_INTEL_LYNXPOINT -+ select SUPERIO_SMSC_SCH555x -+ -+config CBFS_SIZE -+ default 0x600000 -+ -+config MAINBOARD_DIR -+ default "dell/optiplex_9020" -+ -+config MAINBOARD_PART_NUMBER -+ default "OptiPlex 7020/9020 SFF" if BOARD_DELL_OPTIPLEX_9020_SFF -+ default "OptiPlex 7020/9020 MT" if BOARD_DELL_OPTIPLEX_9020_MT -+ -+config OVERRIDE_DEVICETREE -+ default "overridetree_mt.cb" if BOARD_DELL_OPTIPLEX_9020_MT -+ -+endif -diff --git a/src/mainboard/dell/optiplex_9020/Kconfig.name b/src/mainboard/dell/optiplex_9020/Kconfig.name -new file mode 100644 -index 0000000000..c25c330a44 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/Kconfig.name -@@ -0,0 +1,11 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_DELL_OPTIPLEX_9020_SFF -+ bool "OptiPlex 7020/9020 SFF" -+ help -+ The 7020 SFF and 9020 SFF mainboards are physically identical. -+ -+config BOARD_DELL_OPTIPLEX_9020_MT -+ bool "OptiPlex 7020/9020 MT" -+ help -+ The 7020 MT and 9020 MT mainboards are physically identical. -diff --git a/src/mainboard/dell/optiplex_9020/Makefile.inc b/src/mainboard/dell/optiplex_9020/Makefile.inc -new file mode 100644 -index 0000000000..6ca2f2afaa ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/Makefile.inc -@@ -0,0 +1,5 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+romstage-y += gpio.c -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -+bootblock-y += bootblock.c -diff --git a/src/mainboard/dell/optiplex_9020/acpi/ec.asl b/src/mainboard/dell/optiplex_9020/acpi/ec.asl -new file mode 100644 -index 0000000000..16990d45f4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/acpi/ec.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: CC-PDDC */ -+ -+/* Please update the license if adding licensable material. */ -diff --git a/src/mainboard/dell/optiplex_9020/acpi/platform.asl b/src/mainboard/dell/optiplex_9020/acpi/platform.asl -new file mode 100644 -index 0000000000..cda7682e3e ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/acpi/platform.asl -@@ -0,0 +1,11 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Method(_WAK, 1) -+{ -+ Return(Package() { 0, 0 }) -+} -+ -+Method(_PTS, 1) -+{ -+ -+} -diff --git a/src/mainboard/dell/optiplex_9020/acpi/superio.asl b/src/mainboard/dell/optiplex_9020/acpi/superio.asl -new file mode 100644 -index 0000000000..16990d45f4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/acpi/superio.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: CC-PDDC */ -+ -+/* Please update the license if adding licensable material. */ -diff --git a/src/mainboard/dell/optiplex_9020/board_info.txt b/src/mainboard/dell/optiplex_9020/board_info.txt -new file mode 100644 -index 0000000000..e30cf9c41f ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/board_info.txt -@@ -0,0 +1,8 @@ -+Vendor name: Dell Inc. -+Board name: OptiPlex 7020/9020 -+Release year: 2014 -+Category: desktop -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c -new file mode 100644 -index 0000000000..2837cf9cf1 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/bootblock.c -@@ -0,0 +1,116 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <arch/io.h> -+#include <device/pnp_ops.h> -+#include <superio/smsc/sch555x/sch555x.h> -+#include <southbridge/intel/lynxpoint/pch.h> -+ -+static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) -+{ -+ // Clear EC-to-Host mailbox -+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); -+ outb(tmp, SCH555x_EMI_IOBASE + 1); -+ -+ // Send address and value to the EC -+ sch555x_emi_write16(0, (addr1 * 2) | 0x101); -+ sch555x_emi_write32(4, val | (addr2 << 16)); -+ -+ // Wait for acknowledgement message from EC -+ outb(1, SCH555x_EMI_IOBASE); -+ size_t timeout = 0; -+ do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0); -+} -+ -+struct ec_init_entry { -+ uint16_t addr; -+ uint8_t val; -+}; -+ -+static void ec_init(void) -+{ -+ /* -+ * Tables from CORE_PEI -+ */ -+ -+ static const struct ec_init_entry init_table1[] = { -+ {0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10}, -+ {0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10}, -+ {0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12}, -+ {0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12}, -+ {0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10}, -+ {0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11}, -+ }; -+ -+ for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i) -+ ec_write(2, init_table1[i].addr, init_table1[i].val); -+ -+ static const struct ec_init_entry init_table2[] = { -+ {0x0005, 0x33}, {0x0018, 0x2f}, {0x0019, 0x2f}, {0x001a, 0x2f}, -+ {0x0083, 0xbb}, {0x0085, 0xd9}, {0x0086, 0x2c}, {0x008a, 0x34}, -+ {0x008b, 0x60}, {0x0090, 0x5e}, {0x0091, 0x5e}, {0x0092, 0x86}, -+ {0x0096, 0xa4}, {0x0097, 0xa4}, {0x0098, 0xa4}, {0x009b, 0xa4}, -+ {0x00a0, 0x0a}, {0x00a1, 0x0a}, {0x00ae, 0x7c}, {0x00af, 0x7c}, -+ {0x00b0, 0x9e}, {0x00b3, 0x7c}, {0x00b6, 0x08}, {0x00b7, 0x08}, -+ {0x00ea, 0x64}, {0x00ef, 0xff}, {0x00f8, 0x15}, {0x00f9, 0x00}, -+ {0x00f0, 0x30}, {0x00fd, 0x01}, {0x01a1, 0x00}, {0x01a2, 0x00}, -+ {0x01b1, 0x08}, {0x01be, 0x90}, {0x0280, 0x24}, {0x0281, 0x13}, -+ {0x0282, 0x03}, {0x0283, 0x0a}, {0x0284, 0x80}, {0x0285, 0x03}, -+ {0x0288, 0x80}, {0x0289, 0x0c}, {0x028a, 0x03}, {0x028b, 0x0a}, -+ {0x028c, 0x80}, {0x028d, 0x03}, {0x0040, 0x01}, -+ }; -+ -+ for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i) -+ ec_write(1, init_table2[i].addr, init_table2[i].val); -+ -+ /* -+ * Table from PeiHwmInit -+ */ -+ -+ static const struct ec_init_entry hwm_init_table[] = { -+ {0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f}, -+ {0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33}, -+ {0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff}, -+ {0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00}, -+ {0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00}, -+ {0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80}, -+ {0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02}, -+ {0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04}, -+ {0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50}, -+ {0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50}, -+ {0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c}, -+ {0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd}, -+ {0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e}, -+ {0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00}, -+ {0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff}, -+ {0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00}, -+ {0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c}, -+ {0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02}, -+ {0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03}, -+ }; -+ -+ for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i) -+ ec_write(1, hwm_init_table[i].addr, hwm_init_table[i].val); -+} -+ -+#define SCH555x_IOBASE 0x2e -+#define GLOBAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL) -+#define SERIAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1) -+ -+void mainboard_config_superio(void) -+{ -+ // Super I/O early init will map Runtime and EMI registers -+ sch555x_early_init(GLOBAL_DEV); -+ -+ // Changes LED color among a few other things (extracted from Dell's FW) -+ outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS); -+ outb(0x00, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN); -+ outb(0x18, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN1); -+ outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); -+ outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); -+ -+ // Magic EC init -+ ec_init(); -+ -+ // Magic EC init is needed for UART1 initialization to work -+ sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -+} -diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default -new file mode 100644 -index 0000000000..b159660aa8 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/cmos.default -@@ -0,0 +1,4 @@ -+boot_option=Fallback -+debug_level=Debug -+nmi=Disable -+power_on_after_fail=Disable -diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout -new file mode 100644 -index 0000000000..c9ba76c78f ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/cmos.layout -@@ -0,0 +1,58 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 3 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 4 debug_level -+ -+#400 8 r 0 reserved for century byte -+ -+# coreboot config options: southbridge -+408 1 e 1 nmi -+409 2 e 5 power_on_after_fail -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+ -+2 0 Enable -+2 1 Disable -+ -+3 0 Fallback -+3 1 Normal -+ -+4 0 Emergency -+4 1 Alert -+4 2 Critical -+4 3 Error -+4 4 Warning -+4 5 Notice -+4 6 Info -+4 7 Debug -+4 8 Spew -+ -+5 0 Disable -+5 1 Enable -+5 2 Keep -+ -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 415 984 -diff --git a/src/mainboard/dell/optiplex_9020/data.vbt b/src/mainboard/dell/optiplex_9020/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..1779f3b8d1018ba0aae480103b145bd7b6dd6187 -GIT binary patch -literal 4409 -zcmdT{T}&KR6h8B_yR)-1!!lr9XiE<T5h_au1f&hdSy<_UtKG6lH%+yR*`>u$pi5g@ -zP3)>@YHE~+rqQIfO&U!#QHhDMkD3^5qG|e|_!FbV_|P=QG{y&G)b-q%VY>waTYnNg -zlQZY%p84*%_nv!argpGv03)IJ_Pe7|bSMP|Y$`oQ_r=uJyEVQm92yAi>WXgdz6a04 -zD)5&6aRng7aW^T=MoU}o*#7ireSZT+;@h#UsjZ1Q4>q^r@OTD8dxst!AG;&CDL8Oo -z^uXRm#BdDb@opR+9u95~SuwW<QzMfTqeF)qF*csrKZ)H~hheKJ9Bag}aojteN>8Tu -zlb(JA9~v1O%8aBZS%1O)#VHqfy2mFDXGV7K*^l+z4cKBBMzF<bZbmC*>>kfdG+}6T -z6#H4sB=%D$nS<$6lPaq+z<VHx902D6&lA9LzqdfOh#}ETa^{d^Qa3IULMDVoxLYjf -zv_SO(uW~#!R!i{VA*TVEBzVEHO|WbbVKxbVzx(ZS+aUqD7$Jw01c2!TeBcCl0o=?F -z28TS8$Zmu%>jW^<CJybs=4~hTnz>lR#jfi;e=$Iyv50HHXlZTl*xYG$g?l1>(OCb$ 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mainboard has VGA -+ register "gpu_ddi_e_connected" = "1" -+ -+ chip cpu/intel/haswell -+ device cpu_cluster 0 on ops haswell_cpu_bus_ops end -+ end -+ -+ device domain 0 on -+ ops haswell_pci_domain_ops -+ -+ subsystemid 0x1028 0x05a5 inherit -+ -+ device pci 00.0 on end # Host bridge -+ device pci 01.0 on end # PCIe graphics -+ device pci 02.0 on end # VGA controller -+ device pci 03.0 on end # Mini-HD audio -+ -+ chip southbridge/intel/lynxpoint -+ register "gen1_dec" = "0x007c0a01" -+ register "gen2_dec" = "0x007c0901" -+ register "gen3_dec" = "0x003c07e1" -+ register "gen4_dec" = "0x001c0901" -+ register "sata_port_map" = "0x33" -+ -+ device pci 14.0 on end # xHCI controller -+ device pci 16.0 on end # Management Engine interface 1 -+ device pci 16.1 off end # Management Engine interface 2 -+ device pci 16.2 off end # Management Engine IDE-R -+ device pci 16.3 on end # Management Engine KT -+ device pci 19.0 on # Intel Gigabit Ethernet -+ subsystemid 0x1028 0x05a4 -+ end -+ device pci 1a.0 on end # EHCI controller #2 -+ device pci 1b.0 on end # HD audio controller -+ device pci 1c.0 off end -+ device pci 1c.1 off end -+ device pci 1c.2 off end -+ device pci 1c.3 off end -+ device pci 1c.4 on end # PCIe 4x slot -+ device pci 1c.5 off end -+ device pci 1c.6 off end -+ device pci 1c.7 off end -+ device pci 1d.0 on end # EHCI controller #1 -+ device pci 1f.0 on # LPC bridge -+ chip superio/smsc/sch555x -+ device pnp 2e.0 on # EMI -+ io 0x60 = 0xa00 -+ end -+ device pnp 2e.1 on # 8042 -+ io 0x60 = 0x60 -+ irq 0x0f = 0 -+ irq 0x70 = 1 -+ irq 0x72 = 12 -+ end -+ device pnp 2e.7 on # UART1 -+ io 0x60 = 0x3f8 -+ irq 0x0f = 2 -+ irq 0x70 = 4 -+ end -+ device pnp 2e.8 off end # UART2 -+ device pnp 2e.c on # LPC interface -+ io 0x60 = 0x2e -+ end -+ device pnp 2e.a on # Runtime registers -+ io 0x60 = 0xa40 -+ end -+ device pnp 2e.b off end # Floppy Controller -+ device pnp 2e.11 off end # Parallel Port -+ end -+ end -+ device pci 1f.2 on end # SATA controller 1 -+ device pci 1f.3 on end # SMBus -+ device pci 1f.5 off end # SATA controller 2 -+ device pci 1f.6 off end # Thermal -+ end -+ end -+end -diff --git a/src/mainboard/dell/optiplex_9020/dsdt.asl b/src/mainboard/dell/optiplex_9020/dsdt.asl -new file mode 100644 -index 0000000000..7ec1e9775a ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/dsdt.asl -@@ -0,0 +1,25 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <acpi/acpi.h> -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20181031 /* OEM Revision */ -+) -+{ -+ #include <acpi/dsdt_top.asl> -+ #include "acpi/platform.asl" -+ #include <southbridge/intel/common/acpi/platform.asl> -+ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> -+ #include <southbridge/intel/common/acpi/sleepstates.asl> -+ #include <cpu/intel/common/acpi/cpu.asl> -+ -+ Device (\_SB.PCI0) -+ { -+ #include <northbridge/intel/haswell/acpi/hostbridge.asl> -+ #include <southbridge/intel/lynxpoint/acpi/pch.asl> -+ } -+} -diff --git a/src/mainboard/dell/optiplex_9020/gma-mainboard.ads b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads -new file mode 100644 -index 0000000000..173f2f1d0d ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads -@@ -0,0 +1,18 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ (DP1, -+ DP2, -+ DP3, -+ Analog, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/optiplex_9020/gpio.c b/src/mainboard/dell/optiplex_9020/gpio.c -new file mode 100644 -index 0000000000..48b7707e2c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/gpio.c -@@ -0,0 +1,217 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <southbridge/intel/common/gpio.h> -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_GPIO, -+ .gpio1 = GPIO_MODE_GPIO, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_GPIO, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_GPIO, -+ .gpio8 = GPIO_MODE_GPIO, -+ .gpio9 = GPIO_MODE_NATIVE, -+ .gpio10 = GPIO_MODE_NATIVE, -+ .gpio11 = GPIO_MODE_GPIO, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_NATIVE, -+ .gpio15 = GPIO_MODE_GPIO, -+ .gpio16 = GPIO_MODE_NATIVE, -+ .gpio17 = GPIO_MODE_GPIO, -+ .gpio18 = GPIO_MODE_NATIVE, -+ .gpio19 = GPIO_MODE_NATIVE, -+ .gpio20 = GPIO_MODE_NATIVE, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_GPIO, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_GPIO, -+ .gpio26 = GPIO_MODE_GPIO, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_NATIVE, -+ .gpio30 = GPIO_MODE_NATIVE, -+ .gpio31 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio0 = GPIO_DIR_INPUT, -+ .gpio1 = GPIO_DIR_INPUT, -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio5 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio7 = GPIO_DIR_INPUT, -+ .gpio8 = GPIO_DIR_INPUT, -+ .gpio11 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_OUTPUT, -+ .gpio15 = GPIO_DIR_OUTPUT, -+ .gpio17 = GPIO_DIR_INPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_OUTPUT, -+ .gpio23 = GPIO_DIR_OUTPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio25 = GPIO_DIR_OUTPUT, -+ .gpio26 = GPIO_DIR_OUTPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_OUTPUT, -+ .gpio31 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio13 = GPIO_LEVEL_LOW, -+ .gpio15 = GPIO_LEVEL_HIGH, -+ .gpio22 = GPIO_LEVEL_HIGH, -+ .gpio23 = GPIO_LEVEL_HIGH, -+ .gpio25 = GPIO_LEVEL_HIGH, -+ .gpio26 = GPIO_LEVEL_HIGH, -+ .gpio28 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+ .gpio18 = GPIO_BLINK, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio8 = GPIO_INVERT, -+ .gpio9 = GPIO_INVERT, -+ .gpio11 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_reset = { -+ .gpio26 = GPIO_RESET_RSMRST, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_GPIO, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_NATIVE, -+ .gpio37 = GPIO_MODE_NATIVE, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_GPIO, -+ .gpio45 = GPIO_MODE_GPIO, -+ .gpio46 = GPIO_MODE_GPIO, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_GPIO, -+ .gpio51 = GPIO_MODE_GPIO, -+ .gpio52 = GPIO_MODE_GPIO, -+ .gpio53 = GPIO_MODE_GPIO, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_GPIO, -+ .gpio56 = GPIO_MODE_NATIVE, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio32 = GPIO_DIR_INPUT, -+ .gpio33 = GPIO_DIR_OUTPUT, -+ .gpio34 = GPIO_DIR_OUTPUT, -+ .gpio35 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio44 = GPIO_DIR_INPUT, -+ .gpio45 = GPIO_DIR_OUTPUT, -+ .gpio46 = GPIO_DIR_INPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_INPUT, -+ .gpio50 = GPIO_DIR_OUTPUT, -+ .gpio51 = GPIO_DIR_OUTPUT, -+ .gpio52 = GPIO_DIR_OUTPUT, -+ .gpio53 = GPIO_DIR_OUTPUT, -+ .gpio54 = GPIO_DIR_OUTPUT, -+ .gpio55 = GPIO_DIR_OUTPUT, -+ .gpio57 = GPIO_DIR_OUTPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio33 = GPIO_LEVEL_HIGH, -+ .gpio34 = GPIO_LEVEL_HIGH, -+ .gpio45 = GPIO_LEVEL_LOW, -+ .gpio50 = GPIO_LEVEL_HIGH, -+ .gpio51 = GPIO_LEVEL_HIGH, -+ .gpio52 = GPIO_LEVEL_HIGH, -+ .gpio53 = GPIO_LEVEL_HIGH, -+ .gpio54 = GPIO_LEVEL_HIGH, -+ .gpio55 = GPIO_LEVEL_HIGH, -+ .gpio57 = GPIO_LEVEL_HIGH, -+ .gpio60 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_reset = {}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_GPIO, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_GPIO, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_GPIO, -+ .gpio69 = GPIO_MODE_GPIO, -+ .gpio70 = GPIO_MODE_NATIVE, -+ .gpio71 = GPIO_MODE_NATIVE, -+ .gpio72 = GPIO_MODE_GPIO, -+ .gpio73 = GPIO_MODE_GPIO, -+ .gpio74 = GPIO_MODE_GPIO, -+ .gpio75 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio64 = GPIO_DIR_OUTPUT, -+ .gpio66 = GPIO_DIR_OUTPUT, -+ .gpio68 = GPIO_DIR_INPUT, -+ .gpio69 = GPIO_DIR_INPUT, -+ .gpio72 = GPIO_DIR_OUTPUT, -+ .gpio73 = GPIO_DIR_INPUT, -+ .gpio74 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+ .gpio64 = GPIO_LEVEL_HIGH, -+ .gpio66 = GPIO_LEVEL_HIGH, -+ .gpio72 = GPIO_LEVEL_HIGH, -+ .gpio74 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_reset = {}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ .reset = &pch_gpio_set1_reset, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ .reset = &pch_gpio_set2_reset, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ .reset = &pch_gpio_set3_reset, -+ }, -+}; -diff --git a/src/mainboard/dell/optiplex_9020/hda_verb.c b/src/mainboard/dell/optiplex_9020/hda_verb.c -new file mode 100644 -index 0000000000..df43ade3e6 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/hda_verb.c -@@ -0,0 +1,27 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <stdint.h> -+#include <device/azalia_device.h> -+ -+const u32 cim_verb_data[] = { -+ 0x10ec0280, /* Realtek ALC3220 */ -+ 0x102805a5, /* Subsystem ID */ -+ 13, /* Number of entries */ -+ AZALIA_SUBVENDOR(0, 0x102805a5), -+ AZALIA_PIN_CFG(0, 0x12, 0x4008c000), -+ AZALIA_PIN_CFG(0, 0x13, 0x411111f0), -+ AZALIA_PIN_CFG(0, 0x14, 0x90170110), -+ AZALIA_PIN_CFG(0, 0x15, 0x0221401f), -+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0), -+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0), -+ AZALIA_PIN_CFG(0, 0x18, 0x01a13040), -+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0), -+ AZALIA_PIN_CFG(0, 0x1a, 0x02a19030), -+ AZALIA_PIN_CFG(0, 0x1b, 0x01014020), -+ AZALIA_PIN_CFG(0, 0x1d, 0x40400001), -+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), -+}; -+ -+const u32 pc_beep_verbs[] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c -new file mode 100644 -index 0000000000..c834fea5d3 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/mainboard.c -@@ -0,0 +1,15 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/device.h> -+#include <drivers/intel/gma/int15.h> -+ -+static void mainboard_enable(struct device *dev) -+{ -+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, -+ GMA_INT15_PANEL_FIT_DEFAULT, -+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -+} -+ -+struct chip_operations mainboard_ops = { -+ .enable_dev = mainboard_enable, -+}; -diff --git a/src/mainboard/dell/optiplex_9020/overridetree_mt.cb b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb -new file mode 100644 -index 0000000000..90205c2d68 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb -@@ -0,0 +1,10 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+chip northbridge/intel/haswell -+ device domain 0 on -+ chip southbridge/intel/lynxpoint -+ device pci 1c.1 on end # PCI (via XIO2001 bridge) -+ device pci 1c.2 on end # PCIe 1x slot -+ end -+ end -+end -diff --git a/src/mainboard/dell/optiplex_9020/romstage.c b/src/mainboard/dell/optiplex_9020/romstage.c -new file mode 100644 -index 0000000000..2b9cdaa5fd ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/romstage.c -@@ -0,0 +1,53 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <northbridge/intel/haswell/haswell.h> -+#include <northbridge/intel/haswell/raminit.h> -+#include <southbridge/intel/lynxpoint/pch.h> -+ -+void mainboard_config_rcba(void) -+{ -+ RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQC, PIRQD, PIRQA); -+ RCBA16(D29IR) = DIR_ROUTE(PIRQC, PIRQA, PIRQD, PIRQH); -+ RCBA16(D28IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA); -+ RCBA16(D27IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQG); -+ RCBA16(D26IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQF, PIRQA); -+ RCBA16(D25IR) = DIR_ROUTE(PIRQH, PIRQG, PIRQF, PIRQE); -+ RCBA16(D22IR) = DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQA); -+ RCBA16(D20IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA); -+} -+ -+void mb_get_spd_map(struct spd_info *spdi) -+{ -+ spdi->addresses[0] = 0x50; -+ spdi->addresses[1] = 0x51; -+ spdi->addresses[2] = 0x52; -+ spdi->addresses[3] = 0x53; -+} -+ -+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { -+ /* Length, Enable, OCn#, Location */ -+ {0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP}, -+ {0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP}, -+ {0x0040, 1, 1, USB_PORT_BACK_PANEL}, -+ {0x0040, 1, 2, USB_PORT_BACK_PANEL}, -+ {0x0040, 1, 3, USB_PORT_BACK_PANEL}, -+ {0x0040, 1, 3, USB_PORT_BACK_PANEL}, -+ {0x0040, 1, 0, USB_PORT_BACK_PANEL}, -+ {0x0040, 1, 0, USB_PORT_BACK_PANEL}, -+ {0x0040, 1, 4, USB_PORT_BACK_PANEL}, -+ {0x0040, 1, 4, USB_PORT_BACK_PANEL}, -+ {0x0040, 1, 5, USB_PORT_BACK_PANEL}, -+ {0x0040, 1, 5, USB_PORT_BACK_PANEL}, -+ {0x0040, 1, 6, USB_PORT_BACK_PANEL}, -+ {0x0040, 1, 7, USB_PORT_BACK_PANEL}, -+}; -+ -+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { -+ /* Enable, OCn# */ -+ {1, 6}, -+ {1, 7}, -+ {0, USB_OC_PIN_SKIP}, -+ {0, USB_OC_PIN_SKIP}, -+ {1, 1}, -+ {1, 2}, -+}; --- -2.39.2 - diff --git a/config/coreboot/default/patches/0032-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch b/config/coreboot/default/patches/0032-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch deleted file mode 100644 index ddfc6571..00000000 --- a/config/coreboot/default/patches/0032-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch +++ /dev/null @@ -1,774 +0,0 @@ -From 41002e64c92e90903fa591c4a8a1cc0108833743 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Sun, 26 Nov 2023 17:08:52 -0700 -Subject: [PATCH] mb/dell: Add Latitude E6420 (Sandy Bridge) - -Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394 -Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> ---- - src/mainboard/dell/e6420/Kconfig | 38 ++++ - src/mainboard/dell/e6420/Kconfig.name | 2 + - src/mainboard/dell/e6420/Makefile.inc | 6 + - src/mainboard/dell/e6420/acpi/ec.asl | 9 + - src/mainboard/dell/e6420/acpi/platform.asl | 12 ++ - src/mainboard/dell/e6420/acpi/superio.asl | 3 + - src/mainboard/dell/e6420/acpi_tables.c | 16 ++ - src/mainboard/dell/e6420/board_info.txt | 6 + - src/mainboard/dell/e6420/cmos.default | 9 + - src/mainboard/dell/e6420/cmos.layout | 88 ++++++++++ - src/mainboard/dell/e6420/data.vbt | Bin 0 -> 6144 bytes - src/mainboard/dell/e6420/devicetree.cb | 66 +++++++ - src/mainboard/dell/e6420/dsdt.asl | 30 ++++ - src/mainboard/dell/e6420/early_init.c | 32 ++++ - src/mainboard/dell/e6420/gma-mainboard.ads | 20 +++ - src/mainboard/dell/e6420/gpio.c | 191 +++++++++++++++++++++ - src/mainboard/dell/e6420/hda_verb.c | 33 ++++ - src/mainboard/dell/e6420/mainboard.c | 21 +++ - 18 files changed, 582 insertions(+) - create mode 100644 src/mainboard/dell/e6420/Kconfig - create mode 100644 src/mainboard/dell/e6420/Kconfig.name - create mode 100644 src/mainboard/dell/e6420/Makefile.inc - create mode 100644 src/mainboard/dell/e6420/acpi/ec.asl - create mode 100644 src/mainboard/dell/e6420/acpi/platform.asl - create mode 100644 src/mainboard/dell/e6420/acpi/superio.asl - create mode 100644 src/mainboard/dell/e6420/acpi_tables.c - create mode 100644 src/mainboard/dell/e6420/board_info.txt - create mode 100644 src/mainboard/dell/e6420/cmos.default - create mode 100644 src/mainboard/dell/e6420/cmos.layout - create mode 100644 src/mainboard/dell/e6420/data.vbt - create mode 100644 src/mainboard/dell/e6420/devicetree.cb - create mode 100644 src/mainboard/dell/e6420/dsdt.asl - create mode 100644 src/mainboard/dell/e6420/early_init.c - create mode 100644 src/mainboard/dell/e6420/gma-mainboard.ads - create mode 100644 src/mainboard/dell/e6420/gpio.c - create mode 100644 src/mainboard/dell/e6420/hda_verb.c - create mode 100644 src/mainboard/dell/e6420/mainboard.c - -diff --git a/src/mainboard/dell/e6420/Kconfig b/src/mainboard/dell/e6420/Kconfig -new file mode 100644 -index 0000000000..cff62bf70c ---- /dev/null -+++ b/src/mainboard/dell/e6420/Kconfig -@@ -0,0 +1,38 @@ -+if BOARD_DELL_LATITUDE_E6420 -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ select BOARD_ROMSIZE_KB_10240 -+ select EC_ACPI -+ select EC_DELL_MEC5035 -+ select GFX_GMA_PANEL_1_ON_LVDS -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ select INTEL_GMA_HAVE_VBT -+ select INTEL_INT15 -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_USES_IFD_GBE_REGION -+ select NORTHBRIDGE_INTEL_SANDYBRIDGE -+ select SERIRQ_CONTINUOUS_MODE -+ select SOUTHBRIDGE_INTEL_BD82X6X -+ select SYSTEM_TYPE_LAPTOP -+ select USE_NATIVE_RAMINIT -+ -+config DRAM_RESET_GATE_GPIO -+ default 60 -+ -+config MAINBOARD_DIR -+ default "dell/e6420" -+ -+config MAINBOARD_PART_NUMBER -+ default "Latitude E6420" -+ -+config USBDEBUG_HCD_INDEX -+ default 2 -+ -+config VGA_BIOS_ID -+ default "8086,0126" -+ -+endif # BOARD_DELL_LATITUDE_E6420 -diff --git a/src/mainboard/dell/e6420/Kconfig.name b/src/mainboard/dell/e6420/Kconfig.name -new file mode 100644 -index 0000000000..1722891e7b ---- /dev/null -+++ b/src/mainboard/dell/e6420/Kconfig.name -@@ -0,0 +1,2 @@ -+config BOARD_DELL_LATITUDE_E6420 -+ bool "Latitude E6420" -diff --git a/src/mainboard/dell/e6420/Makefile.inc b/src/mainboard/dell/e6420/Makefile.inc -new file mode 100644 -index 0000000000..ba64e93eb8 ---- /dev/null -+++ b/src/mainboard/dell/e6420/Makefile.inc -@@ -0,0 +1,6 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+bootblock-y += early_init.c -+bootblock-y += gpio.c -+romstage-y += early_init.c -+romstage-y += gpio.c -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -diff --git a/src/mainboard/dell/e6420/acpi/ec.asl b/src/mainboard/dell/e6420/acpi/ec.asl -new file mode 100644 -index 0000000000..0d429410a9 ---- /dev/null -+++ b/src/mainboard/dell/e6420/acpi/ec.asl -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Device(EC) -+{ -+ Name (_HID, EISAID("PNP0C09")) -+ Name (_UID, 0) -+ Name (_GPE, 16) -+/* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e6420/acpi/platform.asl b/src/mainboard/dell/e6420/acpi/platform.asl -new file mode 100644 -index 0000000000..2d24bbd9b9 ---- /dev/null -+++ b/src/mainboard/dell/e6420/acpi/platform.asl -@@ -0,0 +1,12 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Method(_WAK, 1) -+{ -+ /* FIXME: EC support */ -+ Return(Package() {0, 0}) -+} -+ -+Method(_PTS,1) -+{ -+ /* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e6420/acpi/superio.asl b/src/mainboard/dell/e6420/acpi/superio.asl -new file mode 100644 -index 0000000000..55b1db5b11 ---- /dev/null -+++ b/src/mainboard/dell/e6420/acpi/superio.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <drivers/pc80/pc/ps2_controller.asl> -diff --git a/src/mainboard/dell/e6420/acpi_tables.c b/src/mainboard/dell/e6420/acpi_tables.c -new file mode 100644 -index 0000000000..e2759659bf ---- /dev/null -+++ b/src/mainboard/dell/e6420/acpi_tables.c -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <acpi/acpi_gnvs.h> -+#include <soc/nvs.h> -+ -+/* FIXME: check this function. */ -+void mainboard_fill_gnvs(struct global_nvs *gnvs) -+{ -+ /* The lid is open by default. */ -+ gnvs->lids = 1; -+ -+ /* Temperature at which OS will shutdown */ -+ gnvs->tcrt = 100; -+ /* Temperature at which OS will throttle CPU */ -+ gnvs->tpsv = 90; -+} -diff --git a/src/mainboard/dell/e6420/board_info.txt b/src/mainboard/dell/e6420/board_info.txt -new file mode 100644 -index 0000000000..34d5ad9e0b ---- /dev/null -+++ b/src/mainboard/dell/e6420/board_info.txt -@@ -0,0 +1,6 @@ -+Category: laptop -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2011 -diff --git a/src/mainboard/dell/e6420/cmos.default b/src/mainboard/dell/e6420/cmos.default -new file mode 100644 -index 0000000000..279415dfd1 ---- /dev/null -+++ b/src/mainboard/dell/e6420/cmos.default -@@ -0,0 +1,9 @@ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -+nmi=Enable -+bluetooth=Enable -+wwan=Enable -+wlan=Enable -+sata_mode=AHCI -+me_state=Disabled -diff --git a/src/mainboard/dell/e6420/cmos.layout b/src/mainboard/dell/e6420/cmos.layout -new file mode 100644 -index 0000000000..1aa7e77bce ---- /dev/null -+++ b/src/mainboard/dell/e6420/cmos.layout -@@ -0,0 +1,88 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+#400 8 r 0 reserved for century byte -+ -+# coreboot config options: southbridge -+408 1 e 1 nmi -+409 2 e 7 power_on_after_fail -+411 1 e 9 sata_mode -+ -+# coreboot config options: EC -+412 1 e 1 bluetooth -+413 1 e 1 wwan -+414 1 e 1 wlan -+ -+# coreboot config options: ME -+424 1 e 14 me_state -+425 2 h 0 me_state_prev -+ -+# coreboot config options: northbridge -+432 3 e 11 gfx_uma_size -+435 2 e 12 hybrid_graphics_mode -+440 8 h 0 volume -+ -+# VBOOT -+448 128 r 0 vbnv -+ -+# SandyBridge MRC Scrambler Seed values -+896 32 r 0 mrc_scrambler_seed -+928 32 r 0 mrc_scrambler_seed_s3 -+960 16 r 0 mrc_scrambler_seed_chk -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+2 0 Enable -+2 1 Disable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+9 0 AHCI -+9 1 Compatible -+11 0 32M -+11 1 64M -+11 2 96M -+11 3 128M -+11 4 160M -+11 5 192M -+11 6 224M -+14 0 Normal -+14 1 Disabled -+ -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 447 984 -diff --git a/src/mainboard/dell/e6420/data.vbt b/src/mainboard/dell/e6420/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..d3662eea1bc78b60be6d0bd2cc38bb46b654afbd -GIT binary patch -literal 6144 -zcmeHKeQZ-z6hE);wSBvNZ|mO1=*HLC2BQN8uVX6{N9eY)75ORymb$R8!YYuAZEgeE -zKk|S@Fen*n41W-viAF;r%)~^EkpLz-B{2q##)LmGAtoY;7*Qhv_1yPbw$TC$2}G0K -z=6Ao&x#ym9?z!i_&TOh(kLzky2cN8MTpny#R<;VU4Rkn?rBIz(YL~BBw<%b&zGhSH -z$~AQ>@D0d=Xx6RE0BwSxspWdrW9y<FZGD@&x3_JL;p$p!;!BVdcKLkht0=-%(Jj&T -z_GkyztZ%>#t7^)^(T-R<7W?O6ZTI%A+j=`<Jw3Q%dk6N!da<_?7oyiU3)^<~_TiSk -zE$y+=RK3PGQ`gzmXYPRBx>C|f*UP9{h|4>ANrAe~?ymV*)83AaT#FuTjP=C2cg5P~ -zt4w78r$t#300cWY_k)mevmAmFI3&oBfytoAAPQiYK$XEIgHwV@5-gJ-Q-*p8yfTDj -zaDz=1Y!X1B3`OpQ&Ik}bM|0xHn0gYNZw0rT=7AXS2in-q8K^?)0|el+Z6geW7i7MM -zv~!|>HqL-|Fk}EYOa@)R<X)VQ7c}d8R1b@RTn5rq(90|QRg0?wwZZz(6Dz}w>zg9Y -z8;!mD_V*XSjT33~$`o`s>zEGBq8AQ`HaH?y!Fh2QiX1v@aCo4LaENf&DZ_cE2A2qb -z5@cC}X)=S^1RvpXLWs~v*hqMau$!=t@B-mg!XV)|;eEm>!Z6`H;R4|&!d1d`f|S7^ -zli+B98*!TfPE&6~NVM5j3v{N3OTjpnm_L@BPh(}esd(J!gj?~iJP?n|OZZOiTqlql -zg<NWR@g&-*W-E%A7|*1Z_`sVO$K&iAP+VIj9{<1hT%SXsK}IBk8!daftR`6-)EUiS -zvv*HR(#-ZwhA~7wcmxbe4%E?Y7P0y{1q|nqR1L29UR8v@#No^g5MH)7!>{%-$T|cR -zZx5|xm>Fl>;@$m};P{0WC>O~<Nl1`*PLgPN_hP2a^h+L$ls&SYrkDYr+&l*%%S?^Q -ziPSdtHE<LNEnr7cs=ihL-C>-p>*$9CpHRLgN|POkqD^UP4nw|4nf0bc8MOBk<;%js -zfpCAWNzqSPlz@X%j9CGrwZDKUl@K{g6pzqiIIARDQ)#@^RW&0pmNG;XZ?!SlHB?L# -zKRAMgq(R;aQd%@Gy38-LS@ix)fR**(P3B9wI=Uk^&cWmmwB<vf21<0#LBA!;qtAh( -zYe5g_T{+gw^mi8QzPPraBoH~8oCz%r=$nVi1A)`Y8IKqIdqm6MihqxtpFaTggaPxu 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mode 100644 -index 0000000000..f9259f7175 ---- /dev/null -+++ b/src/mainboard/dell/e6420/devicetree.cb -@@ -0,0 +1,66 @@ -+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. -+ register "gfx" = "GMA_STATIC_DISPLAYS(1)" -+ register "gpu_cpu_backlight" = "0x0000054f" -+ register "gpu_dp_b_hotplug" = "4" -+ register "gpu_dp_c_hotplug" = "4" -+ register "gpu_dp_d_hotplug" = "4" -+ register "gpu_panel_port_select" = "0" -+ register "gpu_panel_power_backlight_off_delay" = "2300" -+ register "gpu_panel_power_backlight_on_delay" = "2300" -+ register "gpu_panel_power_cycle_delay" = "6" -+ register "gpu_panel_power_down_delay" = "400" -+ register "gpu_panel_power_up_delay" = "400" -+ register "gpu_pch_backlight" = "0x13121312" -+ -+ register "spd_addresses" = "{0x50, 0, 0x52, 0}" -+ -+ device domain 0x0 on -+ subsystemid 0x1028 0x0493 inherit -+ -+ device ref host_bridge on end # Host bridge -+ device ref peg10 on end # PEG -+ device ref igd on end # iGPU -+ -+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH -+ register "docking_supported" = "1" -+ register "gen1_dec" = "0x007c0681" -+ register "gen2_dec" = "0x007c0901" -+ register "gen3_dec" = "0x003c07e1" -+ register "gen4_dec" = "0x001c0901" -+ register "gpi0_routing" = "2" -+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }" -+ register "pcie_port_coalesce" = "1" -+ register "sata_interface_speed_support" = "0x3" -+ register "sata_port_map" = "0x3b" -+ register "spi_lvscc" = "0x2005" -+ register "spi_uvscc" = "0x2005" -+ -+ device ref mei1 off end -+ device ref mei2 off end -+ device ref me_ide_r off end -+ device ref me_kt off end -+ device ref gbe on end -+ device ref ehci2 on end -+ device ref hda on end -+ device ref pcie_rp1 on end -+ device ref pcie_rp2 on end -+ device ref pcie_rp3 on end -+ device ref pcie_rp4 on end -+ device ref pcie_rp5 off end -+ device ref pcie_rp6 on end -+ device ref pcie_rp7 off end -+ device ref pcie_rp8 off end -+ device ref ehci1 on end -+ device ref pci_bridge off end -+ device ref lpc on -+ chip ec/dell/mec5035 -+ device pnp ff.0 on end -+ end -+ end -+ device ref sata1 on end -+ device ref smbus on end -+ device ref sata2 off end -+ device ref thermal off end -+ end -+ end -+end -diff --git a/src/mainboard/dell/e6420/dsdt.asl b/src/mainboard/dell/e6420/dsdt.asl -new file mode 100644 -index 0000000000..7d13c55b08 ---- /dev/null -+++ b/src/mainboard/dell/e6420/dsdt.asl -@@ -0,0 +1,30 @@ -+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+ -+#include <acpi/acpi.h> -+ -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20141018 /* OEM revision */ -+) -+{ -+ #include <acpi/dsdt_top.asl> -+ #include "acpi/platform.asl" -+ #include <cpu/intel/common/acpi/cpu.asl> -+ #include <southbridge/intel/common/acpi/platform.asl> -+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> -+ #include <southbridge/intel/common/acpi/sleepstates.asl> -+ -+ Device (\_SB.PCI0) -+ { -+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> -+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl> -+ #include <southbridge/intel/bd82x6x/acpi/pch.asl> -+ } -+} -diff --git a/src/mainboard/dell/e6420/early_init.c b/src/mainboard/dell/e6420/early_init.c -new file mode 100644 -index 0000000000..0682441ed6 ---- /dev/null -+++ b/src/mainboard/dell/e6420/early_init.c -@@ -0,0 +1,32 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+ -+#include <bootblock_common.h> -+#include <device/pci_ops.h> -+#include <ec/dell/mec5035/mec5035.h> -+#include <southbridge/intel/bd82x6x/pch.h> -+ -+const struct southbridge_usb_port mainboard_usb_ports[] = { -+ { 1, 1, 0 }, -+ { 1, 1, 0 }, -+ { 1, 1, 1 }, -+ { 1, 1, 1 }, -+ { 1, 0, 2 }, -+ { 1, 1, 2 }, -+ { 1, 1, 3 }, -+ { 1, 1, 3 }, -+ { 1, 1, 5 }, -+ { 1, 1, 5 }, -+ { 1, 1, 7 }, -+ { 1, 1, 6 }, -+ { 1, 0, 6 }, -+ { 1, 0, 7 }, -+}; -+ -+void bootblock_mainboard_early_init(void) -+{ -+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN -+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN -+ | COMB_LPC_EN | COMA_LPC_EN); -+ mec5035_early_init(); -+} -diff --git a/src/mainboard/dell/e6420/gma-mainboard.ads b/src/mainboard/dell/e6420/gma-mainboard.ads -new file mode 100644 -index 0000000000..2a16f44360 ---- /dev/null -+++ b/src/mainboard/dell/e6420/gma-mainboard.ads -@@ -0,0 +1,20 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ ( -+ HDMI1, -- mainboard HDMI -+ DP2, -- dock DP -+ DP3, -- dock DP -+ Analog, -- mainboard VGA -+ LVDS, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/e6420/gpio.c b/src/mainboard/dell/e6420/gpio.c -new file mode 100644 -index 0000000000..943c743f48 ---- /dev/null -+++ b/src/mainboard/dell/e6420/gpio.c -@@ -0,0 +1,191 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <southbridge/intel/common/gpio.h> -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_GPIO, -+ .gpio1 = GPIO_MODE_NATIVE, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_NATIVE, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_NATIVE, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_GPIO, -+ .gpio8 = GPIO_MODE_GPIO, -+ .gpio9 = GPIO_MODE_NATIVE, -+ .gpio10 = GPIO_MODE_NATIVE, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_GPIO, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_GPIO, -+ .gpio18 = GPIO_MODE_NATIVE, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_NATIVE, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_GPIO, -+ .gpio31 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio0 = GPIO_DIR_INPUT, -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio7 = GPIO_DIR_INPUT, -+ .gpio8 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio15 = GPIO_DIR_INPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio17 = GPIO_DIR_INPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_INPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+ .gpio30 = GPIO_DIR_OUTPUT, -+ .gpio31 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio30 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_reset = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio0 = GPIO_INVERT, -+ .gpio8 = GPIO_INVERT, -+ .gpio14 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_NATIVE, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_GPIO, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_GPIO, -+ .gpio52 = GPIO_MODE_GPIO, -+ .gpio53 = GPIO_MODE_NATIVE, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_NATIVE, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_OUTPUT, -+ .gpio35 = GPIO_DIR_INPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio45 = GPIO_DIR_OUTPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_OUTPUT, -+ .gpio51 = GPIO_DIR_INPUT, -+ .gpio52 = GPIO_DIR_INPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio34 = GPIO_LEVEL_HIGH, -+ .gpio45 = GPIO_LEVEL_LOW, -+ .gpio49 = GPIO_LEVEL_LOW, -+ .gpio60 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_reset = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_NATIVE, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_NATIVE, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_GPIO, -+ .gpio69 = GPIO_MODE_GPIO, -+ .gpio70 = GPIO_MODE_GPIO, -+ .gpio71 = GPIO_MODE_GPIO, -+ .gpio72 = GPIO_MODE_NATIVE, -+ .gpio73 = GPIO_MODE_NATIVE, -+ .gpio74 = GPIO_MODE_NATIVE, -+ .gpio75 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio68 = GPIO_DIR_INPUT, -+ .gpio69 = GPIO_DIR_INPUT, -+ .gpio70 = GPIO_DIR_INPUT, -+ .gpio71 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_reset = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ .reset = &pch_gpio_set1_reset, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ .reset = &pch_gpio_set2_reset, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ .reset = &pch_gpio_set3_reset, -+ }, -+}; -diff --git a/src/mainboard/dell/e6420/hda_verb.c b/src/mainboard/dell/e6420/hda_verb.c -new file mode 100644 -index 0000000000..b3803b7c65 ---- /dev/null -+++ b/src/mainboard/dell/e6420/hda_verb.c -@@ -0,0 +1,33 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/azalia_device.h> -+ -+const u32 cim_verb_data[] = { -+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */ -+ 0x10280493, /* Subsystem ID */ -+ 11, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(0, 0x10280493), -+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), -+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), -+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), -+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), -+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), -+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), -+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), -+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), -+ -+ 0x80862805, /* Codec Vendor / Device ID: Intel */ -+ 0x80860101, /* Subsystem ID */ -+ 4, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(3, 0x80860101), -+ AZALIA_PIN_CFG(3, 0x05, 0x18560010), -+ AZALIA_PIN_CFG(3, 0x06, 0x18560020), -+ AZALIA_PIN_CFG(3, 0x07, 0x18560030), -+ -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/e6420/mainboard.c b/src/mainboard/dell/e6420/mainboard.c -new file mode 100644 -index 0000000000..31e49802fc ---- /dev/null -+++ b/src/mainboard/dell/e6420/mainboard.c -@@ -0,0 +1,21 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/device.h> -+#include <drivers/intel/gma/int15.h> -+#include <southbridge/intel/bd82x6x/pch.h> -+#include <ec/acpi/ec.h> -+#include <console/console.h> -+#include <pc80/keyboard.h> -+ -+static void mainboard_enable(struct device *dev) -+{ -+ -+ /* FIXME: fix these values. */ -+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, -+ GMA_INT15_PANEL_FIT_DEFAULT, -+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -+} -+ -+struct chip_operations mainboard_ops = { -+ .enable_dev = mainboard_enable, -+}; --- -2.43.0 - diff --git a/config/coreboot/default/patches/0025-use-mirrorservice.org-for-gcc-downloads.patch b/config/coreboot/default/patches/0032-use-mirrorservice.org-for-gcc-downloads.patch index 8275d6c5..e7cfab6f 100644 --- a/config/coreboot/default/patches/0025-use-mirrorservice.org-for-gcc-downloads.patch +++ b/config/coreboot/default/patches/0032-use-mirrorservice.org-for-gcc-downloads.patch @@ -1,7 +1,7 @@ -From 936a8f113772c93d7501e7133159ab4e23436222 Mon Sep 17 00:00:00 2001 +From adb6121970034aa63da8c6303292ff81f340d9db Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 5 Nov 2023 22:57:08 +0000 -Subject: [PATCH 25/30] use mirrorservice.org for gcc downloads +Subject: [PATCH 32/39] use mirrorservice.org for gcc downloads the gnu.org 302 redirect often fails @@ -11,10 +11,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index 36565a906c..4d4ca06113 100755 +index 5faff337b4..2743f96903 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc -@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2" +@@ -69,11 +69,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2" # to the jenkins build as well, or the builder won't download it. # GCC toolchain archive locations diff --git a/config/coreboot/default/patches/0033-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch b/config/coreboot/default/patches/0033-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch deleted file mode 100644 index 39782376..00000000 --- a/config/coreboot/default/patches/0033-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch +++ /dev/null @@ -1,773 +0,0 @@ -From 5e8bff81220d4d0f663feed443e4594b76e442bf Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Wed, 31 Jan 2024 22:07:25 -0700 -Subject: [PATCH] mb/dell: Add Latitude E6520 (Sandy Bridge) - -Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec -Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> ---- - src/mainboard/dell/e6520/Kconfig | 38 +++++ - src/mainboard/dell/e6520/Kconfig.name | 2 + - src/mainboard/dell/e6520/Makefile.inc | 6 + - src/mainboard/dell/e6520/acpi/ec.asl | 9 + - src/mainboard/dell/e6520/acpi/platform.asl | 12 ++ - src/mainboard/dell/e6520/acpi/superio.asl | 3 + - src/mainboard/dell/e6520/acpi_tables.c | 16 ++ - src/mainboard/dell/e6520/board_info.txt | 6 + - src/mainboard/dell/e6520/cmos.default | 9 + - src/mainboard/dell/e6520/cmos.layout | 88 ++++++++++ - src/mainboard/dell/e6520/data.vbt | Bin 0 -> 6144 bytes - src/mainboard/dell/e6520/devicetree.cb | 66 +++++++ - src/mainboard/dell/e6520/dsdt.asl | 30 ++++ - src/mainboard/dell/e6520/early_init.c | 32 ++++ - src/mainboard/dell/e6520/gma-mainboard.ads | 20 +++ - src/mainboard/dell/e6520/gpio.c | 190 +++++++++++++++++++++ - src/mainboard/dell/e6520/hda_verb.c | 33 ++++ - src/mainboard/dell/e6520/mainboard.c | 21 +++ - 18 files changed, 581 insertions(+) - create mode 100644 src/mainboard/dell/e6520/Kconfig - create mode 100644 src/mainboard/dell/e6520/Kconfig.name - create mode 100644 src/mainboard/dell/e6520/Makefile.inc - create mode 100644 src/mainboard/dell/e6520/acpi/ec.asl - create mode 100644 src/mainboard/dell/e6520/acpi/platform.asl - create mode 100644 src/mainboard/dell/e6520/acpi/superio.asl - create mode 100644 src/mainboard/dell/e6520/acpi_tables.c - create mode 100644 src/mainboard/dell/e6520/board_info.txt - create mode 100644 src/mainboard/dell/e6520/cmos.default - create mode 100644 src/mainboard/dell/e6520/cmos.layout - create mode 100644 src/mainboard/dell/e6520/data.vbt - create mode 100644 src/mainboard/dell/e6520/devicetree.cb - create mode 100644 src/mainboard/dell/e6520/dsdt.asl - create mode 100644 src/mainboard/dell/e6520/early_init.c - create mode 100644 src/mainboard/dell/e6520/gma-mainboard.ads - create mode 100644 src/mainboard/dell/e6520/gpio.c - create mode 100644 src/mainboard/dell/e6520/hda_verb.c - create mode 100644 src/mainboard/dell/e6520/mainboard.c - -diff --git a/src/mainboard/dell/e6520/Kconfig b/src/mainboard/dell/e6520/Kconfig -new file mode 100644 -index 0000000000..db9f25b4ac ---- /dev/null -+++ b/src/mainboard/dell/e6520/Kconfig -@@ -0,0 +1,38 @@ -+if BOARD_DELL_LATITUDE_E6520 -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ select BOARD_ROMSIZE_KB_10240 -+ select EC_ACPI -+ select EC_DELL_MEC5035 -+ select GFX_GMA_PANEL_1_ON_LVDS -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ select INTEL_GMA_HAVE_VBT -+ select INTEL_INT15 -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_USES_IFD_GBE_REGION -+ select NORTHBRIDGE_INTEL_SANDYBRIDGE -+ select SERIRQ_CONTINUOUS_MODE -+ select SOUTHBRIDGE_INTEL_BD82X6X -+ select SYSTEM_TYPE_LAPTOP -+ select USE_NATIVE_RAMINIT -+ -+config DRAM_RESET_GATE_GPIO -+ default 60 -+ -+config MAINBOARD_DIR -+ default "dell/e6520" -+ -+config MAINBOARD_PART_NUMBER -+ default "Latitude E6520" -+ -+config USBDEBUG_HCD_INDEX -+ default 2 -+ -+config VGA_BIOS_ID -+ default "8086,0116" -+ -+endif # BOARD_DELL_LATITUDE_E6520 -diff --git a/src/mainboard/dell/e6520/Kconfig.name b/src/mainboard/dell/e6520/Kconfig.name -new file mode 100644 -index 0000000000..25968e80e5 ---- /dev/null -+++ b/src/mainboard/dell/e6520/Kconfig.name -@@ -0,0 +1,2 @@ -+config BOARD_DELL_LATITUDE_E6520 -+ bool "Latitude E6520" -diff --git a/src/mainboard/dell/e6520/Makefile.inc b/src/mainboard/dell/e6520/Makefile.inc -new file mode 100644 -index 0000000000..ba64e93eb8 ---- /dev/null -+++ b/src/mainboard/dell/e6520/Makefile.inc -@@ -0,0 +1,6 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+bootblock-y += early_init.c -+bootblock-y += gpio.c -+romstage-y += early_init.c -+romstage-y += gpio.c -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -diff --git a/src/mainboard/dell/e6520/acpi/ec.asl b/src/mainboard/dell/e6520/acpi/ec.asl -new file mode 100644 -index 0000000000..0d429410a9 ---- /dev/null -+++ b/src/mainboard/dell/e6520/acpi/ec.asl -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Device(EC) -+{ -+ Name (_HID, EISAID("PNP0C09")) -+ Name (_UID, 0) -+ Name (_GPE, 16) -+/* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e6520/acpi/platform.asl b/src/mainboard/dell/e6520/acpi/platform.asl -new file mode 100644 -index 0000000000..2d24bbd9b9 ---- /dev/null -+++ b/src/mainboard/dell/e6520/acpi/platform.asl -@@ -0,0 +1,12 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Method(_WAK, 1) -+{ -+ /* FIXME: EC support */ -+ Return(Package() {0, 0}) -+} -+ -+Method(_PTS,1) -+{ -+ /* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e6520/acpi/superio.asl b/src/mainboard/dell/e6520/acpi/superio.asl -new file mode 100644 -index 0000000000..55b1db5b11 ---- /dev/null -+++ b/src/mainboard/dell/e6520/acpi/superio.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <drivers/pc80/pc/ps2_controller.asl> -diff --git a/src/mainboard/dell/e6520/acpi_tables.c b/src/mainboard/dell/e6520/acpi_tables.c -new file mode 100644 -index 0000000000..e2759659bf ---- /dev/null -+++ b/src/mainboard/dell/e6520/acpi_tables.c -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <acpi/acpi_gnvs.h> -+#include <soc/nvs.h> -+ -+/* FIXME: check this function. */ -+void mainboard_fill_gnvs(struct global_nvs *gnvs) -+{ -+ /* The lid is open by default. */ -+ gnvs->lids = 1; -+ -+ /* Temperature at which OS will shutdown */ -+ gnvs->tcrt = 100; -+ /* Temperature at which OS will throttle CPU */ -+ gnvs->tpsv = 90; -+} -diff --git a/src/mainboard/dell/e6520/board_info.txt b/src/mainboard/dell/e6520/board_info.txt -new file mode 100644 -index 0000000000..34d5ad9e0b ---- /dev/null -+++ b/src/mainboard/dell/e6520/board_info.txt -@@ -0,0 +1,6 @@ -+Category: laptop -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2011 -diff --git a/src/mainboard/dell/e6520/cmos.default b/src/mainboard/dell/e6520/cmos.default -new file mode 100644 -index 0000000000..279415dfd1 ---- /dev/null -+++ b/src/mainboard/dell/e6520/cmos.default -@@ -0,0 +1,9 @@ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -+nmi=Enable -+bluetooth=Enable -+wwan=Enable -+wlan=Enable -+sata_mode=AHCI -+me_state=Disabled -diff --git a/src/mainboard/dell/e6520/cmos.layout b/src/mainboard/dell/e6520/cmos.layout -new file mode 100644 -index 0000000000..1aa7e77bce ---- /dev/null -+++ b/src/mainboard/dell/e6520/cmos.layout -@@ -0,0 +1,88 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+#400 8 r 0 reserved for century byte -+ -+# coreboot config options: southbridge -+408 1 e 1 nmi -+409 2 e 7 power_on_after_fail -+411 1 e 9 sata_mode -+ -+# coreboot config options: EC -+412 1 e 1 bluetooth -+413 1 e 1 wwan -+414 1 e 1 wlan -+ -+# coreboot config options: ME -+424 1 e 14 me_state -+425 2 h 0 me_state_prev -+ -+# coreboot config options: northbridge -+432 3 e 11 gfx_uma_size -+435 2 e 12 hybrid_graphics_mode -+440 8 h 0 volume -+ -+# VBOOT -+448 128 r 0 vbnv -+ -+# SandyBridge MRC Scrambler Seed values -+896 32 r 0 mrc_scrambler_seed -+928 32 r 0 mrc_scrambler_seed_s3 -+960 16 r 0 mrc_scrambler_seed_chk -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+2 0 Enable -+2 1 Disable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+9 0 AHCI -+9 1 Compatible -+11 0 32M -+11 1 64M -+11 2 96M -+11 3 128M -+11 4 160M -+11 5 192M -+11 6 224M -+14 0 Normal -+14 1 Disabled -+ -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 447 984 -diff --git a/src/mainboard/dell/e6520/data.vbt b/src/mainboard/dell/e6520/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..0ef16ee7cb482d2cb91ea80c3f419759355f7ba0 -GIT binary patch -literal 6144 -zcmeHKZ){Ul6hE);wSB#PZ|mL$bQ^!}HW(eF@H)0JafGfbqsZ9G21{L7Sg{or$5uN) -z_QgG55e!O(8p8*oBhhF`l$n^QF%rN;rzFNqqcPzFCd5QSB1Y7RKt1=pmTk1aFo9^Y -z+x+gi_nvdlJ@?#m&wZWW=G#bH>ze$J`&!oe*Q|E0r!)d89LYY8b$aowZEoG-uiIF+ -z#n;$ezm6V<nGnvtc?lrGaf)1_);!W0?uqnojdw-1MQM|dwy`OcF?M@A)KgVV*N2}7 -zcXx+--0R}IwzW3-+`f2k?^Av5V7MpRO-q(9rn_R1@Xlz2Ztdy`$Gf6^w6~|bKi!!7 -z9;xq*^~bxmZQn^<^<`+2s=BdSM%VW2#FguN<FO^QuDhGIFquBu677q|cSj>jWFixQ -z)4V8f0Gt`D`+>9Fr~tnJ76EJ`5D_F1cn-`0$RgN9unI6kfYkzIiO?W`ON4+34lv1_ -zNdPDkq1cf$p8^EW;TS*O$CdzNo#1fbIG_Oi0T(ti0jwyt0le_p_HlvX^CFvr)>$b> -zO-z8^CSU`w=mIK7Q)@9fR;XUzrFu{T=rRyygIZBpU9+Or>+?4R9%~G?Y-|g)Z`Sti -z+do(U*Wb-xR~DzjS<75#=Us4sH^C9U2FCbND7L7u$>M|<;t=AnRfI9C0v8c~AVg7t -zIU<3D2oK^>L;%r(*o=4*u?Mja@dDyi#4zFn;(f#^#3*76aUSs#;tJv#La-6YLRdQB -zdcvfERkvH?k~GJlfM<HR476j(@nfm+47<!Ult@^ua5M3h6A}q=C0ognX9aX4mxq)U -zXOhm=DbLene?C%_16Q)2NRV@Yacz`D;{V>Ve-1?&ZXy}n)YwnVAgNlz#zX;=IX)-F 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-z77rMcJlH4Mkc#U2(IDv>rsm1aHpsdL_RdT^i_ACcQUMIJcSus}*(?CIiy^#^=t=g1 -z+*^Zbh30&^#_bKclSy9pL$<B~pK8m*sLpIdnHM@W$nA7Ea@Z`x27K?aNK<@lCW(2L -zb@kB3H8kKy4W3Hu)NN|kd!DL^o#iR9a{QYV-Wl&r&hmIFX{ezkIV<4zFiVUQ@K>ao -z00DnFy~Uek!JRwhVX!of0)$Sa*X^S~LMQH0<E(UUx}L=|;Kgw(r(4q=nD)T52c|tR -O?SW|zOncy=dEg(6JAK&z - -literal 0 -HcmV?d00001 - -diff --git a/src/mainboard/dell/e6520/devicetree.cb b/src/mainboard/dell/e6520/devicetree.cb -new file mode 100644 -index 0000000000..cfba8ef4e7 ---- /dev/null -+++ b/src/mainboard/dell/e6520/devicetree.cb -@@ -0,0 +1,66 @@ -+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. -+ register "gfx" = "GMA_STATIC_DISPLAYS(1)" -+ register "gpu_cpu_backlight" = "0x00001312" -+ register "gpu_dp_b_hotplug" = "4" -+ register "gpu_dp_c_hotplug" = "4" -+ register "gpu_dp_d_hotplug" = "4" -+ register "gpu_panel_port_select" = "0" -+ register "gpu_panel_power_backlight_off_delay" = "2300" -+ register "gpu_panel_power_backlight_on_delay" = "2300" -+ register "gpu_panel_power_cycle_delay" = "6" -+ register "gpu_panel_power_down_delay" = "400" -+ register "gpu_panel_power_up_delay" = "400" -+ register "gpu_pch_backlight" = "0x13121312" -+ -+ register "spd_addresses" = "{0x50, 0, 0x52, 0}" -+ -+ device domain 0x0 on -+ subsystemid 0x1028 0x0494 inherit -+ -+ device ref host_bridge on end # Host bridge -+ device ref peg10 on end # PEG -+ device ref igd on end # iGPU -+ -+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH -+ register "docking_supported" = "1" -+ register "gen1_dec" = "0x007c0681" -+ register "gen2_dec" = "0x007c0901" -+ register "gen3_dec" = "0x003c07e1" -+ register "gen4_dec" = "0x001c0901" -+ register "gpi0_routing" = "2" -+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }" -+ register "pcie_port_coalesce" = "1" -+ register "sata_interface_speed_support" = "0x3" -+ register "sata_port_map" = "0x3b" -+ register "spi_lvscc" = "0x2005" -+ register "spi_uvscc" = "0x2005" -+ -+ device ref mei1 off end -+ device ref mei2 off end -+ device ref me_ide_r off end -+ device ref me_kt off end -+ device ref gbe on end -+ device ref ehci2 on end -+ device ref hda on end -+ device ref pcie_rp1 on end -+ device ref pcie_rp2 on end -+ device ref pcie_rp3 on end -+ device ref pcie_rp4 on end -+ device ref pcie_rp5 off end -+ device ref pcie_rp6 on end -+ device ref pcie_rp7 off end -+ device ref pcie_rp8 off end -+ device ref ehci1 on end -+ device ref pci_bridge off end -+ device ref lpc on -+ chip ec/dell/mec5035 -+ device pnp ff.0 on end -+ end -+ end -+ device ref sata1 on end -+ device ref smbus on end -+ device ref sata2 off end -+ device ref thermal off end -+ end -+ end -+end -diff --git a/src/mainboard/dell/e6520/dsdt.asl b/src/mainboard/dell/e6520/dsdt.asl -new file mode 100644 -index 0000000000..7d13c55b08 ---- /dev/null -+++ b/src/mainboard/dell/e6520/dsdt.asl -@@ -0,0 +1,30 @@ -+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+ -+#include <acpi/acpi.h> -+ -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20141018 /* OEM revision */ -+) -+{ -+ #include <acpi/dsdt_top.asl> -+ #include "acpi/platform.asl" -+ #include <cpu/intel/common/acpi/cpu.asl> -+ #include <southbridge/intel/common/acpi/platform.asl> -+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> -+ #include <southbridge/intel/common/acpi/sleepstates.asl> -+ -+ Device (\_SB.PCI0) -+ { -+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> -+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl> -+ #include <southbridge/intel/bd82x6x/acpi/pch.asl> -+ } -+} -diff --git a/src/mainboard/dell/e6520/early_init.c b/src/mainboard/dell/e6520/early_init.c -new file mode 100644 -index 0000000000..2a37091df6 ---- /dev/null -+++ b/src/mainboard/dell/e6520/early_init.c -@@ -0,0 +1,32 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+ -+#include <bootblock_common.h> -+#include <device/pci_ops.h> -+#include <ec/dell/mec5035/mec5035.h> -+#include <southbridge/intel/bd82x6x/pch.h> -+ -+const struct southbridge_usb_port mainboard_usb_ports[] = { -+ { 1, 1, 0 }, -+ { 1, 1, 0 }, -+ { 1, 1, 1 }, -+ { 1, 1, 1 }, -+ { 1, 0, 2 }, -+ { 1, 1, 2 }, -+ { 1, 0, 3 }, -+ { 1, 0, 3 }, -+ { 1, 1, 5 }, -+ { 1, 1, 5 }, -+ { 1, 1, 7 }, -+ { 1, 1, 6 }, -+ { 1, 0, 6 }, -+ { 1, 0, 7 }, -+}; -+ -+void bootblock_mainboard_early_init(void) -+{ -+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN -+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN -+ | COMB_LPC_EN | COMA_LPC_EN); -+ mec5035_early_init(); -+} -diff --git a/src/mainboard/dell/e6520/gma-mainboard.ads b/src/mainboard/dell/e6520/gma-mainboard.ads -new file mode 100644 -index 0000000000..2a16f44360 ---- /dev/null -+++ b/src/mainboard/dell/e6520/gma-mainboard.ads -@@ -0,0 +1,20 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ ( -+ HDMI1, -- mainboard HDMI -+ DP2, -- dock DP -+ DP3, -- dock DP -+ Analog, -- mainboard VGA -+ LVDS, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/e6520/gpio.c b/src/mainboard/dell/e6520/gpio.c -new file mode 100644 -index 0000000000..61f01816c4 ---- /dev/null -+++ b/src/mainboard/dell/e6520/gpio.c -@@ -0,0 +1,190 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <southbridge/intel/common/gpio.h> -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_GPIO, -+ .gpio1 = GPIO_MODE_NATIVE, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_NATIVE, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_NATIVE, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_GPIO, -+ .gpio8 = GPIO_MODE_GPIO, -+ .gpio9 = GPIO_MODE_NATIVE, -+ .gpio10 = GPIO_MODE_NATIVE, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_GPIO, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_GPIO, -+ .gpio18 = GPIO_MODE_NATIVE, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_NATIVE, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_GPIO, -+ .gpio31 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio0 = GPIO_DIR_INPUT, -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio7 = GPIO_DIR_INPUT, -+ .gpio8 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio15 = GPIO_DIR_INPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio17 = GPIO_DIR_INPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_INPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+ .gpio30 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio30 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_reset = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio0 = GPIO_INVERT, -+ .gpio8 = GPIO_INVERT, -+ .gpio14 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_NATIVE, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_GPIO, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_GPIO, -+ .gpio52 = GPIO_MODE_GPIO, -+ .gpio53 = GPIO_MODE_NATIVE, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_NATIVE, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_OUTPUT, -+ .gpio35 = GPIO_DIR_INPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio45 = GPIO_DIR_OUTPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_OUTPUT, -+ .gpio51 = GPIO_DIR_INPUT, -+ .gpio52 = GPIO_DIR_INPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio34 = GPIO_LEVEL_HIGH, -+ .gpio45 = GPIO_LEVEL_LOW, -+ .gpio49 = GPIO_LEVEL_LOW, -+ .gpio60 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_reset = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_NATIVE, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_NATIVE, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_GPIO, -+ .gpio69 = GPIO_MODE_GPIO, -+ .gpio70 = GPIO_MODE_GPIO, -+ .gpio71 = GPIO_MODE_GPIO, -+ .gpio72 = GPIO_MODE_NATIVE, -+ .gpio73 = GPIO_MODE_NATIVE, -+ .gpio74 = GPIO_MODE_NATIVE, -+ .gpio75 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio68 = GPIO_DIR_INPUT, -+ .gpio69 = GPIO_DIR_INPUT, -+ .gpio70 = GPIO_DIR_INPUT, -+ .gpio71 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_reset = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ .reset = &pch_gpio_set1_reset, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ .reset = &pch_gpio_set2_reset, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ .reset = &pch_gpio_set3_reset, -+ }, -+}; -diff --git a/src/mainboard/dell/e6520/hda_verb.c b/src/mainboard/dell/e6520/hda_verb.c -new file mode 100644 -index 0000000000..d33eb3b4c5 ---- /dev/null -+++ b/src/mainboard/dell/e6520/hda_verb.c -@@ -0,0 +1,33 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/azalia_device.h> -+ -+const u32 cim_verb_data[] = { -+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */ -+ 0x10280494, /* Subsystem ID */ -+ 11, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(0, 0x10280494), -+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), -+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), -+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), -+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), -+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), -+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), -+ AZALIA_PIN_CFG(0, 0x11, 0x400000f2), -+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), -+ -+ 0x80862805, /* Codec Vendor / Device ID: Intel */ -+ 0x80860101, /* Subsystem ID */ -+ 4, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(3, 0x80860101), -+ AZALIA_PIN_CFG(3, 0x05, 0x18560010), -+ AZALIA_PIN_CFG(3, 0x06, 0x18560020), -+ AZALIA_PIN_CFG(3, 0x07, 0x18560030), -+ -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/e6520/mainboard.c b/src/mainboard/dell/e6520/mainboard.c -new file mode 100644 -index 0000000000..31e49802fc ---- /dev/null -+++ b/src/mainboard/dell/e6520/mainboard.c -@@ -0,0 +1,21 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/device.h> -+#include <drivers/intel/gma/int15.h> -+#include <southbridge/intel/bd82x6x/pch.h> -+#include <ec/acpi/ec.h> -+#include <console/console.h> -+#include <pc80/keyboard.h> -+ -+static void mainboard_enable(struct device *dev) -+{ -+ -+ /* FIXME: fix these values. */ -+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, -+ GMA_INT15_PANEL_FIT_DEFAULT, -+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -+} -+ -+struct chip_operations mainboard_ops = { -+ .enable_dev = mainboard_enable, -+}; --- -2.43.0 - diff --git a/config/coreboot/default/patches/0030-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0033-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch index e0af8372..beb65908 100644 --- a/config/coreboot/default/patches/0030-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch +++ b/config/coreboot/default/patches/0033-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch @@ -1,7 +1,7 @@ -From 4e0b62e6f0977cf922b1947955538ddca63bb954 Mon Sep 17 00:00:00 2001 +From 67b7a9e4d06d595adf8382ee83e82b5019e23afa Mon Sep 17 00:00:00 2001 From: Riku Viitanen <riku.viitanen@protonmail.com> Date: Sat, 23 Dec 2023 19:02:10 +0200 -Subject: [PATCH 30/30] mb/hp: Add Compaq Elite 8300 CMT port +Subject: [PATCH 1/1] mb/hp: Add Compaq Elite 8300 CMT port Based on autoport and Z220 SuperIO code. @@ -32,7 +32,7 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> --- .../hp/compaq_elite_8300_cmt/Kconfig | 39 ++++ .../hp/compaq_elite_8300_cmt/Kconfig.name | 2 + - .../hp/compaq_elite_8300_cmt/Makefile.inc | 7 + + .../hp/compaq_elite_8300_cmt/Makefile.mk | 7 + .../hp/compaq_elite_8300_cmt/acpi/ec.asl | 1 + .../compaq_elite_8300_cmt/acpi/platform.asl | 10 + .../hp/compaq_elite_8300_cmt/acpi/superio.asl | 29 +++ @@ -41,17 +41,17 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> .../hp/compaq_elite_8300_cmt/cmos.default | 7 + .../hp/compaq_elite_8300_cmt/cmos.layout | 74 +++++++ .../hp/compaq_elite_8300_cmt/data.vbt | Bin 0 -> 3902 bytes - .../hp/compaq_elite_8300_cmt/devicetree.cb | 161 +++++++++++++++ + .../hp/compaq_elite_8300_cmt/devicetree.cb | 177 ++++++++++++++++ .../hp/compaq_elite_8300_cmt/dsdt.asl | 26 +++ - .../hp/compaq_elite_8300_cmt/early_init.c | 31 +++ + .../hp/compaq_elite_8300_cmt/early_init.c | 14 ++ .../compaq_elite_8300_cmt/gma-mainboard.ads | 17 ++ src/mainboard/hp/compaq_elite_8300_cmt/gpio.c | 191 ++++++++++++++++++ .../hp/compaq_elite_8300_cmt/hda_verb.c | 33 +++ .../hp/compaq_elite_8300_cmt/mainboard.c | 16 ++ - 18 files changed, 661 insertions(+) + 18 files changed, 660 insertions(+) create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl @@ -121,11 +121,11 @@ index 0000000000..bd399b1e76 @@ -0,0 +1,2 @@ +config BOARD_HP_COMPAQ_ELITE_8300_CMT + bool "Compaq Elite 8300 CMT" -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk new file mode 100644 index 0000000000..fb492d3583 --- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + @@ -353,10 +353,10 @@ HcmV?d00001 diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb new file mode 100644 -index 0000000000..f4efabd792 +index 0000000000..3d21739b72 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -@@ -0,0 +1,161 @@ +@@ -0,0 +1,177 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge @@ -386,6 +386,22 @@ index 0000000000..f4efabd792 + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" ++ register "usb_port_config" = "{ ++ { 1, 0, 0 }, ++ { 1, 0, 0 }, ++ { 1, 0, 1 }, ++ { 1, 0, 1 }, ++ { 1, 0, 2 }, ++ { 1, 0, 2 }, ++ { 1, 0, 3 }, ++ { 1, 0, 3 }, ++ { 1, 0, 4 }, ++ { 1, 0, 4 }, ++ { 1, 0, 6 }, ++ { 1, 0, 5 }, ++ { 1, 0, 5 }, ++ { 1, 0, 6 } ++ }" + + device ref xhci on end # USB 3.0 Controller + device ref mei1 off end # Management Engine Interface 1 @@ -405,7 +421,7 @@ index 0000000000..f4efabd792 + device ref pcie_rp3 on end + device ref pcie_rp4 on end + device ref pcie_rp5 on end -+ device ref pcie_rp5 on end ++ device ref pcie_rp6 on end + device ref pcie_rp7 on end + device ref pcie_rp8 on end + @@ -552,10 +568,10 @@ index 0000000000..e8e2b3a3e5 +} diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c new file mode 100644 -index 0000000000..99b7891c70 +index 0000000000..8d10c6317c --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c -@@ -0,0 +1,31 @@ +@@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> @@ -565,23 +581,6 @@ index 0000000000..99b7891c70 + +#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2) + -+const struct southbridge_usb_port mainboard_usb_ports[] = { -+ { 1, 0, 0 }, -+ { 1, 0, 0 }, -+ { 1, 0, 1 }, -+ { 1, 0, 1 }, -+ { 1, 0, 2 }, -+ { 1, 0, 2 }, -+ { 1, 0, 3 }, -+ { 1, 0, 3 }, -+ { 1, 0, 4 }, -+ { 1, 0, 4 }, -+ { 1, 0, 6 }, -+ { 1, 0, 5 }, -+ { 1, 0, 5 }, -+ { 1, 0, 6 }, -+}; -+ +void bootblock_mainboard_early_init(void) +{ + if (CONFIG(CONSOLE_SERIAL)) diff --git a/config/coreboot/default/patches/0034-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch b/config/coreboot/default/patches/0034-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch deleted file mode 100644 index 9a1bea26..00000000 --- a/config/coreboot/default/patches/0034-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch +++ /dev/null @@ -1,780 +0,0 @@ -From 86911e57c556389eed386bc23d5e87dd520afec9 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Wed, 31 Jan 2024 22:57:07 -0700 -Subject: [PATCH] mb/dell: Add Latitude E5530 (Ivy Bridge) - -Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> ---- - src/mainboard/dell/e5530/Kconfig | 37 ++++ - src/mainboard/dell/e5530/Kconfig.name | 2 + - src/mainboard/dell/e5530/Makefile.inc | 6 + - src/mainboard/dell/e5530/acpi/ec.asl | 9 + - src/mainboard/dell/e5530/acpi/platform.asl | 12 ++ - src/mainboard/dell/e5530/acpi/superio.asl | 3 + - src/mainboard/dell/e5530/acpi_tables.c | 16 ++ - src/mainboard/dell/e5530/board_info.txt | 6 + - src/mainboard/dell/e5530/cmos.default | 9 + - src/mainboard/dell/e5530/cmos.layout | 88 ++++++++++ - src/mainboard/dell/e5530/data.vbt | Bin 0 -> 6144 bytes - src/mainboard/dell/e5530/devicetree.cb | 70 ++++++++ - src/mainboard/dell/e5530/dsdt.asl | 30 ++++ - src/mainboard/dell/e5530/early_init.c | 32 ++++ - src/mainboard/dell/e5530/gma-mainboard.ads | 20 +++ - src/mainboard/dell/e5530/gpio.c | 194 +++++++++++++++++++++ - src/mainboard/dell/e5530/hda_verb.c | 33 ++++ - src/mainboard/dell/e5530/mainboard.c | 21 +++ - 18 files changed, 588 insertions(+) - create mode 100644 src/mainboard/dell/e5530/Kconfig - create mode 100644 src/mainboard/dell/e5530/Kconfig.name - create mode 100644 src/mainboard/dell/e5530/Makefile.inc - create mode 100644 src/mainboard/dell/e5530/acpi/ec.asl - create mode 100644 src/mainboard/dell/e5530/acpi/platform.asl - create mode 100644 src/mainboard/dell/e5530/acpi/superio.asl - create mode 100644 src/mainboard/dell/e5530/acpi_tables.c - create mode 100644 src/mainboard/dell/e5530/board_info.txt - create mode 100644 src/mainboard/dell/e5530/cmos.default - create mode 100644 src/mainboard/dell/e5530/cmos.layout - create mode 100644 src/mainboard/dell/e5530/data.vbt - create mode 100644 src/mainboard/dell/e5530/devicetree.cb - create mode 100644 src/mainboard/dell/e5530/dsdt.asl - create mode 100644 src/mainboard/dell/e5530/early_init.c - create mode 100644 src/mainboard/dell/e5530/gma-mainboard.ads - create mode 100644 src/mainboard/dell/e5530/gpio.c - create mode 100644 src/mainboard/dell/e5530/hda_verb.c - create mode 100644 src/mainboard/dell/e5530/mainboard.c - -diff --git a/src/mainboard/dell/e5530/Kconfig b/src/mainboard/dell/e5530/Kconfig -new file mode 100644 -index 0000000000..3faae4ee50 ---- /dev/null -+++ b/src/mainboard/dell/e5530/Kconfig -@@ -0,0 +1,37 @@ -+if BOARD_DELL_LATITUDE_E5530 -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ select BOARD_ROMSIZE_KB_12288 -+ select EC_ACPI -+ select EC_DELL_MEC5035 -+ select GFX_GMA_PANEL_1_ON_LVDS -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ select INTEL_GMA_HAVE_VBT -+ select INTEL_INT15 -+ select MAINBOARD_HAS_LIBGFXINIT -+ select NORTHBRIDGE_INTEL_SANDYBRIDGE -+ select SERIRQ_CONTINUOUS_MODE -+ select SOUTHBRIDGE_INTEL_C216 -+ select SYSTEM_TYPE_LAPTOP -+ select USE_NATIVE_RAMINIT -+ -+config DRAM_RESET_GATE_GPIO -+ default 60 -+ -+config MAINBOARD_DIR -+ default "dell/e5530" -+ -+config MAINBOARD_PART_NUMBER -+ default "Latitude E5530" -+ -+config USBDEBUG_HCD_INDEX -+ default 2 -+ -+config VGA_BIOS_ID -+ default "8086,0166" -+ -+endif # BOARD_DELL_LATITUDE_E5530 -diff --git a/src/mainboard/dell/e5530/Kconfig.name b/src/mainboard/dell/e5530/Kconfig.name -new file mode 100644 -index 0000000000..775963204a ---- /dev/null -+++ b/src/mainboard/dell/e5530/Kconfig.name -@@ -0,0 +1,2 @@ -+config BOARD_DELL_LATITUDE_E5530 -+ bool "Latitude E5530" -diff --git a/src/mainboard/dell/e5530/Makefile.inc b/src/mainboard/dell/e5530/Makefile.inc -new file mode 100644 -index 0000000000..ba64e93eb8 ---- /dev/null -+++ b/src/mainboard/dell/e5530/Makefile.inc -@@ -0,0 +1,6 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+bootblock-y += early_init.c -+bootblock-y += gpio.c -+romstage-y += early_init.c -+romstage-y += gpio.c -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -diff --git a/src/mainboard/dell/e5530/acpi/ec.asl b/src/mainboard/dell/e5530/acpi/ec.asl -new file mode 100644 -index 0000000000..0d429410a9 ---- /dev/null -+++ b/src/mainboard/dell/e5530/acpi/ec.asl -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Device(EC) -+{ -+ Name (_HID, EISAID("PNP0C09")) -+ Name (_UID, 0) -+ Name (_GPE, 16) -+/* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e5530/acpi/platform.asl b/src/mainboard/dell/e5530/acpi/platform.asl -new file mode 100644 -index 0000000000..2d24bbd9b9 ---- /dev/null -+++ b/src/mainboard/dell/e5530/acpi/platform.asl -@@ -0,0 +1,12 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Method(_WAK, 1) -+{ -+ /* FIXME: EC support */ -+ Return(Package() {0, 0}) -+} -+ -+Method(_PTS,1) -+{ -+ /* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e5530/acpi/superio.asl b/src/mainboard/dell/e5530/acpi/superio.asl -new file mode 100644 -index 0000000000..55b1db5b11 ---- /dev/null -+++ b/src/mainboard/dell/e5530/acpi/superio.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <drivers/pc80/pc/ps2_controller.asl> -diff --git a/src/mainboard/dell/e5530/acpi_tables.c b/src/mainboard/dell/e5530/acpi_tables.c -new file mode 100644 -index 0000000000..e2759659bf ---- /dev/null -+++ b/src/mainboard/dell/e5530/acpi_tables.c -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <acpi/acpi_gnvs.h> -+#include <soc/nvs.h> -+ -+/* FIXME: check this function. */ -+void mainboard_fill_gnvs(struct global_nvs *gnvs) -+{ -+ /* The lid is open by default. */ -+ gnvs->lids = 1; -+ -+ /* Temperature at which OS will shutdown */ -+ gnvs->tcrt = 100; -+ /* Temperature at which OS will throttle CPU */ -+ gnvs->tpsv = 90; -+} -diff --git a/src/mainboard/dell/e5530/board_info.txt b/src/mainboard/dell/e5530/board_info.txt -new file mode 100644 -index 0000000000..4601a4aaba ---- /dev/null -+++ b/src/mainboard/dell/e5530/board_info.txt -@@ -0,0 +1,6 @@ -+Category: laptop -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2012 -diff --git a/src/mainboard/dell/e5530/cmos.default b/src/mainboard/dell/e5530/cmos.default -new file mode 100644 -index 0000000000..279415dfd1 ---- /dev/null -+++ b/src/mainboard/dell/e5530/cmos.default -@@ -0,0 +1,9 @@ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -+nmi=Enable -+bluetooth=Enable -+wwan=Enable -+wlan=Enable -+sata_mode=AHCI -+me_state=Disabled -diff --git a/src/mainboard/dell/e5530/cmos.layout b/src/mainboard/dell/e5530/cmos.layout -new file mode 100644 -index 0000000000..1aa7e77bce ---- /dev/null -+++ b/src/mainboard/dell/e5530/cmos.layout -@@ -0,0 +1,88 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+#400 8 r 0 reserved for century byte -+ -+# coreboot config options: southbridge -+408 1 e 1 nmi -+409 2 e 7 power_on_after_fail -+411 1 e 9 sata_mode -+ -+# coreboot config options: EC -+412 1 e 1 bluetooth -+413 1 e 1 wwan -+414 1 e 1 wlan -+ -+# coreboot config options: ME -+424 1 e 14 me_state -+425 2 h 0 me_state_prev -+ -+# coreboot config options: northbridge -+432 3 e 11 gfx_uma_size -+435 2 e 12 hybrid_graphics_mode -+440 8 h 0 volume -+ -+# VBOOT -+448 128 r 0 vbnv -+ -+# SandyBridge MRC Scrambler Seed values -+896 32 r 0 mrc_scrambler_seed -+928 32 r 0 mrc_scrambler_seed_s3 -+960 16 r 0 mrc_scrambler_seed_chk -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+2 0 Enable -+2 1 Disable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+9 0 AHCI -+9 1 Compatible -+11 0 32M -+11 1 64M -+11 2 96M -+11 3 128M -+11 4 160M -+11 5 192M -+11 6 224M -+14 0 Normal -+14 1 Disabled -+ -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 447 984 -diff --git a/src/mainboard/dell/e5530/data.vbt b/src/mainboard/dell/e5530/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..3c54b70be7856a6420d001112d7f17f8bab46ed3 -GIT binary patch -literal 6144 -zcmeHKU2Gdg5dO}0w$JA~+qs02q)iz56C9e5vuQ#oL0l3O+%|395Q2peO{y4(2uX0t -zuMja1N)bPb1cE+5)fYsCK!89MFQAGChyWpk5PuR<K|G+sLmxmOR4}u5=Rg`mj70g7 -zvgdDic6N4dW^QKhynd)>kS^cR)3#-(r*-?zo-O^C(kLvv8XM<+Y3tdt^YY!P?!oTe -zJ^ed-x6w0Lh5fN#jsv5TWE#mtd*_yky}9xDK(kOwLt+C7_AQAd#iwr=o0`gvQZ`{x -z6ZeT`x^^;8+a~jSa^o~PF@8J6N5;o#dhCwebaM;!_oisw1#O9K={qQM<@Oeu$lXeN -z#wJGcW4Y<2)-A{Bot(NoKX%>qdnw-AOi9bKT9Z~HL5|7PJDHz4kGlEx143q+26EH6 -z{4KfB^9;?<fTOaiNPy%=@LovL&q<^d1Qdi+Xex9SvIM^ZLq%9cP{A1rE>#dw(WfA; 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-@@ -0,0 +1,70 @@ -+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. -+ register "gfx" = "GMA_STATIC_DISPLAYS(1)" -+ register "gpu_cpu_backlight" = "0x00000000" -+ register "gpu_dp_b_hotplug" = "4" -+ register "gpu_dp_c_hotplug" = "4" -+ register "gpu_dp_d_hotplug" = "4" -+ register "gpu_panel_port_select" = "0" -+ register "gpu_panel_power_backlight_off_delay" = "2300" -+ register "gpu_panel_power_backlight_on_delay" = "2300" -+ register "gpu_panel_power_cycle_delay" = "6" -+ register "gpu_panel_power_down_delay" = "400" -+ register "gpu_panel_power_up_delay" = "400" -+ register "gpu_pch_backlight" = "0x03d003d0" -+ -+ register "spd_addresses" = "{0x50, 0, 0x52, 0}" -+ -+ device domain 0x0 on -+ subsystemid 0x1028 0x053d inherit -+ -+ device ref host_bridge on end -+ device ref peg10 off end -+ device ref igd on end -+ -+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH -+ register "docking_supported" = "1" -+ register "gen1_dec" = "0x007c0681" -+ register "gen2_dec" = "0x005c0921" -+ register "gen3_dec" = "0x003c07e1" -+ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC -+ register "gpi0_routing" = "2" -+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }" -+ register "pcie_port_coalesce" = "1" -+ register "sata_interface_speed_support" = "0x3" -+ register "sata_port_map" = "0x33" -+ register "spi_lvscc" = "0x2005" -+ register "spi_uvscc" = "0x2005" -+ register "superspeed_capable_ports" = "0x0000000f" -+ register "xhci_overcurrent_mapping" = "0x00000c03" -+ register "xhci_switchable_ports" = "0x0000000f" -+ -+ device ref xhci on end -+ device ref mei1 off end -+ device ref mei2 off end -+ device ref me_ide_r off end -+ device ref me_kt off end -+ device ref gbe off end -+ device ref ehci2 on end -+ device ref hda on end -+ device ref pcie_rp1 on end # WWAN Slot -+ device ref pcie_rp2 on end # SLAN Slot -+ device ref pcie_rp3 on end # ExpressCard -+ device ref pcie_rp4 off end -+ device ref pcie_rp5 on end # Extra Half Mini PCIe slot -+ device ref pcie_rp6 on end # SD/MMC Card Reader -+ device ref pcie_rp7 on end # BCM5761 Ethernet -+ device ref pcie_rp8 off end -+ device ref ehci1 on end -+ device ref pci_bridge off end -+ device ref lpc on -+ chip ec/dell/mec5035 -+ device pnp ff.0 on end -+ end -+ end -+ device ref sata1 on end -+ device ref smbus on end -+ device ref sata2 off end -+ device ref thermal off end -+ end -+ end -+end -diff --git a/src/mainboard/dell/e5530/dsdt.asl b/src/mainboard/dell/e5530/dsdt.asl -new file mode 100644 -index 0000000000..7d13c55b08 ---- /dev/null -+++ b/src/mainboard/dell/e5530/dsdt.asl -@@ -0,0 +1,30 @@ -+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+ -+#include <acpi/acpi.h> -+ -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20141018 /* OEM revision */ -+) -+{ -+ #include <acpi/dsdt_top.asl> -+ #include "acpi/platform.asl" -+ #include <cpu/intel/common/acpi/cpu.asl> -+ #include <southbridge/intel/common/acpi/platform.asl> -+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> -+ #include <southbridge/intel/common/acpi/sleepstates.asl> -+ -+ Device (\_SB.PCI0) -+ { -+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> -+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl> -+ #include <southbridge/intel/bd82x6x/acpi/pch.asl> -+ } -+} -diff --git a/src/mainboard/dell/e5530/early_init.c b/src/mainboard/dell/e5530/early_init.c -new file mode 100644 -index 0000000000..00fd5f6795 ---- /dev/null -+++ b/src/mainboard/dell/e5530/early_init.c -@@ -0,0 +1,32 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+ -+#include <bootblock_common.h> -+#include <device/pci_ops.h> -+#include <ec/dell/mec5035/mec5035.h> -+#include <southbridge/intel/bd82x6x/pch.h> -+ -+const struct southbridge_usb_port mainboard_usb_ports[] = { -+ { 1, 1, 0 }, -+ { 1, 1, 0 }, -+ { 1, 1, 1 }, -+ { 1, 1, 1 }, -+ { 1, 1, 2 }, -+ { 1, 1, 2 }, -+ { 1, 1, 3 }, -+ { 1, 0, 3 }, -+ { 1, 2, 4 }, -+ { 1, 1, 4 }, -+ { 1, 1, 5 }, -+ { 1, 1, 5 }, -+ { 1, 0, 6 }, -+ { 1, 1, 6 }, -+}; -+ -+void bootblock_mainboard_early_init(void) -+{ -+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN -+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN -+ | COMB_LPC_EN | COMA_LPC_EN); -+ mec5035_early_init(); -+} -diff --git a/src/mainboard/dell/e5530/gma-mainboard.ads b/src/mainboard/dell/e5530/gma-mainboard.ads -new file mode 100644 -index 0000000000..1310830c8e ---- /dev/null -+++ b/src/mainboard/dell/e5530/gma-mainboard.ads -@@ -0,0 +1,20 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ ( -+ HDMI1, -- mainboard HDMI -+ DP2, -- dock DP -+ DP3, -- dock DP -+ Analog, --mainboard VGA -+ LVDS, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/e5530/gpio.c b/src/mainboard/dell/e5530/gpio.c -new file mode 100644 -index 0000000000..0599f13921 ---- /dev/null -+++ b/src/mainboard/dell/e5530/gpio.c -@@ -0,0 +1,194 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <southbridge/intel/common/gpio.h> -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_GPIO, -+ .gpio1 = GPIO_MODE_GPIO, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_NATIVE, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_GPIO, -+ .gpio8 = GPIO_MODE_GPIO, -+ .gpio9 = GPIO_MODE_NATIVE, -+ .gpio10 = GPIO_MODE_NATIVE, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_GPIO, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_GPIO, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_GPIO, -+ .gpio18 = GPIO_MODE_NATIVE, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_NATIVE, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_NATIVE, -+ .gpio31 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio0 = GPIO_DIR_INPUT, -+ .gpio1 = GPIO_DIR_INPUT, -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio7 = GPIO_DIR_INPUT, -+ .gpio8 = GPIO_DIR_INPUT, -+ .gpio12 = GPIO_DIR_OUTPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio15 = GPIO_DIR_INPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio17 = GPIO_DIR_INPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_OUTPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio12 = GPIO_LEVEL_HIGH, -+ .gpio28 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_reset = { -+ .gpio30 = GPIO_RESET_RSMRST, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio0 = GPIO_INVERT, -+ .gpio8 = GPIO_INVERT, -+ .gpio13 = GPIO_INVERT, -+ .gpio14 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_NATIVE, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_GPIO, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_GPIO, -+ .gpio52 = GPIO_MODE_GPIO, -+ .gpio53 = GPIO_MODE_GPIO, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_NATIVE, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_INPUT, -+ .gpio35 = GPIO_DIR_INPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio45 = GPIO_DIR_INPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_INPUT, -+ .gpio51 = GPIO_DIR_INPUT, -+ .gpio52 = GPIO_DIR_INPUT, -+ .gpio53 = GPIO_DIR_INPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio60 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_reset = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_NATIVE, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_NATIVE, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_GPIO, -+ .gpio69 = GPIO_MODE_GPIO, -+ .gpio70 = GPIO_MODE_GPIO, -+ .gpio71 = GPIO_MODE_GPIO, -+ .gpio72 = GPIO_MODE_NATIVE, -+ .gpio73 = GPIO_MODE_NATIVE, -+ .gpio74 = GPIO_MODE_GPIO, -+ .gpio75 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio68 = GPIO_DIR_INPUT, -+ .gpio69 = GPIO_DIR_INPUT, -+ .gpio70 = GPIO_DIR_INPUT, -+ .gpio71 = GPIO_DIR_INPUT, -+ .gpio74 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_reset = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ .reset = &pch_gpio_set1_reset, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ .reset = &pch_gpio_set2_reset, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ .reset = &pch_gpio_set3_reset, -+ }, -+}; -diff --git a/src/mainboard/dell/e5530/hda_verb.c b/src/mainboard/dell/e5530/hda_verb.c -new file mode 100644 -index 0000000000..4c7c36ee05 ---- /dev/null -+++ b/src/mainboard/dell/e5530/hda_verb.c -@@ -0,0 +1,33 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/azalia_device.h> -+ -+const u32 cim_verb_data[] = { -+ 0x111d76df, /* Codec Vendor / Device ID: IDT */ -+ 0x1028053d, /* Subsystem ID */ -+ 11, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(0, 0x1028053d), -+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), -+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), -+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), -+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), -+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), -+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), -+ AZALIA_PIN_CFG(0, 0x11, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x20, 0xd5a301a0), -+ -+ 0x80862806, /* Codec Vendor / Device ID: Intel */ -+ 0x80860101, /* Subsystem ID */ -+ 4, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(3, 0x80860101), -+ AZALIA_PIN_CFG(3, 0x05, 0x18560010), -+ AZALIA_PIN_CFG(3, 0x06, 0x18560020), -+ AZALIA_PIN_CFG(3, 0x07, 0x18560030), -+ -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/e5530/mainboard.c b/src/mainboard/dell/e5530/mainboard.c -new file mode 100644 -index 0000000000..31e49802fc ---- /dev/null -+++ b/src/mainboard/dell/e5530/mainboard.c -@@ -0,0 +1,21 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/device.h> -+#include <drivers/intel/gma/int15.h> -+#include <southbridge/intel/bd82x6x/pch.h> -+#include <ec/acpi/ec.h> -+#include <console/console.h> -+#include <pc80/keyboard.h> -+ -+static void mainboard_enable(struct device *dev) -+{ -+ -+ /* FIXME: fix these values. */ -+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, -+ GMA_INT15_PANEL_FIT_DEFAULT, -+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -+} -+ -+struct chip_operations mainboard_ops = { -+ .enable_dev = mainboard_enable, -+}; --- -2.43.0 - diff --git a/config/coreboot/default/patches/0034-mb-hp-Add-Elitebook-8560w-as-an-HP-Sandy-Ivy-Bridge-.patch b/config/coreboot/default/patches/0034-mb-hp-Add-Elitebook-8560w-as-an-HP-Sandy-Ivy-Bridge-.patch deleted file mode 100644 index 458c3723..00000000 --- a/config/coreboot/default/patches/0034-mb-hp-Add-Elitebook-8560w-as-an-HP-Sandy-Ivy-Bridge-.patch +++ /dev/null @@ -1,1556 +0,0 @@ -From dac71d8ed89f1f1d295157aa62c678e35a320222 Mon Sep 17 00:00:00 2001 -From: Iru Cai <mytbk920423@gmail.com> -Date: Tue, 5 Mar 2019 16:27:36 +0800 -Subject: [PATCH] mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop - variant - -Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 -Signed-off-by: Iru Cai <mytbk920423@gmail.com> ---- - Documentation/mainboard/hp/8560w.md | 82 +++++++ - Documentation/mainboard/hp/8560w_flash.webp | Bin 0 -> 51432 bytes - Documentation/mainboard/index.md | 1 + - src/mainboard/hp/snb_ivb_laptops/Kconfig | 10 +- - src/mainboard/hp/snb_ivb_laptops/Kconfig.name | 3 + - .../variants/8560w/board_info.txt | 7 + - .../variants/8560w/early_init.c | 36 +++ - .../hp/snb_ivb_laptops/variants/8560w/gpio.c | 224 ++++++++++++++++++ - .../snb_ivb_laptops/variants/8560w/hda_verb.c | 25 ++ - .../variants/8560w/overridetree.cb | 51 ++++ - 10 files changed, 438 insertions(+), 1 deletion(-) - create mode 100644 Documentation/mainboard/hp/8560w.md - create mode 100644 Documentation/mainboard/hp/8560w_flash.webp - create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt - create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c - create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c - create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c - create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb - -diff --git a/Documentation/mainboard/hp/8560w.md b/Documentation/mainboard/hp/8560w.md -new file mode 100644 -index 0000000000..cc35a0be1f ---- /dev/null -+++ b/Documentation/mainboard/hp/8560w.md -@@ -0,0 +1,82 @@ -+# HP EliteBook 8560w -+ -+This page describes how to run coreboot on the [HP EliteBook 8560w]. -+ -+## Required proprietary blobs -+ -+- Intel Firmware Descriptor, ME and GbE firmware -+- EC: please read [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops) -+ -+## Flashing instructions -+ -+HP EliteBook 8560w has an 8MiB SOIC-8 flash chip on the bottom of the -+mainboard. You just need to remove the service cover, and use an SOIC-8 -+clip to read and flash the chip. -+ -+ -+ -+```eval_rst -++---------------------+------------+ -+| Type | Value | -++=====================+============+ -+| Socketed flash | no | -++---------------------+------------+ -+| Model | MX25L6406E | -++---------------------+------------+ -+| Size | 8 MiB | -++---------------------+------------+ -+| Package | SOIC-8 | -++---------------------+------------+ -+| Write protection | no | -++---------------------+------------+ -+| Dual BIOS feature | no | -++---------------------+------------+ -+| In circuit flashing | yes | -++---------------------+------------+ -+| Internal flashing | yes | -++---------------------+------------+ -+``` -+ -+## Untested -+ -+- mainboards with 4 memory slots -+ -+## Working -+ -+- i7-2720QM, 8G+8G -+- Arch Linux boot from SeaBIOS payload -+- EHCI debug: the port is beside the eSATA port -+- SATA -+- eSATA -+- USB2 and USB3 -+- keyboard -+- Gigabit Ethernet -+- WLAN -+- WWAN -+- VGA and DisplayPort -+- audio -+- EC ACPI -+- Using `me_cleaner` -+- dock: PS/2 keyboard, USB, DisplayPort -+- TPM -+- S3 suspend/resume -+ -+## Technology -+ -+```eval_rst -++------------------+--------------------------------------------------+ -+| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | -++------------------+--------------------------------------------------+ -+| Southbridge | bd82x6x | -++------------------+--------------------------------------------------+ -+| CPU | model_206ax | -++------------------+--------------------------------------------------+ -+| Super I/O | SMSC LPC47n217 | -++------------------+--------------------------------------------------+ -+| EC | SMSC KBC1126 | -++------------------+--------------------------------------------------+ -+| Coprocessor | Intel Management Engine | -++------------------+--------------------------------------------------+ -+``` -+ -+[HP EliteBook 8560w]: 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-zj{%R4dG@bh_)ig<&rxh}yBLqgyoNEA{C~#1tKjGY&s4zw0G2@hwCAzFdKB?SVs9-P -zHQC5L%~ggn_+EKEPh(fz+DmzN9PKzB!lQ)c0Y0_M9fv*2R~mJ?l~EYpGm-~dn$p_9 -zurpf3(jK{9e!r=!OaX32YQ4|N<+||Rzl9C9t#QTK+`B%3rb>fttSWPyga)`T8|e1h -zZPl!n$`DGVGJ%E2uJvV*M7U%3b6k&)U5Z<Rax>}lsH4oMX3gbi3!E`fNEy$yMYkOO -zbz#5~E(cLjo;O!<fhE1MxDv2<&_x+@yyH0RJxQk6>ArP{n{fckAUMY#F{qQSDkx@= -zA}FrGeAnO~dQ1^wTOTa_@y{b1)n|(Yk4kW2$1HMjK>2~sVL;062^@Zv5k~rs^=OQ+ -z2RI(|#vgy!59LfmAxA=SRJ^rWZU8y`=l;qn{&Szss*Zf~-+2E3&_y63C{I1<jJfMm -zo((q@M3u_+qi_EJuBN~yntD(KUSB+s^``6u)Zh<J)PxN5pkyL2qvaSh74Pd(o|FIx -z&w4;YtF^E(gVw!g;eF<p2ZygMF7+6#W_yt$hH$3<3?6vvURQyUP9)K5l^HbdkEDg( -zp2`5%ZOG&JqwUh2HRY24((6`?qazQnj(-~YuW=m-rDtq)G^~sEv;LAkko!)VDyshg -zY3a<X%8V`t{ykoE@n+@*x3P{Z$Zj3wl2`J`z~MmdeJjlaxA%|dOma?gb48G)QcYR2 -G|JeY!zvB4- - -literal 0 -HcmV?d00001 - -diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md -index 519d88873c..a6be27ae09 100644 ---- a/Documentation/mainboard/index.md -+++ b/Documentation/mainboard/index.md -@@ -84,6 +84,7 @@ The boards in this section are not real mainboards, but emulators. - - [HP Sure Start](hp/hp_sure_start.md) - - [EliteBook 2170p](hp/2170p.md) - - [EliteBook 2560p](hp/2560p.md) -+- [EliteBook 8560w](hp/8560w.md) - - [EliteBook 8760w](hp/8760w.md) - - [EliteBook Folio 9480m](hp/folio_9480m.md) - - [EliteBook 820 G2](hp/elitebook_820_g2.md) -diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig -index f0bd55f64f..f180bca87f 100644 ---- a/src/mainboard/hp/snb_ivb_laptops/Kconfig -+++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig -@@ -69,6 +69,12 @@ config BOARD_HP_8470P - select SOUTHBRIDGE_INTEL_C216 - select SUPERIO_SMSC_LPC47N217 - -+config BOARD_HP_8560W -+ select BOARD_HP_SNB_IVB_LAPTOPS_COMMON -+ select BOARD_ROMSIZE_KB_8192 -+ select SOUTHBRIDGE_INTEL_BD82X6X -+ select SUPERIO_SMSC_LPC47N217 -+ - config BOARD_HP_8770W - select BOARD_HP_SNB_IVB_LAPTOPS_COMMON - select BOARD_ROMSIZE_KB_16384 -@@ -118,6 +124,7 @@ config VARIANT_DIR - default "2760p" if BOARD_HP_2760P - default "8460p" if BOARD_HP_8460P - default "8470p" if BOARD_HP_8470P -+ default "8560w" if BOARD_HP_8560W - default "8770w" if BOARD_HP_8770W - default "folio_9470m" if BOARD_HP_FOLIO_9470M - default "probook_6360b" if BOARD_HP_PROBOOK_6360B -@@ -130,6 +137,7 @@ config MAINBOARD_PART_NUMBER - default "EliteBook 2760p" if BOARD_HP_2760P - default "EliteBook 8460p" if BOARD_HP_8460P - default "EliteBook 8470p" if BOARD_HP_8470P -+ default "EliteBook 8560w" if BOARD_HP_8560W - default "EliteBook 8770w" if BOARD_HP_8770W - default "EliteBook Folio 9470m" if BOARD_HP_FOLIO_9470M - default "ProBook 6360b" if BOARD_HP_PROBOOK_6360B -@@ -146,7 +154,7 @@ config VGA_BIOS_ID - config USBDEBUG_HCD_INDEX - int - default 0 if BOARD_HP_2170P || BOARD_HP_FOLIO_9470M -- default 1 if BOARD_HP_2560P || BOARD_HP_2760P || BOARD_HP_8460P -+ default 1 if BOARD_HP_2560P || BOARD_HP_2760P || BOARD_HP_8460P || BOARD_HP_8560W - default 2 if BOARD_HP_2570P || BOARD_HP_8470P || BOARD_HP_8770W - default 1 if BOARD_HP_PROBOOK_6360B # FIXME: check this - default 2 if BOARD_HP_REVOLVE_810_G1 # FIXME: check this -diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name -index f72e0f622a..fdd1b93bd7 100644 ---- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name -+++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name -@@ -18,6 +18,9 @@ config BOARD_HP_8460P - config BOARD_HP_8470P - bool "EliteBook 8470p" - -+config BOARD_HP_8560W -+ bool "EliteBook 8560w" -+ - config BOARD_HP_8770W - bool "EliteBook 8770w" - -diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt -new file mode 100644 -index 0000000000..558e904a94 ---- /dev/null -+++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt -@@ -0,0 +1,7 @@ -+Category: laptop -+Board URL: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/5071171 -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2011 -diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c -new file mode 100644 -index 0000000000..20c4b68911 ---- /dev/null -+++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c -@@ -0,0 +1,36 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include <bootblock_common.h> -+#include <southbridge/intel/bd82x6x/pch.h> -+#include <superio/smsc/lpc47n217/lpc47n217.h> -+#include <ec/hp/kbc1126/ec.h> -+ -+#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) -+ -+const struct southbridge_usb_port mainboard_usb_ports[] = { -+ { 1, 1, 0 }, /* USB0 */ -+ { 1, 1, 0 }, /* USB1 */ -+ { 1, 1, 1 }, /* eSATA */ -+ { 1, 1, 1 }, /* camera */ -+ { 0, 0, 2 }, -+ { 1, 0, 2 }, /* bluetooth */ -+ { 0, 0, 3 }, -+ { 1, 0, 3 }, -+ { 0, 1, 4 }, -+ { 1, 1, 4 }, /* WWAN */ -+ { 1, 0, 5 }, -+ { 1, 0, 5 }, /* dock */ -+ { 1, 0, 6 }, -+ { 1, 0, 6 }, -+}; -+ -+void bootblock_mainboard_early_init(void) -+{ -+ lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -+ kbc1126_enter_conf(); -+ kbc1126_mailbox_init(); -+ kbc1126_kbc_init(); -+ kbc1126_ec_init(); -+ kbc1126_pm1_init(); -+ kbc1126_exit_conf(); -+} -diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c -new file mode 100644 -index 0000000000..560d668d6f ---- /dev/null -+++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c -@@ -0,0 +1,224 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include <southbridge/intel/common/gpio.h> -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_GPIO, -+ .gpio1 = GPIO_MODE_GPIO, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_NATIVE, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_GPIO, -+ .gpio8 = GPIO_MODE_GPIO, -+ .gpio9 = GPIO_MODE_NATIVE, -+ .gpio10 = GPIO_MODE_GPIO, -+ .gpio11 = GPIO_MODE_GPIO, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_GPIO, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_GPIO, -+ .gpio18 = GPIO_MODE_NATIVE, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_NATIVE, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_GPIO, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_NATIVE, -+ .gpio31 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio0 = GPIO_DIR_OUTPUT, -+ .gpio1 = GPIO_DIR_INPUT, -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio7 = GPIO_DIR_INPUT, -+ .gpio8 = GPIO_DIR_INPUT, -+ .gpio10 = GPIO_DIR_INPUT, -+ .gpio11 = GPIO_DIR_OUTPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio15 = GPIO_DIR_INPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio17 = GPIO_DIR_OUTPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_OUTPUT, -+ .gpio23 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_OUTPUT, -+ .gpio27 = GPIO_DIR_OUTPUT, -+ .gpio28 = GPIO_DIR_OUTPUT, -+ .gpio29 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio0 = GPIO_LEVEL_LOW, -+ .gpio11 = GPIO_LEVEL_LOW, -+ .gpio17 = GPIO_LEVEL_HIGH, -+ .gpio22 = GPIO_LEVEL_HIGH, -+ .gpio24 = GPIO_LEVEL_HIGH, -+ .gpio27 = GPIO_LEVEL_LOW, -+ .gpio28 = GPIO_LEVEL_LOW, -+ .gpio29 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_reset = { -+ .gpio24 = GPIO_RESET_RSMRST, -+ .gpio30 = GPIO_RESET_RSMRST, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio1 = GPIO_INVERT, -+ .gpio3 = GPIO_INVERT, -+ .gpio6 = GPIO_INVERT, -+ .gpio7 = GPIO_INVERT, -+ .gpio10 = GPIO_INVERT, -+ .gpio13 = GPIO_INVERT, -+ .gpio14 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_NATIVE, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_NATIVE, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_GPIO, -+ .gpio45 = GPIO_MODE_NATIVE, -+ .gpio46 = GPIO_MODE_GPIO, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_GPIO, -+ .gpio51 = GPIO_MODE_GPIO, -+ .gpio52 = GPIO_MODE_GPIO, -+ .gpio53 = GPIO_MODE_GPIO, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_GPIO, -+ .gpio56 = GPIO_MODE_NATIVE, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_GPIO, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio33 = GPIO_DIR_OUTPUT, -+ .gpio34 = GPIO_DIR_INPUT, -+ .gpio35 = GPIO_DIR_OUTPUT, -+ .gpio37 = GPIO_DIR_OUTPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio44 = GPIO_DIR_INPUT, -+ .gpio46 = GPIO_DIR_INPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_OUTPUT, -+ .gpio50 = GPIO_DIR_INPUT, -+ .gpio51 = GPIO_DIR_INPUT, -+ .gpio52 = GPIO_DIR_INPUT, -+ .gpio53 = GPIO_DIR_OUTPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio55 = GPIO_DIR_INPUT, -+ .gpio57 = GPIO_DIR_OUTPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+ .gpio61 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio33 = GPIO_LEVEL_LOW, -+ .gpio35 = GPIO_LEVEL_LOW, -+ .gpio37 = GPIO_LEVEL_LOW, -+ .gpio49 = GPIO_LEVEL_LOW, -+ .gpio53 = GPIO_LEVEL_HIGH, -+ .gpio57 = GPIO_LEVEL_LOW, -+ .gpio60 = GPIO_LEVEL_HIGH, -+ .gpio61 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_reset = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_NATIVE, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_NATIVE, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_GPIO, -+ .gpio69 = GPIO_MODE_GPIO, -+ .gpio70 = GPIO_MODE_GPIO, -+ .gpio71 = GPIO_MODE_GPIO, -+ .gpio72 = GPIO_MODE_GPIO, -+ .gpio73 = GPIO_MODE_GPIO, -+ .gpio74 = GPIO_MODE_GPIO, -+ .gpio75 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio68 = GPIO_DIR_OUTPUT, -+ .gpio69 = GPIO_DIR_INPUT, -+ .gpio70 = GPIO_DIR_OUTPUT, -+ .gpio71 = GPIO_DIR_OUTPUT, -+ .gpio72 = GPIO_DIR_OUTPUT, -+ .gpio73 = GPIO_DIR_OUTPUT, -+ .gpio74 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+ .gpio68 = GPIO_LEVEL_HIGH, -+ .gpio70 = GPIO_LEVEL_HIGH, -+ .gpio71 = GPIO_LEVEL_HIGH, -+ .gpio72 = GPIO_LEVEL_LOW, -+ .gpio73 = GPIO_LEVEL_HIGH, -+ .gpio74 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_reset = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ .reset = &pch_gpio_set1_reset, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ .reset = &pch_gpio_set2_reset, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ .reset = &pch_gpio_set3_reset, -+ }, -+}; -diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c -new file mode 100644 -index 0000000000..2f5469fc84 ---- /dev/null -+++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c -@@ -0,0 +1,25 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include <device/azalia_device.h> -+ -+const u32 cim_verb_data[] = { -+ 0x111d7605, /* Codec Vendor / Device ID: IDT */ -+ 0x103c1631, /* Subsystem ID */ -+ -+ 11, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(0, 0x103c1631), -+ AZALIA_PIN_CFG(0, 0x0a, 0x40f000f0), -+ AZALIA_PIN_CFG(0, 0x0b, 0x0421401f), -+ AZALIA_PIN_CFG(0, 0x0c, 0x04a11020), -+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), -+ AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), -+ AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), -+ AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), -+ AZALIA_PIN_CFG(0, 0x11, 0x90a60130), -+ AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), -+ AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb -new file mode 100644 -index 0000000000..4264270ad0 ---- /dev/null -+++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb -@@ -0,0 +1,51 @@ -+# SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/sandybridge -+ register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" -+ device domain 0 on -+ subsystemid 0x103c 0x1631 inherit -+ device pci 01.0 on end # PCIe Bridge for discrete graphics -+ device pci 02.0 off end # Internal graphics -+ -+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH -+ register "docking_supported" = "0" -+ register "gen1_dec" = "0x007c0201" -+ register "gen2_dec" = "0x000c0101" -+ register "gen3_dec" = "0x00fcfe01" -+ register "gen4_dec" = "0x000402e9" -+ register "gpi6_routing" = "2" -+ register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" -+ # HDD(0), ODD(1), eSATA(4) -+ register "sata_port_map" = "0x3b" -+ -+ device pci 1c.0 on end # PCIe Port #1, WWAN -+ device pci 1c.1 on end # PCIe Port #2, ExpressCard -+ device pci 1c.2 on end # PCIe Port #3, SD/MMC -+ device pci 1c.3 on end # PCIe Port #4, WLAN -+ device pci 1c.4 off end # PCIe Port #5 -+ device pci 1c.5 off end # PCIe Port #6 -+ device pci 1c.6 off end # PCIe Port #7 -+ device pci 1c.7 on end # PCIe Port #8, NEC USB 3.0 Host Controller -+ device pci 1f.0 on # LPC bridge -+ chip ec/hp/kbc1126 -+ register "ec_data_port" = "0x60" -+ register "ec_cmd_port" = "0x64" -+ register "ec_ctrl_reg" = "0xca" -+ register "ec_fan_ctrl_value" = "0x6b" -+ device pnp ff.1 off end -+ end -+ chip superio/smsc/lpc47n217 -+ device pnp 4e.3 on # Parallel -+ io 0x60 = 0x378 -+ irq 0x70 = 7 -+ end -+ device pnp 4e.4 on # COM1 -+ io 0x60 = 0x3f8 -+ irq 0x70 = 4 -+ end -+ device pnp 4e.5 off end # COM2 -+ end -+ end -+ end -+ end -+end --- -2.43.0 - diff --git a/config/coreboot/default/patches/0036-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0034-nb-intel-haswell-make-IOMMU-a-runtime-option.patch index 8401e8b8..ed6c0d65 100644 --- a/config/coreboot/default/patches/0036-nb-intel-haswell-make-IOMMU-a-runtime-option.patch +++ b/config/coreboot/default/patches/0034-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -1,7 +1,7 @@ -From 7c755b4502ea007f2216ea76f2ed734452def883 Mon Sep 17 00:00:00 2001 +From eef3e0d517bde40d4761a9af3c004801a89db887 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 22:51:09 +0000 -Subject: [PATCH 1/2] nb/intel/haswell: make IOMMU a runtime option +Subject: [PATCH 34/39] nb/intel/haswell: make IOMMU a runtime option When I tested graphics cards on a coreboot port for Dell OptiPlex 9020 SFF, I could not use a graphics card unless @@ -38,10 +38,10 @@ Signed-off-by: Leah Rowe <info@minifree.org> 14 files changed, 48 insertions(+) diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default -index c51001c03c..1c5c17f841 100644 +index 01bf20ad16..dfc8b80fb0 100644 --- a/src/mainboard/asrock/b85m_pro4/cmos.default +++ b/src/mainboard/asrock/b85m_pro4/cmos.default -@@ -2,3 +2,4 @@ boot_option=Fallback +@@ -4,3 +4,4 @@ boot_option=Fallback debug_level=Debug nmi=Enable power_on_after_fail=Disable @@ -68,10 +68,10 @@ index efdc333fc2..c9883ea71d 100644 # ----------------------------------------------------------------- diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default -index c51001c03c..1c5c17f841 100644 +index 01bf20ad16..dfc8b80fb0 100644 --- a/src/mainboard/asrock/h81m-hds/cmos.default +++ b/src/mainboard/asrock/h81m-hds/cmos.default -@@ -2,3 +2,4 @@ boot_option=Fallback +@@ -4,3 +4,4 @@ boot_option=Fallback debug_level=Debug nmi=Enable power_on_after_fail=Disable @@ -101,16 +101,16 @@ index c9ba76c78f..95ee3d36fb 100644 checksums diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default -index b159660aa8..8253570f19 100644 +index 6c4a2a1be7..8000eea8c0 100644 --- a/src/mainboard/dell/optiplex_9020/cmos.default +++ b/src/mainboard/dell/optiplex_9020/cmos.default -@@ -2,3 +2,4 @@ boot_option=Fallback - debug_level=Debug +@@ -4,3 +4,4 @@ debug_level=Debug nmi=Disable power_on_after_fail=Disable + fan_full_speed=Disable +iommu=Enable diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout -index c9ba76c78f..72ff9c4bee 100644 +index d10ad95b23..4a1496a878 100644 --- a/src/mainboard/dell/optiplex_9020/cmos.layout +++ b/src/mainboard/dell/optiplex_9020/cmos.layout @@ -21,6 +21,9 @@ entries @@ -118,12 +118,12 @@ index c9ba76c78f..72ff9c4bee 100644 409 2 e 5 power_on_after_fail +# turn iommu on or off -+412 1 e 6 iommu ++411 1 e 6 iommu + - # coreboot config options: check sums - 984 16 h 0 check_sum + # coreboot config options: EC + 412 1 e 1 fan_full_speed -@@ -52,6 +55,9 @@ enumerations +@@ -55,6 +58,9 @@ enumerations 5 1 Enable 5 2 Keep @@ -202,10 +202,10 @@ index 78d44c1415..f2c602f541 100644 checksums diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default -index bb8626d48b..051658d757 100644 +index 08db97c5a9..cc6b363cd9 100644 --- a/src/mainboard/lenovo/haswell/cmos.default +++ b/src/mainboard/lenovo/haswell/cmos.default -@@ -12,3 +12,4 @@ trackpoint=Enable +@@ -14,3 +14,4 @@ trackpoint=Enable backlight=Keyboard enable_dual_graphics=Disable usb_always_on=Disable @@ -232,10 +232,10 @@ index 27915d3ab7..59df76b64c 100644 # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default -index f4047147f7..eea2c36b88 100644 +index 7ce38fb5d7..6049e7938a 100644 --- a/src/mainboard/supermicro/x10slm-f/cmos.default +++ b/src/mainboard/supermicro/x10slm-f/cmos.default -@@ -3,3 +3,4 @@ debug_level=Debug +@@ -5,3 +5,4 @@ debug_level=Debug nmi=Enable power_on_after_fail=Keep hide_ast2400=Disable diff --git a/config/coreboot/default/patches/0037-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0035-dell-optiplex_9020-Disable-IOMMU-by-default.patch index c8cde72e..1b9497c2 100644 --- a/config/coreboot/default/patches/0037-dell-optiplex_9020-Disable-IOMMU-by-default.patch +++ b/config/coreboot/default/patches/0035-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -1,7 +1,7 @@ -From 61041d49b94236400e836b8ea518d3a064b95c4e Mon Sep 17 00:00:00 2001 +From b7a80abe673c279e755efbe92851ec0600467fae Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 23:00:09 +0000 -Subject: [PATCH 2/2] dell/optiplex_9020: Disable IOMMU by default +Subject: [PATCH 35/39] dell/optiplex_9020: Disable IOMMU by default Needed to make graphics cards work. Turning it on is recommended if only using iGPU, otherwise leave it off @@ -15,13 +15,13 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default -index 8253570f19..7bccc80e51 100644 +index 8000eea8c0..0700f971ee 100644 --- a/src/mainboard/dell/optiplex_9020/cmos.default +++ b/src/mainboard/dell/optiplex_9020/cmos.default -@@ -2,4 +2,4 @@ boot_option=Fallback - debug_level=Debug +@@ -4,4 +4,4 @@ debug_level=Debug nmi=Disable power_on_after_fail=Disable + fan_full_speed=Disable -iommu=Enable +iommu=Disable -- diff --git a/config/coreboot/default/patches/0035-hp8560w-Add-MXM-System-Infomation-Structure.patch b/config/coreboot/default/patches/0035-hp8560w-Add-MXM-System-Infomation-Structure.patch deleted file mode 100644 index 68ccb801..00000000 --- a/config/coreboot/default/patches/0035-hp8560w-Add-MXM-System-Infomation-Structure.patch +++ /dev/null @@ -1,41 +0,0 @@ -From b2cf0657a2058118baf6f4ec96e356de3c9e493e Mon Sep 17 00:00:00 2001 -From: Riku Viitanen <riku.viitanen@protonmail.com> -Date: Sun, 11 Feb 2024 19:02:20 +0200 -Subject: [PATCH] hp8560w: Add MXM System Infomation Structure - -Change-Id: I45b421f2d7baf8ca8dedbd3b1ab1e38392b6219b -Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> ---- - src/mainboard/hp/snb_ivb_laptops/Makefile.mk | 6 ++++++ - .../hp/snb_ivb_laptops/variants/8560w/mxm-30-sis | Bin 0 -> 129 bytes - 2 files changed, 6 insertions(+) - create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis - -diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk -index c007bb68cd..7950abbc4e 100644 ---- a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk -+++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk -@@ -9,3 +9,9 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainb - - # FIXME: Other variants with same size onboard RAM may exist. - SPD_SOURCES = hynix_4g -+ -+ifeq ($(CONFIG_BOARD_HP_8560W),y) -+cbfs-files-y += mxm-30-sis -+mxm-30-sis-file := variants/$(VARIANT_DIR)/mxm-30-sis -+mxm-30-sis-type := raw -+endif -diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis -new file mode 100644 -index 0000000000000000000000000000000000000000..7e4e245a50d8d5d36ddb22e3b1aed3fa87a2f57d -GIT binary patch -literal 129 -zcmeZ`@Qr6?sAMn@-0}aX9Rou`%?mKiz;Fq|&xF!hw;=rNM_^h3Dy{$(SAdE$zF=lx -o@?l{RW{6;7W}LwIl$Vj2apDSgHUS2PJFE;0Kxqas5d=FN0HAs+0RR91 - -literal 0 -HcmV?d00001 - --- -2.43.1 - diff --git a/config/coreboot/default/patches/0035-mb-dell-Add-Latitude-E5520-Sandybridge.patch b/config/coreboot/default/patches/0035-mb-dell-Add-Latitude-E5520-Sandybridge.patch deleted file mode 100644 index 1ca4b950..00000000 --- a/config/coreboot/default/patches/0035-mb-dell-Add-Latitude-E5520-Sandybridge.patch +++ /dev/null @@ -1,775 +0,0 @@ -From 7c7ce2087e1ff5f0eedb65793254163d01be3056 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Wed, 7 Feb 2024 10:23:38 -0700 -Subject: [PATCH] mb/dell: Add Latitude E5520 (Sandybridge) - -Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> ---- - src/mainboard/dell/e5520/Kconfig | 37 ++++ - src/mainboard/dell/e5520/Kconfig.name | 2 + - src/mainboard/dell/e5520/Makefile.inc | 5 + - src/mainboard/dell/e5520/acpi/ec.asl | 9 + - src/mainboard/dell/e5520/acpi/platform.asl | 12 ++ - src/mainboard/dell/e5520/acpi/superio.asl | 3 + - src/mainboard/dell/e5520/acpi_tables.c | 16 ++ - src/mainboard/dell/e5520/board_info.txt | 6 + - src/mainboard/dell/e5520/cmos.default | 9 + - src/mainboard/dell/e5520/cmos.layout | 88 ++++++++++ - src/mainboard/dell/e5520/data.vbt | Bin 0 -> 6144 bytes - src/mainboard/dell/e5520/devicetree.cb | 66 +++++++ - src/mainboard/dell/e5520/dsdt.asl | 30 ++++ - src/mainboard/dell/e5520/early_init.c | 32 ++++ - src/mainboard/dell/e5520/gma-mainboard.ads | 20 +++ - src/mainboard/dell/e5520/gpio.c | 195 +++++++++++++++++++++ - src/mainboard/dell/e5520/hda_verb.c | 33 ++++ - src/mainboard/dell/e5520/mainboard.c | 21 +++ - 18 files changed, 584 insertions(+) - create mode 100644 src/mainboard/dell/e5520/Kconfig - create mode 100644 src/mainboard/dell/e5520/Kconfig.name - create mode 100644 src/mainboard/dell/e5520/Makefile.inc - create mode 100644 src/mainboard/dell/e5520/acpi/ec.asl - create mode 100644 src/mainboard/dell/e5520/acpi/platform.asl - create mode 100644 src/mainboard/dell/e5520/acpi/superio.asl - create mode 100644 src/mainboard/dell/e5520/acpi_tables.c - create mode 100644 src/mainboard/dell/e5520/board_info.txt - create mode 100644 src/mainboard/dell/e5520/cmos.default - create mode 100644 src/mainboard/dell/e5520/cmos.layout - create mode 100644 src/mainboard/dell/e5520/data.vbt - create mode 100644 src/mainboard/dell/e5520/devicetree.cb - create mode 100644 src/mainboard/dell/e5520/dsdt.asl - create mode 100644 src/mainboard/dell/e5520/early_init.c - create mode 100644 src/mainboard/dell/e5520/gma-mainboard.ads - create mode 100644 src/mainboard/dell/e5520/gpio.c - create mode 100644 src/mainboard/dell/e5520/hda_verb.c - create mode 100644 src/mainboard/dell/e5520/mainboard.c - -diff --git a/src/mainboard/dell/e5520/Kconfig b/src/mainboard/dell/e5520/Kconfig -new file mode 100644 -index 0000000000..213c54cf5c ---- /dev/null -+++ b/src/mainboard/dell/e5520/Kconfig -@@ -0,0 +1,37 @@ -+if BOARD_DELL_LATITUDE_E5520 -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ select BOARD_ROMSIZE_KB_6144 -+ select EC_ACPI -+ select EC_DELL_MEC5035 -+ select GFX_GMA_PANEL_1_ON_LVDS -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ select INTEL_GMA_HAVE_VBT -+ select INTEL_INT15 -+ select MAINBOARD_HAS_LIBGFXINIT -+ select NORTHBRIDGE_INTEL_SANDYBRIDGE -+ select SERIRQ_CONTINUOUS_MODE -+ select SOUTHBRIDGE_INTEL_BD82X6X -+ select SYSTEM_TYPE_LAPTOP -+ select USE_NATIVE_RAMINIT -+ -+config DRAM_RESET_GATE_GPIO -+ default 60 -+ -+config MAINBOARD_DIR -+ default "dell/e5520" -+ -+config MAINBOARD_PART_NUMBER -+ default "Latitude E5520" -+ -+config USBDEBUG_HCD_INDEX -+ default 2 -+ -+config VGA_BIOS_ID -+ default "8086,0126" -+ -+endif # BOARD_DELL_LATITUDE_E5520 -diff --git a/src/mainboard/dell/e5520/Kconfig.name b/src/mainboard/dell/e5520/Kconfig.name -new file mode 100644 -index 0000000000..c88913e8b3 ---- /dev/null -+++ b/src/mainboard/dell/e5520/Kconfig.name -@@ -0,0 +1,2 @@ -+config BOARD_DELL_LATITUDE_E5520 -+ bool "Latitude E5520" -diff --git a/src/mainboard/dell/e5520/Makefile.inc b/src/mainboard/dell/e5520/Makefile.inc -new file mode 100644 -index 0000000000..18391d8b18 ---- /dev/null -+++ b/src/mainboard/dell/e5520/Makefile.inc -@@ -0,0 +1,5 @@ -+bootblock-y += early_init.c -+bootblock-y += gpio.c -+romstage-y += early_init.c -+romstage-y += gpio.c -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -diff --git a/src/mainboard/dell/e5520/acpi/ec.asl b/src/mainboard/dell/e5520/acpi/ec.asl -new file mode 100644 -index 0000000000..0d429410a9 ---- /dev/null -+++ b/src/mainboard/dell/e5520/acpi/ec.asl -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Device(EC) -+{ -+ Name (_HID, EISAID("PNP0C09")) -+ Name (_UID, 0) -+ Name (_GPE, 16) -+/* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e5520/acpi/platform.asl b/src/mainboard/dell/e5520/acpi/platform.asl -new file mode 100644 -index 0000000000..2d24bbd9b9 ---- /dev/null -+++ b/src/mainboard/dell/e5520/acpi/platform.asl -@@ -0,0 +1,12 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Method(_WAK, 1) -+{ -+ /* FIXME: EC support */ -+ Return(Package() {0, 0}) -+} -+ -+Method(_PTS,1) -+{ -+ /* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e5520/acpi/superio.asl b/src/mainboard/dell/e5520/acpi/superio.asl -new file mode 100644 -index 0000000000..55b1db5b11 ---- /dev/null -+++ b/src/mainboard/dell/e5520/acpi/superio.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <drivers/pc80/pc/ps2_controller.asl> -diff --git a/src/mainboard/dell/e5520/acpi_tables.c b/src/mainboard/dell/e5520/acpi_tables.c -new file mode 100644 -index 0000000000..e2759659bf ---- /dev/null -+++ b/src/mainboard/dell/e5520/acpi_tables.c -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <acpi/acpi_gnvs.h> -+#include <soc/nvs.h> -+ -+/* FIXME: check this function. */ -+void mainboard_fill_gnvs(struct global_nvs *gnvs) -+{ -+ /* The lid is open by default. */ -+ gnvs->lids = 1; -+ -+ /* Temperature at which OS will shutdown */ -+ gnvs->tcrt = 100; -+ /* Temperature at which OS will throttle CPU */ -+ gnvs->tpsv = 90; -+} -diff --git a/src/mainboard/dell/e5520/board_info.txt b/src/mainboard/dell/e5520/board_info.txt -new file mode 100644 -index 0000000000..34d5ad9e0b ---- /dev/null -+++ b/src/mainboard/dell/e5520/board_info.txt -@@ -0,0 +1,6 @@ -+Category: laptop -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2011 -diff --git a/src/mainboard/dell/e5520/cmos.default b/src/mainboard/dell/e5520/cmos.default -new file mode 100644 -index 0000000000..279415dfd1 ---- /dev/null -+++ b/src/mainboard/dell/e5520/cmos.default -@@ -0,0 +1,9 @@ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -+nmi=Enable -+bluetooth=Enable -+wwan=Enable -+wlan=Enable -+sata_mode=AHCI -+me_state=Disabled -diff --git a/src/mainboard/dell/e5520/cmos.layout b/src/mainboard/dell/e5520/cmos.layout -new file mode 100644 -index 0000000000..1aa7e77bce ---- /dev/null -+++ b/src/mainboard/dell/e5520/cmos.layout -@@ -0,0 +1,88 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+#400 8 r 0 reserved for century byte -+ -+# coreboot config options: southbridge -+408 1 e 1 nmi -+409 2 e 7 power_on_after_fail -+411 1 e 9 sata_mode -+ -+# coreboot config options: EC -+412 1 e 1 bluetooth -+413 1 e 1 wwan -+414 1 e 1 wlan -+ -+# coreboot config options: ME -+424 1 e 14 me_state -+425 2 h 0 me_state_prev -+ -+# coreboot config options: northbridge -+432 3 e 11 gfx_uma_size -+435 2 e 12 hybrid_graphics_mode -+440 8 h 0 volume -+ -+# VBOOT -+448 128 r 0 vbnv -+ -+# SandyBridge MRC Scrambler Seed values -+896 32 r 0 mrc_scrambler_seed -+928 32 r 0 mrc_scrambler_seed_s3 -+960 16 r 0 mrc_scrambler_seed_chk -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+2 0 Enable -+2 1 Disable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+9 0 AHCI -+9 1 Compatible -+11 0 32M -+11 1 64M -+11 2 96M -+11 3 128M -+11 4 160M -+11 5 192M -+11 6 224M -+14 0 Normal -+14 1 Disabled -+ -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 447 984 -diff --git a/src/mainboard/dell/e5520/data.vbt b/src/mainboard/dell/e5520/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..b511e75262e37fa123d674e9a7b21a8dfe427729 -GIT binary patch -literal 6144 -zcmeHKZ){Ul6hE);wSBvNZ|mL$bmQOM2BTvXUI!}^N9ejTij1vnu+)Wx6<c9(Y_%K6 -zzOV-@f<ehpWB5RHBpMBgG7}RuMuM2=l*E{6G$wq&gqTQ3#E2RZsOP@dvW*rP7>Fjj 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-z1-I{%hr!Y?0uVZpUbl__37xn@jkD6Z>3SATgBQlEoN7&ZV9Eni9+>jLln16fFy(=V -H=7E0zE^L4Z - -literal 0 -HcmV?d00001 - -diff --git a/src/mainboard/dell/e5520/devicetree.cb b/src/mainboard/dell/e5520/devicetree.cb -new file mode 100644 -index 0000000000..bef96ac14c ---- /dev/null -+++ b/src/mainboard/dell/e5520/devicetree.cb -@@ -0,0 +1,66 @@ -+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. -+ register "gfx" = "GMA_STATIC_DISPLAYS(1)" -+ register "gpu_cpu_backlight" = "0x00000218" -+ register "gpu_dp_b_hotplug" = "4" -+ register "gpu_dp_c_hotplug" = "4" -+ register "gpu_dp_d_hotplug" = "4" -+ register "gpu_panel_port_select" = "0" -+ register "gpu_panel_power_backlight_off_delay" = "2300" -+ register "gpu_panel_power_backlight_on_delay" = "2300" -+ register "gpu_panel_power_cycle_delay" = "6" -+ register "gpu_panel_power_down_delay" = "400" -+ register "gpu_panel_power_up_delay" = "400" -+ register "gpu_pch_backlight" = "0x13121312" -+ -+ register "spd_addresses" = "{0x50, 0, 0x52, 0}" -+ -+ device domain 0x0 on -+ subsystemid 0x1028 0x049a inherit -+ -+ device ref host_bridge on end # Host bridge -+ device ref peg10 on end # PEG -+ device ref igd on end # iGPU -+ -+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH -+ register "docking_supported" = "1" -+ register "gen1_dec" = "0x007c0681" -+ register "gen2_dec" = "0x007c0901" -+ register "gen3_dec" = "0x003c07e1" -+ register "gen4_dec" = "0x001c0901" -+ register "gpi0_routing" = "2" -+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }" -+ register "pcie_port_coalesce" = "1" -+ register "sata_interface_speed_support" = "0x3" -+ register "sata_port_map" = "0x3b" -+ register "spi_lvscc" = "0x2005" -+ register "spi_uvscc" = "0x2005" -+ -+ device ref mei1 off end -+ device ref mei2 off end -+ device ref me_ide_r off end -+ device ref me_kt off end -+ device ref gbe off end -+ device ref ehci2 on end -+ device ref hda on end -+ device ref pcie_rp1 on end -+ device ref pcie_rp2 on end -+ device ref pcie_rp3 on end -+ device ref pcie_rp4 off end -+ device ref pcie_rp5 on end -+ device ref pcie_rp6 on end -+ device ref pcie_rp7 on end -+ device ref pcie_rp8 off end -+ device ref ehci1 on end -+ device ref pci_bridge off end -+ device ref lpc on -+ chip ec/dell/mec5035 -+ device pnp ff.0 on end -+ end -+ end -+ device ref sata1 on end -+ device ref smbus on end -+ device ref sata2 off end -+ device ref thermal off end -+ end -+ end -+end -diff --git a/src/mainboard/dell/e5520/dsdt.asl b/src/mainboard/dell/e5520/dsdt.asl -new file mode 100644 -index 0000000000..7d13c55b08 ---- /dev/null -+++ b/src/mainboard/dell/e5520/dsdt.asl -@@ -0,0 +1,30 @@ -+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+ -+#include <acpi/acpi.h> -+ -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20141018 /* OEM revision */ -+) -+{ -+ #include <acpi/dsdt_top.asl> -+ #include "acpi/platform.asl" -+ #include <cpu/intel/common/acpi/cpu.asl> -+ #include <southbridge/intel/common/acpi/platform.asl> -+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> -+ #include <southbridge/intel/common/acpi/sleepstates.asl> -+ -+ Device (\_SB.PCI0) -+ { -+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> -+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl> -+ #include <southbridge/intel/bd82x6x/acpi/pch.asl> -+ } -+} -diff --git a/src/mainboard/dell/e5520/early_init.c b/src/mainboard/dell/e5520/early_init.c -new file mode 100644 -index 0000000000..7297921546 ---- /dev/null -+++ b/src/mainboard/dell/e5520/early_init.c -@@ -0,0 +1,32 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+ -+#include <bootblock_common.h> -+#include <device/pci_ops.h> -+#include <ec/dell/mec5035/mec5035.h> -+#include <southbridge/intel/bd82x6x/pch.h> -+ -+const struct southbridge_usb_port mainboard_usb_ports[] = { -+ { 1, 1, 0 }, -+ { 1, 1, 0 }, -+ { 1, 1, 1 }, -+ { 1, 1, 1 }, -+ { 1, 1, 2 }, -+ { 1, 1, 2 }, -+ { 1, 1, 3 }, -+ { 1, 1, 3 }, -+ { 1, 1, 5 }, -+ { 1, 1, 5 }, -+ { 1, 1, 7 }, -+ { 1, 1, 6 }, -+ { 1, 1, 6 }, -+ { 1, 1, 7 }, -+}; -+ -+void bootblock_mainboard_early_init(void) -+{ -+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN -+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN -+ | COMB_LPC_EN | COMA_LPC_EN); -+ mec5035_early_init(); -+} -diff --git a/src/mainboard/dell/e5520/gma-mainboard.ads b/src/mainboard/dell/e5520/gma-mainboard.ads -new file mode 100644 -index 0000000000..2a16f44360 ---- /dev/null -+++ b/src/mainboard/dell/e5520/gma-mainboard.ads -@@ -0,0 +1,20 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ ( -+ HDMI1, -- mainboard HDMI -+ DP2, -- dock DP -+ DP3, -- dock DP -+ Analog, -- mainboard VGA -+ LVDS, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/e5520/gpio.c b/src/mainboard/dell/e5520/gpio.c -new file mode 100644 -index 0000000000..f76b93d9f0 ---- /dev/null -+++ b/src/mainboard/dell/e5520/gpio.c -@@ -0,0 +1,195 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <southbridge/intel/common/gpio.h> -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_GPIO, -+ .gpio1 = GPIO_MODE_NATIVE, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_NATIVE, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_GPIO, -+ .gpio8 = GPIO_MODE_GPIO, -+ .gpio9 = GPIO_MODE_NATIVE, -+ .gpio10 = GPIO_MODE_NATIVE, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_GPIO, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_GPIO, -+ .gpio16 = GPIO_MODE_NATIVE, -+ .gpio17 = GPIO_MODE_GPIO, -+ .gpio18 = GPIO_MODE_NATIVE, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_NATIVE, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_GPIO, -+ .gpio31 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio0 = GPIO_DIR_INPUT, -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio7 = GPIO_DIR_INPUT, -+ .gpio8 = GPIO_DIR_INPUT, -+ .gpio12 = GPIO_DIR_OUTPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio15 = GPIO_DIR_INPUT, -+ .gpio17 = GPIO_DIR_INPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_INPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+ .gpio30 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio12 = GPIO_LEVEL_HIGH, -+ .gpio30 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_reset = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio0 = GPIO_INVERT, -+ .gpio8 = GPIO_INVERT, -+ .gpio14 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_NATIVE, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_NATIVE, -+ .gpio46 = GPIO_MODE_GPIO, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_NATIVE, -+ .gpio50 = GPIO_MODE_GPIO, -+ .gpio51 = GPIO_MODE_GPIO, -+ .gpio52 = GPIO_MODE_GPIO, -+ .gpio53 = GPIO_MODE_GPIO, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_GPIO, -+ .gpio56 = GPIO_MODE_GPIO, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_OUTPUT, -+ .gpio35 = GPIO_DIR_INPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_OUTPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio46 = GPIO_DIR_OUTPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio50 = GPIO_DIR_OUTPUT, -+ .gpio51 = GPIO_DIR_OUTPUT, -+ .gpio52 = GPIO_DIR_INPUT, -+ .gpio53 = GPIO_DIR_INPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio55 = GPIO_DIR_OUTPUT, -+ .gpio56 = GPIO_DIR_INPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio34 = GPIO_LEVEL_LOW, -+ .gpio37 = GPIO_LEVEL_LOW, -+ .gpio46 = GPIO_LEVEL_HIGH, -+ .gpio50 = GPIO_LEVEL_HIGH, -+ .gpio51 = GPIO_LEVEL_LOW, -+ .gpio55 = GPIO_LEVEL_LOW, -+ .gpio60 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_reset = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_NATIVE, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_NATIVE, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_NATIVE, -+ .gpio69 = GPIO_MODE_NATIVE, -+ .gpio70 = GPIO_MODE_NATIVE, -+ .gpio71 = GPIO_MODE_NATIVE, -+ .gpio72 = GPIO_MODE_NATIVE, -+ .gpio73 = GPIO_MODE_NATIVE, -+ .gpio74 = GPIO_MODE_GPIO, -+ .gpio75 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio74 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_reset = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ .reset = &pch_gpio_set1_reset, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ .reset = &pch_gpio_set2_reset, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ .reset = &pch_gpio_set3_reset, -+ }, -+}; -diff --git a/src/mainboard/dell/e5520/hda_verb.c b/src/mainboard/dell/e5520/hda_verb.c -new file mode 100644 -index 0000000000..e2efee3646 ---- /dev/null -+++ b/src/mainboard/dell/e5520/hda_verb.c -@@ -0,0 +1,33 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/azalia_device.h> -+ -+const u32 cim_verb_data[] = { -+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */ -+ 0x1028049a, /* Subsystem ID */ -+ 11, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(0, 0x1028049a), -+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), -+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), -+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), -+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), -+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), -+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), -+ AZALIA_PIN_CFG(0, 0x11, 0xd5a301a0), -+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), -+ -+ 0x80862805, /* Codec Vendor / Device ID: Intel */ -+ 0x80860101, /* Subsystem ID */ -+ 4, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(3, 0x80860101), -+ AZALIA_PIN_CFG(3, 0x05, 0x18560010), -+ AZALIA_PIN_CFG(3, 0x06, 0x18560020), -+ AZALIA_PIN_CFG(3, 0x07, 0x18560030), -+ -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/e5520/mainboard.c b/src/mainboard/dell/e5520/mainboard.c -new file mode 100644 -index 0000000000..31e49802fc ---- /dev/null -+++ b/src/mainboard/dell/e5520/mainboard.c -@@ -0,0 +1,21 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/device.h> -+#include <drivers/intel/gma/int15.h> -+#include <southbridge/intel/bd82x6x/pch.h> -+#include <ec/acpi/ec.h> -+#include <console/console.h> -+#include <pc80/keyboard.h> -+ -+static void mainboard_enable(struct device *dev) -+{ -+ -+ /* FIXME: fix these values. */ -+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, -+ GMA_INT15_PANEL_FIT_DEFAULT, -+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -+} -+ -+struct chip_operations mainboard_ops = { -+ .enable_dev = mainboard_enable, -+}; --- -2.43.0 - diff --git a/config/coreboot/default/patches/0041-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0036-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch index bc8fd55c..b5606617 100644 --- a/config/coreboot/default/patches/0041-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch +++ b/config/coreboot/default/patches/0036-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -1,7 +1,7 @@ -From 0801b3ba8a0ce0109e30d27f405c912d5d705e9c Mon Sep 17 00:00:00 2001 +From 4c0f0d139cdc0fbfadf76ee576d69503b81dc9dc Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 6 Apr 2024 01:22:47 +0100 -Subject: [PATCH 1/1] nb/haswell: Fully disable iGPU when dGPU is used +Subject: [PATCH 36/39] nb/haswell: Fully disable iGPU when dGPU is used My earlier patch disabled decode *and* disabled the iGPU itself, but a subsequent revision disabled only VGA decode. Upon revisiting, I @@ -33,10 +33,10 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 3 insertions(+) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c -index 48a0ba54c7..f0b848852d 100644 +index f7fad3183d..1b188e92e1 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c -@@ -465,6 +465,9 @@ static void gma_func0_disable(struct device *dev) +@@ -466,6 +466,9 @@ static void gma_func0_disable(struct device *dev) { /* Disable VGA decode */ pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1); diff --git a/config/coreboot/default/patches/0045-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0037-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch index 97f14314..8947fe3c 100644 --- a/config/coreboot/default/patches/0045-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch +++ b/config/coreboot/default/patches/0037-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch @@ -1,7 +1,7 @@ -From a8c4f7004ea1c9b8268a87dd0b700c250ec4747d Mon Sep 17 00:00:00 2001 +From 7e921212d3113320b2d28e66cd6a6788533fcab7 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 11:03:32 -0600 -Subject: [PATCH] ec/dell/mec5035: Add S3 suspend SMI handler +Subject: [PATCH 37/39] ec/dell/mec5035: Add S3 suspend SMI handler Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> @@ -113,5 +113,5 @@ index 0000000000..1db834773d + } +} -- -2.44.0 +2.39.2 diff --git a/config/coreboot/default/patches/0038-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch b/config/coreboot/default/patches/0038-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch deleted file mode 100644 index 11f95a63..00000000 --- a/config/coreboot/default/patches/0038-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch +++ /dev/null @@ -1,774 +0,0 @@ -From 7dd58c8b301404a8bafee25a1e97a8a5d614b3d6 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Mon, 4 Mar 2024 18:05:43 -0700 -Subject: [PATCH] mb/dell: Add Latitude E5420 (Sandy Bridge) - ---- - src/mainboard/dell/e5420/Kconfig | 37 ++++ - src/mainboard/dell/e5420/Kconfig.name | 2 + - src/mainboard/dell/e5420/Makefile.mk | 5 + - src/mainboard/dell/e5420/acpi/ec.asl | 9 + - src/mainboard/dell/e5420/acpi/platform.asl | 12 ++ - src/mainboard/dell/e5420/acpi/superio.asl | 3 + - src/mainboard/dell/e5420/acpi_tables.c | 16 ++ - src/mainboard/dell/e5420/board_info.txt | 6 + - src/mainboard/dell/e5420/cmos.default | 9 + - src/mainboard/dell/e5420/cmos.layout | 88 ++++++++++ - src/mainboard/dell/e5420/data.vbt | Bin 0 -> 6144 bytes - src/mainboard/dell/e5420/devicetree.cb | 66 +++++++ - src/mainboard/dell/e5420/dsdt.asl | 30 ++++ - src/mainboard/dell/e5420/early_init.c | 32 ++++ - src/mainboard/dell/e5420/gma-mainboard.ads | 20 +++ - src/mainboard/dell/e5420/gpio.c | 195 +++++++++++++++++++++ - src/mainboard/dell/e5420/hda_verb.c | 33 ++++ - src/mainboard/dell/e5420/mainboard.c | 21 +++ - 18 files changed, 584 insertions(+) - create mode 100644 src/mainboard/dell/e5420/Kconfig - create mode 100644 src/mainboard/dell/e5420/Kconfig.name - create mode 100644 src/mainboard/dell/e5420/Makefile.mk - create mode 100644 src/mainboard/dell/e5420/acpi/ec.asl - create mode 100644 src/mainboard/dell/e5420/acpi/platform.asl - create mode 100644 src/mainboard/dell/e5420/acpi/superio.asl - create mode 100644 src/mainboard/dell/e5420/acpi_tables.c - create mode 100644 src/mainboard/dell/e5420/board_info.txt - create mode 100644 src/mainboard/dell/e5420/cmos.default - create mode 100644 src/mainboard/dell/e5420/cmos.layout - create mode 100755 src/mainboard/dell/e5420/data.vbt - create mode 100644 src/mainboard/dell/e5420/devicetree.cb - create mode 100644 src/mainboard/dell/e5420/dsdt.asl - create mode 100644 src/mainboard/dell/e5420/early_init.c - create mode 100644 src/mainboard/dell/e5420/gma-mainboard.ads - create mode 100644 src/mainboard/dell/e5420/gpio.c - create mode 100644 src/mainboard/dell/e5420/hda_verb.c - create mode 100644 src/mainboard/dell/e5420/mainboard.c - -diff --git a/src/mainboard/dell/e5420/Kconfig b/src/mainboard/dell/e5420/Kconfig -new file mode 100644 -index 0000000000..f4385045ae ---- /dev/null -+++ b/src/mainboard/dell/e5420/Kconfig -@@ -0,0 +1,37 @@ -+if BOARD_DELL_LATITUDE_E5420 -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ select BOARD_ROMSIZE_KB_6144 -+ select EC_ACPI -+ select EC_DELL_MEC5035 -+ select GFX_GMA_PANEL_1_ON_LVDS -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ select INTEL_GMA_HAVE_VBT -+ select INTEL_INT15 -+ select MAINBOARD_HAS_LIBGFXINIT -+ select NORTHBRIDGE_INTEL_SANDYBRIDGE -+ select SERIRQ_CONTINUOUS_MODE -+ select SOUTHBRIDGE_INTEL_BD82X6X -+ select SYSTEM_TYPE_LAPTOP -+ select USE_NATIVE_RAMINIT -+ -+config DRAM_RESET_GATE_GPIO -+ default 60 -+ -+config MAINBOARD_DIR -+ default "dell/e5420" -+ -+config MAINBOARD_PART_NUMBER -+ default "Latitude E5420" -+ -+config USBDEBUG_HCD_INDEX -+ default 2 -+ -+config VGA_BIOS_ID -+ default "8086,0116" -+ -+endif # BOARD_DELL_LATITUDE_E5420 -diff --git a/src/mainboard/dell/e5420/Kconfig.name b/src/mainboard/dell/e5420/Kconfig.name -new file mode 100644 -index 0000000000..eb495fb705 ---- /dev/null -+++ b/src/mainboard/dell/e5420/Kconfig.name -@@ -0,0 +1,2 @@ -+config BOARD_DELL_LATITUDE_E5420 -+ bool "Latitude E5420" -diff --git a/src/mainboard/dell/e5420/Makefile.mk b/src/mainboard/dell/e5420/Makefile.mk -new file mode 100644 -index 0000000000..18391d8b18 ---- /dev/null -+++ b/src/mainboard/dell/e5420/Makefile.mk -@@ -0,0 +1,5 @@ -+bootblock-y += early_init.c -+bootblock-y += gpio.c -+romstage-y += early_init.c -+romstage-y += gpio.c -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -diff --git a/src/mainboard/dell/e5420/acpi/ec.asl b/src/mainboard/dell/e5420/acpi/ec.asl -new file mode 100644 -index 0000000000..0d429410a9 ---- /dev/null -+++ b/src/mainboard/dell/e5420/acpi/ec.asl -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Device(EC) -+{ -+ Name (_HID, EISAID("PNP0C09")) -+ Name (_UID, 0) -+ Name (_GPE, 16) -+/* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e5420/acpi/platform.asl b/src/mainboard/dell/e5420/acpi/platform.asl -new file mode 100644 -index 0000000000..2d24bbd9b9 ---- /dev/null -+++ b/src/mainboard/dell/e5420/acpi/platform.asl -@@ -0,0 +1,12 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Method(_WAK, 1) -+{ -+ /* FIXME: EC support */ -+ Return(Package() {0, 0}) -+} -+ -+Method(_PTS,1) -+{ -+ /* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e5420/acpi/superio.asl b/src/mainboard/dell/e5420/acpi/superio.asl -new file mode 100644 -index 0000000000..55b1db5b11 ---- /dev/null -+++ b/src/mainboard/dell/e5420/acpi/superio.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <drivers/pc80/pc/ps2_controller.asl> -diff --git a/src/mainboard/dell/e5420/acpi_tables.c b/src/mainboard/dell/e5420/acpi_tables.c -new file mode 100644 -index 0000000000..e2759659bf ---- /dev/null -+++ b/src/mainboard/dell/e5420/acpi_tables.c -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <acpi/acpi_gnvs.h> -+#include <soc/nvs.h> -+ -+/* FIXME: check this function. */ -+void mainboard_fill_gnvs(struct global_nvs *gnvs) -+{ -+ /* The lid is open by default. */ -+ gnvs->lids = 1; -+ -+ /* Temperature at which OS will shutdown */ -+ gnvs->tcrt = 100; -+ /* Temperature at which OS will throttle CPU */ -+ gnvs->tpsv = 90; -+} -diff --git a/src/mainboard/dell/e5420/board_info.txt b/src/mainboard/dell/e5420/board_info.txt -new file mode 100644 -index 0000000000..34d5ad9e0b ---- /dev/null -+++ b/src/mainboard/dell/e5420/board_info.txt -@@ -0,0 +1,6 @@ -+Category: laptop -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2011 -diff --git a/src/mainboard/dell/e5420/cmos.default b/src/mainboard/dell/e5420/cmos.default -new file mode 100644 -index 0000000000..279415dfd1 ---- /dev/null -+++ b/src/mainboard/dell/e5420/cmos.default -@@ -0,0 +1,9 @@ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -+nmi=Enable -+bluetooth=Enable -+wwan=Enable -+wlan=Enable -+sata_mode=AHCI -+me_state=Disabled -diff --git a/src/mainboard/dell/e5420/cmos.layout b/src/mainboard/dell/e5420/cmos.layout -new file mode 100644 -index 0000000000..1aa7e77bce ---- /dev/null -+++ b/src/mainboard/dell/e5420/cmos.layout -@@ -0,0 +1,88 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+#400 8 r 0 reserved for century byte -+ -+# coreboot config options: southbridge -+408 1 e 1 nmi -+409 2 e 7 power_on_after_fail -+411 1 e 9 sata_mode -+ -+# coreboot config options: EC -+412 1 e 1 bluetooth -+413 1 e 1 wwan -+414 1 e 1 wlan -+ -+# coreboot config options: ME -+424 1 e 14 me_state -+425 2 h 0 me_state_prev -+ -+# coreboot config options: northbridge -+432 3 e 11 gfx_uma_size -+435 2 e 12 hybrid_graphics_mode -+440 8 h 0 volume -+ -+# VBOOT -+448 128 r 0 vbnv -+ -+# SandyBridge MRC Scrambler Seed values -+896 32 r 0 mrc_scrambler_seed -+928 32 r 0 mrc_scrambler_seed_s3 -+960 16 r 0 mrc_scrambler_seed_chk -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+2 0 Enable -+2 1 Disable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+9 0 AHCI -+9 1 Compatible -+11 0 32M -+11 1 64M -+11 2 96M -+11 3 128M -+11 4 160M -+11 5 192M -+11 6 224M -+14 0 Normal -+14 1 Disabled -+ -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 447 984 -diff --git a/src/mainboard/dell/e5420/data.vbt b/src/mainboard/dell/e5420/data.vbt -new file mode 100755 -index 0000000000000000000000000000000000000000..98b82fe6110fd295b5749041ec7f8c084ace5f57 -GIT binary patch -literal 6144 -zcmeHKeQZ-z6hE);wSBvNZ!2$ObQ^;MgV6zl*Rhp}BXnCCMZU^_r7jRwT!kfLo8?3H -zk9)u(7?cb(hChhTM57@QFfmbMB!G!dNsO6BW5OSp5EGF^jHnTTdhUBI+h`e+1ft1q -z^SfW?+;h)4_uO+|XEfEV$91)<gOArWE)OnSTD}Ug6?8a~vz+SmQn!4~y3N7b^|hPp -zR<5aEfv-b8M00Lk251!oO|8(YA6XaeXzkt-Z)@Ee!_{@z#Fro^?DqN4SGjRIu8KYp -zZEufuU@5MM@7jv%h;75FS}ezKv?JDzCH}d%tE)A-GuDb*+B%}~w%88r>}c;!*XQ5O -z)OU7u$J@4U+lk)#GSW%c%c)v`%R6?`w)LIyu6bD7-j0o&X9qUMcEsYlW3BU4rZRvt -zqAUpjf*qXuLCCsU0YM2I5@gB1WKd)f1+Yt?%HWd0DZxYumP(K<LxTif8A39+!KMl} -z31FHG)7?qk5g>e?=ER{f^&}W<0k@mxff(?6+Stw+s6y%k1mM$cLk#^FWWI*9bE1GY -z&VY9?WC1u#23^3^UYw5?H0x2S2gN`x18Fko6_x(#MKyuCU_<D!mEp$qO_An}#@>DV -zdkf*li41yW3p$*0Oo3+63kO6S91*KwP#l2i4jnc)JkUirL^$k}VbH0;CBh#BS=OLf -zW-yE3BRon75gG{_2~QIC5cUzCC%i)FCmbidM>tIwAPf>N5Pl?FC0r*+Sq!oXj!keQ -zVKcyK>TL+gc7oLco$28+FpeeXkEP}_Sea=mk#IWUR^m$!BogvszLPu83FJm0k6K<l -z$#$~YiXtY*GpHp#@FvHJ1UnBD*H%d+{_j24XE4nmBa*?5mOWiold28s3}>*}<HaeO -z+1|-8g2)FCfkDZIdb-Ub);z0#;XEbPfGe?A72!{DAUg|$m+Z~(i@h9j4gtm611ni( -z#u>ACcP}M4exU`*MKVwl5+t6JBpTkmm}xWflKUe~7}`!#%z#gAo{NxUrpDAndYktu -zI0}VLU`J7^xmF1AFiz5S^uzp*DPI$%$qq!(ikh0kP+(GKzF|@N?Y%_#Vp@M+xHr$F -z=%+18z`-fT%z)9-TS$~Dh@2yeN7!UIt0h`fWxUu`JvA_ra*8P48l%7KR0&c1;0R75 -z4f0oz(xQ3MWqz5>qW5M4tZWExHs8<H(e1G@4km@5wEzOOP^x<l`YmA|eKs6j3wl8B -z%C%;uygh%<#kGZ{fymL+OlV0!-*T!V5IB>X@p!@CBU=7e{5^Jl{s7by`po-AJqM2l -znk(=^0bHkF0rUw7)^7j;$=_UIs8`6P6b-;vPDZ#U9L)W1_PAYRDP9k~;5$stt5ZiV -zD0>;i-?OlYY2}P9WVnfGos4xee2r=EGWHR}ADH$VV>cO=xU?!4TjIi)OMBYI_PX#b -zm-eBHed5BOT-x6*W>;{IqAga~G6lCQT93k>Q}CpsomJR*1%FjEkv?fuT%c-8RklXO -zU8;6KWk*zeU)4TW+1D!mrE0EhHZfbBeN{4S7X@Pig%};A99QTdA~wZruL*8y?K!jP -zG5R*k=);S}Zn<T;W!Mxt`(!+z7_r@3LVpf|FESauM&4}+wqzXfba-zG>A}on(uzNF -zyu>BcjA})C@bg%<;+Eh2;Sz4heFFCbZ@C{FrXMIbYzu>?Bi-|vZ}JSFU%JA>7$7et -z0Yo%CnOVZm#ZA}4kWZOn15};h5*#OM3b+6vHzgruMP>=5MNJK1y42{YgveP-!j%#( -z0rGe@8t%!=66Ti%K4|Gx=o7gFp83wQ;+s3H7+r^SKlpp3KKcr!3@|n;NCH_=qL=3T -zq3WH?en`b+W-HR-fnrhw*9aZ%M}lHX7@H?E>!6wv_&YQFEHdA$%Z1R--yub>=c@p? -z6@7Fc$&>sAxwiz{BE$1kb$K9Co=ozlA973y^i(^BM|EZ$$^y`0KyHiMJ%O*XbfEX1 -ziZaH>W(1pWL0bo|T!x__N$^$DpmxI=bL6WUK3JGyn?rw-qC4ZA$yGjIB}N(=ldD2O -zAJ@bxp<qR-3lIv<!P~SE8r*#_Ckl?$0|1fZ>2>n}u*mUIYFd>}O_wuwBD^r9<#=!0 -X1LGbT_rSOZ#yv3ZfpHH!G!Og(1Xg~J - -literal 0 -HcmV?d00001 - -diff --git a/src/mainboard/dell/e5420/devicetree.cb b/src/mainboard/dell/e5420/devicetree.cb -new file mode 100644 -index 0000000000..f26413557d ---- /dev/null -+++ b/src/mainboard/dell/e5420/devicetree.cb -@@ -0,0 +1,66 @@ -+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. -+ register "gfx" = "GMA_STATIC_DISPLAYS(1)" -+ register "gpu_cpu_backlight" = "0x00000c31" -+ register "gpu_dp_b_hotplug" = "4" -+ register "gpu_dp_c_hotplug" = "4" -+ register "gpu_dp_d_hotplug" = "4" -+ register "gpu_panel_port_select" = "0" -+ register "gpu_panel_power_backlight_off_delay" = "2300" -+ register "gpu_panel_power_backlight_on_delay" = "2300" -+ register "gpu_panel_power_cycle_delay" = "6" -+ register "gpu_panel_power_down_delay" = "400" -+ register "gpu_panel_power_up_delay" = "400" -+ register "gpu_pch_backlight" = "0x13121312" -+ -+ register "spd_addresses" = "{0x50, 0, 0x52, 0}" -+ -+ device domain 0x0 on -+ subsystemid 0x1028 0x049b inherit -+ -+ device ref host_bridge on end # Host bridge -+ device ref peg10 on end # PEG -+ device ref igd on end # iGPU -+ -+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH -+ register "docking_supported" = "1" -+ register "gen1_dec" = "0x007c0681" -+ register "gen2_dec" = "0x007c0901" -+ register "gen3_dec" = "0x003c07e1" -+ register "gen4_dec" = "0x001c0901" -+ register "gpi0_routing" = "2" -+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }" -+ register "pcie_port_coalesce" = "1" -+ register "sata_interface_speed_support" = "0x3" -+ register "sata_port_map" = "0x3b" -+ register "spi_lvscc" = "0x2005" -+ register "spi_uvscc" = "0x2005" -+ -+ device ref mei1 off end -+ device ref mei2 off end -+ device ref me_ide_r off end -+ device ref me_kt off end -+ device ref gbe off end -+ device ref ehci2 on end -+ device ref hda on end -+ device ref pcie_rp1 on end -+ device ref pcie_rp2 on end -+ device ref pcie_rp3 on end -+ device ref pcie_rp4 off end -+ device ref pcie_rp5 on end -+ device ref pcie_rp6 on end -+ device ref pcie_rp7 on end -+ device ref pcie_rp8 off end -+ device ref ehci1 on end -+ device ref pci_bridge off end -+ device ref lpc on -+ chip ec/dell/mec5035 -+ device pnp ff.0 on end -+ end -+ end -+ device ref sata1 on end -+ device ref smbus on end -+ device ref sata2 off end -+ device ref thermal off end -+ end -+ end -+end -diff --git a/src/mainboard/dell/e5420/dsdt.asl b/src/mainboard/dell/e5420/dsdt.asl -new file mode 100644 -index 0000000000..7d13c55b08 ---- /dev/null -+++ b/src/mainboard/dell/e5420/dsdt.asl -@@ -0,0 +1,30 @@ -+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+ -+#include <acpi/acpi.h> -+ -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20141018 /* OEM revision */ -+) -+{ -+ #include <acpi/dsdt_top.asl> -+ #include "acpi/platform.asl" -+ #include <cpu/intel/common/acpi/cpu.asl> -+ #include <southbridge/intel/common/acpi/platform.asl> -+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> -+ #include <southbridge/intel/common/acpi/sleepstates.asl> -+ -+ Device (\_SB.PCI0) -+ { -+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> -+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl> -+ #include <southbridge/intel/bd82x6x/acpi/pch.asl> -+ } -+} -diff --git a/src/mainboard/dell/e5420/early_init.c b/src/mainboard/dell/e5420/early_init.c -new file mode 100644 -index 0000000000..7297921546 ---- /dev/null -+++ b/src/mainboard/dell/e5420/early_init.c -@@ -0,0 +1,32 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+ -+#include <bootblock_common.h> -+#include <device/pci_ops.h> -+#include <ec/dell/mec5035/mec5035.h> -+#include <southbridge/intel/bd82x6x/pch.h> -+ -+const struct southbridge_usb_port mainboard_usb_ports[] = { -+ { 1, 1, 0 }, -+ { 1, 1, 0 }, -+ { 1, 1, 1 }, -+ { 1, 1, 1 }, -+ { 1, 1, 2 }, -+ { 1, 1, 2 }, -+ { 1, 1, 3 }, -+ { 1, 1, 3 }, -+ { 1, 1, 5 }, -+ { 1, 1, 5 }, -+ { 1, 1, 7 }, -+ { 1, 1, 6 }, -+ { 1, 1, 6 }, -+ { 1, 1, 7 }, -+}; -+ -+void bootblock_mainboard_early_init(void) -+{ -+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN -+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN -+ | COMB_LPC_EN | COMA_LPC_EN); -+ mec5035_early_init(); -+} -diff --git a/src/mainboard/dell/e5420/gma-mainboard.ads b/src/mainboard/dell/e5420/gma-mainboard.ads -new file mode 100644 -index 0000000000..2a16f44360 ---- /dev/null -+++ b/src/mainboard/dell/e5420/gma-mainboard.ads -@@ -0,0 +1,20 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ ( -+ HDMI1, -- mainboard HDMI -+ DP2, -- dock DP -+ DP3, -- dock DP -+ Analog, -- mainboard VGA -+ LVDS, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/e5420/gpio.c b/src/mainboard/dell/e5420/gpio.c -new file mode 100644 -index 0000000000..f76b93d9f0 ---- /dev/null -+++ b/src/mainboard/dell/e5420/gpio.c -@@ -0,0 +1,195 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <southbridge/intel/common/gpio.h> -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_GPIO, -+ .gpio1 = GPIO_MODE_NATIVE, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_NATIVE, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_GPIO, -+ .gpio8 = GPIO_MODE_GPIO, -+ .gpio9 = GPIO_MODE_NATIVE, -+ .gpio10 = GPIO_MODE_NATIVE, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_GPIO, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_GPIO, -+ .gpio16 = GPIO_MODE_NATIVE, -+ .gpio17 = GPIO_MODE_GPIO, -+ .gpio18 = GPIO_MODE_NATIVE, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_NATIVE, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_GPIO, -+ .gpio31 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio0 = GPIO_DIR_INPUT, -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio7 = GPIO_DIR_INPUT, -+ .gpio8 = GPIO_DIR_INPUT, -+ .gpio12 = GPIO_DIR_OUTPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio15 = GPIO_DIR_INPUT, -+ .gpio17 = GPIO_DIR_INPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_INPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+ .gpio30 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio12 = GPIO_LEVEL_HIGH, -+ .gpio30 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_reset = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio0 = GPIO_INVERT, -+ .gpio8 = GPIO_INVERT, -+ .gpio14 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_NATIVE, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_NATIVE, -+ .gpio46 = GPIO_MODE_GPIO, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_NATIVE, -+ .gpio50 = GPIO_MODE_GPIO, -+ .gpio51 = GPIO_MODE_GPIO, -+ .gpio52 = GPIO_MODE_GPIO, -+ .gpio53 = GPIO_MODE_GPIO, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_GPIO, -+ .gpio56 = GPIO_MODE_GPIO, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_OUTPUT, -+ .gpio35 = GPIO_DIR_INPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_OUTPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio46 = GPIO_DIR_OUTPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio50 = GPIO_DIR_OUTPUT, -+ .gpio51 = GPIO_DIR_OUTPUT, -+ .gpio52 = GPIO_DIR_INPUT, -+ .gpio53 = GPIO_DIR_INPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio55 = GPIO_DIR_OUTPUT, -+ .gpio56 = GPIO_DIR_INPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio34 = GPIO_LEVEL_LOW, -+ .gpio37 = GPIO_LEVEL_LOW, -+ .gpio46 = GPIO_LEVEL_HIGH, -+ .gpio50 = GPIO_LEVEL_HIGH, -+ .gpio51 = GPIO_LEVEL_LOW, -+ .gpio55 = GPIO_LEVEL_LOW, -+ .gpio60 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_reset = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_NATIVE, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_NATIVE, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_NATIVE, -+ .gpio69 = GPIO_MODE_NATIVE, -+ .gpio70 = GPIO_MODE_NATIVE, -+ .gpio71 = GPIO_MODE_NATIVE, -+ .gpio72 = GPIO_MODE_NATIVE, -+ .gpio73 = GPIO_MODE_NATIVE, -+ .gpio74 = GPIO_MODE_GPIO, -+ .gpio75 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio74 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_reset = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ .reset = &pch_gpio_set1_reset, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ .reset = &pch_gpio_set2_reset, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ .reset = &pch_gpio_set3_reset, -+ }, -+}; -diff --git a/src/mainboard/dell/e5420/hda_verb.c b/src/mainboard/dell/e5420/hda_verb.c -new file mode 100644 -index 0000000000..70e7c2e79a ---- /dev/null -+++ b/src/mainboard/dell/e5420/hda_verb.c -@@ -0,0 +1,33 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/azalia_device.h> -+ -+const u32 cim_verb_data[] = { -+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */ -+ 0x1028049b, /* Subsystem ID */ -+ 11, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(0, 0x1028049b), -+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), -+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), -+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), -+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), -+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), -+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), -+ AZALIA_PIN_CFG(0, 0x11, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x20, 0xd5a30130), -+ -+ 0x80862805, /* Codec Vendor / Device ID: Intel */ -+ 0x80860101, /* Subsystem ID */ -+ 4, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(3, 0x80860101), -+ AZALIA_PIN_CFG(3, 0x05, 0x18560010), -+ AZALIA_PIN_CFG(3, 0x06, 0x18560020), -+ AZALIA_PIN_CFG(3, 0x07, 0x18560030), -+ -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/e5420/mainboard.c b/src/mainboard/dell/e5420/mainboard.c -new file mode 100644 -index 0000000000..31e49802fc ---- /dev/null -+++ b/src/mainboard/dell/e5420/mainboard.c -@@ -0,0 +1,21 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/device.h> -+#include <drivers/intel/gma/int15.h> -+#include <southbridge/intel/bd82x6x/pch.h> -+#include <ec/acpi/ec.h> -+#include <console/console.h> -+#include <pc80/keyboard.h> -+ -+static void mainboard_enable(struct device *dev) -+{ -+ -+ /* FIXME: fix these values. */ -+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, -+ GMA_INT15_PANEL_FIT_DEFAULT, -+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -+} -+ -+struct chip_operations mainboard_ops = { -+ .enable_dev = mainboard_enable, -+}; --- -2.44.0 - diff --git a/config/coreboot/default/patches/0038-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch b/config/coreboot/default/patches/0038-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch new file mode 100644 index 00000000..8da97601 --- /dev/null +++ b/config/coreboot/default/patches/0038-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch @@ -0,0 +1,31 @@ +From 53bddae0fc8436fe262ca7fc2e19049afa7a38f8 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Fri, 3 May 2024 16:31:12 -0600 +Subject: [PATCH 38/39] mb/dell/: Add S3 SMI handler for SNB/IVB Latitudes + +This should fix S3 suspend on these systems + +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c + +diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c +new file mode 100644 +index 0000000000..334d7b1a5f +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <cpu/x86/smm.h> ++#include <ec/dell/mec5035/mec5035.h> ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_sleep(slp_typ); ++} +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0039-fix-sata-ports-on-dell-9020-sff-and-mt.patch b/config/coreboot/default/patches/0039-fix-sata-ports-on-dell-9020-sff-and-mt.patch deleted file mode 100644 index f4c3939c..00000000 --- a/config/coreboot/default/patches/0039-fix-sata-ports-on-dell-9020-sff-and-mt.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 4889f08306f1530211dcc6f6a4e999c6cc72f3ac Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Sat, 30 Mar 2024 05:57:54 +0000 -Subject: [PATCH 1/1] fix sata ports on dell 9020 sff and mt - -mate kukri has a patch under review on coreboot that sets -sata port map to 0x7 on sff and 0xf on mt. - -see: intel 8 series pch datasheet, section 13.1.35 - -basically, the 6 least significant bits enable the sata -slots; 1 for enable and 0 for disable. there can be up -to 6 ports. least significant bit is port 0, then next -is port 1, and so on. - -coreboot currently enables ports 0, 1, 4 and 5, making this -value 0x33 (converted to binary: 00110011). sff has ports -0, 1 and 2 wired, so mate changed that to 0x7 (00000111). - -on mt, the blue ports are ports 0 and 1, but the two white -ports don't work, but coreboot enables 4 and 5; it is -likely that the blue ports are in fact 0 and 1, and the -white ports are 2 and 3, but we've not tested this! - -it could be that the blue ports are ports 4 and 5, and -the white ports are 2 and 3! we have not yet determined -this, but mate set it to 0xf, meaning ports 0 1 2 and 3 -are enabled, in his patch under review. the chance that -it's 2, 3, 4 and 5 on the board is unlikely, but it is -theoretically possible and has not been confirmed. - -therefore, for now, i will set the value to 0x3f, which -in binary is 00111111, thus enabling all 6 slots. the two -that aren't physically wired don't really matter. enabling -ports (from the pch) that electrically aren't there and -then powering on is electrically equivalent to those ports -being actually being wired, but with no devices plugged -into them. therefore, 0x3f is an effective shotgun fix. - -i'll remove this patch and use mate's fix when the latter -has been tested on MT; it has already been tested on SFF. - -this patch fixes the 3rd sata slot on 9020 sff, and the 3rd -and 4th sata slots on 9020 MT - -Signed-off-by: Leah Rowe <info@minifree.org> ---- - src/mainboard/dell/optiplex_9020/devicetree.cb | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb -index c0b17a15ff..7bfa6736a6 100644 ---- a/src/mainboard/dell/optiplex_9020/devicetree.cb -+++ b/src/mainboard/dell/optiplex_9020/devicetree.cb -@@ -23,7 +23,7 @@ chip northbridge/intel/haswell - register "gen2_dec" = "0x007c0901" - register "gen3_dec" = "0x003c07e1" - register "gen4_dec" = "0x001c0901" -- register "sata_port_map" = "0x33" -+ register "sata_port_map" = "0x3f" - - device pci 14.0 on end # xHCI controller - device pci 16.0 on end # Management Engine interface 1 --- -2.39.2 - diff --git a/config/coreboot/default/patches/0047-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0039-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch index a7af707e..f658b6d0 100644 --- a/config/coreboot/default/patches/0047-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch +++ b/config/coreboot/default/patches/0039-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch @@ -1,7 +1,7 @@ -From fa4f05e39744eb4c4606f940b8acc7fd053b11d4 Mon Sep 17 00:00:00 2001 +From 919cbfa034db5d2ef9e56dd71ef329c38c5ede3c Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 4 May 2024 02:00:53 +0100 -Subject: [PATCH 1/1] nb/haswell: lock policy regs when disabling IOMMU +Subject: [PATCH 39/39] nb/haswell: lock policy regs when disabling IOMMU Angel Pons told me I should do it. See comments here: https://review.coreboot.org/c/coreboot/+/81016 diff --git a/config/coreboot/default/patches/0040-nb-haswell-Disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0040-nb-haswell-Disable-iGPU-when-dGPU-is-used.patch deleted file mode 100644 index 7a02d902..00000000 --- a/config/coreboot/default/patches/0040-nb-haswell-Disable-iGPU-when-dGPU-is-used.patch +++ /dev/null @@ -1,54 +0,0 @@ -From c6ce9c635e6576c86c546177c3d770dec2f3c9ae Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Fri, 23 Feb 2024 13:33:31 +0000 -Subject: [PATCH 1/1] nb/haswell: Disable iGPU when dGPU is used - -This is usually is handled by Haswell mrc.bin, disabling VGA -decode on the iGPU when a dGPU is installed. However, Broadwell -mrc.bin does not, so the iGPU and dGPU are both enabled. - -This patch disables legacy VGA cycles for iGPU, under such -conditions. It has been tested on Broadwell mrc.bin when -using a graphics card on Dell OptiPlex 9020 SFF (currently -under review at this time of writing, submitted by Mate -Kukri). - -This patch has also been tested when Haswell mrc.bin is used, -and there are seemingly no breaking changes caused by it. - -Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b -Signed-off-by: Leah Rowe <info@minifree.org> -Reviewed-on: https://review.coreboot.org/c/coreboot/+/80717 -Tested-by: build bot (Jenkins) <no-reply@coreboot.org> -Reviewed-by: Nico Huber <nico.h@gmx.de> ---- - src/northbridge/intel/haswell/gma.c | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c -index 6e6948b70f..48a0ba54c7 100644 ---- a/src/northbridge/intel/haswell/gma.c -+++ b/src/northbridge/intel/haswell/gma.c -@@ -461,12 +461,19 @@ static void gma_generate_ssdt(const struct device *dev) - drivers_intel_gma_displays_ssdt_generate(&chip->gfx); - } - -+static void gma_func0_disable(struct device *dev) -+{ -+ /* Disable VGA decode */ -+ pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1); -+} -+ - static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = gma_func0_init, - .acpi_fill_ssdt = gma_generate_ssdt, -+ .vga_disable = gma_func0_disable, - .ops_pci = &pci_dev_ops_pci, - }; - --- -2.39.2 - diff --git a/config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch b/config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch deleted file mode 100644 index 37353e20..00000000 --- a/config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch +++ /dev/null @@ -1,602 +0,0 @@ -From c58e0fea2a4e591e5ecd8a1f376c3b3af0fbb306 Mon Sep 17 00:00:00 2001 -From: Mate Kukri <kukri.mate@gmail.com> -Date: Thu, 18 Apr 2024 20:28:45 +0100 -Subject: [PATCH 1/1] mb/dell/optiplex_9020: Implement late HWM initialization - -There are 4 different chassis types specified by vendor firmware, each -with a slightly different HWM configuration. - -The chassis type to use is determined at runtime by reading a set of -4 PCH GPIOs: 70, 38, 17, and 1. - -Additionally vendor firmware also provides an option to run the fans at -full speed. This is substituted with a coreboot nvram option in this -implementation. - -This was tested to make fan control work on my OptiPlex 7020 SFF. - -NOTE: This is superficially similar to the OptiPlex 9010's SCH5545 -however the OptiPlex 9020's SCH5555 does not use externally -programmed EC firmware. - -Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43 -Signed-off-by: Mate Kukri <kukri.mate@gmail.com> ---- - src/mainboard/dell/optiplex_9020/Makefile.inc | 3 +- - src/mainboard/dell/optiplex_9020/bootblock.c | 25 +- - src/mainboard/dell/optiplex_9020/cmos.default | 1 + - src/mainboard/dell/optiplex_9020/cmos.layout | 5 +- - src/mainboard/dell/optiplex_9020/mainboard.c | 387 ++++++++++++++++++ - src/mainboard/dell/optiplex_9020/sch5555_ec.c | 54 +++ - src/mainboard/dell/optiplex_9020/sch5555_ec.h | 10 + - 7 files changed, 463 insertions(+), 22 deletions(-) - create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.c - create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.h - -diff --git a/src/mainboard/dell/optiplex_9020/Makefile.inc b/src/mainboard/dell/optiplex_9020/Makefile.inc -index 6ca2f2afaa..08e2e53577 100644 ---- a/src/mainboard/dell/optiplex_9020/Makefile.inc -+++ b/src/mainboard/dell/optiplex_9020/Makefile.inc -@@ -2,4 +2,5 @@ - - romstage-y += gpio.c - ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads --bootblock-y += bootblock.c -+ramstage-y += sch5555_ec.c -+bootblock-y += bootblock.c sch5555_ec.c -diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c -index 2837cf9cf1..e5e759273e 100644 ---- a/src/mainboard/dell/optiplex_9020/bootblock.c -+++ b/src/mainboard/dell/optiplex_9020/bootblock.c -@@ -4,29 +4,14 @@ - #include <device/pnp_ops.h> - #include <superio/smsc/sch555x/sch555x.h> - #include <southbridge/intel/lynxpoint/pch.h> -- --static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) --{ -- // Clear EC-to-Host mailbox -- uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); -- outb(tmp, SCH555x_EMI_IOBASE + 1); -- -- // Send address and value to the EC -- sch555x_emi_write16(0, (addr1 * 2) | 0x101); -- sch555x_emi_write32(4, val | (addr2 << 16)); -- -- // Wait for acknowledgement message from EC -- outb(1, SCH555x_EMI_IOBASE); -- size_t timeout = 0; -- do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0); --} -+#include "sch5555_ec.h" - - struct ec_init_entry { - uint16_t addr; - uint8_t val; - }; - --static void ec_init(void) -+static void bootblock_ec_init(void) - { - /* - * Tables from CORE_PEI -@@ -108,9 +93,9 @@ void mainboard_config_superio(void) - outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); - outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); - -- // Magic EC init -- ec_init(); -+ // Perform bootblock EC initialization -+ bootblock_ec_init(); - -- // Magic EC init is needed for UART1 initialization to work -+ // Bootblock EC initialization is required for UART1 to work - sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - } -diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default -index 7bccc80e51..1909abcb9f 100644 ---- a/src/mainboard/dell/optiplex_9020/cmos.default -+++ b/src/mainboard/dell/optiplex_9020/cmos.default -@@ -3,3 +3,4 @@ debug_level=Debug - nmi=Disable - power_on_after_fail=Disable - iommu=Disable -+fan_full_speed=Disable -diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout -index 72ff9c4bee..4a1496a878 100644 ---- a/src/mainboard/dell/optiplex_9020/cmos.layout -+++ b/src/mainboard/dell/optiplex_9020/cmos.layout -@@ -22,7 +22,10 @@ entries - 409 2 e 5 power_on_after_fail - - # turn iommu on or off --412 1 e 6 iommu -+411 1 e 6 iommu -+ -+# coreboot config options: EC -+412 1 e 1 fan_full_speed - - # coreboot config options: check sums - 984 16 h 0 check_sum -diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c -index c834fea5d3..0b7829c736 100644 ---- a/src/mainboard/dell/optiplex_9020/mainboard.c -+++ b/src/mainboard/dell/optiplex_9020/mainboard.c -@@ -1,7 +1,12 @@ - /* SPDX-License-Identifier: GPL-2.0-only */ - -+#include <bootstate.h> -+#include <cpu/x86/msr.h> - #include <device/device.h> - #include <drivers/intel/gma/int15.h> -+#include <option.h> -+#include <southbridge/intel/common/gpio.h> -+#include "sch5555_ec.h" - - static void mainboard_enable(struct device *dev) - { -@@ -13,3 +18,385 @@ static void mainboard_enable(struct device *dev) - struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, - }; -+ -+#define HWM_TAB_ADD_TEMP_TARGET 1 -+#define HWM_TAB_PKG_POWER_ANY 0xffff -+#define CHASSIS_TYPE_UNKNOWN 0xff -+ -+struct hwm_tab_entry { -+ uint16_t addr; -+ uint8_t val; -+ uint8_t flags; -+ uint16_t pkg_power; -+}; -+ -+struct hwm_tab_entry HWM_TAB3[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x00, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0x8a, 0, 0x0010 }, -+ { 0x086, 0x4c, 0, 0x0010 }, -+ { 0x08a, 0x66, 0, 0x0010 }, -+ { 0x08b, 0x5b, 0, 0x0010 }, -+ { 0x090, 0x65, 0, 0xffff }, -+ { 0x091, 0x70, 0, 0xffff }, -+ { 0x092, 0x86, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x0e, 0, 0xffff }, -+ { 0x0a1, 0x0e, 0, 0xffff }, -+ { 0x0ae, 0x7c, 0, 0xffff }, -+ { 0x0af, 0x86, 0, 0xffff }, -+ { 0x0b0, 0x9a, 0, 0xffff }, -+ { 0x0b3, 0x9a, 0, 0xffff }, -+ { 0x0b6, 0x08, 0, 0xffff }, -+ { 0x0b7, 0x08, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0x0020 }, -+ { 0x0ea, 0x5c, 0, 0x0010 }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x0fd, 0x01, 0, 0xffff }, -+ { 0x1a1, 0x00, 0, 0xffff }, -+ { 0x1a2, 0x00, 0, 0xffff }, -+ { 0x1b1, 0x08, 0, 0xffff }, -+ { 0x1be, 0x99, 0, 0xffff }, -+ { 0x280, 0xa0, 0, 0x0010 }, -+ { 0x281, 0x0f, 0, 0x0010 }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x288, 0x68, 0, 0x0010 }, -+ { 0x289, 0x10, 0, 0x0010 }, -+ { 0x28a, 0x03, 0, 0xffff }, -+ { 0x28b, 0x0a, 0, 0xffff }, -+ { 0x28c, 0x80, 0, 0xffff }, -+ { 0x28d, 0x03, 0, 0xffff }, -+}; -+ -+struct hwm_tab_entry HWM_TAB4[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x00, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0x99, 0, 0x0020 }, -+ { 0x085, 0xad, 0, 0x0010 }, -+ { 0x086, 0x1c, 0, 0xffff }, -+ { 0x08a, 0x39, 0, 0x0020 }, -+ { 0x08a, 0x41, 0, 0x0010 }, -+ { 0x08b, 0x76, 0, 0x0020 }, -+ { 0x08b, 0x8b, 0, 0x0010 }, -+ { 0x090, 0x5e, 0, 0xffff }, -+ { 0x091, 0x5e, 0, 0xffff }, -+ { 0x092, 0x86, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x0a, 0, 0xffff }, -+ { 0x0a1, 0x0a, 0, 0xffff }, -+ { 0x0ae, 0x7c, 0, 0xffff }, -+ { 0x0af, 0x7c, 0, 0xffff }, -+ { 0x0b0, 0x9a, 0, 0xffff }, -+ { 0x0b3, 0x7c, 0, 0xffff }, -+ { 0x0b6, 0x08, 0, 0xffff }, -+ { 0x0b7, 0x08, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0x0020 }, -+ { 0x0ea, 0x5c, 0, 0x0010 }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x0fd, 0x01, 0, 0xffff }, -+ { 0x1a1, 0x00, 0, 0xffff }, -+ { 0x1a2, 0x00, 0, 0xffff }, -+ { 0x1b1, 0x08, 0, 0xffff }, -+ { 0x1be, 0x90, 0, 0xffff }, -+ { 0x280, 0x94, 0, 0x0020 }, -+ { 0x281, 0x11, 0, 0x0020 }, -+ { 0x280, 0x94, 0, 0x0010 }, -+ { 0x281, 0x11, 0, 0x0010 }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x288, 0x28, 0, 0x0020 }, -+ { 0x289, 0x0a, 0, 0x0020 }, -+ { 0x288, 0x28, 0, 0x0010 }, -+ { 0x289, 0x0a, 0, 0x0010 }, -+ { 0x28a, 0x03, 0, 0xffff }, -+ { 0x28b, 0x0a, 0, 0xffff }, -+ { 0x28c, 0x80, 0, 0xffff }, -+ { 0x28d, 0x03, 0, 0xffff }, -+}; -+ -+struct hwm_tab_entry HWM_TAB5[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x00, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0x66, 0, 0x0020 }, -+ { 0x085, 0x5d, 0, 0x0010 }, -+ { 0x086, 0x1c, 0, 0xffff }, -+ { 0x08a, 0x39, 0, 0x0020 }, -+ { 0x08a, 0x41, 0, 0x0010 }, -+ { 0x08b, 0x76, 0, 0x0020 }, -+ { 0x08b, 0x80, 0, 0x0010 }, -+ { 0x090, 0x5d, 0, 0x0020 }, -+ { 0x090, 0x5e, 0, 0x0010 }, -+ { 0x091, 0x5e, 0, 0xffff }, -+ { 0x092, 0x86, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa3, 0, 0x0020 }, -+ { 0x098, 0xa4, 0, 0x0010 }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x08, 0, 0xffff }, -+ { 0x0a1, 0x0a, 0, 0xffff }, -+ { 0x0ae, 0x7c, 0, 0xffff }, -+ { 0x0af, 0x7c, 0, 0xffff }, -+ { 0x0b0, 0x9a, 0, 0xffff }, -+ { 0x0b3, 0x7c, 0, 0xffff }, -+ { 0x0b6, 0x08, 0, 0xffff }, -+ { 0x0b7, 0x08, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0x0020 }, -+ { 0x0ea, 0x5c, 0, 0x0010 }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x0fd, 0x01, 0, 0xffff }, -+ { 0x1a1, 0x00, 0, 0xffff }, -+ { 0x1a2, 0x00, 0, 0xffff }, -+ { 0x1b1, 0x08, 0, 0xffff }, -+ { 0x1be, 0x98, 0, 0x0020 }, -+ { 0x1be, 0x90, 0, 0x0010 }, -+ { 0x280, 0x94, 0, 0x0020 }, -+ { 0x281, 0x11, 0, 0x0020 }, -+ { 0x280, 0x94, 0, 0x0010 }, -+ { 0x281, 0x11, 0, 0x0010 }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x288, 0x28, 0, 0x0020 }, -+ { 0x289, 0x0a, 0, 0x0020 }, -+ { 0x288, 0x28, 0, 0x0010 }, -+ { 0x289, 0x0a, 0, 0x0010 }, -+ { 0x28a, 0x03, 0, 0xffff }, -+ { 0x28b, 0x0a, 0, 0xffff }, -+ { 0x28c, 0x80, 0, 0xffff }, -+ { 0x28d, 0x03, 0, 0xffff }, -+}; -+ -+struct hwm_tab_entry HWM_TAB6[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x00, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0x98, 0, 0xffff }, -+ { 0x086, 0x3c, 0, 0xffff }, -+ { 0x08a, 0x39, 0, 0x0020 }, -+ { 0x08a, 0x3d, 0, 0x0010 }, -+ { 0x08b, 0x44, 0, 0x0020 }, -+ { 0x08b, 0x51, 0, 0x0010 }, -+ { 0x090, 0x61, 0, 0xffff }, -+ { 0x091, 0x6d, 0, 0xffff }, -+ { 0x092, 0x86, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0x9f, 0, 0x0020 }, -+ { 0x098, 0xa4, 0, 0x0010 }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x0e, 0, 0xffff }, -+ { 0x0a1, 0x0e, 0, 0xffff }, -+ { 0x0ae, 0x7c, 0, 0xffff }, -+ { 0x0af, 0x7c, 0, 0xffff }, -+ { 0x0b0, 0x9b, 0, 0x0020 }, -+ { 0x0b0, 0x98, 0, 0x0010 }, -+ { 0x0b3, 0x9a, 0, 0xffff }, -+ { 0x0b6, 0x08, 0, 0xffff }, -+ { 0x0b7, 0x08, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0x0020 }, -+ { 0x0ea, 0x5c, 0, 0x0010 }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x0fd, 0x01, 0, 0xffff }, -+ { 0x1a1, 0x00, 0, 0xffff }, -+ { 0x1a2, 0x00, 0, 0xffff }, -+ { 0x1b1, 0x08, 0, 0xffff }, -+ { 0x1be, 0x9a, 0, 0x0020 }, -+ { 0x1be, 0x96, 0, 0x0010 }, -+ { 0x280, 0x94, 0, 0x0020 }, -+ { 0x281, 0x11, 0, 0x0020 }, -+ { 0x280, 0x94, 0, 0x0010 }, -+ { 0x281, 0x11, 0, 0x0010 }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x288, 0x94, 0, 0x0020 }, -+ { 0x289, 0x11, 0, 0x0020 }, -+ { 0x288, 0x94, 0, 0x0010 }, -+ { 0x289, 0x11, 0, 0x0010 }, -+ { 0x28a, 0x03, 0, 0xffff }, -+ { 0x28b, 0x0a, 0, 0xffff }, -+ { 0x28c, 0x80, 0, 0xffff }, -+ { 0x28d, 0x03, 0, 0xffff }, -+}; -+ -+static uint8_t get_chassis_type(void) -+{ -+ uint8_t gpio_chassis_type; -+ -+ // Read chassis type from GPIO -+ gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 | -+ get_gpio(17) << 1 | get_gpio(1); -+ -+ printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type); -+ -+ // Turn it into internal chassis index -+ switch (gpio_chassis_type) { -+ case 0x08: -+ case 0x0a: -+ return 4; -+ case 0x0b: -+ return 3; -+ case 0x0c: -+ return 5; -+ case 0x0d: // SFF -+ case 0x0e: -+ case 0x0f: -+ return 6; -+ default: -+ return CHASSIS_TYPE_UNKNOWN; -+ } -+ -+} -+ -+static uint8_t get_temp_target(void) -+{ -+ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; -+ if (!val) -+ val = 20; -+ return 0x95 - val; -+} -+ -+static uint16_t get_pkg_power(void) -+{ -+ uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf; -+ if (rapl_power_unit) -+ rapl_power_unit = 2 << (rapl_power_unit - 1); -+ uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff; -+ if (pkg_power_info / rapl_power_unit > 0x41) -+ return 32; -+ else -+ return 16; -+} -+ -+static void apply_hwm_tab(struct hwm_tab_entry *arr, size_t size) -+{ -+ uint8_t temp_target = get_temp_target(); -+ uint16_t pkg_power = get_pkg_power(); -+ -+ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target); -+ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power); -+ -+ for (size_t i = 0; i < size; ++i) { -+ // Skip entry if it doesn't apply for this package power -+ if (arr[i].pkg_power != pkg_power && -+ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY) -+ continue; -+ -+ uint8_t val = arr[i].val; -+ -+ // Add temp target to value if requested (current tables never do) -+ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET) -+ val += temp_target; -+ -+ // Perform write -+ ec_write(1, arr[i].addr, val); -+ -+ } -+} -+ -+static void sch5555_ec_hwm_init(void *arg) -+{ -+ uint8_t chassis_type, saved_2fc; -+ -+ printk(BIOS_DEBUG, "OptiPlex 9020 late HWM init\n"); -+ -+ saved_2fc = ec_read(1, 0x2fc); -+ ec_write(1, 0x2fc, 0xa0); -+ ec_write(1, 0x2fd, 0x32); -+ -+ chassis_type = get_chassis_type(); -+ -+ if (chassis_type != CHASSIS_TYPE_UNKNOWN) { -+ printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type); -+ } else { -+ printk(BIOS_DEBUG, "WARNING: Unknown chassis type\n"); -+ } -+ -+ // Apply HWM table based on chassis type -+ switch (chassis_type) { -+ case 3: -+ apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3)); -+ break; -+ case 4: -+ apply_hwm_tab(HWM_TAB4, ARRAY_SIZE(HWM_TAB4)); -+ break; -+ case 5: -+ apply_hwm_tab(HWM_TAB5, ARRAY_SIZE(HWM_TAB5)); -+ break; -+ case 6: -+ apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6)); -+ break; -+ } -+ -+ // NOTE: vendor firmware applies these when "max core address" > 2 -+ // i think this is always the case -+ ec_write(1, 0x9e, 0x30); -+ ec_write(1, 0xeb, ec_read(1, 0xea)); -+ -+ ec_write(1, 0x2fc, saved_2fc); -+ -+ // Apply full speed fan config if requested or if the chassis type is unknown -+ if (chassis_type == CHASSIS_TYPE_UNKNOWN || get_uint_option("fan_full_speed", 0)) { -+ printk(BIOS_DEBUG, "Setting full fan speed\n"); -+ ec_write(1, 0x80, 0x60 | ec_read(1, 0x80)); -+ ec_write(1, 0x81, 0x60 | ec_read(1, 0x81)); -+ } -+ -+ ec_read(1, 0xb8); -+ -+ if ((chassis_type == 4 || chassis_type == 5) && ec_read(1, 0x26) == 0) { -+ ec_write(1, 0xa0, ec_read(1, 0xa0) & 0xfb); -+ ec_write(1, 0xa1, ec_read(1, 0xa1) & 0xfb); -+ ec_write(1, 0xa2, ec_read(1, 0xa2) & 0xfb); -+ ec_write(1, 0x8a, 0x99); -+ ec_write(1, 0x8b, 0x47); -+ ec_write(1, 0x8c, 0x91); -+ } -+} -+ -+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); -diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c -new file mode 100644 -index 0000000000..a1067ac063 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c -@@ -0,0 +1,54 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <arch/io.h> -+#include <device/pnp_ops.h> -+#include <superio/smsc/sch555x/sch555x.h> -+#include "sch5555_ec.h" -+ -+uint8_t ec_read(uint8_t addr1, uint16_t addr2) -+{ -+ // clear ec-to-host mailbox -+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); -+ outb(tmp, SCH555x_EMI_IOBASE + 1); -+ -+ // send address -+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); -+ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); -+ -+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); -+ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); -+ -+ // send message to ec -+ outb(1, SCH555x_EMI_IOBASE); -+ -+ // wait for ack -+ for (size_t retry = 0; retry < 0xfff; ++retry) -+ if (inb(SCH555x_EMI_IOBASE + 1) & 1) -+ break; -+ -+ // read result -+ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); -+ return inb(SCH555x_EMI_IOBASE + 4); -+} -+ -+void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) -+{ -+ // clear ec-to-host mailbox -+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); -+ outb(tmp, SCH555x_EMI_IOBASE + 1); -+ -+ // send address and value -+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); -+ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); -+ -+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); -+ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); -+ -+ // send message to ec -+ outb(1, SCH555x_EMI_IOBASE); -+ -+ // wait for ack -+ for (size_t retry = 0; retry < 0xfff; ++retry) -+ if (inb(SCH555x_EMI_IOBASE + 1) & 1) -+ break; -+} -diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h -new file mode 100644 -index 0000000000..7e399e8e74 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h -@@ -0,0 +1,10 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __SCH5555_EC_H__ -+#define __SCH5555_EC_H__ -+ -+uint8_t ec_read(uint8_t addr1, uint16_t addr2); -+ -+void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val); -+ -+#endif --- -2.39.2 - diff --git a/config/coreboot/default/patches/0043-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch b/config/coreboot/default/patches/0043-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch deleted file mode 100644 index 556e8e07..00000000 --- a/config/coreboot/default/patches/0043-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch +++ /dev/null @@ -1,49 +0,0 @@ -From cd3c553a313a26494e5dc31ff8323c3a919f190a Mon Sep 17 00:00:00 2001 -From: Mate Kukri <kukri.mate@gmail.com> -Date: Wed, 10 Apr 2024 20:31:35 +0100 -Subject: [PATCH 1/1] mb/dell/optiplex_9020: Add support for TPM1.2 device - -These machines come with a TPM1.2 device by default. It is somewhat -obsolete these days, but there is no harm in enabling it. - -Change-Id: Iec05321862aed58695c256b00494e5953219786d -Signed-off-by: Mate Kukri <kukri.mate@gmail.com> -Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827 -Reviewed-by: Angel Pons <th3fanbus@gmail.com> -Tested-by: build bot (Jenkins) <no-reply@coreboot.org> ---- - src/mainboard/dell/optiplex_9020/Kconfig | 2 ++ - src/mainboard/dell/optiplex_9020/devicetree.cb | 3 +++ - 2 files changed, 5 insertions(+) - -diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig -index 774a72f161..296938aa8d 100644 ---- a/src/mainboard/dell/optiplex_9020/Kconfig -+++ b/src/mainboard/dell/optiplex_9020/Kconfig -@@ -12,7 +12,9 @@ config BOARD_SPECIFIC_OPTIONS - select INTEL_GMA_HAVE_VBT - select INTEL_INT15 - select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_HAS_TPM1 - select MAINBOARD_USES_IFD_GBE_REGION -+ select MEMORY_MAPPED_TPM - select NORTHBRIDGE_INTEL_HASWELL - select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_LYNXPOINT -diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb -index 7bfa6736a6..e5cbd64127 100644 ---- a/src/mainboard/dell/optiplex_9020/devicetree.cb -+++ b/src/mainboard/dell/optiplex_9020/devicetree.cb -@@ -70,6 +70,9 @@ chip northbridge/intel/haswell - device pnp 2e.b off end # Floppy Controller - device pnp 2e.11 off end # Parallel Port - end -+ chip drivers/pc80/tpm -+ device pnp 0c31.0 on end -+ end - end - device pci 1f.2 on end # SATA controller 1 - device pci 1f.3 on end # SMBus --- -2.39.2 - diff --git a/config/coreboot/default/patches/0044-hp-8560w-turn-on-wifi.patch b/config/coreboot/default/patches/0044-hp-8560w-turn-on-wifi.patch deleted file mode 100644 index bb4a7b47..00000000 --- a/config/coreboot/default/patches/0044-hp-8560w-turn-on-wifi.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 4ccef4fffd98071c339cb4135e2d8c805e554378 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Fri, 3 May 2024 17:45:52 +0100 -Subject: [PATCH 1/1] hp/8560w: turn on wifi - -according to angel pons, this gpio is WLAN_TRN_OFF# -and setting it high will make wifi work. testing with -this change as suggested by angel. see: - -https://review.coreboot.org/c/coreboot/+/39398/4/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c#158 - -if it makes it into a libreboot release, you can assume -the fix works. right now we have this problem: - -https://codeberg.org/libreboot/lbmk/issues/201 - -Riku reported: - -[ 333.890080] atkbd serio0: Unknown key pressed (translated set 2, code 0xf8 on isa0060/serio0). -[ 333.890102] atkbd serio0: Use 'setkeycodes e078 <keycode>' to make it known. -[ 334.104069] atkbd serio0: Unknown key released (translated set 2, code 0xf8 on isa0060/serio0). -[ 334.104090] atkbd serio0: Use 'setkeycodes e078 <keycode>' to make it known. - -The wifi stays to hardblocked in rfkill. When the wireless button -is pressed, nothing changes except for these lines in dmesg. - -Signed-off-by: Leah Rowe <info@minifree.org> ---- - src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c -index 560d668d6f..10cd11ce48 100644 ---- a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c -+++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c -@@ -155,7 +155,7 @@ static const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio37 = GPIO_LEVEL_LOW, - .gpio49 = GPIO_LEVEL_LOW, - .gpio53 = GPIO_LEVEL_HIGH, -- .gpio57 = GPIO_LEVEL_LOW, -+ .gpio57 = GPIO_LEVEL_HIGH, - .gpio60 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_HIGH, - }; --- -2.39.2 - diff --git a/config/coreboot/default/patches/0046-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch b/config/coreboot/default/patches/0046-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch deleted file mode 100644 index 34d92278..00000000 --- a/config/coreboot/default/patches/0046-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch +++ /dev/null @@ -1,133 +0,0 @@ -From 9ff35368733c5e5a852ebd6295f262710553913b Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Fri, 3 May 2024 16:31:12 -0600 -Subject: [PATCH] mb/dell/: Add S3 SMI handler for SNB/IVB Latitudes - -This should fix S3 suspend on these systems - -Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> ---- - src/mainboard/dell/e5420/smihandler.c | 9 +++++++++ - src/mainboard/dell/e5520/smihandler.c | 9 +++++++++ - src/mainboard/dell/e5530/smihandler.c | 9 +++++++++ - src/mainboard/dell/e6420/smihandler.c | 9 +++++++++ - src/mainboard/dell/e6430/smihandler.c | 9 +++++++++ - src/mainboard/dell/e6520/smihandler.c | 9 +++++++++ - src/mainboard/dell/e6530/smihandler.c | 9 +++++++++ - 7 files changed, 63 insertions(+) - create mode 100644 src/mainboard/dell/e5420/smihandler.c - create mode 100644 src/mainboard/dell/e5520/smihandler.c - create mode 100644 src/mainboard/dell/e5530/smihandler.c - create mode 100644 src/mainboard/dell/e6420/smihandler.c - create mode 100644 src/mainboard/dell/e6430/smihandler.c - create mode 100644 src/mainboard/dell/e6520/smihandler.c - create mode 100644 src/mainboard/dell/e6530/smihandler.c - -diff --git a/src/mainboard/dell/e5420/smihandler.c b/src/mainboard/dell/e5420/smihandler.c -new file mode 100644 -index 0000000000..334d7b1a5f ---- /dev/null -+++ b/src/mainboard/dell/e5420/smihandler.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <cpu/x86/smm.h> -+#include <ec/dell/mec5035/mec5035.h> -+ -+void mainboard_smi_sleep(u8 slp_typ) -+{ -+ mec5035_sleep(slp_typ); -+} -diff --git a/src/mainboard/dell/e5520/smihandler.c b/src/mainboard/dell/e5520/smihandler.c -new file mode 100644 -index 0000000000..334d7b1a5f ---- /dev/null -+++ b/src/mainboard/dell/e5520/smihandler.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <cpu/x86/smm.h> -+#include <ec/dell/mec5035/mec5035.h> -+ -+void mainboard_smi_sleep(u8 slp_typ) -+{ -+ mec5035_sleep(slp_typ); -+} -diff --git a/src/mainboard/dell/e5530/smihandler.c b/src/mainboard/dell/e5530/smihandler.c -new file mode 100644 -index 0000000000..334d7b1a5f ---- /dev/null -+++ b/src/mainboard/dell/e5530/smihandler.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <cpu/x86/smm.h> -+#include <ec/dell/mec5035/mec5035.h> -+ -+void mainboard_smi_sleep(u8 slp_typ) -+{ -+ mec5035_sleep(slp_typ); -+} -diff --git a/src/mainboard/dell/e6420/smihandler.c b/src/mainboard/dell/e6420/smihandler.c -new file mode 100644 -index 0000000000..334d7b1a5f ---- /dev/null -+++ b/src/mainboard/dell/e6420/smihandler.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <cpu/x86/smm.h> -+#include <ec/dell/mec5035/mec5035.h> -+ -+void mainboard_smi_sleep(u8 slp_typ) -+{ -+ mec5035_sleep(slp_typ); -+} -diff --git a/src/mainboard/dell/e6430/smihandler.c b/src/mainboard/dell/e6430/smihandler.c -new file mode 100644 -index 0000000000..334d7b1a5f ---- /dev/null -+++ b/src/mainboard/dell/e6430/smihandler.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <cpu/x86/smm.h> -+#include <ec/dell/mec5035/mec5035.h> -+ -+void mainboard_smi_sleep(u8 slp_typ) -+{ -+ mec5035_sleep(slp_typ); -+} -diff --git a/src/mainboard/dell/e6520/smihandler.c b/src/mainboard/dell/e6520/smihandler.c -new file mode 100644 -index 0000000000..334d7b1a5f ---- /dev/null -+++ b/src/mainboard/dell/e6520/smihandler.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <cpu/x86/smm.h> -+#include <ec/dell/mec5035/mec5035.h> -+ -+void mainboard_smi_sleep(u8 slp_typ) -+{ -+ mec5035_sleep(slp_typ); -+} -diff --git a/src/mainboard/dell/e6530/smihandler.c b/src/mainboard/dell/e6530/smihandler.c -new file mode 100644 -index 0000000000..334d7b1a5f ---- /dev/null -+++ b/src/mainboard/dell/e6530/smihandler.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <cpu/x86/smm.h> -+#include <ec/dell/mec5035/mec5035.h> -+ -+void mainboard_smi_sleep(u8 slp_typ) -+{ -+ mec5035_sleep(slp_typ); -+} --- -2.44.0 - diff --git a/config/coreboot/default/target.cfg b/config/coreboot/default/target.cfg index a70633c4..3a773b43 100644 --- a/config/coreboot/default/target.cfg +++ b/config/coreboot/default/target.cfg @@ -1,2 +1,2 @@ tree="default" -rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a" +rev="97bc693abc482139774a656212935387d43df8e2" |