diff options
| author | Leah Rowe <leah@libreboot.org> | 2023-09-04 02:36:41 +0100 |
|---|---|---|
| committer | Leah Rowe <leah@libreboot.org> | 2023-09-04 02:47:25 +0100 |
| commit | da3c9bb3c5c3b1f2e6e67a3695ce39b17bf68d5b (patch) | |
| tree | b81cdd418a4906c846800a8c5094b312e74f57df /config/coreboot/default/patches | |
| parent | a05010503f9a748943033d1fc40e36625e72dcbb (diff) | |
merge config/ and resources/
Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/default/patches')
23 files changed, 2109 insertions, 0 deletions
diff --git a/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch b/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch new file mode 100644 index 00000000..2e7dfbc0 --- /dev/null +++ b/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch @@ -0,0 +1,23 @@ +From 21270ad036cdd1ee708a04c41ba6c4f279e4e6c0 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@retroboot.org> +Date: Fri, 19 Mar 2021 05:54:58 +0000 +Subject: [PATCH 01/19] apple/macbook21: Set default VRAM to 64MiB instead of + 8MiB + +--- + src/mainboard/apple/macbook21/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default +index cf1bc4566e..dc0df3b6d6 100644 +--- a/src/mainboard/apple/macbook21/cmos.default ++++ b/src/mainboard/apple/macbook21/cmos.default +@@ -5,4 +5,4 @@ boot_devices='' + boot_default=0x40 + cmos_defaults_loaded=Yes + lpt=Enable +-gfx_uma_size=8M ++gfx_uma_size=64M +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch new file mode 100644 index 00000000..deb6b1fb --- /dev/null +++ b/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch @@ -0,0 +1,68 @@ +From 6fa4c1488911b98e29d3e2858be68b9b72182573 Mon Sep 17 00:00:00 2001 +From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> +Date: Wed, 27 Oct 2021 13:36:01 +0200 +Subject: [PATCH 02/19] add c3 and clockgen to apple/macbook21 + +--- + src/mainboard/apple/macbook21/Kconfig | 1 + + src/mainboard/apple/macbook21/cstates.c | 13 +++++++++++++ + src/mainboard/apple/macbook21/devicetree.cb | 6 ++++++ + 3 files changed, 20 insertions(+) + +diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig +index 5f5ffde588..27377b737c 100644 +--- a/src/mainboard/apple/macbook21/Kconfig ++++ b/src/mainboard/apple/macbook21/Kconfig +@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select I945_LVDS ++ select DRIVERS_I2C_CK505 + + config MAINBOARD_DIR + default "apple/macbook21" +diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c +index 13d06f0839..88b8669c61 100644 +--- a/src/mainboard/apple/macbook21/cstates.c ++++ b/src/mainboard/apple/macbook21/cstates.c +@@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = { + .addrh = 0, + } + }, ++ { ++ .ctype = 3, ++ .latency = 17, ++ .power = 250, ++ .resource = { ++ .space_id = ACPI_ADDRESS_SPACE_FIXED, ++ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, ++ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, ++ .access_size = ACPI_ACCESS_SIZE_UNDEFINED, ++ .addrl = 0x20, ++ .addrh = 0, ++ } ++ }, + }; + + int get_cst_entries(const acpi_cstate_t **entries) +diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb +index fd86e939b9..263fbabcd1 100644 +--- a/src/mainboard/apple/macbook21/devicetree.cb ++++ b/src/mainboard/apple/macbook21/devicetree.cb +@@ -100,7 +100,13 @@ chip northbridge/intel/i945 + end + device pci 1f.3 on # SMBUS + subsystemid 0x8086 0x7270 ++ chip drivers/i2c/ck505 ++ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }" ++ register "regs" = "{ 0x77, 0x77, 0x2d, 0x00, 0x21, 0x10, 0x3b, 0x06, 0x07, 0x0f, 0xf0, 0x01, 0x1e, 0x7f, 0x80, 0x80, 0x10, 0x08, 0x04, 0x01 }" ++ device i2c 69 on end ++ end + end ++ + end + end + end +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch b/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch new file mode 100644 index 00000000..65606127 --- /dev/null +++ b/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch @@ -0,0 +1,23 @@ +From 79d9155c71f6014ff6adb454fe65466642bc2413 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@osboot.org> +Date: Sun, 3 Jan 2021 03:34:01 +0000 +Subject: [PATCH 03/19] lenovo/x60: 64MiB Video RAM changed to default + (previously it was 8MiB) + +--- + src/mainboard/lenovo/x60/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default +index 5c3576d1f3..88170a1aab 100644 +--- a/src/mainboard/lenovo/x60/cmos.default ++++ b/src/mainboard/lenovo/x60/cmos.default +@@ -15,4 +15,4 @@ trackpoint=Enable + sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable +-gfx_uma_size=8M ++gfx_uma_size=64M +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch b/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch new file mode 100644 index 00000000..ca5d0a8f --- /dev/null +++ b/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch @@ -0,0 +1,22 @@ +From 51a20e0db3fb9bf26ce138c9a17abe963bb8b289 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@osboot.org> +Date: Mon, 22 Feb 2021 22:16:59 +0000 +Subject: [PATCH 04/19] lenovo/t60: make 64MiB VRAM the default in cmos.default + +--- + src/mainboard/lenovo/t60/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default +index af865f16da..7f03157df7 100644 +--- a/src/mainboard/lenovo/t60/cmos.default ++++ b/src/mainboard/lenovo/t60/cmos.default +@@ -15,4 +15,4 @@ trackpoint=Enable + sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable +-gfx_uma_size=8M ++gfx_uma_size=64M +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch b/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch new file mode 100644 index 00000000..a108a75c --- /dev/null +++ b/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch @@ -0,0 +1,23 @@ +From 400e23c5149ab53300f57d8334ab25645d27b0c8 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Fri, 14 May 2021 13:10:33 +0100 +Subject: [PATCH 05/19] lenovo/t400: set VRAM to 256MiB VRAM by default + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/mainboard/lenovo/t400/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default +index a326e315b1..b907a3e2df 100644 +--- a/src/mainboard/lenovo/t400/cmos.default ++++ b/src/mainboard/lenovo/t400/cmos.default +@@ -13,4 +13,4 @@ power_management_beeps=Enable + low_battery_beep=Enable + sata_mode=AHCI + hybrid_graphics_mode=Integrated Only +-gfx_uma_size=32M ++gfx_uma_size=256M +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch new file mode 100644 index 00000000..3ba4b07a --- /dev/null +++ b/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch @@ -0,0 +1,23 @@ +From 29e6f78973928ad9ae86b26d5cf308a2680c88bf Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Fri, 14 May 2021 13:11:59 +0100 +Subject: [PATCH 06/19] lenovo/x200: set VRAM to 256MiB by default + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/mainboard/lenovo/x200/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default +index bb4323836e..458b3f19c5 100644 +--- a/src/mainboard/lenovo/x200/cmos.default ++++ b/src/mainboard/lenovo/x200/cmos.default +@@ -12,4 +12,4 @@ sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable + sata_mode=AHCI +-gfx_uma_size=32M ++gfx_uma_size=256M +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch new file mode 100644 index 00000000..5bbbccb4 --- /dev/null +++ b/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch @@ -0,0 +1,23 @@ +From 9339fbdd36ceed6b1606b7a6ff07404f4f2a2d6d Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Fri, 14 May 2021 13:18:26 +0100 +Subject: [PATCH 07/19] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default +index 8372032119..bedad54d2a 100644 +--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default ++++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default +@@ -2,4 +2,4 @@ boot_option=Fallback + debug_level=Debug + power_on_after_fail=Enable + nmi=Enable +-gfx_uma_size=64M ++gfx_uma_size=256M +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch new file mode 100644 index 00000000..ab5c2279 --- /dev/null +++ b/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch @@ -0,0 +1,23 @@ +From 54197e66c6ecf33743489be9ab0352cfc4b1ffe2 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Fri, 14 May 2021 13:21:39 +0100 +Subject: [PATCH 08/19] acer/g43t-am3: set VRAM to 256MiB by default + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/mainboard/acer/g43t-am3/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default +index 706f5dd551..e8b45ea22c 100644 +--- a/src/mainboard/acer/g43t-am3/cmos.default ++++ b/src/mainboard/acer/g43t-am3/cmos.default +@@ -3,4 +3,4 @@ debug_level=Debug + power_on_after_fail=Disable + nmi=Enable + sata_mode=AHCI +-gfx_uma_size=64M ++gfx_uma_size=256M +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch new file mode 100644 index 00000000..1aa74086 --- /dev/null +++ b/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch @@ -0,0 +1,34 @@ +From bc4ef158c4c6836351a395e8f0ff24f7c6d1f2c6 Mon Sep 17 00:00:00 2001 +From: persmule <persmule@gmail.com> +Date: Sun, 31 Oct 2021 23:33:26 +0000 +Subject: [PATCH 09/19] lenovo/t400: Enable all SATA ports + +There are 2 SATA ports on the chassis of t400(s), but at least one dock for +t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its +chassis, and another one on its dock. + +They have to be unmasked via device tree to use. + +This patch unmasked all SATA ports found within t400s with factory firmware. +--- + src/mainboard/lenovo/t400/devicetree.cb | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb +index 259c3e1b21..3d007533a4 100644 +--- a/src/mainboard/lenovo/t400/devicetree.cb ++++ b/src/mainboard/lenovo/t400/devicetree.cb +@@ -46,8 +46,8 @@ chip northbridge/intel/gm45 + register "gpe0_en" = "0x01000000" + register "gpi1_routing" = "2" + +- # Set AHCI mode, enable ports 1 and 2. +- register "sata_port_map" = "0x03" ++ # Set AHCI mode, enable ports 1, 2, 5 and 6. ++ register "sata_port_map" = "0x33" + register "sata_clock_request" = "0" + register "sata_traffic_monitor" = "0" + +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch b/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch new file mode 100644 index 00000000..c16884c5 --- /dev/null +++ b/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch @@ -0,0 +1,22 @@ +From 5987d9e821931ce097e265c13ca80a2090d3d821 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Mon, 20 Dec 2021 01:29:31 +0000 +Subject: [PATCH 10/19] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by + default + +--- + src/mainboard/lenovo/x230/cmos.default | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default +index 7314066c2b..2e315d4521 100644 +--- a/src/mainboard/lenovo/x230/cmos.default ++++ b/src/mainboard/lenovo/x230/cmos.default +@@ -16,3 +16,4 @@ backlight=Both + usb_always_on=Disable + f1_to_f12_as_primary=Enable + me_state=Normal ++gfx_uma_size=224M +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch new file mode 100644 index 00000000..3a96bc3a --- /dev/null +++ b/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -0,0 +1,38 @@ +From e5a6fac5b3c75c5aa4ae5106ec336a18083fbab0 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Mon, 3 Jan 2022 19:06:22 +0000 +Subject: [PATCH 11/19] lenovo/x230: set me_state=Disabled in cmos.default + +I only recently found out about this. It's possible to use me_cleaner to +do the same thing, but some people might just flash coreboot and not do +anything with the ME region + +With this change, the ME is set to disabled. It's my understanding that this +will accomplish more or less the same thing as me_cleaner, without actually +using that. Of course, I still recommend using me_cleaner + +I saw this when I audited coreboot's git history, and saw this: + +commit 833e9bad4762e0dca6c867d3a18dbaf6d5166be8 +Author: Evgeny Zinoviev <me@ch1p.io> +Date: Thu Nov 21 21:47:31 2019 +0300 + + sb/intel/bd82x6x: Support ME Soft Temporary Disable Mode +--- + src/mainboard/lenovo/x230/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default +index 2e315d4521..3585cbd58b 100644 +--- a/src/mainboard/lenovo/x230/cmos.default ++++ b/src/mainboard/lenovo/x230/cmos.default +@@ -15,5 +15,5 @@ trackpoint=Enable + backlight=Both + usb_always_on=Disable + f1_to_f12_as_primary=Enable +-me_state=Normal ++me_state=Disabled + gfx_uma_size=224M +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch new file mode 100644 index 00000000..9efc5198 --- /dev/null +++ b/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -0,0 +1,122 @@ +From 03610ab506bdaca92c1623abd18b4812f92273ed Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Wed, 2 Mar 2022 21:50:01 +0000 +Subject: [PATCH 12/19] set me_state=Disabled on all cmos.default files! + +yeah. why the hell isn't this the default + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/mainboard/lenovo/l520/cmos.default | 2 +- + src/mainboard/lenovo/t420/cmos.default | 2 +- + src/mainboard/lenovo/t420s/cmos.default | 2 +- + src/mainboard/lenovo/t430/cmos.default | 2 +- + src/mainboard/lenovo/t430s/cmos.default | 2 +- + src/mainboard/lenovo/t520/cmos.default | 2 +- + src/mainboard/lenovo/t530/cmos.default | 2 +- + src/mainboard/lenovo/x220/cmos.default | 2 +- + src/mainboard/protectli/vault_cml/cmos.default | 2 +- + src/mainboard/system76/tgl-u/cmos.default | 2 +- + 10 files changed, 10 insertions(+), 10 deletions(-) + +diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default +index 681c40e78b..57cdcf9162 100644 +--- a/src/mainboard/lenovo/l520/cmos.default ++++ b/src/mainboard/lenovo/l520/cmos.default +@@ -14,4 +14,4 @@ sticky_fn=Disable + trackpoint=Enable + backlight=Both + usb_always_on=Disable +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default +index 8244071b8a..c011867916 100644 +--- a/src/mainboard/lenovo/t420/cmos.default ++++ b/src/mainboard/lenovo/t420/cmos.default +@@ -14,4 +14,4 @@ sticky_fn=Disable + trackpoint=Enable + hybrid_graphics_mode=Integrated Only + usb_always_on=Disable +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default +index 8244071b8a..c011867916 100644 +--- a/src/mainboard/lenovo/t420s/cmos.default ++++ b/src/mainboard/lenovo/t420s/cmos.default +@@ -14,4 +14,4 @@ sticky_fn=Disable + trackpoint=Enable + hybrid_graphics_mode=Integrated Only + usb_always_on=Disable +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default +index 26795fe5cf..55e1e6c04e 100644 +--- a/src/mainboard/lenovo/t430/cmos.default ++++ b/src/mainboard/lenovo/t430/cmos.default +@@ -15,4 +15,4 @@ trackpoint=Enable + backlight=Both + usb_always_on=Disable + hybrid_graphics_mode=Integrated Only +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default +index 52dbf70377..b16800ca9e 100644 +--- a/src/mainboard/lenovo/t430s/cmos.default ++++ b/src/mainboard/lenovo/t430s/cmos.default +@@ -16,4 +16,4 @@ backlight=Both + enable_dual_graphics=Disable + usb_always_on=Disable + f1_to_f12_as_primary=Enable +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default +index cf79b391e2..b66f7034dc 100644 +--- a/src/mainboard/lenovo/t520/cmos.default ++++ b/src/mainboard/lenovo/t520/cmos.default +@@ -15,4 +15,4 @@ trackpoint=Enable + backlight=Both + hybrid_graphics_mode=Integrated Only + usb_always_on=Disable +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default +index cf79b391e2..b66f7034dc 100644 +--- a/src/mainboard/lenovo/t530/cmos.default ++++ b/src/mainboard/lenovo/t530/cmos.default +@@ -15,4 +15,4 @@ trackpoint=Enable + backlight=Both + hybrid_graphics_mode=Integrated Only + usb_always_on=Disable +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default +index 6d1d57a795..52f303dfdb 100644 +--- a/src/mainboard/lenovo/x220/cmos.default ++++ b/src/mainboard/lenovo/x220/cmos.default +@@ -13,4 +13,4 @@ usb_always_on=Disable + fn_ctrl_swap=Disable + sticky_fn=Disable + trackpoint=Enable +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default +index 62715bc6ba..129b5fd121 100644 +--- a/src/mainboard/protectli/vault_cml/cmos.default ++++ b/src/mainboard/protectli/vault_cml/cmos.default +@@ -1,3 +1,3 @@ + boot_option=Fallback + debug_level=Debug +-me_state=Enable ++me_state=Disabled +diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default +index 62715bc6ba..129b5fd121 100644 +--- a/src/mainboard/system76/tgl-u/cmos.default ++++ b/src/mainboard/system76/tgl-u/cmos.default +@@ -1,3 +1,3 @@ + boot_option=Fallback + debug_level=Debug +-me_state=Enable ++me_state=Disabled +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch b/config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch new file mode 100644 index 00000000..9bc43e78 --- /dev/null +++ b/config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch @@ -0,0 +1,198 @@ +From f4e5f11762e4c54829e1d6515d7fd369d86ac9d7 Mon Sep 17 00:00:00 2001 +From: Alexander Couzens <lynxis@fe80.eu> +Date: Sat, 19 Mar 2022 13:42:33 +0000 +Subject: [PATCH 13/19] lenovo/x230: introduce FHD variant + +There is a modification for the x230 which uses the 2nd DP from the dock +as the integrated panel's connection, which allows using a custom eDP +panel instead of the stock LVDS display. + +There are several adapter boards present on the market and all of them +uses the same method of enabling the custom eDP panel. + +To make this work with coreboot, the internal LVDS connector should be +disabled in libgfxinit. The VBT has been modified as well, which allows +brightness controls to work out of the box. + +The modifications done to the VBT are: +- Remove the LVDS port entry. +- Move the DP-3 (which is the 2nd DP on the dock) entry to the first + position on the list. +- Set the DP-3 as internally connected. + +This has been reported to work with the following panels: +- LP125WF2-SPB4 (1920*1080, 12.5") +- LQ125T1JW02 (2560*1440, 12.5") +- LQ133M1JW21 (1920*1080, 13.3") +- LTN133HL10-201 (1920*1080, 13.3") +- B133HAN04.6 (1920*1080, 13.3") +- B133QAN02.0 (2560*1600, 13.3") + +Other eDP panels not on this list should work as well. + +Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 +Signed-off-by: Alexander Couzens <lynxis@fe80.eu> +Signed-off-by: Felix Singer <felixsinger@posteo.net> +--- + src/mainboard/lenovo/x230/Kconfig | 15 ++++++++----- + src/mainboard/lenovo/x230/Kconfig.name | 3 +++ + src/mainboard/lenovo/x230/Makefile.inc | 5 +++++ + .../lenovo/x230/variants/x230_edp/data.vbt | Bin 0 -> 4281 bytes + .../x230/variants/x230_edp/gma-mainboard.ads | 21 ++++++++++++++++++ + 5 files changed, 38 insertions(+), 6 deletions(-) + create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/data.vbt + create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads + +diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig +index 279095629b..acfd0ed561 100644 +--- a/src/mainboard/lenovo/x230/Kconfig ++++ b/src/mainboard/lenovo/x230/Kconfig +@@ -1,4 +1,4 @@ +-if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S ++if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP + + config BOARD_SPECIFIC_OPTIONS + def_bool y +@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS + select H8_HAS_BAT_THRESHOLDS_IMPL + select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S + select NO_UART_ON_SUPERIO +- select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T ++ select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP + select BOARD_ROMSIZE_KB_16384 if BOARD_LENOVO_X230S + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE +@@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS + select INTEL_INT15 + select DRIVERS_RICOH_RCE822 + select MEMORY_MAPPED_TPM +- select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T ++ select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T + select INTEL_GMA_HAVE_VBT +@@ -47,17 +47,20 @@ config MAINBOARD_DIR + default "lenovo/x230" + + config VARIANT_DIR +- default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T ++ default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP + default "x230s" if BOARD_LENOVO_X230S + + config MAINBOARD_PART_NUMBER +- default "ThinkPad X230" if BOARD_LENOVO_X230 ++ default "ThinkPad X230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230_EDP + default "ThinkPad X230t" if BOARD_LENOVO_X230T + default "ThinkPad X230s" if BOARD_LENOVO_X230S + + config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + ++config INTEL_GMA_VBT_FILE ++ default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP ++ + config USBDEBUG_HCD_INDEX + int + default 2 +@@ -79,4 +82,4 @@ config PS2M_EISAID + config THINKPADEC_HKEY_EISAID + default "LEN0068" + +-endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S ++endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP +diff --git a/src/mainboard/lenovo/x230/Kconfig.name b/src/mainboard/lenovo/x230/Kconfig.name +index 1a01436879..e7290a12dd 100644 +--- a/src/mainboard/lenovo/x230/Kconfig.name ++++ b/src/mainboard/lenovo/x230/Kconfig.name +@@ -6,3 +6,6 @@ config BOARD_LENOVO_X230T + + config BOARD_LENOVO_X230S + bool "ThinkPad X230s" ++ ++config BOARD_LENOVO_X230_EDP ++ bool "ThinkPad X230 eDP Mod (2K/FHD)" +diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc +index 8e801f145d..6e6f9f90b9 100644 +--- a/src/mainboard/lenovo/x230/Makefile.inc ++++ b/src/mainboard/lenovo/x230/Makefile.inc +@@ -5,4 +5,9 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c + romstage-y += variants/$(VARIANT_DIR)/early_init.c + romstage-y += variants/$(VARIANT_DIR)/gpio.c + ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ++ ++ifeq ($(CONFIG_BOARD_LENOVO_X230_EDP),y) ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x230_edp/gma-mainboard.ads ++else + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads ++endif +diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt b/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..13384d45571ff76e592335143d01315e37893186 +GIT binary patch +literal 4281 +zcmdT`Z)_aZ5&ym0y}P}=-MjTVC6^<yCLz$XvE%h&S*h!)@6LAcg^PXugKH2XcDRE^ +zHNiLuN+i^5TbBk=p_5vr0Ri$CB!v1Q6%yhL5TS}%ZG|E}(5mW(6!8It5AdN?tBP`+ +zx3_i!7V#AnmCow7GdpkI?0YkBW_RywafYVHi@l}UV$Y$8VyQezRd{&CInDRYR4h$Q +zA08>p6b={56T^4V^SA+LolmX+RUx+79#iSqiP~ars*|P{j#W<|Sw32Qpw?S@B$TK! +zT%y8#_th3_%L^xJRhpi?y+F#XZ5B@+U98gh$p??rmIq1sVr%N_-*;O-QJ>e_m+#Gc +zeSJjvzQO*1!F<1Mj*JdZ9IBMcg_+XCI898^NNKt-Jw1A;SiXxYQxjvQVrgb{#5RMi +z3_rAVdim%B-#tOO;ZDl)3wi>F!IEkCq2;B0R9IZ3DP?n<rfSD)%a7Em`)pG=xClcR +zfQTY3AQJz|BVh>3(8mm!Gbk$bf{?ofjp)+WX;f0xKuMreM_FPop&M`zu|-4&b{lx} +z6dXr%nIN^a1Q1g^?g`SApyQo+We^Ju;y^Soa0Kxp0ExE)gG^{(s5wk=5)@Iwe?zpD +z@%1v$crW@+c=`T;{ewfYIC5a@V7W3iGdp+pJ^l}V_@k99K7NB27i?KEp$JF`50mi@ +zjG1XXrseRG7Qw69ek|x~_*Klqd$9}}jBGpu*K}~RX~1KAld;P%uwb}2&iFCo7mQyT +zCSGP-Wc-%#2gY9*A29yLh$l?6F>Yks%;;r&gE7oF#P|+lf$=@YNyZt*<BXp%o@K;N +z;^Rid2d9zA7a?zJayUAk?1cYJsDCEZCq4>N3Nz%%kOxj$xHTH_I6i5-#j$7@-%=}( +z?1954MnX?xAuk79(<<Tf409Fpx$wEsNX+wNp0De7H-87y*XOlHqw#v9f#_UhUAnlg +zi_2(JC*w<@<i}S-iI)}-&;1HW$=_hN&+7=v86dSJ5nbA)_y+kbU2PDFE??VVW9GW> +zSr6;_4gTc~tacpa=As!xD;@CT7xX)U4}W57_`9~2N<i$1-Hq?ZdXRnseAKTSC4vUn +zvU_KR`>pCP65!^@JyGbYMG6B#@{r1i&qF#431THdvdmK?gb!}@x&d86kH8RtSun)L +zMg&qo8p@sxlqPr)H*t1i5Xc8fNK*dW_}wA77I--u)J{nAs;))bo<l6#G>8v<p5gy; +z<c2$V&sxyMI7lIRD=DCSpmMmfaICgCzVKkJ#fR-<sP2F);1(})cA)7k<8|TuBs}RY +zwKp{#FZ7<eJej>k&YfS^jD1^rM=s>0ytuB(<S=kXYsT9eI1^R*2UrsIpx#)DflmYL +zcI2=F|Kw{2>VlIOTx;M223I$qhjl3%0pyLp$ECQ*_^UYE{?(M!zFMP3W9I<gN%(cT +zyvs4>_cUj9w4&M7&s8K0k<cwUM!E2PTu7mct3rr`5sB*7)nZ4R`hWT~<uZuic%Tb% +z5{?q{&YwfGl9W%nBS~{SNhgx-V@b1~q?eQKTGD(wN&iT?re$ukXwY)YmN{$Dqn7)m +zWuCX_HOswZnSZhfw(HvFPMeChJ7b&o+O%T3=WKJ;rZ;W(kGA=)O-9Pirp&!5I+$|r +zNtySj=%*?7xs>@rirz}Oms94I6gg>kPulEG+g%^&e&n+7+xV#SfijjY{5o+C7V}H- +zZs9PGrN7SK-OZ8YGZ>yr(&i#tdss~q`sQ|0&fnIIOUJ;O2*-=b;v=kW?O}6KsoH4P +z0smI&%EQn#cd@w$RZTVP=TtP?l7~|?nRTSIQO2qkgO+Z!=3#T$D-XeMvn68}T3Ey8 +zHleye(7mkLXe*JtfA{Q*lj!gc)Wck4IFj|C#q&~HiNmA&>Z|kF4(U<Y;5eIloj)C% +zP4#WvIv2Sie|71?P3)md%>vj%v~DWNT8*x>a2}rST)i~8vd61DwO!2$JZMNNi6hyH +z2d_)6&979w%w$-vyatVrqw??t&t%}iZhDAP3%j_I#cGANdzLq>W;J(F=Xwkxxj%^H +zwQDmn=w}|@-y`RG{*wz0>A(ZGtk~AM=#-fE(LV1uZE98+Nk>UmiyyuJ8?##<Mr{1g +p(B@uj-Va_SU#<T#GXLCvin_ms#}9BYOE7UKDyX7coWuJX{tbC=%boxL + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads +new file mode 100644 +index 0000000000..f7cf0bc264 +--- /dev/null ++++ b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads +@@ -0,0 +1,21 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (DP1, ++ DP2, ++ DP3, ++ HDMI1, ++ HDMI2, ++ HDMI3, ++ Analog, ++ others => Disabled); ++ ++end GMA.Mainboard; +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch b/config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch new file mode 100644 index 00000000..d391d0c3 --- /dev/null +++ b/config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch @@ -0,0 +1,25 @@ +From 982734642e0c8a960b99180371a5a12c3851b6e9 Mon Sep 17 00:00:00 2001 +From: Alexei Sorokin <sor.alexei@meowr.ru> +Date: Sun, 27 Nov 2022 18:36:26 +0300 +Subject: [PATCH 14/19] lenovo/x230: fix the data.vbt path for the EDP variant + +--- + src/mainboard/lenovo/x230/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig +index acfd0ed561..34108c3c04 100644 +--- a/src/mainboard/lenovo/x230/Kconfig ++++ b/src/mainboard/lenovo/x230/Kconfig +@@ -59,7 +59,7 @@ config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + + config INTEL_GMA_VBT_FILE +- default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP ++ default "src/mainboard/\$(MAINBOARDDIR)/variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP + + config USBDEBUG_HCD_INDEX + int +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch new file mode 100644 index 00000000..d8a701d9 --- /dev/null +++ b/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -0,0 +1,205 @@ +From 35425512e05c989d2d6789551cc448719ab1ca38 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Sun, 19 Feb 2023 18:21:43 +0000 +Subject: [PATCH 15/19] util/ifdtool: add --nuke flag (all 0xFF on region) + +When this option is used, the region's contents are overwritten +with all ones (0xFF). + +Example: + +./ifdtool --nuke gbe coreboot.rom +./ifdtool --nuke bios coreboot.com +./ifdtool --nuke me coreboot.com + +Rebased since the last revision update in lbmk. + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++----------- + 1 file changed, 83 insertions(+), 31 deletions(-) + +diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c +index ddbc0fb91b..7af9235ae3 100644 +--- a/util/ifdtool/ifdtool.c ++++ b/util/ifdtool/ifdtool.c +@@ -1847,6 +1847,7 @@ static void print_usage(const char *name) + " wbg - Wellsburg\n" + " -S | --setpchstrap Write a PCH strap\n" + " -V | --newvalue The new value to write into PCH strap specified by -S\n" ++ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n" + " -v | --version: print the version\n" + " -h | --help: print this help\n\n" + "<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, " +@@ -1854,6 +1855,60 @@ static void print_usage(const char *name) + "\n"); + } + ++static int ++get_region_type_string(const char *region_type_string) ++{ ++ if (!strcasecmp("Descriptor", region_type_string)) ++ return 0; ++ else if (!strcasecmp("BIOS", region_type_string)) ++ return 1; ++ else if (!strcasecmp("ME", region_type_string)) ++ return 2; ++ else if (!strcasecmp("GbE", region_type_string)) ++ return 3; ++ else if (!strcasecmp("Platform Data", region_type_string)) ++ return 4; ++ else if (!strcasecmp("Device Exp1", region_type_string)) ++ return 5; ++ else if (!strcasecmp("Secondary BIOS", region_type_string)) ++ return 6; ++ else if (!strcasecmp("Reserved", region_type_string)) ++ return 7; ++ else if (!strcasecmp("EC", region_type_string)) ++ return 8; ++ else if (!strcasecmp("Device Exp2", region_type_string)) ++ return 9; ++ else if (!strcasecmp("IE", region_type_string)) ++ return 10; ++ else if (!strcasecmp("10GbE_0", region_type_string)) ++ return 11; ++ else if (!strcasecmp("10GbE_1", region_type_string)) ++ return 12; ++ else if (!strcasecmp("PTT", region_type_string)) ++ return 15; ++ return -1; ++} ++ ++static void ++nuke(const char *filename, char *image, int size, int region_type) ++{ ++ int i; ++ struct region region; ++ const struct frba *frba = find_frba(image, size); ++ if (!frba) ++ exit(EXIT_FAILURE); ++ ++ region = get_region(frba, region_type); ++ if (region.size > 0) { ++ for (i = region.base; i <= region.limit; i++) { ++ if ((i + 1) > (size)) ++ break; ++ image[i] = 0xFF; ++ } ++ write_image(filename, image, size); ++ } ++} ++ + int main(int argc, char *argv[]) + { + int opt, option_index = 0; +@@ -1861,6 +1916,7 @@ int main(int argc, char *argv[]) + int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; + int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; + int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; ++ int mode_nuke = 0; + char *region_type_string = NULL, *region_fname = NULL; + const char *layout_fname = NULL; + char *new_filename = NULL; +@@ -1892,6 +1948,7 @@ int main(int argc, char *argv[]) + {"validate", 0, NULL, 't'}, + {"setpchstrap", 1, NULL, 'S'}, + {"newvalue", 1, NULL, 'V'}, ++ {"nuke", 1, NULL, 'N'}, + {0, 0, 0, 0} + }; + +@@ -1941,35 +1998,8 @@ int main(int argc, char *argv[]) + region_fname++; + // Descriptor, BIOS, ME, GbE, Platform + // valid type? +- if (!strcasecmp("Descriptor", region_type_string)) +- region_type = 0; +- else if (!strcasecmp("BIOS", region_type_string)) +- region_type = 1; +- else if (!strcasecmp("ME", region_type_string)) +- region_type = 2; +- else if (!strcasecmp("GbE", region_type_string)) +- region_type = 3; +- else if (!strcasecmp("Platform Data", region_type_string)) +- region_type = 4; +- else if (!strcasecmp("Device Exp1", region_type_string)) +- region_type = 5; +- else if (!strcasecmp("Secondary BIOS", region_type_string)) +- region_type = 6; +- else if (!strcasecmp("Reserved", region_type_string)) +- region_type = 7; +- else if (!strcasecmp("EC", region_type_string)) +- region_type = 8; +- else if (!strcasecmp("Device Exp2", region_type_string)) +- region_type = 9; +- else if (!strcasecmp("IE", region_type_string)) +- region_type = 10; +- else if (!strcasecmp("10GbE_0", region_type_string)) +- region_type = 11; +- else if (!strcasecmp("10GbE_1", region_type_string)) +- region_type = 12; +- else if (!strcasecmp("PTT", region_type_string)) +- region_type = 15; +- if (region_type == -1) { ++ if ((region_type = ++ get_region_type_string(region_type_string)) == -1) { + fprintf(stderr, "No such region type: '%s'\n\n", + region_type_string); + fprintf(stderr, "run '%s -h' for usage\n", argv[0]); +@@ -2135,6 +2165,22 @@ int main(int argc, char *argv[]) + case 't': + mode_validate = 1; + break; ++ case 'N': ++ region_type_string = strdup(optarg); ++ if (!region_type_string) { ++ fprintf(stderr, "No region specified\n"); ++ print_usage(argv[0]); ++ exit(EXIT_FAILURE); ++ } ++ if ((region_type = ++ get_region_type_string(region_type_string)) == -1) { ++ fprintf(stderr, "No such region type: '%s'\n\n", ++ region_type_string); ++ print_usage(argv[0]); ++ exit(EXIT_FAILURE); ++ } ++ mode_nuke = 1; ++ break; + case 'v': + print_version(); + exit(EXIT_SUCCESS); +@@ -2150,7 +2196,8 @@ int main(int argc, char *argv[]) + + if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + + mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 | +- mode_unlocked | mode_locked) + mode_altmedisable + mode_validate) > 1) { ++ mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + ++ mode_nuke) > 1) { + fprintf(stderr, "You may not specify more than one mode.\n\n"); + fprintf(stderr, "run '%s -h' for usage\n", argv[0]); + exit(EXIT_FAILURE); +@@ -2158,7 +2205,8 @@ int main(int argc, char *argv[]) + + if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + + mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 + +- mode_locked + mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) { ++ mode_locked + mode_unlocked + mode_density + mode_altmedisable + ++ mode_validate + mode_nuke) == 0) { + fprintf(stderr, "You need to specify a mode.\n\n"); + fprintf(stderr, "run '%s -h' for usage\n", argv[0]); + exit(EXIT_FAILURE); +@@ -2262,6 +2310,10 @@ int main(int argc, char *argv[]) + write_image(new_filename, image, size); + } + ++ if (mode_nuke) { ++ nuke(new_filename, image, size, region_type); ++ } ++ + if (mode_altmedisable) { + struct fpsba *fpsba = find_fpsba(image, size); + struct fmsba *fmsba = find_fmsba(image, size); +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch b/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch new file mode 100644 index 00000000..df43eeb3 --- /dev/null +++ b/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch @@ -0,0 +1,47 @@ +From 929974434bbd627ab7add5ef4ec4eb62e5412f57 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Wed, 1 Dec 2021 02:53:00 +0000 +Subject: [PATCH 16/19] fix speedstep on x200/t400: Revert + "cpu/intel/model_1067x: enable PECI" + +This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f. + +Enabling PECI without microcode updates loaded causes the CPUID feature set +to become corrupted. And one consequence is broken SpeedStep. At least, that's +my understanding looking at Intel Errata. This revert is not a fix, because +upstream is correct (upstream assumes microcode updates). We will simply +maintain this revert patch in Libreboot, from now on. +--- + src/cpu/intel/model_1067x/model_1067x_init.c | 9 --------- + 1 file changed, 9 deletions(-) + +diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c +index 315e7c36fc..1423fd72bc 100644 +--- a/src/cpu/intel/model_1067x/model_1067x_init.c ++++ b/src/cpu/intel/model_1067x/model_1067x_init.c +@@ -141,8 +141,6 @@ static void configure_emttm_tables(void) + wrmsr(MSR_EMTTM_CR_TABLE(5), msr); + } + +-#define IA32_PECI_CTL 0x5a0 +- + static void configure_misc(const int eist, const int tm2, const int emttm) + { + msr_t msr; +@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm) + msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ + wrmsr(IA32_MISC_ENABLE, msr); + } +- +- /* Enable PECI +- WARNING: due to Erratum AW67 described in Intel document #318733 +- the microcode must be updated before this MSR is written to. */ +- msr = rdmsr(IA32_PECI_CTL); +- msr.lo |= 1; +- wrmsr(IA32_PECI_CTL, msr); + } + + #define PIC_SENS_CFG 0x1aa +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch b/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch new file mode 100644 index 00000000..750628cf --- /dev/null +++ b/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch @@ -0,0 +1,173 @@ +From f5859da443fc1ff2450051d1d88bee56346fe63b Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Mon, 17 Apr 2023 15:49:57 +0100 +Subject: [PATCH 17/19] GM45-type CPUs: don't enable alternative SMRR + +This reverts the changes in coreboot revision: +df7aecd92643d207feaf7fd840f8835097346644 + +While this fix is *technically correct*, the one in +coreboot, it breaks rebooting as tested on several +GM45 ThinkPads e.g. X200, T400, when microcode +updates are not applied. + +Since November 2022, Libreboot includes microcode +updates by default, but it tells users how to remove +it from the ROM (with cbfstool) if they wish. + +Well, with Libreboot 20221214, 20230319 and 20230413, +mitigations present in Libreboot 20220710 (which did +not have microcode updates) do not exist. + +This patch, along with the other patch to remove PECI +support (which breaks speedstep when microcode updates +are not applied) have now been re-added to Libreboot. + +It is still best to use microcode updates by default. +These patches in coreboot are not critically urgent, +and you can use the machines with or without them, +regardless of ucode. + +I'll probably re-write this and the other patch at +some point, applying the change conditionally upon +whether or not microcode is applied. + +Pragmatism is a good thing. I recommend it. +--- + src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++ + src/cpu/intel/model_1067x/mp_init.c | 26 -------------------- + src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++ + src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++ + src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++ + 5 files changed, 16 insertions(+), 26 deletions(-) + +diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c +index 1423fd72bc..d1f98ca43a 100644 +--- a/src/cpu/intel/model_1067x/model_1067x_init.c ++++ b/src/cpu/intel/model_1067x/model_1067x_init.c +@@ -8,6 +8,7 @@ + #include <cpu/x86/cache.h> + #include <cpu/x86/name.h> + #include <cpu/intel/smm_reloc.h> ++#include <cpu/intel/common/common.h> + + #define MSR_BBL_CR_CTL3 0x11e + +@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu) + fill_processor_name(processor_name); + printk(BIOS_INFO, "CPU: %s.\n", processor_name); + ++ /* Set virtualization based on Kconfig option */ ++ set_vmx_and_lock(); ++ + /* Configure C States */ + configure_c_states(quad); + +diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c +index bc53214310..72f40f6762 100644 +--- a/src/cpu/intel/model_1067x/mp_init.c ++++ b/src/cpu/intel/model_1067x/mp_init.c +@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void) + smm_initialize(); + } + +-#define SMRR_SUPPORTED (1 << 11) +- + static void per_cpu_smm_trigger(void) + { +- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); +- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) { +- set_feature_ctrl_vmx(); +- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL); +- /* We don't care if the lock is already setting +- as our smm relocation handler is able to handle +- setups where SMRR is not enabled here. */ +- if (ia32_ft_ctrl.lo & (1 << 0)) { +- /* IA32_FEATURE_CONTROL locked. If we set it again we +- get an illegal instruction. */ +- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n"); +- printk(BIOS_DEBUG, "SMRR status: %senabled\n", +- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not "); +- } else { +- if (!CONFIG(SET_IA32_FC_LOCK_BIT)) +- printk(BIOS_INFO, +- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n"); +- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0); +- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl); +- } +- } else { +- set_vmx_and_lock(); +- } +- + /* Relocate the SMM handler. */ + smm_relocate(); + } +diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c +index 05f5f327cc..0450c2ad83 100644 +--- a/src/cpu/intel/model_106cx/model_106cx_init.c ++++ b/src/cpu/intel/model_106cx/model_106cx_init.c +@@ -7,6 +7,7 @@ + #include <cpu/intel/speedstep.h> + #include <cpu/x86/cache.h> + #include <cpu/x86/name.h> ++#include <cpu/intel/common/common.h> + + #define HIGHEST_CLEVEL 3 + static void configure_c_states(void) +@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu) + fill_processor_name(processor_name); + printk(BIOS_INFO, "CPU: %s.\n", processor_name); + ++ /* Set virtualization based on Kconfig option */ ++ set_vmx_and_lock(); ++ + /* Configure C States */ + configure_c_states(); + +diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c +index 5bd1c32815..f3bb08cde3 100644 +--- a/src/cpu/intel/model_6ex/model_6ex_init.c ++++ b/src/cpu/intel/model_6ex/model_6ex_init.c +@@ -7,6 +7,7 @@ + #include <cpu/intel/speedstep.h> + #include <cpu/x86/cache.h> + #include <cpu/x86/name.h> ++#include <cpu/intel/common/common.h> + + #define HIGHEST_CLEVEL 3 + static void configure_c_states(void) +@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu) + /* Setup Page Attribute Tables (PAT) */ + // TODO set up PAT + ++ /* Set virtualization based on Kconfig option */ ++ set_vmx_and_lock(); ++ + /* Configure C States */ + configure_c_states(); + +diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c +index 535fb8fae7..f7b05facd2 100644 +--- a/src/cpu/intel/model_6fx/model_6fx_init.c ++++ b/src/cpu/intel/model_6fx/model_6fx_init.c +@@ -7,6 +7,7 @@ + #include <cpu/intel/speedstep.h> + #include <cpu/x86/cache.h> + #include <cpu/x86/name.h> ++#include <cpu/intel/common/common.h> + + #define HIGHEST_CLEVEL 3 + static void configure_c_states(void) +@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu) + /* Setup Page Attribute Tables (PAT) */ + // TODO set up PAT + ++ /* Set virtualization based on Kconfig option */ ++ set_vmx_and_lock(); ++ + /* Configure C States */ + configure_c_states(); + +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch new file mode 100644 index 00000000..42fa8399 --- /dev/null +++ b/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -0,0 +1,28 @@ +From 6dc133e52c1ede4dbd3207133dd8ed0eb053fcd0 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Sat, 6 May 2023 15:53:41 -0600 +Subject: [PATCH 18/19] mb/dell/e6400: Enable 01.0 device in devicetree for + dGPU models + +Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/e6400/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb +index bb954cbd7b..e9f3915d17 100644 +--- a/src/mainboard/dell/e6400/devicetree.cb ++++ b/src/mainboard/dell/e6400/devicetree.cb +@@ -19,7 +19,7 @@ chip northbridge/intel/gm45 + ops gm45_pci_domain_ops + + device pci 00.0 on end # host bridge +- device pci 01.0 off end ++ device pci 01.0 on end + device pci 02.0 on end # VGA + device pci 02.1 on end # Display + device pci 03.0 on end # ME +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch new file mode 100644 index 00000000..85bf47a1 --- /dev/null +++ b/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -0,0 +1,39 @@ +From eb0fa411af62bf33cac69f3ba082e2d513bd9ab2 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Fri, 12 May 2023 19:55:15 -0600 +Subject: [PATCH 19/19] Remove warning for coreboot images built without a + payload + +I added this in upstream to prevent people from accidentally flashing +roms without a payload resulting in a no boot situation, but in +libreboot lbmk handles the payload and thus this warning always comes +up. This has caused confusion and concern so just patch it out. +--- + payloads/Makefile.inc | 13 +------------ + 1 file changed, 1 insertion(+), 12 deletions(-) + +diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc +index e735443a76..4f1692a873 100644 +--- a/payloads/Makefile.inc ++++ b/payloads/Makefile.inc +@@ -49,16 +49,5 @@ distclean-payloads: + print-repo-info-payloads: + -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) + +-ifeq ($(CONFIG_PAYLOAD_NONE),y) +-files_added:: warn_no_payload +-endif +- +-warn_no_payload: +- printf "\n\t** WARNING **\n" +- printf "coreboot has been built without a payload. Writing\n" +- printf "a coreboot image without a payload to your board's\n" +- printf "flash chip will result in a non-booting system. You\n" +- printf "can use cbfstool to add a payload to the image.\n\n" +- + .PHONY: force-payload coreinfo nvramcui +-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload ++.PHONY: clean-payloads distclean-payloads print-repo-info-payloads +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0020-hp8300usdt-enable-mSATA.patch b/config/coreboot/default/patches/0020-hp8300usdt-enable-mSATA.patch new file mode 100644 index 00000000..22e06c98 --- /dev/null +++ b/config/coreboot/default/patches/0020-hp8300usdt-enable-mSATA.patch @@ -0,0 +1,32 @@ +From 19ebc65d2c5854d9dea6f4a710ebfa695c80f030 Mon Sep 17 00:00:00 2001 +From: Riku Viitanen <riku.viitanen@protonmail.com> +Date: Tue, 22 Aug 2023 20:07:22 +0300 +Subject: [PATCH] mb/hp8300usdt: enable mSATA + +Enables the mSATA slot on HP Compaq Elite 8300 USDT. +Tested, it works at the same speed as vendor FW (3Gb/s). + +Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> +--- + src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb +index ba4ac6d7f2..f7f321fc83 100644 +--- a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb ++++ b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb +@@ -9,9 +9,9 @@ chip northbridge/intel/sandybridge + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" +- register "sata_port_map" = "0x3" # 0x1: 2.5" slot ++ register "sata_port_map" = "0x7" # 0x1: 2.5" slot + # 0x2: DVD +- # 0x?: mSATA ++ # 0x4: mSATA + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" +-- +2.41.0 + diff --git a/config/coreboot/default/patches/0021-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch b/config/coreboot/default/patches/0021-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch new file mode 100644 index 00000000..f3dad1e1 --- /dev/null +++ b/config/coreboot/default/patches/0021-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch @@ -0,0 +1,61 @@ +From f4c41a930b777128bd418cbae525ba509e5f19ff Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Sun, 27 Aug 2023 17:36:36 -0600 +Subject: [PATCH 1/3] ec/dell/mec5035: Add command to enable/disable radios + +These were determined by sniffing the LPC bus while toggling the +hardware wireless switch on the Latitude E6400. To differentiate devices +options in the vendor BIOS to change which radios the switch controlled +were used. + +Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/ec/dell/mec5035/mec5035.c | 9 +++++++++ + src/ec/dell/mec5035/mec5035.h | 8 ++++++++ + 2 files changed, 17 insertions(+) + +diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c +index 8da11e5b1c..e0335a4635 100644 +--- a/src/ec/dell/mec5035/mec5035.c ++++ b/src/ec/dell/mec5035/mec5035.c +@@ -84,6 +84,15 @@ u8 mec5035_mouse_touchpad(u8 setting) + return buf[0]; + } + ++void mec5035_radio_enable(enum mec5035_radio_dev dev, u8 on) ++{ ++ /* From LPC traces and userspace testing with other values, ++ the second byte has to be 2 for an unknown reason. */ ++ u8 buf[3] = {dev, 2, on}; ++ write_mailbox_regs(buf, 2, 3); ++ ec_command(CMD_RADIO_EN); ++} ++ + void mec5035_early_init(void) + { + /* If this isn't sent the EC shuts down the system after about 15 +diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h +index e7a05b64d4..16512e2cc2 100644 +--- a/src/ec/dell/mec5035/mec5035.h ++++ b/src/ec/dell/mec5035/mec5035.h +@@ -16,8 +16,16 @@ + + #define CMD_CPU_OK 0xc2 + ++#define CMD_RADIO_EN 0x2b ++enum mec5035_radio_dev { ++ RADIO_WLAN = 0, ++ RADIO_WWAN = 1, ++ RADIO_WPAN = 2, ++}; ++ + u8 mec5035_mouse_touchpad(u8 setting); + void mec5035_cpu_ok(void); + void mec5035_early_init(void); ++void mec5035_radio_enable(enum mec5035_radio_dev device, u8 on); + + #endif /* _EC_DELL_MEC5035_H_ */ +-- +2.42.0 + diff --git a/config/coreboot/default/patches/0022-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch b/config/coreboot/default/patches/0022-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch new file mode 100644 index 00000000..48fda76b --- /dev/null +++ b/config/coreboot/default/patches/0022-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch @@ -0,0 +1,37 @@ +From 1b607998e3e7054ce1107ba6af48902f6b6ffb02 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Sun, 27 Aug 2023 19:15:37 -0600 +Subject: [PATCH 2/3] ec/dell/mec5035: Hook up radio enables to option API + +Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/ec/dell/mec5035/mec5035.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c +index e0335a4635..20a33cc0ad 100644 +--- a/src/ec/dell/mec5035/mec5035.c ++++ b/src/ec/dell/mec5035/mec5035.c +@@ -4,6 +4,7 @@ + #include <console/console.h> + #include <device/device.h> + #include <device/pnp.h> ++#include <option.h> + #include <pc80/keyboard.h> + #include <stdint.h> + #include "mec5035.h" +@@ -108,6 +109,10 @@ static void mec5035_init(struct device *dev) + mec5035_mouse_touchpad(TP_PS2_MOUSE); + + pc_keyboard_init(NO_AUX_DEVICE); ++ ++ mec5035_radio_enable(RADIO_WLAN, get_uint_option("wlan", 1)); ++ mec5035_radio_enable(RADIO_WWAN, get_uint_option("wwan", 1)); ++ mec5035_radio_enable(RADIO_WPAN, get_uint_option("bluetooth", 1)); + } + + static struct device_operations ops = { +-- +2.42.0 + diff --git a/config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch b/config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch new file mode 100644 index 00000000..be3d1189 --- /dev/null +++ b/config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch @@ -0,0 +1,820 @@ +From e4e508c3375d38c434678a2e0652b55e7ea79fc5 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Sat, 19 Aug 2023 16:19:10 -0600 +Subject: [PATCH 3/3] mb/dell: Add Latitude E6430 (Ivy Bridge) + +Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested. +This is based on the autoport output with some manual tweaks. The flash +is 8MiB + 4MiB, and is fairly easily accessed by removing the keyboard. +It can also be internally flashed by sending a command to the EC, which +causes the EC to pull the FDO pin low and the firmware to skip setting +up any chipset based write protections. [1] The EC is the SMSC MEC5055, +which seems to be compatible with the existing MEC5035 code. + +Working: +- Libgfxinit +- USB EHCI debug (left side usb port is HCD index 2, middle port on the + right side is HCD index 1) +- Keyboard +- Touchpad/trackpoint +- ExpressCard +- Audio +- Ethernet +- SD card reader +- mPCIe WiFi +- SeaBIOS 1.16.2 +- edk2 (MrChromebox' fork, uefipayload_202306) +- Internal flashing + +Not working: +- S3 suspend: It seems like the EC also controls the DRAM reset gate so + there may be a command that needs to be implemented for this +- Physical Wireless switch +- Battery reporting +- Brightness hotkeys + +Unknown/untested: +- Dock +- eSATA +- TPM +- dGPU on non-UMA model + +[1] https://github.com/nic3-14159/e6400-flash-unlock + +Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/e6430/Kconfig | 36 ++++ + src/mainboard/dell/e6430/Kconfig.name | 2 + + src/mainboard/dell/e6430/Makefile.inc | 6 + + src/mainboard/dell/e6430/acpi/ec.asl | 9 + + src/mainboard/dell/e6430/acpi/platform.asl | 12 ++ + src/mainboard/dell/e6430/acpi/superio.asl | 3 + + src/mainboard/dell/e6430/acpi_tables.c | 16 ++ + src/mainboard/dell/e6430/board_info.txt | 6 + + src/mainboard/dell/e6430/cmos.default | 9 + + src/mainboard/dell/e6430/cmos.layout | 88 ++++++++++ + src/mainboard/dell/e6430/data.vbt | Bin 0 -> 6144 bytes + src/mainboard/dell/e6430/devicetree.cb | 68 ++++++++ + src/mainboard/dell/e6430/dsdt.asl | 30 ++++ + src/mainboard/dell/e6430/early_init.c | 38 ++++ + src/mainboard/dell/e6430/gma-mainboard.ads | 20 +++ + src/mainboard/dell/e6430/gpio.c | 192 +++++++++++++++++++++ + src/mainboard/dell/e6430/hda_verb.c | 33 ++++ + src/mainboard/dell/e6430/mainboard.c | 21 +++ + 18 files changed, 589 insertions(+) + create mode 100644 src/mainboard/dell/e6430/Kconfig + create mode 100644 src/mainboard/dell/e6430/Kconfig.name + create mode 100644 src/mainboard/dell/e6430/Makefile.inc + create mode 100644 src/mainboard/dell/e6430/acpi/ec.asl + create mode 100644 src/mainboard/dell/e6430/acpi/platform.asl + create mode 100644 src/mainboard/dell/e6430/acpi/superio.asl + create mode 100644 src/mainboard/dell/e6430/acpi_tables.c + create mode 100644 src/mainboard/dell/e6430/board_info.txt + create mode 100644 src/mainboard/dell/e6430/cmos.default + create mode 100644 src/mainboard/dell/e6430/cmos.layout + create mode 100644 src/mainboard/dell/e6430/data.vbt + create mode 100644 src/mainboard/dell/e6430/devicetree.cb + create mode 100644 src/mainboard/dell/e6430/dsdt.asl + create mode 100644 src/mainboard/dell/e6430/early_init.c + create mode 100644 src/mainboard/dell/e6430/gma-mainboard.ads + create mode 100644 src/mainboard/dell/e6430/gpio.c + create mode 100644 src/mainboard/dell/e6430/hda_verb.c + create mode 100644 src/mainboard/dell/e6430/mainboard.c + +diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig +new file mode 100644 +index 0000000000..3178d12aff +--- /dev/null ++++ b/src/mainboard/dell/e6430/Kconfig +@@ -0,0 +1,36 @@ ++if BOARD_DELL_LATITUDE_E6430 ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ select BOARD_ROMSIZE_KB_12288 ++ select EC_ACPI ++ select EC_DELL_MEC5035 ++ select GFX_GMA_PANEL_1_ON_LVDS ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ select INTEL_INT15 ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select NORTHBRIDGE_INTEL_SANDYBRIDGE ++ select SERIRQ_CONTINUOUS_MODE ++ select SOUTHBRIDGE_INTEL_C216 ++ select SYSTEM_TYPE_LAPTOP ++ select USE_NATIVE_RAMINIT ++ ++config MAINBOARD_DIR ++ default "dell/e6430" ++ ++config MAINBOARD_PART_NUMBER ++ default "Latitude E6430" ++ ++config VGA_BIOS_ID ++ default "8086,0166" ++ ++config DRAM_RESET_GATE_GPIO ++ default 60 ++ ++config USBDEBUG_HCD_INDEX ++ default 2 ++endif +diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name +new file mode 100644 +index 0000000000..f866b03585 +--- /dev/null ++++ b/src/mainboard/dell/e6430/Kconfig.name +@@ -0,0 +1,2 @@ ++config BOARD_DELL_LATITUDE_E6430 ++ bool "Latitude E6430" +diff --git a/src/mainboard/dell/e6430/Makefile.inc b/src/mainboard/dell/e6430/Makefile.inc +new file mode 100644 +index 0000000000..ba64e93eb8 +--- /dev/null ++++ b/src/mainboard/dell/e6430/Makefile.inc +@@ -0,0 +1,6 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++bootblock-y += early_init.c ++bootblock-y += gpio.c ++romstage-y += early_init.c ++romstage-y += gpio.c ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +diff --git a/src/mainboard/dell/e6430/acpi/ec.asl b/src/mainboard/dell/e6430/acpi/ec.asl +new file mode 100644 +index 0000000000..0d429410a9 +--- /dev/null ++++ b/src/mainboard/dell/e6430/acpi/ec.asl +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++Device(EC) ++{ ++ Name (_HID, EISAID("PNP0C09")) ++ Name (_UID, 0) ++ Name (_GPE, 16) ++/* FIXME: EC support */ ++} +diff --git a/src/mainboard/dell/e6430/acpi/platform.asl b/src/mainboard/dell/e6430/acpi/platform.asl +new file mode 100644 +index 0000000000..2d24bbd9b9 +--- /dev/null ++++ b/src/mainboard/dell/e6430/acpi/platform.asl +@@ -0,0 +1,12 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++Method(_WAK, 1) ++{ ++ /* FIXME: EC support */ ++ Return(Package() {0, 0}) ++} ++ ++Method(_PTS,1) ++{ ++ /* FIXME: EC support */ ++} +diff --git a/src/mainboard/dell/e6430/acpi/superio.asl b/src/mainboard/dell/e6430/acpi/superio.asl +new file mode 100644 +index 0000000000..55b1db5b11 +--- /dev/null ++++ b/src/mainboard/dell/e6430/acpi/superio.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <drivers/pc80/pc/ps2_controller.asl> +diff --git a/src/mainboard/dell/e6430/acpi_tables.c b/src/mainboard/dell/e6430/acpi_tables.c +new file mode 100644 +index 0000000000..e2759659bf +--- /dev/null ++++ b/src/mainboard/dell/e6430/acpi_tables.c +@@ -0,0 +1,16 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <acpi/acpi_gnvs.h> ++#include <soc/nvs.h> ++ ++/* FIXME: check this function. */ ++void mainboard_fill_gnvs(struct global_nvs *gnvs) ++{ ++ /* The lid is open by default. */ ++ gnvs->lids = 1; ++ ++ /* Temperature at which OS will shutdown */ ++ gnvs->tcrt = 100; ++ /* Temperature at which OS will throttle CPU */ ++ gnvs->tpsv = 90; ++} +diff --git a/src/mainboard/dell/e6430/board_info.txt b/src/mainboard/dell/e6430/board_info.txt +new file mode 100644 +index 0000000000..4601a4aaba +--- /dev/null ++++ b/src/mainboard/dell/e6430/board_info.txt +@@ -0,0 +1,6 @@ ++Category: laptop ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y ++Release year: 2012 +diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default +new file mode 100644 +index 0000000000..2a5b30f2b7 +--- /dev/null ++++ b/src/mainboard/dell/e6430/cmos.default +@@ -0,0 +1,9 @@ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Disable ++nmi=Enable ++bluetooth=Enable ++wwan=Enable ++wlan=Enable ++sata_mode=AHCI ++me_state=Normal +diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout +new file mode 100644 +index 0000000000..e85ea4c661 +--- /dev/null ++++ b/src/mainboard/dell/e6430/cmos.layout +@@ -0,0 +1,88 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++ ++#400 8 r 0 reserved for century byte ++ ++# coreboot config options: southbridge ++408 1 e 1 nmi ++409 2 e 7 power_on_after_fail ++411 1 e 9 sata_mode ++ ++# coreboot config options: EC ++412 1 e 1 bluetooth ++413 1 e 1 wwan ++415 1 e 1 wlan ++ ++# coreboot config options: ME ++424 1 e 14 me_state ++425 2 h 0 me_state_prev ++ ++# coreboot config options: northbridge ++432 3 e 11 gfx_uma_size ++435 2 e 12 hybrid_graphics_mode ++440 8 h 0 volume ++ ++# VBOOT ++448 128 r 0 vbnv ++ ++# SandyBridge MRC Scrambler Seed values ++896 32 r 0 mrc_scrambler_seed ++928 32 r 0 mrc_scrambler_seed_s3 ++960 16 r 0 mrc_scrambler_seed_chk ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++2 0 Enable ++2 1 Disable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 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b/src/mainboard/dell/e6430/devicetree.cb +@@ -0,0 +1,68 @@ ++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. ++ register "gfx" = "GMA_STATIC_DISPLAYS(1)" ++ register "gpu_cpu_backlight" = "0x00001312" ++ register "gpu_dp_b_hotplug" = "4" ++ register "gpu_dp_c_hotplug" = "4" ++ register "gpu_dp_d_hotplug" = "4" ++ register "gpu_panel_port_select" = "0" ++ register "gpu_panel_power_backlight_off_delay" = "2300" ++ register "gpu_panel_power_backlight_on_delay" = "2300" ++ register "gpu_panel_power_cycle_delay" = "6" ++ register "gpu_panel_power_down_delay" = "400" ++ register "gpu_panel_power_up_delay" = "400" ++ register "gpu_pch_backlight" = "0x13121312" ++ ++ device domain 0x0 on ++ subsystemid 0x1028 0x0534 inherit ++ ++ device ref host_bridge on end # Host bridge ++ device ref peg10 off end # PEG ++ device ref igd on end # iGPU ++ ++ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH ++ register "docking_supported" = "1" ++ register "gen1_dec" = "0x007c0681" ++ register "gen2_dec" = "0x005c0921" ++ register "gen3_dec" = "0x003c07e1" ++ register "gen4_dec" = "0x007c0901" ++ register "gpi0_routing" = "2" ++ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }" ++ register "pcie_port_coalesce" = "1" ++ register "sata_interface_speed_support" = "0x3" ++ register "sata_port_map" = "0x33" ++ register "spi_lvscc" = "0x2005" ++ register "spi_uvscc" = "0x2005" ++ register "superspeed_capable_ports" = "0x0000000f" ++ register "xhci_overcurrent_mapping" = "0x00000c03" ++ register "xhci_switchable_ports" = "0x0000000f" ++ ++ device ref xhci on end # USB 3.0 Controller ++ device ref mei1 on end # Management Engine Interface 1 ++ device ref mei2 off end # Management Engine Interface 2 ++ device ref me_ide_r off end # Management Engine IDE-R ++ device ref me_kt on end # Management Engine KT ++ device ref gbe on end # Intel Gigabit Ethernet ++ device ref ehci2 on end # USB2 EHCI #2 ++ device ref hda on end # High Definition Audio ++ device ref pcie_rp1 on end # PCIe Port #1 ++ device ref pcie_rp2 on end # PCIe Port #2 ++ device ref pcie_rp3 on end # PCIe Port #3 ++ device ref pcie_rp4 on end # PCIe Port #4 ++ device ref pcie_rp5 off end # PCIe Port #5 ++ device ref pcie_rp6 on end # PCIe Port #6 ++ device ref pcie_rp7 off end # PCIe Port #7 ++ device ref pcie_rp8 off end # PCIe Port #8 ++ device ref ehci1 on end # USB2 EHCI #1 ++ device ref pci_bridge off end # PCI bridge ++ device ref lpc on # LPC bridge ++ chip ec/dell/mec5035 ++ device pnp ff.0 on end ++ end ++ end ++ device ref sata1 on end # SATA Controller 1 ++ device ref smbus on end # SMBus ++ device ref sata2 off end # SATA Controller 2 ++ device ref thermal off end # Thermal ++ end ++ end ++end +diff --git a/src/mainboard/dell/e6430/dsdt.asl b/src/mainboard/dell/e6430/dsdt.asl +new file mode 100644 +index 0000000000..7d13c55b08 +--- /dev/null ++++ b/src/mainboard/dell/e6430/dsdt.asl +@@ -0,0 +1,30 @@ ++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB ++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++ ++#include <acpi/acpi.h> ++ ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20141018 /* OEM revision */ ++) ++{ ++ #include <acpi/dsdt_top.asl> ++ #include "acpi/platform.asl" ++ #include <cpu/intel/common/acpi/cpu.asl> ++ #include <southbridge/intel/common/acpi/platform.asl> ++ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> ++ #include <southbridge/intel/common/acpi/sleepstates.asl> ++ ++ Device (\_SB.PCI0) ++ { ++ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> ++ #include <drivers/intel/gma/acpi/default_brightness_levels.asl> ++ #include <southbridge/intel/bd82x6x/acpi/pch.asl> ++ } ++} +diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c +new file mode 100644 +index 0000000000..7944157f59 +--- /dev/null ++++ b/src/mainboard/dell/e6430/early_init.c +@@ -0,0 +1,38 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++ ++#include <bootblock_common.h> ++#include <device/pci_ops.h> ++#include <ec/dell/mec5035/mec5035.h> ++#include <northbridge/intel/sandybridge/raminit_native.h> ++#include <southbridge/intel/bd82x6x/pch.h> ++ ++const struct southbridge_usb_port mainboard_usb_ports[] = { ++ { 1, 1, 0 }, ++ { 1, 1, 0 }, ++ { 1, 1, 1 }, ++ { 1, 1, 1 }, ++ { 1, 0, 2 }, ++ { 1, 1, 2 }, ++ { 1, 1, 3 }, ++ { 1, 1, 3 }, ++ { 1, 1, 4 }, ++ { 1, 1, 4 }, ++ { 1, 1, 5 }, ++ { 1, 1, 5 }, ++ { 1, 2, 6 }, ++ { 1, 2, 6 }, ++}; ++ ++void bootblock_mainboard_early_init(void) ++{ ++ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f); ++ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); ++ mec5035_early_init(); ++} ++ ++void mainboard_get_spd(spd_raw_data *spd, bool id_only) ++{ ++ read_spd(&spd[0], 0x50, id_only); ++ read_spd(&spd[2], 0x52, id_only); ++} +diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads +new file mode 100644 +index 0000000000..1310830c8e +--- /dev/null ++++ b/src/mainboard/dell/e6430/gma-mainboard.ads +@@ -0,0 +1,20 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ ( ++ HDMI1, -- mainboard HDMI ++ DP2, -- dock DP ++ DP3, -- dock DP ++ Analog, --mainboard VGA ++ LVDS, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/e6430/gpio.c b/src/mainboard/dell/e6430/gpio.c +new file mode 100644 +index 0000000000..777570765a +--- /dev/null ++++ b/src/mainboard/dell/e6430/gpio.c +@@ -0,0 +1,192 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_GPIO, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_NATIVE, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio1 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio28 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++ .gpio30 = GPIO_RESET_RSMRST, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio0 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++ .gpio13 = GPIO_INVERT, ++ .gpio14 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_GPIO, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_NATIVE, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_OUTPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio45 = GPIO_DIR_OUTPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_INPUT, ++ .gpio51 = GPIO_DIR_INPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio34 = GPIO_LEVEL_HIGH, ++ .gpio45 = GPIO_LEVEL_LOW, ++ .gpio60 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_GPIO, ++ .gpio69 = GPIO_MODE_GPIO, ++ .gpio70 = GPIO_MODE_GPIO, ++ .gpio71 = GPIO_MODE_GPIO, ++ .gpio72 = GPIO_MODE_NATIVE, ++ .gpio73 = GPIO_MODE_NATIVE, ++ .gpio74 = GPIO_MODE_NATIVE, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio68 = GPIO_DIR_INPUT, ++ .gpio69 = GPIO_DIR_INPUT, ++ .gpio70 = GPIO_DIR_INPUT, ++ .gpio71 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/dell/e6430/hda_verb.c b/src/mainboard/dell/e6430/hda_verb.c +new file mode 100644 +index 0000000000..56ada95c58 +--- /dev/null ++++ b/src/mainboard/dell/e6430/hda_verb.c +@@ -0,0 +1,33 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ 0x111d76df, /* Codec Vendor / Device ID: IDT */ ++ 0x10280534, /* Subsystem ID */ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x10280534), ++ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), ++ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), ++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), ++ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), ++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), ++ ++ 0x80862806, /* Codec Vendor / Device ID: Intel */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(3, 0x80860101), ++ AZALIA_PIN_CFG(3, 0x05, 0x18560010), ++ AZALIA_PIN_CFG(3, 0x06, 0x18560020), ++ AZALIA_PIN_CFG(3, 0x07, 0x18560030), ++ ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/e6430/mainboard.c b/src/mainboard/dell/e6430/mainboard.c +new file mode 100644 +index 0000000000..31e49802fc +--- /dev/null ++++ b/src/mainboard/dell/e6430/mainboard.c +@@ -0,0 +1,21 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/device.h> ++#include <drivers/intel/gma/int15.h> ++#include <southbridge/intel/bd82x6x/pch.h> ++#include <ec/acpi/ec.h> ++#include <console/console.h> ++#include <pc80/keyboard.h> ++ ++static void mainboard_enable(struct device *dev) ++{ ++ ++ /* FIXME: fix these values. */ ++ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, ++ GMA_INT15_PANEL_FIT_DEFAULT, ++ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); ++} ++ ++struct chip_operations mainboard_ops = { ++ .enable_dev = mainboard_enable, ++}; +-- +2.42.0 + |