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authorLeah Rowe <leah@libreboot.org>2024-01-25 15:24:02 +0000
committerLeah Rowe <leah@libreboot.org>2024-01-25 15:41:15 +0000
commit4a6dc5553f2a15542f730ca735fb8bf95fb8f49b (patch)
tree2cd281908a37816a526a0b6deab51376fec9cf69 /config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch
parentece5463109721347c2008b7791907ac4d6825588 (diff)
coreboot/default: update coreboot to January 2024
Base revision changed to: commit b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a Author: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Date: Fri Jan 5 16:48:17 2024 +0800 mb/google/dedede/var/metaknight:Add fw_config probe for multi codec and amplifier Of note: Several out-of-tree ports have been adjusted to use the new SPD config style, where it is defined in devicetree. I manually updated the E6530 patch myself, based on the update that Nicholas did on E6430 (Nicholas will later update the E6530 patch himself, and I'll re-merge the patch). Several upstream patches now exist in this revision, that we were able to remove from lbmk. The heap size patch was reverted upstream, as we did, but see: https://review.coreboot.org/c/coreboot/+/80023 https://review.coreboot.org/c/coreboot/+/79525 Although we still disable the TSEG Stage Cache, ivy/sandy/haswell should be reliable on S3 now (leaving TSEG Stage Cache disabled, for now, anyway). Also included in upstream now: commit 29030d0f3dad2ec6b86000dfe2c8e951ae80bf94 Author: Bill Xie <persmule@hardenedlinux.org> Date: Sat Oct 7 01:32:51 2023 +0800 drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume Further patches from upstream: commit 432e92688eca0e85cbaebca3232f65936b305a98 Author: Bill Xie <persmule@hardenedlinux.org> Date: Fri Nov 3 12:34:01 2023 +0800 drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum This should fix S3 on GM45 thinkpads. Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch')
-rw-r--r--config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch54
1 files changed, 54 insertions, 0 deletions
diff --git a/config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch b/config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch
new file mode 100644
index 00000000..fa7ab40d
--- /dev/null
+++ b/config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch
@@ -0,0 +1,54 @@
+From 8705b719573d2159adde10af9c6a4d8806b7d27b Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Thu, 25 Jan 2024 14:37:30 +0000
+Subject: [PATCH 28/30] dell/e6*30: disable the ME device in devicetree
+
+we neuter anyway. disabling it in devicetree will prevent linux
+from ever trying to use it or load a driver for it, and thus
+might prevent benign error messages from appearing in dmesg.
+
+this change was suggested by nicholas when asked on irc.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ src/mainboard/dell/e6430/devicetree.cb | 4 ++--
+ src/mainboard/dell/e6530/devicetree.cb | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
+index 054b01c5ac..2b8574c984 100644
+--- a/src/mainboard/dell/e6430/devicetree.cb
++++ b/src/mainboard/dell/e6430/devicetree.cb
+@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device ref xhci on end
+- device ref mei1 on end
++ device ref mei1 off end
+ device ref mei2 off end
+ device ref me_ide_r off end
+- device ref me_kt on end
++ device ref me_kt off end
+ device ref gbe on end
+ device ref ehci2 on end
+ device ref hda on end
+diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
+index 37135bcf0f..010200bb6d 100644
+--- a/src/mainboard/dell/e6530/devicetree.cb
++++ b/src/mainboard/dell/e6530/devicetree.cb
+@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device ref xhci on end # USB 3.0 Controller
+- device ref mei1 on end # Management Engine Interface 1
++ device ref mei1 off end # Management Engine Interface 1
+ device ref mei2 off end # Management Engine Interface 2
+ device ref me_ide_r off end # Management Engine IDE-R
+- device ref me_kt on end # Management Engine KT
++ device ref me_kt off end # Management Engine KT
+ device ref gbe on end # Intel Gigabit Ethernet
+ device ref ehci2 on end # USB2 EHCI #2
+ device ref hda on end # High Definition Audio
+--
+2.39.2
+