coreboot/default: Re-base all patches

There were a lot of unnecessary patches, such as the VRAM
patches; as Nicholas Chin has explained to me, the drivers
for these machines will just allocate what RAM they want
anyway, so in a lot of cases the extra allocated Video RAM
simply reduces the total amount of memory for other uses.

In general, we have a lot of patches that have existed for
years. A much more aggressive sweep will be done in the next
major audit, especially when the revisions are updated again.

Signed-off-by: Leah Rowe <leah@libreboot.org>

1 files changed, 0 insertions, 449 deletions

diff --git a/config/coreboot/default/patches/0021-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch b/config/coreboot/default/patches/0021-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch
deleted file mode 100644
index 9c210c8c..00000000
--- a/config/coreboot/default/patches/0021-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch
+++ /dev/null
@@ -1,449 +0,0 @@
-From 73313e682ba8808f8db6259ac7d93f54c11cb884 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Wed, 31 Jan 2024 22:07:25 -0700
-Subject: [PATCH 21/65] mb/dell: Add Latitude E6520 (Sandy Bridge)
-
-Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was
-not tested. I do not physically have this system; someone with physical
-access to one sent me the output of autoport which I then modified to
-produce this port. I was also sent the VBT binary, which was obtained
-from `/sys/kernel/debug/dri/0/i915_vbt` while running version A08 of the
-vendor firmware.
-
-This was originally tested and found to be working as a standalone board
-port in Libreboot, but this variant based port in upstream coreboot has
-not been tested.
-
-This can be internally flashed by sending a command to the EC, which
-causes the EC to pull the FDO pin low and the firmware to skip setting
-up any chipset based write protections [1]. The EC is the SMSC MEC5055,
-which seems to be compatible with the existing MEC5035 code.
-
-[1] https://gitlab.com/nic3-14159/dell-flash-unlock
-
-Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/snb_ivb_latitude/Kconfig   |   9 +
- .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
- .../snb_ivb_latitude/variants/e6520/data.vbt  | Bin 0 -> 6144 bytes
- .../variants/e6520/early_init.c               |  31 +++
- .../snb_ivb_latitude/variants/e6520/gpio.c    | 190 ++++++++++++++++++
- .../variants/e6520/hda_verb.c                 |  32 +++
- .../variants/e6520/overridetree.cb            |  35 ++++
- 7 files changed, 300 insertions(+)
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-index d2786970ee..72bdc96c0a 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-@@ -23,6 +23,12 @@ config BOARD_DELL_LATITUDE_E6420
- 	select MAINBOARD_USES_IFD_GBE_REGION
- 	select SOUTHBRIDGE_INTEL_BD82X6X
- 
-+config BOARD_DELL_LATITUDE_E6520
-+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
-+	select BOARD_ROMSIZE_KB_10240
-+	select MAINBOARD_USES_IFD_GBE_REGION
-+	select SOUTHBRIDGE_INTEL_BD82X6X
-+
- config BOARD_DELL_LATITUDE_E5530
- 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- 	select BOARD_ROMSIZE_KB_12288
-@@ -50,6 +56,7 @@ config MAINBOARD_DIR
- 
- config MAINBOARD_PART_NUMBER
- 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
-+	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
- 	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
- 	default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
- 	default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
-@@ -62,11 +69,13 @@ config USBDEBUG_HCD_INDEX
- 
- config VARIANT_DIR
- 	default "e6420" if BOARD_DELL_LATITUDE_E6420
-+	default "e6520" if BOARD_DELL_LATITUDE_E6520
- 	default "e5530" if BOARD_DELL_LATITUDE_E5530
- 	default "e6430" if BOARD_DELL_LATITUDE_E6430
- 	default "e6530" if BOARD_DELL_LATITUDE_E6530
- 
- config VGA_BIOS_ID
-+	default "8086,0116" if BOARD_DELL_LATITUDE_E6520
- 	default "8086,0166" if BOARD_DELL_LATITUDE_E5530
- 	default "8086,0126" if BOARD_DELL_LATITUDE_E6420
- 	default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-index 257d428a70..c7665ac263 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-@@ -3,6 +3,9 @@
- config BOARD_DELL_LATITUDE_E6420
- 	bool "Latitude E6420"
- 
-+config BOARD_DELL_LATITUDE_E6520
-+	bool "Latitude E6520"
-+
- config BOARD_DELL_LATITUDE_E5530
- 	bool "Latitude E5530"
- 
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..0ef16ee7cb482d2cb91ea80c3f419759355f7ba0
-GIT binary patch
-literal 6144
-zcmeHKZ){Ul6hE);wSB#PZ|mL$bQ^!}HW(eF@H)0JafGfbqsZ9G21{L7Sg{or$5uN)
-z_QgG55e!O(8p8*oBhhF`l$n^QF%rN;rzFNqqcPzFCd5QSB1Y7RKt1=pmTk1aFo9^Y
-z+x+gi_nvdlJ@?#m&wZWW=G#bH>ze$J`&!oe*Q|E0r!)d89LYY8b$aowZEoG-uiIF+
-z#n;$ezm6V<nGnvtc?lrGaf)1_);!W0?uqnojdw-1MQM|dwy`OcF?M@A)KgVV*N2}7
-zcXx+--0R}IwzW3-+`f2k?^Av5V7MpRO-q(9rn_R1@Xlz2Ztdy`$Gf6^w6~|bKi!!7
-z9;xq*^~bxmZQn^<^<`+2s=BdSM%VW2#FguN<FO^QuDhGIFquBu677q|cSj>jWFixQ
-z)4V8f0Gt`D`+>9Fr~tnJ76EJ`5D_F1cn-`0$RgN9unI6kfYkzIiO?W`ON4+34lv1_
-zNdPDkq1cf$p8^EW;TS*O$CdzNo#1fbIG_Oi0T(ti0jwyt0le_p_HlvX^CFvr)>$b>
-zO-z8^CSU`w=mIK7Q)@9fR;XUzrFu{T=rRyygIZBpU9+Or>+?4R9%~G?Y-|g)Z`Sti
-z+do(U*Wb-xR~DzjS<75#=Us4sH^C9U2FCbND7L7u$>M|<;t=AnRfI9C0v8c~AVg7t
-zIU<3D2oK^>L;%r(*o=4*u?Mja@dDyi#4zFn;(f#^#3*76aUSs#;tJv#La-6YLRdQB
-zdcvfERkvH?k~GJlfM<HR476j(@nfm+47<!Ult@^ua5M3h6A}q=C0ognX9aX4mxq)U
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-z-jp>o1ffJNommZ4?=TIPlePIw0hgQ706f*tBC`#pg>9&zRHe>J2%RxBTrOc6Adh9E
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-O?SW|zOncy=dEg(6JAK&z
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c
-new file mode 100644
-index 0000000000..b6415a428b
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c
-@@ -0,0 +1,31 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+const struct southbridge_usb_port mainboard_usb_ports[] = {
-+	{ 1, 1, 0 },
-+	{ 1, 1, 0 },
-+	{ 1, 1, 1 },
-+	{ 1, 1, 1 },
-+	{ 1, 0, 2 },
-+	{ 1, 1, 2 },
-+	{ 1, 0, 3 },
-+	{ 1, 0, 3 },
-+	{ 1, 1, 5 },
-+	{ 1, 1, 5 },
-+	{ 1, 1, 7 },
-+	{ 1, 1, 6 },
-+	{ 1, 0, 6 },
-+	{ 1, 0, 7 },
-+};
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c
-new file mode 100644
-index 0000000000..61f01816c4
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c
-@@ -0,0 +1,190 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_NATIVE,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_NATIVE,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_GPIO,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_INPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+	.gpio30 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio30 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_GPIO,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_NATIVE,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio45 = GPIO_DIR_OUTPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_OUTPUT,
-+	.gpio51 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio34 = GPIO_LEVEL_HIGH,
-+	.gpio45 = GPIO_LEVEL_LOW,
-+	.gpio49 = GPIO_LEVEL_LOW,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_GPIO,
-+	.gpio69 = GPIO_MODE_GPIO,
-+	.gpio70 = GPIO_MODE_GPIO,
-+	.gpio71 = GPIO_MODE_GPIO,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_NATIVE,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio68 = GPIO_DIR_INPUT,
-+	.gpio69 = GPIO_DIR_INPUT,
-+	.gpio70 = GPIO_DIR_INPUT,
-+	.gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c
-new file mode 100644
-index 0000000000..ae376691e7
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
-+	0x10280494,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x10280494),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0x400000f2),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+	0x80862805,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb
-new file mode 100644
-index 0000000000..f90f2dee1f
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb
-@@ -0,0 +1,35 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/sandybridge
-+	device domain 0 on
-+		subsystemid 0x1028 0x0494 inherit
-+
-+		device ref igd on
-+			register "gpu_cpu_backlight" = "0x00001312"
-+			register "gpu_pch_backlight" = "0x13121312"
-+		end
-+
-+		chip southbridge/intel/bd82x6x
-+			register "usb_port_config" = "{
-+				{ 1, 1, 0 },
-+				{ 1, 1, 0 },
-+				{ 1, 1, 1 },
-+				{ 1, 1, 1 },
-+				{ 1, 0, 2 },
-+				{ 1, 1, 2 },
-+				{ 1, 1, 3 },
-+				{ 1, 1, 3 },
-+				{ 1, 1, 5 },
-+				{ 1, 1, 5 },
-+				{ 1, 1, 7 },
-+				{ 1, 1, 6 },
-+				{ 1, 0, 6 },
-+				{ 1, 0, 7 },
-+			}"
-+
-+			device ref sata1 on
-+				register "sata_port_map" = "0x3b"
-+			end
-+		end
-+	end
-+end
--- 
-2.39.5
-