coreboot/default: Re-base all patches

There were a lot of unnecessary patches, such as the VRAM
patches; as Nicholas Chin has explained to me, the drivers
for these machines will just allocate what RAM they want
anyway, so in a lot of cases the extra allocated Video RAM
simply reduces the total amount of memory for other uses.

In general, we have a lot of patches that have existed for
years. A much more aggressive sweep will be done in the next
major audit, especially when the revisions are updated again.

Signed-off-by: Leah Rowe <leah@libreboot.org>

1 files changed, 440 insertions, 0 deletions

diff --git a/config/coreboot/default/patches/0017-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch b/config/coreboot/default/patches/0017-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch
new file mode 100644
index 00000000..412b8471
--- /dev/null
+++ b/config/coreboot/default/patches/0017-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch
@@ -0,0 +1,440 @@
+From 84d7f3201eb4492acd7d290a02d19c4850c85791 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Thu, 26 Oct 2017 21:26:43 +0800
+Subject: [PATCH 17/51] mb/dell: Add Latitude E6230 (Ivy Bridge)
+
+This was adapted from CB:22693 from Iru Cai, which was based on
+autoport. I do not physically have this system. Someone with physical
+access to an E6230 running version A11 of the vendor firmware sent me
+the VBT after running the command `intelvbttool --inlegacy --outvbt
+data.vbt`. This new version of the port has not yet been tested.
+
+The EC is the SMSC MEC5055, which seems to be compatible with the
+existing MEC5035 code. As with the other Dell systems with this EC, this
+board is assumed to be internally flashable using an EC command that
+tells it to pull the FDO pin low on the next boot, which also tells the
+vendor firmware to disable all write protections to the flash [1].
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Original-Change-Id: I8cdc01e902e670310628809416290045c2102340
+Change-Id: I32927beea7c29b96a851ab77ed15b0160f16d369
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/snb_ivb_latitude/Kconfig   |  11 +-
+ .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
+ .../snb_ivb_latitude/variants/e6230/data.vbt  | Bin 0 -> 4280 bytes
+ .../variants/e6230/early_init.c               |  12 ++
+ .../snb_ivb_latitude/variants/e6230/gpio.c    | 193 ++++++++++++++++++
+ .../variants/e6230/hda_verb.c                 |  32 +++
+ .../variants/e6230/overridetree.cb            |  40 ++++
+ 7 files changed, 290 insertions(+), 1 deletion(-)
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+index 49bf225fe2..f6e097930b 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+@@ -56,6 +56,12 @@ config BOARD_DELL_LATITUDE_E5530
+ 	select BOARD_ROMSIZE_KB_12288
+ 	select SOUTHBRIDGE_INTEL_C216
+ 
++config BOARD_DELL_LATITUDE_E6230
++	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
++	select BOARD_ROMSIZE_KB_12288
++	select MAINBOARD_USES_IFD_GBE_REGION
++	select SOUTHBRIDGE_INTEL_C216
++
+ config BOARD_DELL_LATITUDE_E6330
+ 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ 	select BOARD_ROMSIZE_KB_12288
+@@ -90,6 +96,7 @@ config MAINBOARD_PART_NUMBER
+ 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
+ 	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
++	default "Latitude E6230" if BOARD_DELL_LATITUDE_E6230
+ 	default "Latitude E6330" if BOARD_DELL_LATITUDE_E6330
+ 	default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
+ 	default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
+@@ -108,6 +115,7 @@ config VARIANT_DIR
+ 	default "e6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "e6520" if BOARD_DELL_LATITUDE_E6520
+ 	default "e5530" if BOARD_DELL_LATITUDE_E5530
++	default "e6230" if BOARD_DELL_LATITUDE_E6230
+ 	default "e6330" if BOARD_DELL_LATITUDE_E6330
+ 	default "e6430" if BOARD_DELL_LATITUDE_E6430
+ 	default "e6530" if BOARD_DELL_LATITUDE_E6530
+@@ -121,7 +129,8 @@ config VGA_BIOS_ID
+ 		|| BOARD_DELL_LATITUDE_E5520 \
+ 		|| BOARD_DELL_LATITUDE_E6220 \
+ 		|| BOARD_DELL_LATITUDE_E6320
+-	default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
++	default "8086,0166" if BOARD_DELL_LATITUDE_E6230 \
++		|| BOARD_DELL_LATITUDE_E6430 \
+ 		|| BOARD_DELL_LATITUDE_E6530
+ 
+ endif
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+index d6fc8eb224..cb7bbd5cdb 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
++++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+@@ -21,6 +21,9 @@ config BOARD_DELL_LATITUDE_E6520
+ config BOARD_DELL_LATITUDE_E5530
+ 	bool "Latitude E5530"
+ 
++config BOARD_DELL_LATITUDE_E6230
++	bool "Latitude E6230"
++
+ config BOARD_DELL_LATITUDE_E6330
+ 	bool "Latitude E6330"
+ 
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..45ce8f435eea647a0bddaab3fd1e9282c87afc66
+GIT binary patch
+literal 4280
+zcmdT{Yiu0V75-*tAG5PFyX&zDekA7P<*tbx&o1`j23L%CmvkLWvN7(mLa6alZ?J`9
+zo3#m4YVlG`2;w12Ajppt<qra(R;8*G@uw*8gIcsg2vxi!q_pBkmGUD$s9IGi+jD1T
+zO`Kg43n@JA>~|mMp8L%`XU@4ZyCa_(r`z|Z`bP4p-rEkOMn-R;Ntk#o`b)0sOKRl6
+z?T0eM<HLtiqX*Kr(o5Kc<Iyk90h5ws=!y8i;K=M^X(l$-Eoeyyj>ZS*@LZWP#hD{>
+z<r2jcJ;b8e!oAb;^QB2D#7*krI^IpA=?ra8?xvqj6=&}$QL2a1J(QuD($UfkElf=x
+zUM!UtXmO4PP4h^;&)jWJvd(Pj0lIs7wpgAnE!1!MB1w8~{^#ZCd!`mCmhPs6X_~zW
+zGae^<%aoog&+n$;nHd@rItw&bS}2u|mL_-Ws;&ZOWW_51k`IALAW8pAz~@C!!B)bs
+z1x-OrK~}*8L07Po(5+xZL6I<}phTEf5QRsVJYHa{f^AWEV+2@lvrPVS%snsOn?N)w
+zpKbvwOnk&Q_6Y?aB;r1=!TYwts;yA@BnbFfECo!7JVJq7g^yhYMUV;wlBjksp(hI2
+z^<}E7r698{-pw!*{mH>SLslxYH@j~%H#VLx+<8~!;a@$n+>Q%xHrQ8KGI21_iL4sI
+zF*$}m$R7Mr9z@Z*ir@Q9eClsSmC+t(g`q~VQ&nIxZenav_^Buc78s8*o@e|<QE{4a
+zhVeGz1IFJN|784&5eTYiVstQeGWr-lWTY9lG45a#8TT^oXDl%uXFS9BHN$^DE>t}g
+z1Z-O>lG`>pEuvmL-HpmgSANo!2hWQq2B>Zua$8%tfvQ>!1n@=m9ri_4`H|Rx#SH9n
+zDdRF_-FDP&WjW`L$GK%a6x?yO8l2!^g0HJrtA7TknNzCO?|U!wCv2^-5pJ%LW6!+P
+z)anX%E>`gP%3Er4c6+J9x=Atk1{Abrr1|WSY3P`SO5j!R5F*vbbQ%AaSHnR_+x&Op
+zA%8C-Pk=-Hs+FL90B)E*y3FUTIA1J)&pxRF$tzAkNr7a6_-8v$@j~G~3keqYd5I<T
+z`Kb3Q@LKkANhE_aMG_R&<ewt+nVbp5l*3G7mYJEKr<kXS;TA&^G;5`q5b>;y8g^P<
+zfWO_D2@EyVVBxnpv*}hgTeeRzWz9BoISh>M%^k`WXG=5ti$_Wu99)~lWE-qubeXNk
+zla9Tu=Jhyn5T<3$H#?Hfm-`+(d$7IBDx9cEvNv1i-LEDr>r7438bfkPcKod+mwd22
+z%{^(w&NuG)MKl0fTMTXZFJEm~k;KCj*D60g=j!2jsP)<fOUGaEZa`&xE*)?FZuW#-
+z8!Of7<|N(^R#xcjmZ&nZ%~{pC5y_T*PB2LdDjuI#Te}-4Qccvj+u4N3TBx|oVy*mP
+z<9xfFziy4n?sPv3Sqo7jWMo3>{tzvOjAJ2nB}At~#%f4?FGT+d8LFnXXtYN&Mm06B
+z(JwUPX-z$$(d(M=uBLvh@h6#K=;~&jQo1p&t3TCgSvQ{3)l)jXr5hjW>fd!z!bW>o
+z-4UjJVdJi_dN@o^hK(1(>dRqzCv2PztLMTLjTqY^YEMMJ{=B#1IV)9~IMg|yl(NPF
+zQSfMX`?(b5)))B!zjy0B$ua20CCLTPl^IS&2=T&Zid9-1*K{VAJP?rxjYC+zGDCe*
+ziQI7VfF17@3`3W-qCN>lPC5CL_c?p0F<ekqB;g0q3P1R5KNubPsT>TGXaGB3i~{ZE
+zr=QtIprytDnU7C*Wj%x0k)O{Y%nUnl%}K%F|J_iVaD&ubW4Qbtx;pZEb9}f^Yd;Ea
+zI1Ha{7Yt~z{LAY++1QG{F6*_4WsUziY{x?%I9B}i5-Tphhk8FGm%J<d_0CUoV^%N&
+zTe02j+LXk=ZyWoe7L$#wsEY@VC>f!3d-ysG_9>uk%#)4xpxb+ZkJdel#+h}l9j9`1
+zt*M!5u?i4YtZ+WECo6$LJF06|G-mMZskGiV*lQJf-ItB+hltI<?{5E<^P=0rL<P+g
+z(P)!c<?MlvMK0O~UwZ4*;x|ms(&&#Vn_-4{KM#g~a=;$N2QD7mSX0{t<cf>sId@e&
+z-cN<SWA3VKCN6g3lx#+PySpWu*+pw}>vr(fgI)K*zkikg6TDJi?^}ghc*U*%A%EGg
+Y$$8Z}9a~<{Q@y10T!W`-d%n2+Kj)*Kg#Z8m
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c
+new file mode 100644
+index 0000000000..24c1b32467
+--- /dev/null
++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <bootblock_common.h>
++#include <device/pci_ops.h>
++#include <ec/dell/mec5035/mec5035.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++void bootblock_mainboard_early_init(void)
++{
++	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
++	mec5035_early_init();
++}
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c
+new file mode 100644
+index 0000000000..c07e4b1c56
+--- /dev/null
++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c
+@@ -0,0 +1,193 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_GPIO,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_GPIO,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_NATIVE,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_NATIVE,
++	.gpio12 = GPIO_MODE_NATIVE,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_GPIO,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_GPIO,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_GPIO,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_NATIVE,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_NATIVE,
++	.gpio26 = GPIO_MODE_NATIVE,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_GPIO,
++	.gpio30 = GPIO_MODE_NATIVE,
++	.gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio1 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio3 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio13 = GPIO_DIR_INPUT,
++	.gpio14 = GPIO_DIR_INPUT,
++	.gpio15 = GPIO_DIR_INPUT,
++	.gpio16 = GPIO_DIR_INPUT,
++	.gpio17 = GPIO_DIR_OUTPUT,
++	.gpio19 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_INPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_OUTPUT,
++	.gpio29 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio17 = GPIO_LEVEL_HIGH,
++	.gpio28 = GPIO_LEVEL_LOW,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++	.gpio30 = GPIO_RESET_RSMRST,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio0 = GPIO_INVERT,
++	.gpio8 = GPIO_INVERT,
++	.gpio13 = GPIO_INVERT,
++	.gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_NATIVE,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_GPIO,
++	.gpio37 = GPIO_MODE_GPIO,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_NATIVE,
++	.gpio45 = GPIO_MODE_GPIO,
++	.gpio46 = GPIO_MODE_NATIVE,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_GPIO,
++	.gpio50 = GPIO_MODE_NATIVE,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_NATIVE,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_NATIVE,
++	.gpio56 = GPIO_MODE_NATIVE,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio33 = GPIO_DIR_INPUT,
++	.gpio34 = GPIO_DIR_OUTPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio36 = GPIO_DIR_INPUT,
++	.gpio37 = GPIO_DIR_INPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio45 = GPIO_DIR_OUTPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio49 = GPIO_DIR_INPUT,
++	.gpio51 = GPIO_DIR_INPUT,
++	.gpio52 = GPIO_DIR_INPUT,
++	.gpio54 = GPIO_DIR_INPUT,
++	.gpio57 = GPIO_DIR_INPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio34 = GPIO_LEVEL_HIGH,
++	.gpio45 = GPIO_LEVEL_LOW,
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_NATIVE,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_NATIVE,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_GPIO,
++	.gpio69 = GPIO_MODE_GPIO,
++	.gpio70 = GPIO_MODE_GPIO,
++	.gpio71 = GPIO_MODE_GPIO,
++	.gpio72 = GPIO_MODE_NATIVE,
++	.gpio73 = GPIO_MODE_NATIVE,
++	.gpio74 = GPIO_MODE_NATIVE,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio68 = GPIO_DIR_INPUT,
++	.gpio69 = GPIO_DIR_INPUT,
++	.gpio70 = GPIO_DIR_INPUT,
++	.gpio71 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 = {
++		.mode		= &pch_gpio_set1_mode,
++		.direction	= &pch_gpio_set1_direction,
++		.level		= &pch_gpio_set1_level,
++		.blink		= &pch_gpio_set1_blink,
++		.invert		= &pch_gpio_set1_invert,
++		.reset		= &pch_gpio_set1_reset,
++	},
++	.set2 = {
++		.mode		= &pch_gpio_set2_mode,
++		.direction	= &pch_gpio_set2_direction,
++		.level		= &pch_gpio_set2_level,
++		.reset		= &pch_gpio_set2_reset,
++	},
++	.set3 = {
++		.mode		= &pch_gpio_set3_mode,
++		.direction	= &pch_gpio_set3_direction,
++		.level		= &pch_gpio_set3_level,
++		.reset		= &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c
+new file mode 100644
+index 0000000000..f6876f9e09
+--- /dev/null
++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x111d76df, /* Codec Vendor / Device ID: IDT */
++	0x10280532, /* Subsystem ID */
++	11, /* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(0, 0x10280532),
++	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
++	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
++	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
++	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
++
++	0x80862806, /* Codec Vendor / Device ID: Intel */
++	0x80860101, /* Subsystem ID */
++	4, /* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(3, 0x80860101),
++	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb
+new file mode 100644
+index 0000000000..3a0fa720da
+--- /dev/null
++++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb
+@@ -0,0 +1,40 @@
++## SPDX-License-Identifier: GPL-2.0-or-later
++
++chip northbridge/intel/sandybridge
++	device domain 0 on
++		subsystemid 0x1028 0x0532 inherit
++
++		device ref igd on
++			register "gpu_cpu_backlight" = "0x000009e9"
++			register "gpu_pch_backlight" = "0x13121312"
++		end
++
++		chip southbridge/intel/bd82x6x
++			register "usb_port_config" = "{
++				{ 1, 1, 0 },
++				{ 1, 1, 0 },
++				{ 1, 0, 1 },
++				{ 1, 2, 1 },
++				{ 1, 0, 2 },
++				{ 1, 0, 2 },
++				{ 1, 0, 3 },
++				{ 1, 1, 3 },
++				{ 1, 2, 4 },
++				{ 1, 1, 4 },
++				{ 1, 1, 5 },
++				{ 1, 1, 5 },
++				{ 1, 2, 6 },
++				{ 1, 0, 6 },
++			}"
++
++			device ref xhci on
++				register "superspeed_capable_ports" = "0x0000000f"
++				register "xhci_overcurrent_mapping" = "0x00000c03"
++				register "xhci_switchable_ports" = "0x0000000f"
++			end
++			device ref sata1 on
++				register "sata_port_map" = "0x31"
++			end
++		end
++	end
++end
+-- 
+2.39.5
+