diff options
author | Leah Rowe <leah@libreboot.org> | 2024-01-25 15:24:02 +0000 |
---|---|---|
committer | Leah Rowe <leah@libreboot.org> | 2024-01-25 15:41:15 +0000 |
commit | 4a6dc5553f2a15542f730ca735fb8bf95fb8f49b (patch) | |
tree | 2cd281908a37816a526a0b6deab51376fec9cf69 /config/coreboot/d510mo_16mb/config | |
parent | ece5463109721347c2008b7791907ac4d6825588 (diff) |
coreboot/default: update coreboot to January 2024
Base revision changed to:
commit b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a
Author: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Date: Fri Jan 5 16:48:17 2024 +0800
mb/google/dedede/var/metaknight:Add fw_config probe for multi codec
and amplifier
Of note:
Several out-of-tree ports have been adjusted to use the new SPD config
style, where it is defined in devicetree. I manually updated the E6530
patch myself, based on the update that Nicholas did on E6430 (Nicholas
will later update the E6530 patch himself, and I'll re-merge the patch).
Several upstream patches now exist in this revision, that we were able
to remove from lbmk.
The heap size patch was reverted upstream, as we did, but see:
https://review.coreboot.org/c/coreboot/+/80023
https://review.coreboot.org/c/coreboot/+/79525
Although we still disable the TSEG Stage Cache, ivy/sandy/haswell should
be reliable on S3 now (leaving TSEG Stage Cache disabled, for now, anyway).
Also included in upstream now:
commit 29030d0f3dad2ec6b86000dfe2c8e951ae80bf94
Author: Bill Xie <persmule@hardenedlinux.org>
Date: Sat Oct 7 01:32:51 2023 +0800
drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume
Further patches from upstream:
commit 432e92688eca0e85cbaebca3232f65936b305a98
Author: Bill Xie <persmule@hardenedlinux.org>
Date: Fri Nov 3 12:34:01 2023 +0800
drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum
This should fix S3 on GM45 thinkpads.
Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/d510mo_16mb/config')
-rw-r--r-- | config/coreboot/d510mo_16mb/config/libgfxinit_txtmode | 32 |
1 files changed, 23 insertions, 9 deletions
diff --git a/config/coreboot/d510mo_16mb/config/libgfxinit_txtmode b/config/coreboot/d510mo_16mb/config/libgfxinit_txtmode index db50e6a6..d2ec2b67 100644 --- a/config/coreboot/d510mo_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/d510mo_16mb/config/libgfxinit_txtmode @@ -22,6 +22,7 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -129,6 +130,8 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=256 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" @@ -141,7 +144,6 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y @@ -189,6 +191,7 @@ CONFIG_BOARD_INTEL_D510MO=y # CONFIG_BOARD_INTEL_MINNOW3 is not set # CONFIG_BOARD_INTEL_MTLRVP_P is not set # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set +# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set # CONFIG_BOARD_INTEL_SKLSDLBRK is not set # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set @@ -201,15 +204,12 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO" CONFIG_PCIEXP_HOTPLUG_BUSES=32 CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 -CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_1024=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -223,6 +223,7 @@ CONFIG_BOARD_ROMSIZE_KB_1024=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -248,6 +249,7 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x80000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 CONFIG_EHCI_BAR=0xfef00000 CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 @@ -256,17 +258,18 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 # CONFIG_PCIEXP_COMMON_CLOCK is not set +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 # # CPU @@ -355,6 +358,8 @@ CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_SIPI_VECTOR_IN_ROM=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -386,7 +391,7 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x10000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -397,8 +402,6 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set CONFIG_PCIEXP_HOTPLUG_IO=0x2000 -CONFIG_FIRMWARE_CONNECTION_MANAGER=y -# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -428,6 +431,7 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -442,6 +446,10 @@ CONFIG_DRIVERS_I2C_CK505=y CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y @@ -473,6 +481,7 @@ CONFIG_NO_TPM=y CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module @@ -500,6 +509,7 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_HEAP_SIZE=0x100000 # # Console @@ -564,6 +574,10 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # +# Vendorcode Debug Settings +# + +# # BLOB Debug Settings # |