From dac71d8ed89f1f1d295157aa62c678e35a320222 Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Tue, 5 Mar 2019 16:27:36 +0800 Subject: [PATCH] mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Signed-off-by: Iru Cai --- Documentation/mainboard/hp/8560w.md | 82 +++++++ Documentation/mainboard/hp/8560w_flash.webp | Bin 0 -> 51432 bytes Documentation/mainboard/index.md | 1 + src/mainboard/hp/snb_ivb_laptops/Kconfig | 10 +- src/mainboard/hp/snb_ivb_laptops/Kconfig.name | 3 + .../variants/8560w/board_info.txt | 7 + .../variants/8560w/early_init.c | 36 +++ .../hp/snb_ivb_laptops/variants/8560w/gpio.c | 224 ++++++++++++++++++ .../snb_ivb_laptops/variants/8560w/hda_verb.c | 25 ++ .../variants/8560w/overridetree.cb | 51 ++++ 10 files changed, 438 insertions(+), 1 deletion(-) create mode 100644 Documentation/mainboard/hp/8560w.md create mode 100644 Documentation/mainboard/hp/8560w_flash.webp create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb diff --git a/Documentation/mainboard/hp/8560w.md b/Documentation/mainboard/hp/8560w.md new file mode 100644 index 0000000000..cc35a0be1f --- /dev/null +++ b/Documentation/mainboard/hp/8560w.md @@ -0,0 +1,82 @@ +# HP EliteBook 8560w + +This page describes how to run coreboot on the [HP EliteBook 8560w]. + +## Required proprietary blobs + +- Intel Firmware Descriptor, ME and GbE firmware +- EC: please read [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops) + +## Flashing instructions + +HP EliteBook 8560w has an 8MiB SOIC-8 flash chip on the bottom of the +mainboard. You just need to remove the service cover, and use an SOIC-8 +clip to read and flash the chip. + +![8560w_chip_location](8560w_flash.webp) + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Model | MX25L6406E | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | no | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| In circuit flashing | yes | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +## Untested + +- mainboards with 4 memory slots + +## Working + +- i7-2720QM, 8G+8G +- Arch Linux boot from SeaBIOS payload +- EHCI debug: the port is beside the eSATA port +- SATA +- eSATA +- USB2 and USB3 +- keyboard +- Gigabit Ethernet +- WLAN +- WWAN +- VGA and DisplayPort +- audio +- EC ACPI +- Using `me_cleaner` +- dock: PS/2 keyboard, USB, DisplayPort +- TPM +- S3 suspend/resume + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | SMSC LPC47n217 | ++------------------+--------------------------------------------------+ +| EC | SMSC KBC1126 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[HP EliteBook 8560w]: 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zHsg5*ASgU>$;Z;UIW-_g(By)7_7vMmWtL_|EJ5QVj1T_+Ra8)?V2~!$lxvxn0P>v?nhdY}4ts{y{=kJC=|J zB~CGn9E|$bX0sd+cwbDuxk*jJ%&yW#+a$@{P6+p-l^aH++vUE8Qyra^{i3@>%^ag8 zS=;hF*DvuDCBKF>AOYCAd&UNTyvjeNXvyL`O*c#fOSZVwBYFlqNOhgVc39fjz zam!6Ed41|LM!Rjq<9G~*u05)we`kQfns_As>0$@ud98cPDWyk^OGfI!m6T@$R2#KO z(8kckGM)<)`t#DdfUjxgmi^Rh#~*x>aZ@r7xiq%Iyp`+U0wq}o&=t04)?pOlV{8E=?PecLF%+5_FILZwc z`x-ey=RNji3$$oc5I@`F`PEr0Ev}_=_IJ11c9{3{uAk0uFk3&3W&nQCaK{AsqpE^`mJ_c`hEhK$&S@rsGGAXw2Mz!G4-SxExvLdPi|{d zW=S2rX{9}lE>ssY#+3rAe)>(vjPcT=8a2BdG_oJWR*_%Ny)niB8bMmP?^{0g>G1DU%rjUr(W=xO{MS7>gSb?zD9|PtPC+5by zw5H?N>t4I?o)7q^wIUdgGVa|s4x^E?PEdx=Zkf#_ld?j$OD)Q@EXn1% zqV@FSAHpeI>Qs4My8i&0Bzvc`S#9C6Zy*dTTQ~!6P7h8EdFPF1k}rpzTk!sLP-CwO zWFzzfyV(a$ltyvKPr>*@#$PA#O%T0*r46NH);VR9U}Js0D6VEsza8WcDMWn zj{%R4dG@bh_)ig<&rxh}yBLqgyoNEA{C~#1tKjGY&s4zw0G2@hwCAzFdKB?SVs9-P zHQC5L%~ggn_+EKEPh(fz+DmzN9PKzB!lQ)c0Y0_M9fv*2R~mJ?l~EYpGm-~dn$p_9 zurpf3(jK{9e!r=!OaX32YQ4|N<+||Rzl9C9t#QTK+`B%3rb>fttSWPyga)`T8|e1h zZPl!n$`DGVGJ%E2uJvV*M7U%3b6k&)U5Z}lsH4oMX3gbi3!E`fNEy$yMYkOO zbz#5~E(cLjo;O!ArP{n{fckAUMY#F{qQSDkx@= zA}FrGeAnO~dQ1^wTOTa_@y{b1)n|(Yk4kW2$1HMjK>2~sVL;062^@Zv5k~rs^=OQ+ z2RI(|#vgy!59LfmAxA=SRJ^rWZU8y`=l;qn{&Szss*Zf~-+2E3&_y63C{I1 +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* USB0 */ + { 1, 1, 0 }, /* USB1 */ + { 1, 1, 1 }, /* eSATA */ + { 1, 1, 1 }, /* camera */ + { 0, 0, 2 }, + { 1, 0, 2 }, /* bluetooth */ + { 0, 0, 3 }, + { 1, 0, 3 }, + { 0, 1, 4 }, + { 1, 1, 4 }, /* WWAN */ + { 1, 0, 5 }, + { 1, 0, 5 }, /* dock */ + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c new file mode 100644 index 0000000000..560d668d6f --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c @@ -0,0 +1,224 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c new file mode 100644 index 0000000000..2f5469fc84 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c1631, /* Subsystem ID */ + + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c1631), + AZALIA_PIN_CFG(0, 0x0a, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0b, 0x0421401f), + AZALIA_PIN_CFG(0, 0x0c, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0x90a60130), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb new file mode 100644 index 0000000000..4264270ad0 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + device domain 0 on + subsystemid 0x103c 0x1631 inherit + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 off end # Internal graphics + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" + # HDD(0), ODD(1), eSATA(4) + register "sata_port_map" = "0x3b" + + device pci 1c.0 on end # PCIe Port #1, WWAN + device pci 1c.1 on end # PCIe Port #2, ExpressCard + device pci 1c.2 on end # PCIe Port #3, SD/MMC + device pci 1c.3 on end # PCIe Port #4, WLAN + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8, NEC USB 3.0 Host Controller + device pci 1f.0 on # LPC bridge + chip ec/hp/kbc1126 + register "ec_data_port" = "0x60" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off end # COM2 + end + end + end + end +end -- 2.43.0