From 27bf50138af0c5267581f8cc1f80676fb1836572 Mon Sep 17 00:00:00 2001 From: Denis 'GNUtoo' Carikli Date: Mon, 27 Mar 2017 22:05:16 +0200 Subject: [PATCH 1/1] sb/intel/ibexpeak/setup_heci_uma.c: Add timeouts when waiting for heci Since until now, the code running on the management engine is: - Signed by its manufacturer - Proprietary software, without corresponding source code It can desirable to run the least ammount possible of such code, which is what me_cleaner[1] enables. It does it by removing partitions of the management engine firmwares, however when doing so, the HECI interface might not be present anymore. So it is desirable not to have the RAM initialisation code wait forever for the HECI interface to appear. [1] https://github.com/corna/me_cleaner/ MERGENOTE: Adapted from this patch: https://mail.coreboot.org/pipermail/coreboot/2017-March/083798.html Author on this version of the patch set to same author as in the linked one, with same date set, but the commit message is modified to match the new code path. Patch author Denis Carikli, but this versions of the patch was rebased from it by Leah Rowe on 29 Oct 2023. Signed-off-by: Leah Rowe --- src/southbridge/intel/ibexpeak/setup_heci_uma.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/setup_heci_uma.c b/src/southbridge/intel/ibexpeak/setup_heci_uma.c index 572e5e7a76..3a68344d97 100644 --- a/src/southbridge/intel/ibexpeak/setup_heci_uma.c +++ b/src/southbridge/intel/ibexpeak/setup_heci_uma.c @@ -8,28 +8,30 @@ #include #include #include +#include #define HECIDEV PCI_DEV(0, 0x16, 0) -/* FIXME: add timeout. */ static void wait_heci_ready(void) { - while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) // = 0x8000000c - ; + int i = 1000*1000; + while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8)) /* = 0x8000000c */ + udelay(1); write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc); } -/* FIXME: add timeout. */ static void wait_heci_cb_avail(int len) { + int i = 1000*1000; + union { struct mei_csr csr; u32 raw; } csr; - while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) - ; + while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8)) + udelay(1); do { csr.raw = read32(DEFAULT_HECIBAR + 0x4); -- 2.39.2