From 705149a3e089fb99e671a47b0acd3a30378dd659 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 5 Aug 2023 23:36:42 +0100 Subject: coreboot/default: bump revision to 2 August 2023 coreboot revision: d86260a134575b083f35103e1cd5c7c7ad883bce from 2 August 2023 The patches were updated. HP 8300 USDT has now been merged upstream, so that patch is no longer included in lbmk. SD card fix for E6400 merged upstream, so now it's removed in lbmk. The nvidia E6400 patch (devicetree.cb) has not yet merged upstream. The ifdtool --nuke option has been rebased. Patches as follow-ups to earlier patches removed; for example, patches that set VRAM to 352MB on GM45 have been removed, and replaced with patches that just set 256MB in the first place (this is more stable). This was mostly a clean rebase, of all the patches. It went smooth. I haven't updated cros/haswell yet; the 4.11_branch revision used on fam15h will also remain, for now. The coreboot configurations have been updated, for this new revision of coreboot. Signed-off-by: Leah Rowe --- ...ep-on-x200-t400-Revert-cpu-intel-model_10.patch | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 resources/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch (limited to 'resources/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch') diff --git a/resources/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch b/resources/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch new file mode 100644 index 00000000..df43eeb3 --- /dev/null +++ b/resources/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch @@ -0,0 +1,47 @@ +From 929974434bbd627ab7add5ef4ec4eb62e5412f57 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Wed, 1 Dec 2021 02:53:00 +0000 +Subject: [PATCH 16/19] fix speedstep on x200/t400: Revert + "cpu/intel/model_1067x: enable PECI" + +This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f. + +Enabling PECI without microcode updates loaded causes the CPUID feature set +to become corrupted. And one consequence is broken SpeedStep. At least, that's +my understanding looking at Intel Errata. This revert is not a fix, because +upstream is correct (upstream assumes microcode updates). We will simply +maintain this revert patch in Libreboot, from now on. +--- + src/cpu/intel/model_1067x/model_1067x_init.c | 9 --------- + 1 file changed, 9 deletions(-) + +diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c +index 315e7c36fc..1423fd72bc 100644 +--- a/src/cpu/intel/model_1067x/model_1067x_init.c ++++ b/src/cpu/intel/model_1067x/model_1067x_init.c +@@ -141,8 +141,6 @@ static void configure_emttm_tables(void) + wrmsr(MSR_EMTTM_CR_TABLE(5), msr); + } + +-#define IA32_PECI_CTL 0x5a0 +- + static void configure_misc(const int eist, const int tm2, const int emttm) + { + msr_t msr; +@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm) + msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ + wrmsr(IA32_MISC_ENABLE, msr); + } +- +- /* Enable PECI +- WARNING: due to Erratum AW67 described in Intel document #318733 +- the microcode must be updated before this MSR is written to. */ +- msr = rdmsr(IA32_PECI_CTL); +- msr.lo |= 1; +- wrmsr(IA32_PECI_CTL, msr); + } + + #define PIC_SENS_CFG 0x1aa +-- +2.39.2 + -- cgit v1.2.1