From 4a9fca57f377349ee03cdf51afcc90ab2910a698 Mon Sep 17 00:00:00 2001 From: Riku Viitanen Date: Sun, 11 Feb 2024 19:13:36 +0200 Subject: Patch SeaBIOS: Add MXM support Signed-off-by: Riku Viitanen --- .../0001-romfile-implement-a-generic-loader.patch | 86 ++++++++++ ...s-optionroms-implement-mxm-3.0-interrupts.patch | 188 +++++++++++++++++++++ 2 files changed, 274 insertions(+) create mode 100644 config/seabios/default/patches/0001-romfile-implement-a-generic-loader.patch create mode 100644 config/seabios/default/patches/0002-vgahooks-optionroms-implement-mxm-3.0-interrupts.patch (limited to 'config') diff --git a/config/seabios/default/patches/0001-romfile-implement-a-generic-loader.patch b/config/seabios/default/patches/0001-romfile-implement-a-generic-loader.patch new file mode 100644 index 00000000..f0682c11 --- /dev/null +++ b/config/seabios/default/patches/0001-romfile-implement-a-generic-loader.patch @@ -0,0 +1,86 @@ +From 2aff8adc1dcd1315877fdb4ac4ef5e649c5b7d11 Mon Sep 17 00:00:00 2001 +From: Riku Viitanen +Date: Sat, 10 Feb 2024 21:23:33 +0200 +Subject: [PATCH 1/2] romfile: implement a generic loader + +romfile_loadfile_g: +Based on romfile_loadfile but more flexible. User has to supply pointer +to a malloc function and the number of trailing padding bytes. Thus, any +memory region may be used. + +romfile_loadfile: +It is now a wrapper around romfile_loadfile_g. Functionality is the same. + +Signed-off-by: Riku Viitanen +--- + src/romfile.c | 25 ++++++++++++++++++++----- + src/romfile.h | 2 ++ + 2 files changed, 22 insertions(+), 5 deletions(-) + +diff --git a/src/romfile.c b/src/romfile.c +index b598274e..8bf95713 100644 +--- a/src/romfile.c ++++ b/src/romfile.c +@@ -47,10 +47,12 @@ romfile_find(const char *name) + return __romfile_findprefix(name, strlen(name) + 1, NULL); + } + +-// Helper function to find, malloc_tmphigh, and copy a romfile. This +-// function adds a trailing zero to the malloc'd copy. ++// Generic function to find romfile, malloc (using provided function ++// pointer), and copy a romfile. add_len specifies how many additional ++// trailing bytes to reserve. The extra bytes will not be initialised. + void * +-romfile_loadfile(const char *name, int *psize) ++romfile_loadfile_g(const char *name, int *psize, ++ void *(*malloc_fn)(), int add_len) + { + struct romfile_s *file = romfile_find(name); + if (!file) +@@ -60,7 +62,7 @@ romfile_loadfile(const char *name, int *psize) + if (!filesize) + return NULL; + +- char *data = malloc_tmphigh(filesize+1); ++ char *data = malloc_fn(filesize+add_len); + if (!data) { + warn_noalloc(); + return NULL; +@@ -74,7 +76,20 @@ romfile_loadfile(const char *name, int *psize) + } + if (psize) + *psize = filesize; +- data[filesize] = '\0'; ++ ++ return data; ++} ++ ++// Helper function to find, malloc_tmphigh, and copy a romfile. This ++// function adds a trailing zero to the malloc'd copy. ++void * ++romfile_loadfile(const char *name, int *psize) ++{ ++ char *data = romfile_loadfile_g(name, psize, &malloc_tmphigh, 1); ++ if (!data) ++ return NULL; ++ ++ data[*psize] = '\0'; + return data; + } + +diff --git a/src/romfile.h b/src/romfile.h +index 3e0f8200..a320a5bc 100644 +--- a/src/romfile.h ++++ b/src/romfile.h +@@ -13,6 +13,8 @@ struct romfile_s { + void romfile_add(struct romfile_s *file); + struct romfile_s *romfile_findprefix(const char *prefix, struct romfile_s *prev); + struct romfile_s *romfile_find(const char *name); ++void *romfile_loadfile_g(const char *name, int *psize, ++ void *(*malloc_fn)(), int add_len); + void *romfile_loadfile(const char *name, int *psize); + u64 romfile_loadint(const char *name, u64 defval); + +-- +2.43.0 + diff --git a/config/seabios/default/patches/0002-vgahooks-optionroms-implement-mxm-3.0-interrupts.patch b/config/seabios/default/patches/0002-vgahooks-optionroms-implement-mxm-3.0-interrupts.patch new file mode 100644 index 00000000..f05a34c2 --- /dev/null +++ b/config/seabios/default/patches/0002-vgahooks-optionroms-implement-mxm-3.0-interrupts.patch @@ -0,0 +1,188 @@ +From 1e7c443d069ef817c4e699bd6675efff4ebddb86 Mon Sep 17 00:00:00 2001 +From: Riku Viitanen +Date: Sat, 10 Feb 2024 21:38:17 +0200 +Subject: [PATCH 2/2] vgahooks, optionroms: implement mxm 3.0 interrupts + +VGAROMs on MXM graphics cards need certain int15h functions present. + +Tested on a HP EliteBook 8560w with coreboot and Quadro 2000M. A warning +is displayed for 30 seconds and performance is nerfed: + + ERROR: Valid MXM Structure not found. + POST halted for 30 seconds, P-state limited to P10... + +This patch implements the minimum required on this system (and implemented +by the OEM BIOS): functions 0 and 1. + +These functions are specific to the MXM 3.0 Software Specification, +earlier versions are not implemented due to lack of hardware. Documentation +for versions 2.1 and 3.0 can be found freely online. + +Functions aren't specific to mainboards or GPUs (though some mainboards +could need more functions implemented). The structure is +mainboard-specific and is read from romfile "mxm-30-sis". + +It can be extracted from vendor BIOS by running those same interrupts. +I wrote a tool to do it on Linux: https://codeberg.org/Riku_V/mxmdump/ + +Signed-off-by: Riku Viitanen +--- + src/optionroms.c | 9 +++++++ + src/vgahooks.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++++ + src/vgahooks.h | 9 +++++++ + 3 files changed, 87 insertions(+) + create mode 100644 src/vgahooks.h + +diff --git a/src/optionroms.c b/src/optionroms.c +index e906ab97..fcce7900 100644 +--- a/src/optionroms.c ++++ b/src/optionroms.c +@@ -22,6 +22,7 @@ + #include "string.h" // memset + #include "util.h" // get_pnp_offset + #include "tcgbios.h" // tpm_* ++#include "vgahooks.h" // MXM30SIS + + static int EnforceChecksum, S3ResumeVga, RunPCIroms; + +@@ -463,6 +464,14 @@ vgarom_setup(void) + RunPCIroms = romfile_loadint("etc/pci-optionrom-exec", 2); + ScreenAndDebug = romfile_loadint("etc/screen-and-debug", 1); + ++ // Load MXM 3.0 System Information Structure ++ void *mxm_sis = romfile_loadfile_g("mxm-30-sis", NULL, &malloc_low, 0); ++ if (mxm_sis) { ++ MXM30SIS = (u32)mxm_sis; ++ } else { ++ MXM30SIS = 0; ++ } ++ + // Clear option rom memory + memset((void*)BUILD_ROM_START, 0, rom_get_max() - BUILD_ROM_START); + +diff --git a/src/vgahooks.c b/src/vgahooks.c +index 1f149532..a94840b2 100644 +--- a/src/vgahooks.c ++++ b/src/vgahooks.c +@@ -18,8 +18,10 @@ + #define VH_VIA 1 + #define VH_INTEL 2 + #define VH_SMI 3 ++#define VH_MXM 4 + + int VGAHookHandlerType VARFSEG; ++u32 MXM30SIS VARFSEG; + + static void + handle_155fXX(struct bregs *regs) +@@ -59,6 +61,7 @@ via_155f02(struct bregs *regs) + dprintf(1, "Warning: VGA TV/CRT output type is hardcoded\n"); + } + ++ + static void + via_155f18(struct bregs *regs) + { +@@ -296,6 +299,69 @@ winent_mb6047_setup(struct pci_device *pci) + SmiBootDisplay = 0x02; + } + ++/**************************************************************** ++ * MXM VGA hooks ++ ****************************************************************/ ++ ++// Function 0: Return Specification Support Level ++static void ++mxm_V30_F00(struct bregs *regs) ++{ ++ regs->ax = 0x005f; // Success ++ regs->bl = 0x30; // MXM 3.0 ++ regs->cx = 0x0003; // Supported Functions ++ set_success(regs); ++} ++ ++// Function 1: Return a Pointer to the MXM Structure ++static void ++mxm_V30_F01(struct bregs *regs) ++{ ++ switch (regs->cx) { ++ case 0x0030: ++ regs->ax = 0x005f; // Success ++ regs->es = GET_GLOBAL(MXM30SIS)/16; ++ regs->di = GET_GLOBAL(MXM30SIS)%16; ++ set_success(regs); ++ break; ++ default: ++ handle_155fXX(regs); ++ break; ++ } ++} ++ ++static void ++mxm_V30(struct bregs *regs) ++{ ++ switch (regs->bx) { ++ case 0xff00: mxm_V30_F00(regs); break; ++ case 0xff01: mxm_V30_F01(regs); break; ++ default: handle_155fXX(regs); break; ++ } ++} ++ ++static void ++mxm_155f80(struct bregs *regs) ++{ ++ // TODO: implement other versions, like 2.1 ++ mxm_V30(regs); ++} ++ ++static void ++mxm_155f(struct bregs *regs) ++{ ++ switch (regs->al) { ++ case 0x80: mxm_155f80(regs); break; ++ default: handle_155fXX(regs); break; ++ } ++} ++ ++void ++mxm_setup(void) ++{ ++ VGAHookHandlerType = VH_MXM; ++} ++ + /**************************************************************** + * Entry and setup + ****************************************************************/ +@@ -313,6 +379,7 @@ handle_155f(struct bregs *regs) + switch (htype) { + case VH_VIA: via_155f(regs); break; + case VH_INTEL: intel_155f(regs); break; ++ case VH_MXM: mxm_155f(regs); break; + default: handle_155fXX(regs); break; + } + } +@@ -352,4 +419,6 @@ vgahook_setup(struct pci_device *pci) + via_setup(pci); + else if (pci->vendor == PCI_VENDOR_ID_INTEL) + intel_setup(pci); ++ else if (GET_GLOBAL(MXM30SIS)) ++ mxm_setup(); + } +diff --git a/src/vgahooks.h b/src/vgahooks.h +new file mode 100644 +index 00000000..f0c203af +--- /dev/null ++++ b/src/vgahooks.h +@@ -0,0 +1,9 @@ ++#ifndef __VGAHOOKS_H ++#define __VGAHOOKS_H ++ ++#include "types.h" // u32 ++ ++extern u32 MXM30SIS; ++ ++ ++#endif // vgahooks.h +-- +2.43.0 + -- cgit v1.2.1 From f9ed92e4d2809f3b1ee5dceef92f4f15673b41c1 Mon Sep 17 00:00:00 2001 From: Riku Viitanen Date: Mon, 12 Feb 2024 01:09:41 +0200 Subject: Add HP EliteBook 8560w Iru Cai's port from Gerrit: https://review.coreboot.org/c/coreboot/+/39398 Now with the proper MXM structure, which removes the 30 second POST delay. Tested with i7-2670QM, Quadro 2000M and 32GB RAM. Signed-off-by: Riku Viitanen --- ...litebook-8560w-as-an-HP-Sandy-Ivy-Bridge-.patch | 1556 ++++++++++++++++++++ ...8560w-Add-MXM-System-Infomation-Structure.patch | 41 + config/coreboot/hp8560w_8mb/config/normal | 642 ++++++++ config/coreboot/hp8560w_8mb/target.cfg | 7 + config/vendor/sources | 13 + 5 files changed, 2259 insertions(+) create mode 100644 config/coreboot/default/patches/0034-mb-hp-Add-Elitebook-8560w-as-an-HP-Sandy-Ivy-Bridge-.patch create mode 100644 config/coreboot/default/patches/0035-hp8560w-Add-MXM-System-Infomation-Structure.patch create mode 100644 config/coreboot/hp8560w_8mb/config/normal create mode 100644 config/coreboot/hp8560w_8mb/target.cfg (limited to 'config') diff --git a/config/coreboot/default/patches/0034-mb-hp-Add-Elitebook-8560w-as-an-HP-Sandy-Ivy-Bridge-.patch b/config/coreboot/default/patches/0034-mb-hp-Add-Elitebook-8560w-as-an-HP-Sandy-Ivy-Bridge-.patch new file mode 100644 index 00000000..458c3723 --- /dev/null +++ b/config/coreboot/default/patches/0034-mb-hp-Add-Elitebook-8560w-as-an-HP-Sandy-Ivy-Bridge-.patch @@ -0,0 +1,1556 @@ +From dac71d8ed89f1f1d295157aa62c678e35a320222 Mon Sep 17 00:00:00 2001 +From: Iru Cai +Date: Tue, 5 Mar 2019 16:27:36 +0800 +Subject: [PATCH] mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop + variant + +Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 +Signed-off-by: Iru Cai +--- + Documentation/mainboard/hp/8560w.md | 82 +++++++ + Documentation/mainboard/hp/8560w_flash.webp | Bin 0 -> 51432 bytes + Documentation/mainboard/index.md | 1 + + src/mainboard/hp/snb_ivb_laptops/Kconfig | 10 +- + src/mainboard/hp/snb_ivb_laptops/Kconfig.name | 3 + + .../variants/8560w/board_info.txt | 7 + + .../variants/8560w/early_init.c | 36 +++ + .../hp/snb_ivb_laptops/variants/8560w/gpio.c | 224 ++++++++++++++++++ + .../snb_ivb_laptops/variants/8560w/hda_verb.c | 25 ++ + .../variants/8560w/overridetree.cb | 51 ++++ + 10 files changed, 438 insertions(+), 1 deletion(-) + create mode 100644 Documentation/mainboard/hp/8560w.md + create mode 100644 Documentation/mainboard/hp/8560w_flash.webp + create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt + create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c + create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c + create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c + create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb + +diff --git a/Documentation/mainboard/hp/8560w.md b/Documentation/mainboard/hp/8560w.md +new file mode 100644 +index 0000000000..cc35a0be1f +--- /dev/null ++++ b/Documentation/mainboard/hp/8560w.md +@@ -0,0 +1,82 @@ ++# HP EliteBook 8560w ++ ++This page describes how to run coreboot on the [HP EliteBook 8560w]. ++ ++## Required proprietary blobs ++ ++- Intel Firmware Descriptor, ME and GbE firmware ++- EC: please read [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops) ++ ++## Flashing instructions ++ ++HP EliteBook 8560w has an 8MiB SOIC-8 flash chip on the bottom of the ++mainboard. You just need to remove the service cover, and use an SOIC-8 ++clip to read and flash the chip. ++ ++![8560w_chip_location](8560w_flash.webp) ++ ++```eval_rst +++---------------------+------------+ ++| Type | Value | +++=====================+============+ ++| Socketed flash | no | +++---------------------+------------+ ++| Model | MX25L6406E | +++---------------------+------------+ ++| Size | 8 MiB | +++---------------------+------------+ ++| Package | SOIC-8 | +++---------------------+------------+ ++| Write protection | no | +++---------------------+------------+ ++| Dual BIOS feature | no | +++---------------------+------------+ ++| In circuit flashing | yes | +++---------------------+------------+ ++| Internal flashing | yes | +++---------------------+------------+ ++``` ++ ++## Untested ++ ++- mainboards with 4 memory slots ++ ++## Working ++ ++- i7-2720QM, 8G+8G ++- Arch Linux boot from SeaBIOS payload ++- EHCI debug: the port is beside the eSATA port ++- SATA ++- eSATA ++- USB2 and USB3 ++- keyboard ++- Gigabit Ethernet ++- WLAN ++- WWAN ++- VGA and DisplayPort ++- audio ++- EC ACPI ++- Using `me_cleaner` ++- dock: PS/2 keyboard, USB, DisplayPort ++- TPM ++- S3 suspend/resume ++ ++## Technology ++ ++```eval_rst +++------------------+--------------------------------------------------+ ++| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +++------------------+--------------------------------------------------+ ++| Southbridge | bd82x6x | +++------------------+--------------------------------------------------+ ++| CPU | model_206ax | +++------------------+--------------------------------------------------+ ++| Super I/O | SMSC LPC47n217 | +++------------------+--------------------------------------------------+ ++| EC | SMSC KBC1126 | +++------------------+--------------------------------------------------+ ++| Coprocessor | Intel Management Engine | +++------------------+--------------------------------------------------+ ++``` ++ ++[HP EliteBook 8560w]: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/5071171 +diff --git a/Documentation/mainboard/hp/8560w_flash.webp b/Documentation/mainboard/hp/8560w_flash.webp +new file mode 100644 +index 0000000000000000000000000000000000000000..b8295bc6e920a4c59c4282e419200569672e8267 +GIT binary patch +literal 51432 +zcmV(yKi^#M#r=Q%pZ))E|LninKi>Lq`uzU;=x6#L +z_&@o-?ETe$>3-vT;{MnEqxD1mAIJywPw<|$U-P}6|HA*`_8R_e{wx1quNUrz!vFQ( +z`ailK1K+U!`h9>u|N4M)|HH?i9X9$?`G4I1)BNG~ipu|R`k#1@{jXU6>v(JWxA;DT +zzVYCB<~+)LFXXY_?^gd(^$Px*{sYs$Cy&nm<@OZ*r~b>;kHUVUM7XZoNl5?NT#upf +zN&A7rW!}LZIRxR$wDur&7VUBA0xZvzt<<(jl};j2H9V;iW?H%RiPDDJaE`$cD{p_6 +z&aby;HFJ_5G0iB@G{~#T#w{-)w6SNww#bz$HJQZtP(7B=^h`1XE=@n4DsicnR)5Q* +zyNIAnUTJaL?vs`>qc0?184k@tv#tDe9waUUSma|L-LrZeZ7rgB0z7eBFftnS +zJ!5hyeVmP1Cu@ulbam*rBAozr%zmJ1_%2${ioa;XGtNvRcj~u8942+Jr6{0)Drp?4 +ze9!s%Csz5>s5)@=aar2$;gc%yO?gACgGWgM_Fj2i)Iw9)DUS%>jtviy2Uo&?P3a@m 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+zW=S2rX{9}lE>ssY#+3rAe)>(vjPcT=8a2BdG_oJWR*_%Ny)niB8bMmP?^{0g>G1DU%rjUr(W=xO{MS7>gSb?zD9|PtPC+5by +zw5H?N>t4I?o)7q^wIUdgGVa|s4x^E?PEdx=Zkf#_ld?j$OD)Q@EXn1% +zqV@FSAHpeI>Qs4My8i&0Bzvc`S#9C6Zy*dTTQ~!6P7h8EdFPF1k}rpzTk!sLP-CwO +zWFzzfyV(a$ltyvKPr>*@#$PA#O%T0*r46NH);VR9U}Js0D6VEsza8WcDMWn +zj{%R4dG@bh_)ig<&rxh}yBLqgyoNEA{C~#1tKjGY&s4zw0G2@hwCAzFdKB?SVs9-P +zHQC5L%~ggn_+EKEPh(fz+DmzN9PKzB!lQ)c0Y0_M9fv*2R~mJ?l~EYpGm-~dn$p_9 +zurpf3(jK{9e!r=!OaX32YQ4|N<+||Rzl9C9t#QTK+`B%3rb>fttSWPyga)`T8|e1h +zZPl!n$`DGVGJ%E2uJvV*M7U%3b6k&)U5Z}lsH4oMX3gbi3!E`fNEy$yMYkOO +zbz#5~E(cLjo;O!ArP{n{fckAUMY#F{qQSDkx@= +zA}FrGeAnO~dQ1^wTOTa_@y{b1)n|(Yk4kW2$1HMjK>2~sVL;062^@Zv5k~rs^=OQ+ +z2RI(|#vgy!59LfmAxA=SRJ^rWZU8y`=l;qn{&Szss*Zf~-+2E3&_y63C{I1 ++#include ++#include ++#include ++ ++#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) ++ ++const struct southbridge_usb_port mainboard_usb_ports[] = { ++ { 1, 1, 0 }, /* USB0 */ ++ { 1, 1, 0 }, /* USB1 */ ++ { 1, 1, 1 }, /* eSATA */ ++ { 1, 1, 1 }, /* camera */ ++ { 0, 0, 2 }, ++ { 1, 0, 2 }, /* bluetooth */ ++ { 0, 0, 3 }, ++ { 1, 0, 3 }, ++ { 0, 1, 4 }, ++ { 1, 1, 4 }, /* WWAN */ ++ { 1, 0, 5 }, ++ { 1, 0, 5 }, /* dock */ ++ { 1, 0, 6 }, ++ { 1, 0, 6 }, ++}; ++ ++void bootblock_mainboard_early_init(void) ++{ ++ lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ++ kbc1126_enter_conf(); ++ kbc1126_mailbox_init(); ++ kbc1126_kbc_init(); ++ kbc1126_ec_init(); ++ kbc1126_pm1_init(); ++ kbc1126_exit_conf(); ++} +diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c +new file mode 100644 +index 0000000000..560d668d6f +--- /dev/null ++++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c +@@ -0,0 +1,224 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_GPIO, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_GPIO, ++ .gpio11 = GPIO_MODE_GPIO, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_GPIO, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_NATIVE, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_OUTPUT, ++ .gpio1 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio10 = GPIO_DIR_INPUT, ++ .gpio11 = GPIO_DIR_OUTPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_OUTPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_OUTPUT, ++ .gpio23 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_OUTPUT, ++ .gpio27 = GPIO_DIR_OUTPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio0 = GPIO_LEVEL_LOW, ++ .gpio11 = GPIO_LEVEL_LOW, ++ .gpio17 = GPIO_LEVEL_HIGH, ++ .gpio22 = GPIO_LEVEL_HIGH, ++ .gpio24 = GPIO_LEVEL_HIGH, ++ .gpio27 = GPIO_LEVEL_LOW, ++ .gpio28 = GPIO_LEVEL_LOW, ++ .gpio29 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++ .gpio24 = GPIO_RESET_RSMRST, ++ .gpio30 = GPIO_RESET_RSMRST, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio1 = GPIO_INVERT, ++ .gpio3 = GPIO_INVERT, ++ .gpio6 = GPIO_INVERT, ++ .gpio7 = GPIO_INVERT, ++ .gpio10 = GPIO_INVERT, ++ .gpio13 = GPIO_INVERT, ++ .gpio14 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_NATIVE, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_GPIO, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_GPIO, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_GPIO, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_GPIO, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_GPIO, ++ .gpio56 = GPIO_MODE_NATIVE, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_GPIO, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_OUTPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio35 = GPIO_DIR_OUTPUT, ++ .gpio37 = GPIO_DIR_OUTPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio44 = GPIO_DIR_INPUT, ++ .gpio46 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio50 = GPIO_DIR_INPUT, ++ .gpio51 = GPIO_DIR_INPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio53 = GPIO_DIR_OUTPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio55 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_OUTPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++ .gpio61 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio33 = GPIO_LEVEL_LOW, ++ .gpio35 = GPIO_LEVEL_LOW, ++ .gpio37 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_LOW, ++ .gpio53 = GPIO_LEVEL_HIGH, ++ .gpio57 = GPIO_LEVEL_LOW, ++ .gpio60 = GPIO_LEVEL_HIGH, ++ .gpio61 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_GPIO, ++ .gpio69 = GPIO_MODE_GPIO, ++ .gpio70 = GPIO_MODE_GPIO, ++ .gpio71 = GPIO_MODE_GPIO, ++ .gpio72 = GPIO_MODE_GPIO, ++ .gpio73 = GPIO_MODE_GPIO, ++ .gpio74 = GPIO_MODE_GPIO, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio68 = GPIO_DIR_OUTPUT, ++ .gpio69 = GPIO_DIR_INPUT, ++ .gpio70 = GPIO_DIR_OUTPUT, ++ .gpio71 = GPIO_DIR_OUTPUT, ++ .gpio72 = GPIO_DIR_OUTPUT, ++ .gpio73 = GPIO_DIR_OUTPUT, ++ .gpio74 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++ .gpio68 = GPIO_LEVEL_HIGH, ++ .gpio70 = GPIO_LEVEL_HIGH, ++ .gpio71 = GPIO_LEVEL_HIGH, ++ .gpio72 = GPIO_LEVEL_LOW, ++ .gpio73 = GPIO_LEVEL_HIGH, ++ .gpio74 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c +new file mode 100644 +index 0000000000..2f5469fc84 +--- /dev/null ++++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c +@@ -0,0 +1,25 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ 0x111d7605, /* Codec Vendor / Device ID: IDT */ ++ 0x103c1631, /* Subsystem ID */ ++ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x103c1631), ++ AZALIA_PIN_CFG(0, 0x0a, 0x40f000f0), ++ AZALIA_PIN_CFG(0, 0x0b, 0x0421401f), ++ AZALIA_PIN_CFG(0, 0x0c, 0x04a11020), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), ++ AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), ++ AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), ++ AZALIA_PIN_CFG(0, 0x11, 0x90a60130), ++ AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), ++ AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb +new file mode 100644 +index 0000000000..4264270ad0 +--- /dev/null ++++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb +@@ -0,0 +1,51 @@ ++# SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/sandybridge ++ register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" ++ device domain 0 on ++ subsystemid 0x103c 0x1631 inherit ++ device pci 01.0 on end # PCIe Bridge for discrete graphics ++ device pci 02.0 off end # Internal graphics ++ ++ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH ++ register "docking_supported" = "0" ++ register "gen1_dec" = "0x007c0201" ++ register "gen2_dec" = "0x000c0101" ++ register "gen3_dec" = "0x00fcfe01" ++ register "gen4_dec" = "0x000402e9" ++ register "gpi6_routing" = "2" ++ register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" ++ # HDD(0), ODD(1), eSATA(4) ++ register "sata_port_map" = "0x3b" ++ ++ device pci 1c.0 on end # PCIe Port #1, WWAN ++ device pci 1c.1 on end # PCIe Port #2, ExpressCard ++ device pci 1c.2 on end # PCIe Port #3, SD/MMC ++ device pci 1c.3 on end # PCIe Port #4, WLAN ++ device pci 1c.4 off end # PCIe Port #5 ++ device pci 1c.5 off end # PCIe Port #6 ++ device pci 1c.6 off end # PCIe Port #7 ++ device pci 1c.7 on end # PCIe Port #8, NEC USB 3.0 Host Controller ++ device pci 1f.0 on # LPC bridge ++ chip ec/hp/kbc1126 ++ register "ec_data_port" = "0x60" ++ register "ec_cmd_port" = "0x64" ++ register "ec_ctrl_reg" = "0xca" ++ register "ec_fan_ctrl_value" = "0x6b" ++ device pnp ff.1 off end ++ end ++ chip superio/smsc/lpc47n217 ++ device pnp 4e.3 on # Parallel ++ io 0x60 = 0x378 ++ irq 0x70 = 7 ++ end ++ device pnp 4e.4 on # COM1 ++ io 0x60 = 0x3f8 ++ irq 0x70 = 4 ++ end ++ device pnp 4e.5 off end # COM2 ++ end ++ end ++ end ++ end ++end +-- +2.43.0 + diff --git a/config/coreboot/default/patches/0035-hp8560w-Add-MXM-System-Infomation-Structure.patch b/config/coreboot/default/patches/0035-hp8560w-Add-MXM-System-Infomation-Structure.patch new file mode 100644 index 00000000..68ccb801 --- /dev/null +++ b/config/coreboot/default/patches/0035-hp8560w-Add-MXM-System-Infomation-Structure.patch @@ -0,0 +1,41 @@ +From b2cf0657a2058118baf6f4ec96e356de3c9e493e Mon Sep 17 00:00:00 2001 +From: Riku Viitanen +Date: Sun, 11 Feb 2024 19:02:20 +0200 +Subject: [PATCH] hp8560w: Add MXM System Infomation Structure + +Change-Id: I45b421f2d7baf8ca8dedbd3b1ab1e38392b6219b +Signed-off-by: Riku Viitanen +--- + src/mainboard/hp/snb_ivb_laptops/Makefile.mk | 6 ++++++ + .../hp/snb_ivb_laptops/variants/8560w/mxm-30-sis | Bin 0 -> 129 bytes + 2 files changed, 6 insertions(+) + create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis + +diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk +index c007bb68cd..7950abbc4e 100644 +--- a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk ++++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk +@@ -9,3 +9,9 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainb + + # FIXME: Other variants with same size onboard RAM may exist. + SPD_SOURCES = hynix_4g ++ ++ifeq ($(CONFIG_BOARD_HP_8560W),y) ++cbfs-files-y += mxm-30-sis ++mxm-30-sis-file := variants/$(VARIANT_DIR)/mxm-30-sis ++mxm-30-sis-type := raw ++endif +diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis +new file mode 100644 +index 0000000000000000000000000000000000000000..7e4e245a50d8d5d36ddb22e3b1aed3fa87a2f57d +GIT binary patch +literal 129 +zcmeZ`@Qr6?sAMn@-0}aX9Rou`%?mKiz;Fq|&xF!hw;=rNM_^h3Dy{$(SAdE$zF=lx +o@?l{RW{6;7W}LwIl$Vj2apDSgHUS2PJFE;0Kxqas5d=FN0HAs+0RR91 + +literal 0 +HcmV?d00001 + +-- +2.43.1 + diff --git a/config/coreboot/hp8560w_8mb/config/normal b/config/coreboot/hp8560w_8mb/config/normal new file mode 100644 index 00000000..d3e4d52d --- /dev/null +++ b/config/coreboot/hp8560w_8mb/config/normal @@ -0,0 +1,642 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_OPTION_BACKEND_NONE=y +# CONFIG_USE_OPTION_TABLE is not set +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_TSEG_STAGE_CACHE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +CONFIG_VENDOR_HP=y +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_MAINBOARD_PART_NUMBER="EliteBook 8560w" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="hp/snb_ivb_laptops" +CONFIG_VGA_BIOS_ID="8086,0116" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="HP" +CONFIG_CBFS_SIZE=0x7E9000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_VARIANT_DIR="8560w" +CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="HP" +CONFIG_DRAM_RESET_GATE_GPIO=60 +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=1 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xfefe0000 +CONFIG_DCACHE_RAM_SIZE=0x20000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x10000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_sandybridge/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_sandybridge/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_sandybridge/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_280_G2 is not set +# CONFIG_BOARD_HP_COMPAQ_8200_ELITE_SFF_PC is not set +# CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set +# CONFIG_BOARD_HP_COMPAQ_ELITE_8300_USDT is not set +# CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set +# CONFIG_BOARD_HP_FOLIO_9480M is not set +# CONFIG_BOARD_HP_Z220_CMT_WORKSTATION is not set +# CONFIG_BOARD_HP_Z220_SFF_WORKSTATION is not set +# CONFIG_BOARD_HP_2170P is not set +# CONFIG_BOARD_HP_2560P is not set +# CONFIG_BOARD_HP_2570P is not set +# CONFIG_BOARD_HP_2760P is not set +# CONFIG_BOARD_HP_8460P is not set +# CONFIG_BOARD_HP_8470P is not set +CONFIG_BOARD_HP_8560W=y +# CONFIG_BOARD_HP_8770W is not set +# CONFIG_BOARD_HP_FOLIO_9470M is not set +# CONFIG_BOARD_HP_PROBOOK_6360B is not set +# CONFIG_BOARD_HP_REVOLVE_810_G1 is not set +CONFIG_EC_HP_KBC1126_ECFW_IN_CBFS=y +CONFIG_EC_HP_KBC1126_GPE=0x16 +CONFIG_BOARD_HP_SNB_IVB_LAPTOPS_COMMON=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="EliteBook 8560w" +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x00800000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +# CONFIG_USE_EXP_X86_64_SUPPORT is not set +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_MODEL_206AX=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_USE_NATIVE_RAMINIT=y +CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y +# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set +# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set +# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set +# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set +CONFIG_RAMINIT_ENABLE_ECC=y + +# +# Southbridge +# +CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y +CONFIG_HIDE_MEI_ON_ERROR=y +CONFIG_PCIEXP_HOTPLUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_LPC47N217=y + +# +# Embedded Controllers +# +CONFIG_EC_HP_KBC1126=y + +# +# Please select the following otherwise your laptop cannot be powered on. +# +CONFIG_KBC1126_FIRMWARE=y +CONFIG_ECFW_PTR_ADDR=0xffffff00 +CONFIG_ECFW_PTR_SIZE=8 +CONFIG_KBC1126_FW1="../../../ec/hp8560w/ec.bin.fw1" +CONFIG_KBC1126_FW1_OFFSET=0xfffe8000 +CONFIG_KBC1126_FW2="../../../ec/hp8560w/ec.bin.fw2" +CONFIG_KBC1126_FW2_OFFSET=0xfffd0000 + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_HAVE_EXP_X86_64_SUPPORT=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +# CONFIG_VGA_ROM_RUN is not set +CONFIG_NO_GFX_INIT=y +CONFIG_NO_EARLY_GFX_INIT=y +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x800 +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT is not set +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_USE_PC_CMOS_ALTCENTURY=y +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/hp8560w_8mb/target.cfg b/config/coreboot/hp8560w_8mb/target.cfg new file mode 100644 index 00000000..ae56c735 --- /dev/null +++ b/config/coreboot/hp8560w_8mb/target.cfg @@ -0,0 +1,7 @@ +tree="default" +xarch="i386-elf" +payload_seabios_withgrub="y" +payload_seabios_grubonly="y" +payload_memtest="y" +grub_scan_disk="ahci" +grub_timeout=10 diff --git a/config/vendor/sources b/config/vendor/sources index f4ec2842..b4b806cb 100644 --- a/config/vendor/sources +++ b/config/vendor/sources @@ -120,6 +120,19 @@ EC_url_bkup https://web.archive.org/web/20211231004901/https://ftp.ext.hp.com/pub/softpaq/sp85501-86000/sp85528.exe } +# 68SVD family ROM +# for 8560w +# release notes: https://support.hp.com/soar-attachment/519/col44309-ob-185196-2-ob-185196-2_sp78085_releasedoc.html +{hp8560w}{ + DL_hash 81c9917938c4a2a4f128c976250451931efd0f25b51ff34f058ddacb8eec27272691371864a683ec7abcb924fea32592d061584c7b2571a5d3e84eb870281cc3 + DL_url https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe + DL_url_bkup https://web.archive.org/web/20220202201637/https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe + + EC_hash 8e2bc5dca1a1cf0cfc1ac9df74eb6fda333f8ae560019f8182a49d3a716d72938f6cde4aa5ee56942def08207d3ef95706653bd238768fd029da43e9a4fbcc67 + EC_url https://ftp.hp.com/pub/softpaq/sp78001-78500/sp78085.exe + EC_url_bkup https://web.archive.org/web/20230402085323/https://ftp.hp.com/pub/softpaq/sp78001-78500/sp78085.exe +} + # 68ICE or 68ICF family ROM # for 8470p, 8470w, 6470b, 8570p, 6570b # release notes: https://support.hp.com/soar-attachment/1021/col43350-ob-229442-2-ob-229442-2_sp96091_releasedoc.html -- cgit v1.2.1