From 2ecec55af77868ed97fa9785a7f09d25dcd1ec9e Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Wed, 10 Jul 2024 16:27:28 +0300 Subject: u-boot: Update to v2024.07 Set default U-Boot revision to v2024.07 and rebase patches on top of that. One patch that fixes drawing box characters (UTF-8 to CP437) had an alternative merged, another hack we have to fix regulator issues is no longer neccessary as the issue is fixed, and my QEMU patches were merged upstream, so drop these patches. One patch we have to disable binman images can be replaced by a simpler alternative so drop it too. Upstream kconfig status is still unstable, so updating configs with `make oldconfig` would miss important upstream changes, since they rely on carrying defaults via upstream defconfigs. Update the configs as such, like before: - Turn old configs into defconfigs (./update trees -s u-boot) - Save the diff from old upstream defconfig (diffconfig $theirs $ours) - Update U-Boot revision, rebase patches, and clean old trees - Prepare new U-Boot tree (./update trees -f u-boot) - Review the diffconfigs to see if any options were renamed upstream - Copy over the new upstream defconfigs and apply earlier diff - Turn new defconfigs into configs (./update trees -l u-boot) Signed-off-by: Alper Nebi Yasak --- ...001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch') diff --git a/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch b/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch index 4a3e8687..4ceeac59 100644 --- a/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch +++ b/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch @@ -1,4 +1,4 @@ -From 27d49512277677afb7f71e093b007b3e2022b83e Mon Sep 17 00:00:00 2001 +From f98475a64fcfe6ef710acb29391c33c17903e580 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Fri, 8 Oct 2021 17:33:22 +0300 Subject: [PATCH] clk: rockchip: rk3399: Set hardcoded clock rates same as @@ -60,7 +60,7 @@ index d941a129f3e5..54035c0df1f3 100644 #define PWM_CLOCK_HZ PMU_PCLK_HZ diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c -index f748fb5189e0..33f02c2d633c 100644 +index 67b2c05ec9ed..754b35c23197 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -54,10 +54,11 @@ struct pll_div { @@ -87,7 +87,7 @@ index f748fb5189e0..33f02c2d633c 100644 void *aclkreg_addr, *dclkreg_addr; u32 div; -@@ -1336,6 +1337,7 @@ static void rkclk_init(struct rockchip_cru *cru) +@@ -1395,6 +1396,7 @@ static void rkclk_init(struct rockchip_cru *cru) /* configure gpll cpll */ rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg); @@ -96,5 +96,5 @@ index f748fb5189e0..33f02c2d633c 100644 /* configure perihp aclk, hclk, pclk */ aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; -- -2.42.0 +2.45.2 -- cgit v1.2.1