From d8ac9d53b66a3a940962945c4102f1fcd644cde1 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 27 Oct 2024 01:12:56 +0100 Subject: Switch Dell 3050 Micro to newer coreboot revision Specifically, use the same revision that Mate used in patchset 15. This will ensure that any issues are *not* caused by the coreboot revision; this is being done, because the old coreboot revision was from July, but patchset 15 from Mate is based on a September revision of coreboot. I've been eliminating as many variables as possible, trying to fix SeaBIOS payload on this machine, because it hangs in Libreboot, but not when building from gerrit directly, which means the coreboot revision may be a factor (since I'm using his patches on an older revision so upstream might have made some changes since then that the port relies on). For this, a new coreboot tree is used, called "dell7", referring to the fact that Kabylake is Intel's 7th generation. Signed-off-by: Leah Rowe --- ...gma-plls.adb-Make-reference-clock-frequen.patch | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 config/submodule/coreboot/dell7/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch (limited to 'config/submodule/coreboot/dell7/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch') diff --git a/config/submodule/coreboot/dell7/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch b/config/submodule/coreboot/dell7/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch new file mode 100644 index 00000000..2d248941 --- /dev/null +++ b/config/submodule/coreboot/dell7/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch @@ -0,0 +1,42 @@ +From ba078864500de99c26b6ea7e3fdcef19bca582a7 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Mon, 20 May 2024 10:10:03 -0600 +Subject: [PATCH 1/1] g45/hw-gfx-gma-plls.adb: Make reference clock frequency + configurable + +Instead of assuming a 96 MHz reference clock frequency, use the value +specified by the new INTEL_GMA_DPLL_REF_FREQ Kconfig. This defaults to +96 MHz to preserve the existing behavior. An example of where this is +needed is the DPLL_REF_SSCLK input, which will typically be 100 MHz +to support LVDS spread spectrum clocking. + +Signed-off-by: Nicholas Chin +--- + common/g45/hw-gfx-gma-plls.adb | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/common/g45/hw-gfx-gma-plls.adb b/common/g45/hw-gfx-gma-plls.adb +index 67242f2..5e970d7 100644 +--- a/common/g45/hw-gfx-gma-plls.adb ++++ b/common/g45/hw-gfx-gma-plls.adb +@@ -12,6 +12,8 @@ + -- GNU General Public License for more details. + -- + ++with CB.Config; ++ + with HW.Time; + with HW.GFX.GMA.Config; + with HW.GFX.GMA.Registers; +@@ -460,7 +462,7 @@ is + (Display => Port_Cfg.Display, + Target_Dotclock => Target_Clock, + -- should be, but doesn't has to be always the same: +- Reference_Clock => 96_000_000, ++ Reference_Clock => CB.Config.INTEL_GMA_DPLL_REF_FREQ, + Best_Clock => Clk, + Valid => Success); + else +-- +2.39.2 + -- cgit v1.2.1