From 7b009049e6c40bd142905dd1b315e1302489cefa Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 21 Sep 2026 09:15:09 +0100 Subject: coreboot/default: use latest revision, 18-Sep-2026 Updated to coreboot revision: 8ce4c91c41da3f042979f92095149a85bc93227d Up to date as of 18 September 2026. crossgcc tarballs updated (subfiles), and their versions: * update to acpica 20251212 * update to binutils 2.46.1 * update to gcc 15.2.0 * update to mpc 1.4.1 * update to nasm 3.02 submodules updated (git repos), and their new revisions: * arm-trusted-firmware b5eaba47efc5e4e3029086d5c25eee0e8dbb0129 * fsp 98426bfd958eb7397c474ff5d440dc9a1d146215 * intel-microcode 927e65c8d5a6e4ec05cc74b1778283ab2284d0c1 * libgfxinit 6e74c703132a8b4af4354a5158f286dc8f2407ab * libhwbase 61f7287f18b249408a79bf9ab5e72568965cca2c * vboot 5c360ef458b0a013d8a6d47724bb0fffb5accbcf Signed-off-by: Leah Rowe --- ...029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'config/module/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch') diff --git a/config/module/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/module/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch index 78ccf785..50cdd870 100644 --- a/config/module/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch +++ b/config/module/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch @@ -1,7 +1,7 @@ -From 95a0af0eea56e1bddcb243ed135835448b90fa56 Mon Sep 17 00:00:00 2001 +From 2f493545f7e895b8eca3e8b9f7d83d354b0105bc Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 6 Jan 2025 01:36:23 +0000 -Subject: [PATCH 29/48] src/intel/skylake: Disable stack overflow debug options +Subject: [PATCH 29/50] src/intel/skylake: Disable stack overflow debug options The option was appearing in T480/3050micro configs of lbmk, after updating on the coreboot/next uprev for 20241206 rev8: @@ -37,10 +37,10 @@ Signed-off-by: Leah Rowe 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 7c530f2c75..70c2a7643c 100644 +index beb6f13feea7..420dbf44f88c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig -@@ -131,6 +131,15 @@ config DCACHE_RAM_SIZE +@@ -137,6 +137,15 @@ config DCACHE_RAM_SIZE The size of the cache-as-ram region required during bootblock and/or romstage. -- cgit v1.2.1