From b4c3bafb0eb7de0cd836d66a1b675430645d8513 Mon Sep 17 00:00:00 2001 From: Riku Viitanen Date: Sat, 27 Sep 2025 10:53:05 +0300 Subject: New mainboard: X2E_N150 Patch in Gerrit: https://review.coreboot.org/c/coreboot/+/89281 Not working: USB3 ports only work at USB2 speeds. IFD: Modified the original by: - Removing Device Exp2 region (empty anyway) - Enlarging the BIOS region to use this freed space - Setting the HAP bit in PCHSTRP55 using a fork of me_cleaner: https://github.com/XutaxKamay/me_cleaner Signed-off-by: Riku Viitanen Signed-off-by: Leah Rowe --- config/coreboot/x2e_n150/target.cfg | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 config/coreboot/x2e_n150/target.cfg (limited to 'config/coreboot/x2e_n150/target.cfg') diff --git a/config/coreboot/x2e_n150/target.cfg b/config/coreboot/x2e_n150/target.cfg new file mode 100644 index 00000000..2d576527 --- /dev/null +++ b/config/coreboot/x2e_n150/target.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-3.0-or-later + +tree="default" +xarch="i386-elf" +payload_seabios="y" +payload_grub="y" +payload_memtest="y" +grub_scan_disk="nvme ahci" +grubtree="xhci" +vcfg="x2e_n150" +build_depend="seabios/default grub/xhci memtest86plus u-boot/amd64coreboot" +IFD_platform="adl" +payload_uboot="amd64" -- cgit v1.2.1