From 72e7d090c9deeba6a8ce27aa4c2e96246ad350f6 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 5 Nov 2023 12:58:54 +0000 Subject: coreboot: re-configure gm45 thinkpads from scratch TSEG Stage Cache enabled again, because disabling it did not affect S3 in any way. Many configs have changed, and debug level is set to 7. In testing with V-T60 on IRC, it wasn't just removal of the DDR2 patch that I did, but I re-did the configs too, in exactly the same way I've done them here, when testing on an X200 to fix boot issues. Libreboot does not use defconfigs, instead it uses full configs, and these have to be updated. I normally just run make-oldconfig on every config, for revision updates. However, every now and then, we need to re-do them. Play it safe and re-do every config. I've double- and triple-checked that the configs are correct. Signed-off-by: Leah Rowe --- config/coreboot/w500_8mb/target.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'config/coreboot/w500_8mb/target.cfg') diff --git a/config/coreboot/w500_8mb/target.cfg b/config/coreboot/w500_8mb/target.cfg index ffd4bc58..58ae8733 100644 --- a/config/coreboot/w500_8mb/target.cfg +++ b/config/coreboot/w500_8mb/target.cfg @@ -1,5 +1,5 @@ tree="default" -romtype="8MiB ICH9 IFD NOR flash" +romtype="normal" arch="x86_64" payload_grub="y" payload_grub_withseabios="y" -- cgit v1.2.1