From 614c5efa6550a0c1935965848a2b86382bf6c67a Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 25 Jan 2024 15:58:29 +0000 Subject: update coreboot/dell to same rev as default re-use the same patches, and drop the same patches. this tree uses hell's special ddr2 fix, which we apply for the dell latitude e6400. Signed-off-by: Leah Rowe --- ...ep-on-x200-t400-Revert-cpu-intel-model_10.patch | 47 ---------------------- 1 file changed, 47 deletions(-) delete mode 100644 config/coreboot/dell/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch (limited to 'config/coreboot/dell/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch') diff --git a/config/coreboot/dell/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch b/config/coreboot/dell/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch deleted file mode 100644 index 0f9b192d..00000000 --- a/config/coreboot/dell/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 3ec06fa2393995b87af1dbc0387c5d3255d5c0db Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Wed, 1 Dec 2021 02:53:00 +0000 -Subject: [PATCH 16/22] fix speedstep on x200/t400: Revert - "cpu/intel/model_1067x: enable PECI" - -This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f. - -Enabling PECI without microcode updates loaded causes the CPUID feature set -to become corrupted. And one consequence is broken SpeedStep. At least, that's -my understanding looking at Intel Errata. This revert is not a fix, because -upstream is correct (upstream assumes microcode updates). We will simply -maintain this revert patch in Libreboot, from now on. ---- - src/cpu/intel/model_1067x/model_1067x_init.c | 9 --------- - 1 file changed, 9 deletions(-) - -diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c -index 315e7c36fc..1423fd72bc 100644 ---- a/src/cpu/intel/model_1067x/model_1067x_init.c -+++ b/src/cpu/intel/model_1067x/model_1067x_init.c -@@ -141,8 +141,6 @@ static void configure_emttm_tables(void) - wrmsr(MSR_EMTTM_CR_TABLE(5), msr); - } - --#define IA32_PECI_CTL 0x5a0 -- - static void configure_misc(const int eist, const int tm2, const int emttm) - { - msr_t msr; -@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm) - msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); - } -- -- /* Enable PECI -- WARNING: due to Erratum AW67 described in Intel document #318733 -- the microcode must be updated before this MSR is written to. */ -- msr = rdmsr(IA32_PECI_CTL); -- msr.lo |= 1; -- wrmsr(IA32_PECI_CTL, msr); - } - - #define PIC_SENS_CFG 0x1aa --- -2.39.2 - -- cgit v1.2.1