From 42068f7ce11b88e13b4bf3f2d2290bc4d16d60b7 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 12 Oct 2023 23:12:17 +0100 Subject: coreboot/default bump: rev d862695f5f, 12 Oct 2023 Riku's mSATA patch for HP8300USDT was merged upstream, so the patch has been dropped from lbmk because it is contained within this new coreboot revision. Signed-off-by: Leah Rowe --- ...ok21-Set-default-VRAM-to-64MiB-instead-of.patch | 4 +- ...02-add-c3-and-clockgen-to-apple-macbook21.patch | 4 +- ...64MiB-Video-RAM-changed-to-default-previo.patch | 4 +- ...make-64MiB-VRAM-the-default-in-cmos.defau.patch | 4 +- ...o-t400-set-VRAM-to-256MiB-VRAM-by-default.patch | 4 +- ...lenovo-x200-set-VRAM-to-256MiB-by-default.patch | 4 +- ...a-g41m-es2l-set-VRAM-to-256MiB-by-default.patch | 4 +- ...er-g43t-am3-set-VRAM-to-256MiB-by-default.patch | 4 +- .../0009-lenovo-t400-Enable-all-SATA-ports.patch | 4 +- ...d-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch | 4 +- ...230-set-me_state-Disabled-in-cmos.default.patch | 4 +- ..._state-Disabled-on-all-cmos.default-files.patch | 4 +- .../0013-lenovo-x230-introduce-FHD-variant.patch | 4 +- ...-fix-the-data.vbt-path-for-the-EDP-varian.patch | 4 +- ...-ifdtool-add-nuke-flag-all-0xFF-on-region.patch | 4 +- ...ep-on-x200-t400-Revert-cpu-intel-model_10.patch | 4 +- ...5-type-CPUs-don-t-enable-alternative-SMRR.patch | 4 +- ...00-Enable-01.0-device-in-devicetree-for-d.patch | 4 +- ...ing-for-coreboot-images-built-without-a-p.patch | 4 +- ...5035-Add-command-to-enable-disable-radios.patch | 61 ++ .../patches/0020-hp8300usdt-enable-mSATA.patch | 32 - ...5035-Add-command-to-enable-disable-radios.patch | 61 -- ...c5035-Hook-up-radio-enables-to-option-API.patch | 37 + ...c5035-Hook-up-radio-enables-to-option-API.patch | 37 - ...022-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch | 820 +++++++++++++++++++++ ...023-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch | 820 --------------------- config/coreboot/default/target.cfg | 2 +- 27 files changed, 957 insertions(+), 989 deletions(-) create mode 100644 config/coreboot/default/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch delete mode 100644 config/coreboot/default/patches/0020-hp8300usdt-enable-mSATA.patch delete mode 100644 config/coreboot/default/patches/0021-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch create mode 100644 config/coreboot/default/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch delete mode 100644 config/coreboot/default/patches/0022-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch create mode 100644 config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch delete mode 100644 config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch (limited to 'config/coreboot/default') diff --git a/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch b/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch index 2e7dfbc0..c494390e 100644 --- a/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch +++ b/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch @@ -1,7 +1,7 @@ -From 21270ad036cdd1ee708a04c41ba6c4f279e4e6c0 Mon Sep 17 00:00:00 2001 +From e8f5f6c372152c7deddd3080954d0f4fdd39ae2b Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 19 Mar 2021 05:54:58 +0000 -Subject: [PATCH 01/19] apple/macbook21: Set default VRAM to 64MiB instead of +Subject: [PATCH 01/22] apple/macbook21: Set default VRAM to 64MiB instead of 8MiB --- diff --git a/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch index deb6b1fb..bf36faea 100644 --- a/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch +++ b/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch @@ -1,7 +1,7 @@ -From 6fa4c1488911b98e29d3e2858be68b9b72182573 Mon Sep 17 00:00:00 2001 +From fdd756a8217548981a1eb62e504cc37371c9fd51 Mon Sep 17 00:00:00 2001 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> Date: Wed, 27 Oct 2021 13:36:01 +0200 -Subject: [PATCH 02/19] add c3 and clockgen to apple/macbook21 +Subject: [PATCH 02/22] add c3 and clockgen to apple/macbook21 --- src/mainboard/apple/macbook21/Kconfig | 1 + diff --git a/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch b/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch index 65606127..98943d72 100644 --- a/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch +++ b/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch @@ -1,7 +1,7 @@ -From 79d9155c71f6014ff6adb454fe65466642bc2413 Mon Sep 17 00:00:00 2001 +From c8332a8bac4986afec6c639f55c5876f83e50b76 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 3 Jan 2021 03:34:01 +0000 -Subject: [PATCH 03/19] lenovo/x60: 64MiB Video RAM changed to default +Subject: [PATCH 03/22] lenovo/x60: 64MiB Video RAM changed to default (previously it was 8MiB) --- diff --git a/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch b/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch index ca5d0a8f..0f1f7b1b 100644 --- a/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch +++ b/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch @@ -1,7 +1,7 @@ -From 51a20e0db3fb9bf26ce138c9a17abe963bb8b289 Mon Sep 17 00:00:00 2001 +From 2e3ad35c24a86cb3109f4e5139b9ffba931eb80b Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 22 Feb 2021 22:16:59 +0000 -Subject: [PATCH 04/19] lenovo/t60: make 64MiB VRAM the default in cmos.default +Subject: [PATCH 04/22] lenovo/t60: make 64MiB VRAM the default in cmos.default --- src/mainboard/lenovo/t60/cmos.default | 2 +- diff --git a/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch b/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch index a108a75c..0818f1f8 100644 --- a/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch +++ b/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch @@ -1,7 +1,7 @@ -From 400e23c5149ab53300f57d8334ab25645d27b0c8 Mon Sep 17 00:00:00 2001 +From 5fc03fbf8c7fa30588dab93c76b5532ce03b1610 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 14 May 2021 13:10:33 +0100 -Subject: [PATCH 05/19] lenovo/t400: set VRAM to 256MiB VRAM by default +Subject: [PATCH 05/22] lenovo/t400: set VRAM to 256MiB VRAM by default Signed-off-by: Leah Rowe --- diff --git a/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch index 3ba4b07a..cbb00058 100644 --- a/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch +++ b/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch @@ -1,7 +1,7 @@ -From 29e6f78973928ad9ae86b26d5cf308a2680c88bf Mon Sep 17 00:00:00 2001 +From 93f607fed477b3e63b7929808937436ac2898b34 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 14 May 2021 13:11:59 +0100 -Subject: [PATCH 06/19] lenovo/x200: set VRAM to 256MiB by default +Subject: [PATCH 06/22] lenovo/x200: set VRAM to 256MiB by default Signed-off-by: Leah Rowe --- diff --git a/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch index 5bbbccb4..bea37df8 100644 --- a/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch +++ b/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch @@ -1,7 +1,7 @@ -From 9339fbdd36ceed6b1606b7a6ff07404f4f2a2d6d Mon Sep 17 00:00:00 2001 +From 9faa780b2ac45bc1bf61aa252364ee3158c4cb10 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 14 May 2021 13:18:26 +0100 -Subject: [PATCH 07/19] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default +Subject: [PATCH 07/22] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default Signed-off-by: Leah Rowe --- diff --git a/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch index ab5c2279..949ea696 100644 --- a/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch +++ b/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch @@ -1,7 +1,7 @@ -From 54197e66c6ecf33743489be9ab0352cfc4b1ffe2 Mon Sep 17 00:00:00 2001 +From f1c59cd67446303a5cdf9107461247a63f894de3 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 14 May 2021 13:21:39 +0100 -Subject: [PATCH 08/19] acer/g43t-am3: set VRAM to 256MiB by default +Subject: [PATCH 08/22] acer/g43t-am3: set VRAM to 256MiB by default Signed-off-by: Leah Rowe --- diff --git a/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch index 1aa74086..9d901c45 100644 --- a/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch +++ b/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch @@ -1,7 +1,7 @@ -From bc4ef158c4c6836351a395e8f0ff24f7c6d1f2c6 Mon Sep 17 00:00:00 2001 +From 75858ba200a2a5835bca0af9b5f508a52ed978de Mon Sep 17 00:00:00 2001 From: persmule Date: Sun, 31 Oct 2021 23:33:26 +0000 -Subject: [PATCH 09/19] lenovo/t400: Enable all SATA ports +Subject: [PATCH 09/22] lenovo/t400: Enable all SATA ports There are 2 SATA ports on the chassis of t400(s), but at least one dock for t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its diff --git a/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch b/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch index c16884c5..297dd223 100644 --- a/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch +++ b/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch @@ -1,7 +1,7 @@ -From 5987d9e821931ce097e265c13ca80a2090d3d821 Mon Sep 17 00:00:00 2001 +From 2c103a71a37eb4db9d33928b2371a682ca04e65f Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 20 Dec 2021 01:29:31 +0000 -Subject: [PATCH 10/19] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by +Subject: [PATCH 10/22] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by default --- diff --git a/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch index 3a96bc3a..2fe4460d 100644 --- a/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch +++ b/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -1,7 +1,7 @@ -From e5a6fac5b3c75c5aa4ae5106ec336a18083fbab0 Mon Sep 17 00:00:00 2001 +From 040f15039fa59d70cd54b8fff5d947e155666aa1 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 3 Jan 2022 19:06:22 +0000 -Subject: [PATCH 11/19] lenovo/x230: set me_state=Disabled in cmos.default +Subject: [PATCH 11/22] lenovo/x230: set me_state=Disabled in cmos.default I only recently found out about this. It's possible to use me_cleaner to do the same thing, but some people might just flash coreboot and not do diff --git a/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch index 9efc5198..b0dba3ba 100644 --- a/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch +++ b/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -1,7 +1,7 @@ -From 03610ab506bdaca92c1623abd18b4812f92273ed Mon Sep 17 00:00:00 2001 +From 81febff42c66bd53e44176f14b651339b503a9f3 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 2 Mar 2022 21:50:01 +0000 -Subject: [PATCH 12/19] set me_state=Disabled on all cmos.default files! +Subject: [PATCH 12/22] set me_state=Disabled on all cmos.default files! yeah. why the hell isn't this the default diff --git a/config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch b/config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch index 9bc43e78..c940c9e1 100644 --- a/config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch +++ b/config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch @@ -1,7 +1,7 @@ -From f4e5f11762e4c54829e1d6515d7fd369d86ac9d7 Mon Sep 17 00:00:00 2001 +From c73269315626678c191ea494338581abdc417f21 Mon Sep 17 00:00:00 2001 From: Alexander Couzens Date: Sat, 19 Mar 2022 13:42:33 +0000 -Subject: [PATCH 13/19] lenovo/x230: introduce FHD variant +Subject: [PATCH 13/22] lenovo/x230: introduce FHD variant There is a modification for the x230 which uses the 2nd DP from the dock as the integrated panel's connection, which allows using a custom eDP diff --git a/config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch b/config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch index d391d0c3..83f99148 100644 --- a/config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch +++ b/config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch @@ -1,7 +1,7 @@ -From 982734642e0c8a960b99180371a5a12c3851b6e9 Mon Sep 17 00:00:00 2001 +From c32229e3f82c00abb2bee4d0f7ddf33d4c7a04dc Mon Sep 17 00:00:00 2001 From: Alexei Sorokin Date: Sun, 27 Nov 2022 18:36:26 +0300 -Subject: [PATCH 14/19] lenovo/x230: fix the data.vbt path for the EDP variant +Subject: [PATCH 14/22] lenovo/x230: fix the data.vbt path for the EDP variant --- src/mainboard/lenovo/x230/Kconfig | 2 +- diff --git a/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch index d8a701d9..6a293287 100644 --- a/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ b/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -1,7 +1,7 @@ -From 35425512e05c989d2d6789551cc448719ab1ca38 Mon Sep 17 00:00:00 2001 +From 38c76afbea4abfed2976bfbe10977e41f21665b0 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 15/19] util/ifdtool: add --nuke flag (all 0xFF on region) +Subject: [PATCH 15/22] util/ifdtool: add --nuke flag (all 0xFF on region) When this option is used, the region's contents are overwritten with all ones (0xFF). diff --git a/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch b/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch index df43eeb3..0f9b192d 100644 --- a/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch +++ b/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch @@ -1,7 +1,7 @@ -From 929974434bbd627ab7add5ef4ec4eb62e5412f57 Mon Sep 17 00:00:00 2001 +From 3ec06fa2393995b87af1dbc0387c5d3255d5c0db Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 1 Dec 2021 02:53:00 +0000 -Subject: [PATCH 16/19] fix speedstep on x200/t400: Revert +Subject: [PATCH 16/22] fix speedstep on x200/t400: Revert "cpu/intel/model_1067x: enable PECI" This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f. diff --git a/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch b/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch index 750628cf..4d7b3421 100644 --- a/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch +++ b/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch @@ -1,7 +1,7 @@ -From f5859da443fc1ff2450051d1d88bee56346fe63b Mon Sep 17 00:00:00 2001 +From fdde15b69bd5c8bf54339adf3581a32fa992a503 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 17 Apr 2023 15:49:57 +0100 -Subject: [PATCH 17/19] GM45-type CPUs: don't enable alternative SMRR +Subject: [PATCH 17/22] GM45-type CPUs: don't enable alternative SMRR This reverts the changes in coreboot revision: df7aecd92643d207feaf7fd840f8835097346644 diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch index 42fa8399..04f3bd63 100644 --- a/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ b/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -1,7 +1,7 @@ -From 6dc133e52c1ede4dbd3207133dd8ed0eb053fcd0 Mon Sep 17 00:00:00 2001 +From a65797a9e7e610b1c916cb4d275b72848622c218 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 18/19] mb/dell/e6400: Enable 01.0 device in devicetree for +Subject: [PATCH 18/22] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU models Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed diff --git a/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch index 85bf47a1..3f21ad02 100644 --- a/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,7 +1,7 @@ -From eb0fa411af62bf33cac69f3ba082e2d513bd9ab2 Mon Sep 17 00:00:00 2001 +From 7d5452bc3358cf82eea48fde312494bcb4ca8101 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 19/19] Remove warning for coreboot images built without a +Subject: [PATCH 19/22] Remove warning for coreboot images built without a payload I added this in upstream to prevent people from accidentally flashing diff --git a/config/coreboot/default/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch b/config/coreboot/default/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch new file mode 100644 index 00000000..2f2cddfe --- /dev/null +++ b/config/coreboot/default/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch @@ -0,0 +1,61 @@ +From f0db13a15c76c2947eec8919fd121450048914ce Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Sun, 27 Aug 2023 17:36:36 -0600 +Subject: [PATCH 20/22] ec/dell/mec5035: Add command to enable/disable radios + +These were determined by sniffing the LPC bus while toggling the +hardware wireless switch on the Latitude E6400. To differentiate devices +options in the vendor BIOS to change which radios the switch controlled +were used. + +Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b +Signed-off-by: Nicholas Chin +--- + src/ec/dell/mec5035/mec5035.c | 9 +++++++++ + src/ec/dell/mec5035/mec5035.h | 8 ++++++++ + 2 files changed, 17 insertions(+) + +diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c +index 8da11e5b1c..e0335a4635 100644 +--- a/src/ec/dell/mec5035/mec5035.c ++++ b/src/ec/dell/mec5035/mec5035.c +@@ -84,6 +84,15 @@ u8 mec5035_mouse_touchpad(u8 setting) + return buf[0]; + } + ++void mec5035_radio_enable(enum mec5035_radio_dev dev, u8 on) ++{ ++ /* From LPC traces and userspace testing with other values, ++ the second byte has to be 2 for an unknown reason. */ ++ u8 buf[3] = {dev, 2, on}; ++ write_mailbox_regs(buf, 2, 3); ++ ec_command(CMD_RADIO_EN); ++} ++ + void mec5035_early_init(void) + { + /* If this isn't sent the EC shuts down the system after about 15 +diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h +index e7a05b64d4..16512e2cc2 100644 +--- a/src/ec/dell/mec5035/mec5035.h ++++ b/src/ec/dell/mec5035/mec5035.h +@@ -16,8 +16,16 @@ + + #define CMD_CPU_OK 0xc2 + ++#define CMD_RADIO_EN 0x2b ++enum mec5035_radio_dev { ++ RADIO_WLAN = 0, ++ RADIO_WWAN = 1, ++ RADIO_WPAN = 2, ++}; ++ + u8 mec5035_mouse_touchpad(u8 setting); + void mec5035_cpu_ok(void); + void mec5035_early_init(void); ++void mec5035_radio_enable(enum mec5035_radio_dev device, u8 on); + + #endif /* _EC_DELL_MEC5035_H_ */ +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0020-hp8300usdt-enable-mSATA.patch b/config/coreboot/default/patches/0020-hp8300usdt-enable-mSATA.patch deleted file mode 100644 index 22e06c98..00000000 --- a/config/coreboot/default/patches/0020-hp8300usdt-enable-mSATA.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 19ebc65d2c5854d9dea6f4a710ebfa695c80f030 Mon Sep 17 00:00:00 2001 -From: Riku Viitanen -Date: Tue, 22 Aug 2023 20:07:22 +0300 -Subject: [PATCH] mb/hp8300usdt: enable mSATA - -Enables the mSATA slot on HP Compaq Elite 8300 USDT. -Tested, it works at the same speed as vendor FW (3Gb/s). - -Signed-off-by: Riku Viitanen ---- - src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb -index ba4ac6d7f2..f7f321fc83 100644 ---- a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb -+++ b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb -@@ -9,9 +9,9 @@ chip northbridge/intel/sandybridge - register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" - register "sata_interface_speed_support" = "0x3" -- register "sata_port_map" = "0x3" # 0x1: 2.5" slot -+ register "sata_port_map" = "0x7" # 0x1: 2.5" slot - # 0x2: DVD -- # 0x?: mSATA -+ # 0x4: mSATA - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - register "superspeed_capable_ports" = "0x0000000f" --- -2.41.0 - diff --git a/config/coreboot/default/patches/0021-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch b/config/coreboot/default/patches/0021-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch deleted file mode 100644 index f3dad1e1..00000000 --- a/config/coreboot/default/patches/0021-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch +++ /dev/null @@ -1,61 +0,0 @@ -From f4c41a930b777128bd418cbae525ba509e5f19ff Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Sun, 27 Aug 2023 17:36:36 -0600 -Subject: [PATCH 1/3] ec/dell/mec5035: Add command to enable/disable radios - -These were determined by sniffing the LPC bus while toggling the -hardware wireless switch on the Latitude E6400. To differentiate devices -options in the vendor BIOS to change which radios the switch controlled -were used. - -Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b -Signed-off-by: Nicholas Chin ---- - src/ec/dell/mec5035/mec5035.c | 9 +++++++++ - src/ec/dell/mec5035/mec5035.h | 8 ++++++++ - 2 files changed, 17 insertions(+) - -diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index 8da11e5b1c..e0335a4635 100644 ---- a/src/ec/dell/mec5035/mec5035.c -+++ b/src/ec/dell/mec5035/mec5035.c -@@ -84,6 +84,15 @@ u8 mec5035_mouse_touchpad(u8 setting) - return buf[0]; - } - -+void mec5035_radio_enable(enum mec5035_radio_dev dev, u8 on) -+{ -+ /* From LPC traces and userspace testing with other values, -+ the second byte has to be 2 for an unknown reason. */ -+ u8 buf[3] = {dev, 2, on}; -+ write_mailbox_regs(buf, 2, 3); -+ ec_command(CMD_RADIO_EN); -+} -+ - void mec5035_early_init(void) - { - /* If this isn't sent the EC shuts down the system after about 15 -diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h -index e7a05b64d4..16512e2cc2 100644 ---- a/src/ec/dell/mec5035/mec5035.h -+++ b/src/ec/dell/mec5035/mec5035.h -@@ -16,8 +16,16 @@ - - #define CMD_CPU_OK 0xc2 - -+#define CMD_RADIO_EN 0x2b -+enum mec5035_radio_dev { -+ RADIO_WLAN = 0, -+ RADIO_WWAN = 1, -+ RADIO_WPAN = 2, -+}; -+ - u8 mec5035_mouse_touchpad(u8 setting); - void mec5035_cpu_ok(void); - void mec5035_early_init(void); -+void mec5035_radio_enable(enum mec5035_radio_dev device, u8 on); - - #endif /* _EC_DELL_MEC5035_H_ */ --- -2.42.0 - diff --git a/config/coreboot/default/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch b/config/coreboot/default/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch new file mode 100644 index 00000000..d02ad724 --- /dev/null +++ b/config/coreboot/default/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch @@ -0,0 +1,37 @@ +From 4537c365dae010645404fdb5d2d4e5f478dede67 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Sun, 27 Aug 2023 19:15:37 -0600 +Subject: [PATCH 21/22] ec/dell/mec5035: Hook up radio enables to option API + +Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db +Signed-off-by: Nicholas Chin +--- + src/ec/dell/mec5035/mec5035.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c +index e0335a4635..20a33cc0ad 100644 +--- a/src/ec/dell/mec5035/mec5035.c ++++ b/src/ec/dell/mec5035/mec5035.c +@@ -4,6 +4,7 @@ + #include + #include + #include ++#include + #include + #include + #include "mec5035.h" +@@ -108,6 +109,10 @@ static void mec5035_init(struct device *dev) + mec5035_mouse_touchpad(TP_PS2_MOUSE); + + pc_keyboard_init(NO_AUX_DEVICE); ++ ++ mec5035_radio_enable(RADIO_WLAN, get_uint_option("wlan", 1)); ++ mec5035_radio_enable(RADIO_WWAN, get_uint_option("wwan", 1)); ++ mec5035_radio_enable(RADIO_WPAN, get_uint_option("bluetooth", 1)); + } + + static struct device_operations ops = { +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0022-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch b/config/coreboot/default/patches/0022-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch deleted file mode 100644 index 48fda76b..00000000 --- a/config/coreboot/default/patches/0022-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 1b607998e3e7054ce1107ba6af48902f6b6ffb02 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Sun, 27 Aug 2023 19:15:37 -0600 -Subject: [PATCH 2/3] ec/dell/mec5035: Hook up radio enables to option API - -Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db -Signed-off-by: Nicholas Chin ---- - src/ec/dell/mec5035/mec5035.c | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index e0335a4635..20a33cc0ad 100644 ---- a/src/ec/dell/mec5035/mec5035.c -+++ b/src/ec/dell/mec5035/mec5035.c -@@ -4,6 +4,7 @@ - #include - #include - #include -+#include - #include - #include - #include "mec5035.h" -@@ -108,6 +109,10 @@ static void mec5035_init(struct device *dev) - mec5035_mouse_touchpad(TP_PS2_MOUSE); - - pc_keyboard_init(NO_AUX_DEVICE); -+ -+ mec5035_radio_enable(RADIO_WLAN, get_uint_option("wlan", 1)); -+ mec5035_radio_enable(RADIO_WWAN, get_uint_option("wwan", 1)); -+ mec5035_radio_enable(RADIO_WPAN, get_uint_option("bluetooth", 1)); - } - - static struct device_operations ops = { --- -2.42.0 - diff --git a/config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch b/config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch new file mode 100644 index 00000000..e38f243d --- /dev/null +++ b/config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch @@ -0,0 +1,820 @@ +From db1cb588b64f17c7ed08201bf1e09ab5393e4b04 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Sat, 19 Aug 2023 16:19:10 -0600 +Subject: [PATCH 22/22] mb/dell: Add Latitude E6430 (Ivy Bridge) + +Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested. +This is based on the autoport output with some manual tweaks. The flash +is 8MiB + 4MiB, and is fairly easily accessed by removing the keyboard. +It can also be internally flashed by sending a command to the EC, which +causes the EC to pull the FDO pin low and the firmware to skip setting +up any chipset based write protections. [1] The EC is the SMSC MEC5055, +which seems to be compatible with the existing MEC5035 code. + +Working: +- Libgfxinit +- USB EHCI debug (left side usb port is HCD index 2, middle port on the + right side is HCD index 1) +- Keyboard +- Touchpad/trackpoint +- ExpressCard +- Audio +- Ethernet +- SD card reader +- mPCIe WiFi +- SeaBIOS 1.16.2 +- edk2 (MrChromebox' fork, uefipayload_202306) +- Internal flashing + +Not working: +- S3 suspend: It seems like the EC also controls the DRAM reset gate so + there may be a command that needs to be implemented for this +- Physical Wireless switch +- Battery reporting +- Brightness hotkeys + +Unknown/untested: +- Dock +- eSATA +- TPM +- dGPU on non-UMA model + +[1] https://github.com/nic3-14159/e6400-flash-unlock + +Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/e6430/Kconfig | 36 ++++ + src/mainboard/dell/e6430/Kconfig.name | 2 + + src/mainboard/dell/e6430/Makefile.inc | 6 + + src/mainboard/dell/e6430/acpi/ec.asl | 9 + + src/mainboard/dell/e6430/acpi/platform.asl | 12 ++ + src/mainboard/dell/e6430/acpi/superio.asl | 3 + + src/mainboard/dell/e6430/acpi_tables.c | 16 ++ + src/mainboard/dell/e6430/board_info.txt | 6 + + src/mainboard/dell/e6430/cmos.default | 9 + + src/mainboard/dell/e6430/cmos.layout | 88 ++++++++++ + src/mainboard/dell/e6430/data.vbt | Bin 0 -> 6144 bytes + src/mainboard/dell/e6430/devicetree.cb | 68 ++++++++ + src/mainboard/dell/e6430/dsdt.asl | 30 ++++ + src/mainboard/dell/e6430/early_init.c | 38 ++++ + src/mainboard/dell/e6430/gma-mainboard.ads | 20 +++ + src/mainboard/dell/e6430/gpio.c | 192 +++++++++++++++++++++ + src/mainboard/dell/e6430/hda_verb.c | 33 ++++ + src/mainboard/dell/e6430/mainboard.c | 21 +++ + 18 files changed, 589 insertions(+) + create mode 100644 src/mainboard/dell/e6430/Kconfig + create mode 100644 src/mainboard/dell/e6430/Kconfig.name + create mode 100644 src/mainboard/dell/e6430/Makefile.inc + create mode 100644 src/mainboard/dell/e6430/acpi/ec.asl + create mode 100644 src/mainboard/dell/e6430/acpi/platform.asl + create mode 100644 src/mainboard/dell/e6430/acpi/superio.asl + create mode 100644 src/mainboard/dell/e6430/acpi_tables.c + create mode 100644 src/mainboard/dell/e6430/board_info.txt + create mode 100644 src/mainboard/dell/e6430/cmos.default + create mode 100644 src/mainboard/dell/e6430/cmos.layout + create mode 100644 src/mainboard/dell/e6430/data.vbt + create mode 100644 src/mainboard/dell/e6430/devicetree.cb + create mode 100644 src/mainboard/dell/e6430/dsdt.asl + create mode 100644 src/mainboard/dell/e6430/early_init.c + create mode 100644 src/mainboard/dell/e6430/gma-mainboard.ads + create mode 100644 src/mainboard/dell/e6430/gpio.c + create mode 100644 src/mainboard/dell/e6430/hda_verb.c + create mode 100644 src/mainboard/dell/e6430/mainboard.c + +diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig +new file mode 100644 +index 0000000000..3178d12aff +--- /dev/null ++++ b/src/mainboard/dell/e6430/Kconfig +@@ -0,0 +1,36 @@ ++if BOARD_DELL_LATITUDE_E6430 ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ select BOARD_ROMSIZE_KB_12288 ++ select EC_ACPI ++ select EC_DELL_MEC5035 ++ select GFX_GMA_PANEL_1_ON_LVDS ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ select INTEL_INT15 ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select NORTHBRIDGE_INTEL_SANDYBRIDGE ++ select SERIRQ_CONTINUOUS_MODE ++ select SOUTHBRIDGE_INTEL_C216 ++ select SYSTEM_TYPE_LAPTOP ++ select USE_NATIVE_RAMINIT ++ ++config MAINBOARD_DIR ++ default "dell/e6430" ++ ++config MAINBOARD_PART_NUMBER ++ default "Latitude E6430" ++ ++config VGA_BIOS_ID ++ default "8086,0166" ++ ++config DRAM_RESET_GATE_GPIO ++ default 60 ++ ++config USBDEBUG_HCD_INDEX ++ default 2 ++endif +diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name +new file mode 100644 +index 0000000000..f866b03585 +--- /dev/null ++++ b/src/mainboard/dell/e6430/Kconfig.name +@@ -0,0 +1,2 @@ ++config BOARD_DELL_LATITUDE_E6430 ++ bool "Latitude E6430" +diff --git a/src/mainboard/dell/e6430/Makefile.inc b/src/mainboard/dell/e6430/Makefile.inc +new file mode 100644 +index 0000000000..ba64e93eb8 +--- /dev/null ++++ b/src/mainboard/dell/e6430/Makefile.inc +@@ -0,0 +1,6 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++bootblock-y += early_init.c ++bootblock-y += gpio.c ++romstage-y += early_init.c ++romstage-y += gpio.c ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +diff --git a/src/mainboard/dell/e6430/acpi/ec.asl b/src/mainboard/dell/e6430/acpi/ec.asl +new file mode 100644 +index 0000000000..0d429410a9 +--- /dev/null ++++ b/src/mainboard/dell/e6430/acpi/ec.asl +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++Device(EC) ++{ ++ Name (_HID, EISAID("PNP0C09")) ++ Name (_UID, 0) ++ Name (_GPE, 16) ++/* FIXME: EC support */ ++} +diff --git a/src/mainboard/dell/e6430/acpi/platform.asl b/src/mainboard/dell/e6430/acpi/platform.asl +new file mode 100644 +index 0000000000..2d24bbd9b9 +--- /dev/null ++++ b/src/mainboard/dell/e6430/acpi/platform.asl +@@ -0,0 +1,12 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++Method(_WAK, 1) ++{ ++ /* FIXME: EC support */ ++ Return(Package() {0, 0}) ++} ++ ++Method(_PTS,1) ++{ ++ /* FIXME: EC support */ ++} +diff --git a/src/mainboard/dell/e6430/acpi/superio.asl b/src/mainboard/dell/e6430/acpi/superio.asl +new file mode 100644 +index 0000000000..55b1db5b11 +--- /dev/null ++++ b/src/mainboard/dell/e6430/acpi/superio.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include +diff --git a/src/mainboard/dell/e6430/acpi_tables.c b/src/mainboard/dell/e6430/acpi_tables.c +new file mode 100644 +index 0000000000..e2759659bf +--- /dev/null ++++ b/src/mainboard/dell/e6430/acpi_tables.c +@@ -0,0 +1,16 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++/* FIXME: check this function. */ ++void mainboard_fill_gnvs(struct global_nvs *gnvs) ++{ ++ /* The lid is open by default. */ ++ gnvs->lids = 1; ++ ++ /* Temperature at which OS will shutdown */ ++ gnvs->tcrt = 100; ++ /* Temperature at which OS will throttle CPU */ ++ gnvs->tpsv = 90; ++} +diff --git a/src/mainboard/dell/e6430/board_info.txt b/src/mainboard/dell/e6430/board_info.txt +new file mode 100644 +index 0000000000..4601a4aaba +--- /dev/null ++++ b/src/mainboard/dell/e6430/board_info.txt +@@ -0,0 +1,6 @@ ++Category: laptop ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y ++Release year: 2012 +diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default +new file mode 100644 +index 0000000000..2a5b30f2b7 +--- /dev/null ++++ b/src/mainboard/dell/e6430/cmos.default +@@ -0,0 +1,9 @@ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Disable ++nmi=Enable ++bluetooth=Enable ++wwan=Enable ++wlan=Enable ++sata_mode=AHCI ++me_state=Normal +diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout +new file mode 100644 +index 0000000000..e85ea4c661 +--- /dev/null ++++ b/src/mainboard/dell/e6430/cmos.layout +@@ -0,0 +1,88 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++ ++#400 8 r 0 reserved for century byte ++ ++# coreboot config options: southbridge ++408 1 e 1 nmi ++409 2 e 7 power_on_after_fail ++411 1 e 9 sata_mode ++ ++# coreboot config options: EC ++412 1 e 1 bluetooth ++413 1 e 1 wwan ++415 1 e 1 wlan ++ ++# coreboot config options: ME ++424 1 e 14 me_state ++425 2 h 0 me_state_prev ++ ++# coreboot config options: northbridge ++432 3 e 11 gfx_uma_size ++435 2 e 12 hybrid_graphics_mode ++440 8 h 0 volume ++ ++# VBOOT ++448 128 r 0 vbnv ++ ++# SandyBridge MRC Scrambler Seed values ++896 32 r 0 mrc_scrambler_seed ++928 32 r 0 mrc_scrambler_seed_s3 ++960 16 r 0 mrc_scrambler_seed_chk ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++2 0 Enable ++2 1 Disable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++9 0 AHCI ++9 1 Compatible ++11 0 32M ++11 1 64M ++11 2 96M ++11 3 128M ++11 4 160M ++11 5 192M ++11 6 224M ++14 0 Normal ++14 1 Disabled ++ ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 447 984 +diff --git a/src/mainboard/dell/e6430/data.vbt b/src/mainboard/dell/e6430/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..08952c26ab82933ebb5cc5b9c7e2265963a87b2d +GIT binary patch +literal 6144 +zcmeHKU2Gdw7XHRFw#VZc+nI!tq)j-qG$b@>#vu)%WW~fb!7ZV6LkJc^+qlG~(WXgp +zLU)l?#Jhyj)dGqHf<6H13kV^8g;enZDm*~=5kd&@Cn1Fu52*0a2hgri!F%q^IFQ;) +zjkMh#DR=zcpL5Use9xJ4?#x^=mKdcQb|t!Zj3v6R-<{Yod<{*&!ppI%xUMXT9lLMX +zn;IM)+?yEQoxF~o#5x>}{dfwPkR;RSiC=!jj_JAlRQpJWpd}$VY+XtFX9|?cO&y#m +zIdrG4zSq6a*B6 +zRA?%66|w}s0z*YuMNq*73a(KQQ8A>TT}4_&3_e5hDZs@lHpaYN60rOh%jBQN+*9zu +zIASsRL<3j>pYk93g@PXvaUZbpk)yEWDA4C2Ai!cNXi4M~3gjt#<|(LxR49-{<^K|T +zqL5SnLUq0r*kw>Q!0PGk>)$?LCsIS{ox_=t(Xs5!w-o>M=erl0apv_Z`-(^w_5@pz +z)}lBfx8o(*hgal&)aMG1rKzf_^2m;)RTu!i#rBrUK{pWM_5BuDg}f1vGgAMqNM&t?7(IQ +zcDa=Dn9^Q5?6k6+@y4UvvL3SDxKs*_^RS1n^H*!{fYZz^rPBXmV(=eO(Cd-pvqPqVBRYz~7nA{nO7|Kv{w^;?LXb8F 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++ ++ Device (\_SB.PCI0) ++ { ++ #include ++ #include ++ #include ++ } ++} +diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c +new file mode 100644 +index 0000000000..7944157f59 +--- /dev/null ++++ b/src/mainboard/dell/e6430/early_init.c +@@ -0,0 +1,38 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++ ++const struct southbridge_usb_port mainboard_usb_ports[] = { ++ { 1, 1, 0 }, ++ { 1, 1, 0 }, ++ { 1, 1, 1 }, ++ { 1, 1, 1 }, ++ { 1, 0, 2 }, ++ { 1, 1, 2 }, ++ { 1, 1, 3 }, ++ { 1, 1, 3 }, ++ { 1, 1, 4 }, ++ { 1, 1, 4 }, ++ { 1, 1, 5 }, ++ { 1, 1, 5 }, ++ { 1, 2, 6 }, ++ { 1, 2, 6 }, ++}; ++ ++void bootblock_mainboard_early_init(void) ++{ ++ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f); ++ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); ++ mec5035_early_init(); ++} ++ ++void mainboard_get_spd(spd_raw_data *spd, bool id_only) ++{ ++ read_spd(&spd[0], 0x50, id_only); ++ read_spd(&spd[2], 0x52, id_only); ++} +diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads +new file mode 100644 +index 0000000000..1310830c8e +--- /dev/null ++++ b/src/mainboard/dell/e6430/gma-mainboard.ads +@@ -0,0 +1,20 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ ( ++ HDMI1, -- mainboard HDMI ++ DP2, -- dock DP ++ DP3, -- dock DP ++ Analog, --mainboard VGA ++ LVDS, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/e6430/gpio.c b/src/mainboard/dell/e6430/gpio.c +new file mode 100644 +index 0000000000..777570765a +--- /dev/null ++++ b/src/mainboard/dell/e6430/gpio.c +@@ -0,0 +1,192 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_GPIO, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_NATIVE, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio1 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio28 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++ .gpio30 = GPIO_RESET_RSMRST, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio0 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++ .gpio13 = GPIO_INVERT, ++ .gpio14 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_GPIO, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_NATIVE, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_OUTPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio45 = GPIO_DIR_OUTPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_INPUT, ++ .gpio51 = GPIO_DIR_INPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio34 = GPIO_LEVEL_HIGH, ++ .gpio45 = GPIO_LEVEL_LOW, ++ .gpio60 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_GPIO, ++ .gpio69 = GPIO_MODE_GPIO, ++ .gpio70 = GPIO_MODE_GPIO, ++ .gpio71 = GPIO_MODE_GPIO, ++ .gpio72 = GPIO_MODE_NATIVE, ++ .gpio73 = GPIO_MODE_NATIVE, ++ .gpio74 = GPIO_MODE_NATIVE, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio68 = GPIO_DIR_INPUT, ++ .gpio69 = GPIO_DIR_INPUT, ++ .gpio70 = GPIO_DIR_INPUT, ++ .gpio71 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/dell/e6430/hda_verb.c b/src/mainboard/dell/e6430/hda_verb.c +new file mode 100644 +index 0000000000..56ada95c58 +--- /dev/null ++++ b/src/mainboard/dell/e6430/hda_verb.c +@@ -0,0 +1,33 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ 0x111d76df, /* Codec Vendor / Device ID: IDT */ ++ 0x10280534, /* Subsystem ID */ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x10280534), ++ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), ++ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), ++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), ++ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), ++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), ++ ++ 0x80862806, /* Codec Vendor / Device ID: Intel */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(3, 0x80860101), ++ AZALIA_PIN_CFG(3, 0x05, 0x18560010), ++ AZALIA_PIN_CFG(3, 0x06, 0x18560020), ++ AZALIA_PIN_CFG(3, 0x07, 0x18560030), ++ ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/e6430/mainboard.c b/src/mainboard/dell/e6430/mainboard.c +new file mode 100644 +index 0000000000..31e49802fc +--- /dev/null ++++ b/src/mainboard/dell/e6430/mainboard.c +@@ -0,0 +1,21 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static void mainboard_enable(struct device *dev) ++{ ++ ++ /* FIXME: fix these values. */ ++ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, ++ GMA_INT15_PANEL_FIT_DEFAULT, ++ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); ++} ++ ++struct chip_operations mainboard_ops = { ++ .enable_dev = mainboard_enable, ++}; +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch b/config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch deleted file mode 100644 index be3d1189..00000000 --- a/config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch +++ /dev/null @@ -1,820 +0,0 @@ -From e4e508c3375d38c434678a2e0652b55e7ea79fc5 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Sat, 19 Aug 2023 16:19:10 -0600 -Subject: [PATCH 3/3] mb/dell: Add Latitude E6430 (Ivy Bridge) - -Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested. -This is based on the autoport output with some manual tweaks. The flash -is 8MiB + 4MiB, and is fairly easily accessed by removing the keyboard. -It can also be internally flashed by sending a command to the EC, which -causes the EC to pull the FDO pin low and the firmware to skip setting -up any chipset based write protections. [1] The EC is the SMSC MEC5055, -which seems to be compatible with the existing MEC5035 code. - -Working: -- Libgfxinit -- USB EHCI debug (left side usb port is HCD index 2, middle port on the - right side is HCD index 1) -- Keyboard -- Touchpad/trackpoint -- ExpressCard -- Audio -- Ethernet -- SD card reader -- mPCIe WiFi -- SeaBIOS 1.16.2 -- edk2 (MrChromebox' fork, uefipayload_202306) -- Internal flashing - -Not working: -- S3 suspend: It seems like the EC also controls the DRAM reset gate so - there may be a command that needs to be implemented for this -- Physical Wireless switch -- Battery reporting -- Brightness hotkeys - -Unknown/untested: -- Dock -- eSATA -- TPM -- dGPU on non-UMA model - -[1] https://github.com/nic3-14159/e6400-flash-unlock - -Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/e6430/Kconfig | 36 ++++ - src/mainboard/dell/e6430/Kconfig.name | 2 + - src/mainboard/dell/e6430/Makefile.inc | 6 + - src/mainboard/dell/e6430/acpi/ec.asl | 9 + - src/mainboard/dell/e6430/acpi/platform.asl | 12 ++ - src/mainboard/dell/e6430/acpi/superio.asl | 3 + - src/mainboard/dell/e6430/acpi_tables.c | 16 ++ - src/mainboard/dell/e6430/board_info.txt | 6 + - src/mainboard/dell/e6430/cmos.default | 9 + - src/mainboard/dell/e6430/cmos.layout | 88 ++++++++++ - src/mainboard/dell/e6430/data.vbt | Bin 0 -> 6144 bytes - src/mainboard/dell/e6430/devicetree.cb | 68 ++++++++ - src/mainboard/dell/e6430/dsdt.asl | 30 ++++ - src/mainboard/dell/e6430/early_init.c | 38 ++++ - src/mainboard/dell/e6430/gma-mainboard.ads | 20 +++ - src/mainboard/dell/e6430/gpio.c | 192 +++++++++++++++++++++ - src/mainboard/dell/e6430/hda_verb.c | 33 ++++ - src/mainboard/dell/e6430/mainboard.c | 21 +++ - 18 files changed, 589 insertions(+) - create mode 100644 src/mainboard/dell/e6430/Kconfig - create mode 100644 src/mainboard/dell/e6430/Kconfig.name - create mode 100644 src/mainboard/dell/e6430/Makefile.inc - create mode 100644 src/mainboard/dell/e6430/acpi/ec.asl - create mode 100644 src/mainboard/dell/e6430/acpi/platform.asl - create mode 100644 src/mainboard/dell/e6430/acpi/superio.asl - create mode 100644 src/mainboard/dell/e6430/acpi_tables.c - create mode 100644 src/mainboard/dell/e6430/board_info.txt - create mode 100644 src/mainboard/dell/e6430/cmos.default - create mode 100644 src/mainboard/dell/e6430/cmos.layout - create mode 100644 src/mainboard/dell/e6430/data.vbt - create mode 100644 src/mainboard/dell/e6430/devicetree.cb - create mode 100644 src/mainboard/dell/e6430/dsdt.asl - create mode 100644 src/mainboard/dell/e6430/early_init.c - create mode 100644 src/mainboard/dell/e6430/gma-mainboard.ads - create mode 100644 src/mainboard/dell/e6430/gpio.c - create mode 100644 src/mainboard/dell/e6430/hda_verb.c - create mode 100644 src/mainboard/dell/e6430/mainboard.c - -diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig -new file mode 100644 -index 0000000000..3178d12aff ---- /dev/null -+++ b/src/mainboard/dell/e6430/Kconfig -@@ -0,0 +1,36 @@ -+if BOARD_DELL_LATITUDE_E6430 -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ select BOARD_ROMSIZE_KB_12288 -+ select EC_ACPI -+ select EC_DELL_MEC5035 -+ select GFX_GMA_PANEL_1_ON_LVDS -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ select INTEL_INT15 -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_USES_IFD_GBE_REGION -+ select NORTHBRIDGE_INTEL_SANDYBRIDGE -+ select SERIRQ_CONTINUOUS_MODE -+ select SOUTHBRIDGE_INTEL_C216 -+ select SYSTEM_TYPE_LAPTOP -+ select USE_NATIVE_RAMINIT -+ -+config MAINBOARD_DIR -+ default "dell/e6430" -+ -+config MAINBOARD_PART_NUMBER -+ default "Latitude E6430" -+ -+config VGA_BIOS_ID -+ default "8086,0166" -+ -+config DRAM_RESET_GATE_GPIO -+ default 60 -+ -+config USBDEBUG_HCD_INDEX -+ default 2 -+endif -diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name -new file mode 100644 -index 0000000000..f866b03585 ---- /dev/null -+++ b/src/mainboard/dell/e6430/Kconfig.name -@@ -0,0 +1,2 @@ -+config BOARD_DELL_LATITUDE_E6430 -+ bool "Latitude E6430" -diff --git a/src/mainboard/dell/e6430/Makefile.inc b/src/mainboard/dell/e6430/Makefile.inc -new file mode 100644 -index 0000000000..ba64e93eb8 ---- /dev/null -+++ b/src/mainboard/dell/e6430/Makefile.inc -@@ -0,0 +1,6 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+bootblock-y += early_init.c -+bootblock-y += gpio.c -+romstage-y += early_init.c -+romstage-y += gpio.c -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -diff --git a/src/mainboard/dell/e6430/acpi/ec.asl b/src/mainboard/dell/e6430/acpi/ec.asl -new file mode 100644 -index 0000000000..0d429410a9 ---- /dev/null -+++ b/src/mainboard/dell/e6430/acpi/ec.asl -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Device(EC) -+{ -+ Name (_HID, EISAID("PNP0C09")) -+ Name (_UID, 0) -+ Name (_GPE, 16) -+/* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e6430/acpi/platform.asl b/src/mainboard/dell/e6430/acpi/platform.asl -new file mode 100644 -index 0000000000..2d24bbd9b9 ---- /dev/null -+++ b/src/mainboard/dell/e6430/acpi/platform.asl -@@ -0,0 +1,12 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Method(_WAK, 1) -+{ -+ /* FIXME: EC support */ -+ Return(Package() {0, 0}) -+} -+ -+Method(_PTS,1) -+{ -+ /* FIXME: EC support */ -+} -diff --git a/src/mainboard/dell/e6430/acpi/superio.asl b/src/mainboard/dell/e6430/acpi/superio.asl -new file mode 100644 -index 0000000000..55b1db5b11 ---- /dev/null -+++ b/src/mainboard/dell/e6430/acpi/superio.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -diff --git a/src/mainboard/dell/e6430/acpi_tables.c b/src/mainboard/dell/e6430/acpi_tables.c -new file mode 100644 -index 0000000000..e2759659bf ---- /dev/null -+++ b/src/mainboard/dell/e6430/acpi_tables.c -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+ -+/* FIXME: check this function. */ -+void mainboard_fill_gnvs(struct global_nvs *gnvs) -+{ -+ /* The lid is open by default. */ -+ gnvs->lids = 1; -+ -+ /* Temperature at which OS will shutdown */ -+ gnvs->tcrt = 100; -+ /* Temperature at which OS will throttle CPU */ -+ gnvs->tpsv = 90; -+} -diff --git a/src/mainboard/dell/e6430/board_info.txt b/src/mainboard/dell/e6430/board_info.txt -new file mode 100644 -index 0000000000..4601a4aaba ---- /dev/null -+++ b/src/mainboard/dell/e6430/board_info.txt -@@ -0,0 +1,6 @@ -+Category: laptop -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2012 -diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default -new file mode 100644 -index 0000000000..2a5b30f2b7 ---- /dev/null -+++ b/src/mainboard/dell/e6430/cmos.default -@@ -0,0 +1,9 @@ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -+nmi=Enable -+bluetooth=Enable -+wwan=Enable -+wlan=Enable -+sata_mode=AHCI -+me_state=Normal -diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout -new file mode 100644 -index 0000000000..e85ea4c661 ---- /dev/null -+++ b/src/mainboard/dell/e6430/cmos.layout -@@ -0,0 +1,88 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+#400 8 r 0 reserved for century byte -+ -+# coreboot config options: southbridge -+408 1 e 1 nmi -+409 2 e 7 power_on_after_fail -+411 1 e 9 sata_mode -+ -+# coreboot config options: EC -+412 1 e 1 bluetooth -+413 1 e 1 wwan -+415 1 e 1 wlan -+ -+# coreboot config options: ME -+424 1 e 14 me_state -+425 2 h 0 me_state_prev -+ -+# coreboot config options: northbridge -+432 3 e 11 gfx_uma_size -+435 2 e 12 hybrid_graphics_mode -+440 8 h 0 volume -+ -+# VBOOT -+448 128 r 0 vbnv -+ -+# SandyBridge MRC Scrambler Seed values -+896 32 r 0 mrc_scrambler_seed -+928 32 r 0 mrc_scrambler_seed_s3 -+960 16 r 0 mrc_scrambler_seed_chk -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+2 0 Enable -+2 1 Disable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+9 0 AHCI -+9 1 Compatible -+11 0 32M -+11 1 64M -+11 2 96M -+11 3 128M -+11 4 160M -+11 5 192M -+11 6 224M -+14 0 Normal -+14 1 Disabled -+ -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 447 984 -diff --git a/src/mainboard/dell/e6430/data.vbt b/src/mainboard/dell/e6430/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..08952c26ab82933ebb5cc5b9c7e2265963a87b2d -GIT binary patch -literal 6144 -zcmeHKU2Gdw7XHRFw#VZc+nI!tq)j-qG$b@>#vu)%WW~fb!7ZV6LkJc^+qlG~(WXgp -zLU)l?#Jhyj)dGqHf<6H13kV^8g;enZDm*~=5kd&@Cn1Fu52*0a2hgri!F%q^IFQ;) -zjkMh#DR=zcpL5Use9xJ4?#x^=mKdcQb|t!Zj3v6R-<{Yod<{*&!ppI%xUMXT9lLMX -zn;IM)+?yEQoxF~o#5x>}{dfwPkR;RSiC=!jj_JAlRQpJWpd}$VY+XtFX9|?cO&y#m -zIdrG4zSq6a*B6 -zRA?%66|w}s0z*YuMNq*73a(KQQ8A>TT}4_&3_e5hDZs@lHpaYN60rOh%jBQN+*9zu -zIASsRL<3j>pYk93g@PXvaUZbpk)yEWDA4C2Ai!cNXi4M~3gjt#<|(LxR49-{<^K|T -zqL5SnLUq0r*kw>Q!0PGk>)$?LCsIS{ox_=t(Xs5!w-o>M=erl0apv_Z`-(^w_5@pz -z)}lBfx8o(*hgal&)aMG1rKzf_^2m;)RTu!i#rBrUK{pWM_5BuDg}f1vGgAMqNM&t?7(IQ -zcDa=Dn9^Q5?6k6+@y4UvvL3SDxKs*_^RS1n^H*!{fYZz^rPBXmV(=eO(Cd-pvqPqVBRYz~7nA{nO7|Kv{w^;?LXb8F -zZpK}KE=2zd4)ya^Le2qLGkt7<&s%Z6*Z`k>QW26OPC!Y8WP|wUI8Rlea-W3+oBO=P -z7W#bDD=HM*SuTlWaHmLu%9{LBg+7xrp>y^-%p_)+nfZB&dFmKmF?B(+QtAm&-^!?J -zr{Qq~n%$Y;KvfME{x@gVUB~vz&MBs@*k&z6fZ?Ic-b`*fKea1&Fkj=~!ZaqDU=O0r -zYCPKK+S_PdhGTnR+18g0GR_nHOE`gieuP-A>69j*W0 -z>h~9>kwTD6>nL4 -zBSLUr+fHA!LgjQi9)hfgsV8iv!rHDd&4tY)VQn!?C&K1ZSo>gEHwc1)*Nb@P2)`%EVorfFy!3`!X0sGp0XopwxoS -z0g?6TPW!DCql9>N1GN_$T-UVr&HErC5juykd~Sxy -zq!PK|<^jJ^DuQ9)7pt` -z7FKz(x)t4R_RHf7I)6EA!d)M`R($wttvJgMee=p9zrFL_EL#DYA0wUzD?Ryj%h>lB -ztg|e-5!;@t?uT+rR=1)e9yp?8gwNW88`Zyt!8rx=+B{i(4~DY`_-WO>sGeD;nsGcs -z7h1ZN6srJX#Uke;d$JhpccQxNhw2Qz?Zw91`@8IHm-n!7{19~*_}LvecV2YZ7%!rJ -zJQk}HtK2>CvB*WQ@u9a$Eq*zF2M=FM=@c`>dwDQ;<8EgZ-}dvt6=k(8Kqfa=nDJJ{ -z`Qth}G~%sFr{ZEKZb_%aySrD?sV%fJw`vFfda&ho1a>X)H^I}D_0A<|*{8kwEBU8> -qS -+ -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20141018 /* OEM revision */ -+) -+{ -+ #include -+ #include "acpi/platform.asl" -+ #include -+ #include -+ #include -+ #include -+ -+ Device (\_SB.PCI0) -+ { -+ #include -+ #include -+ #include -+ } -+} -diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c -new file mode 100644 -index 0000000000..7944157f59 ---- /dev/null -+++ b/src/mainboard/dell/e6430/early_init.c -@@ -0,0 +1,38 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+ -+#include -+#include -+#include -+#include -+#include -+ -+const struct southbridge_usb_port mainboard_usb_ports[] = { -+ { 1, 1, 0 }, -+ { 1, 1, 0 }, -+ { 1, 1, 1 }, -+ { 1, 1, 1 }, -+ { 1, 0, 2 }, -+ { 1, 1, 2 }, -+ { 1, 1, 3 }, -+ { 1, 1, 3 }, -+ { 1, 1, 4 }, -+ { 1, 1, 4 }, -+ { 1, 1, 5 }, -+ { 1, 1, 5 }, -+ { 1, 2, 6 }, -+ { 1, 2, 6 }, -+}; -+ -+void bootblock_mainboard_early_init(void) -+{ -+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f); -+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); -+ mec5035_early_init(); -+} -+ -+void mainboard_get_spd(spd_raw_data *spd, bool id_only) -+{ -+ read_spd(&spd[0], 0x50, id_only); -+ read_spd(&spd[2], 0x52, id_only); -+} -diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads -new file mode 100644 -index 0000000000..1310830c8e ---- /dev/null -+++ b/src/mainboard/dell/e6430/gma-mainboard.ads -@@ -0,0 +1,20 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ ( -+ HDMI1, -- mainboard HDMI -+ DP2, -- dock DP -+ DP3, -- dock DP -+ Analog, --mainboard VGA -+ LVDS, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/e6430/gpio.c b/src/mainboard/dell/e6430/gpio.c -new file mode 100644 -index 0000000000..777570765a ---- /dev/null -+++ b/src/mainboard/dell/e6430/gpio.c -@@ -0,0 +1,192 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_GPIO, -+ .gpio1 = GPIO_MODE_GPIO, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_NATIVE, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_GPIO, -+ .gpio8 = GPIO_MODE_GPIO, -+ .gpio9 = GPIO_MODE_NATIVE, -+ .gpio10 = GPIO_MODE_NATIVE, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_GPIO, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_GPIO, -+ .gpio18 = GPIO_MODE_NATIVE, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_NATIVE, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_NATIVE, -+ .gpio31 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio0 = GPIO_DIR_INPUT, -+ .gpio1 = GPIO_DIR_INPUT, -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio7 = GPIO_DIR_INPUT, -+ .gpio8 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio15 = GPIO_DIR_INPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio17 = GPIO_DIR_INPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_OUTPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio28 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_reset = { -+ .gpio30 = GPIO_RESET_RSMRST, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio0 = GPIO_INVERT, -+ .gpio8 = GPIO_INVERT, -+ .gpio13 = GPIO_INVERT, -+ .gpio14 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_NATIVE, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_GPIO, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_GPIO, -+ .gpio52 = GPIO_MODE_GPIO, -+ .gpio53 = GPIO_MODE_NATIVE, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_NATIVE, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_OUTPUT, -+ .gpio35 = GPIO_DIR_INPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio45 = GPIO_DIR_OUTPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_INPUT, -+ .gpio51 = GPIO_DIR_INPUT, -+ .gpio52 = GPIO_DIR_INPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio34 = GPIO_LEVEL_HIGH, -+ .gpio45 = GPIO_LEVEL_LOW, -+ .gpio60 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_reset = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_NATIVE, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_NATIVE, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_GPIO, -+ .gpio69 = GPIO_MODE_GPIO, -+ .gpio70 = GPIO_MODE_GPIO, -+ .gpio71 = GPIO_MODE_GPIO, -+ .gpio72 = GPIO_MODE_NATIVE, -+ .gpio73 = GPIO_MODE_NATIVE, -+ .gpio74 = GPIO_MODE_NATIVE, -+ .gpio75 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio68 = GPIO_DIR_INPUT, -+ .gpio69 = GPIO_DIR_INPUT, -+ .gpio70 = GPIO_DIR_INPUT, -+ .gpio71 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_reset = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ .reset = &pch_gpio_set1_reset, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ .reset = &pch_gpio_set2_reset, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ .reset = &pch_gpio_set3_reset, -+ }, -+}; -diff --git a/src/mainboard/dell/e6430/hda_verb.c b/src/mainboard/dell/e6430/hda_verb.c -new file mode 100644 -index 0000000000..56ada95c58 ---- /dev/null -+++ b/src/mainboard/dell/e6430/hda_verb.c -@@ -0,0 +1,33 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ 0x111d76df, /* Codec Vendor / Device ID: IDT */ -+ 0x10280534, /* Subsystem ID */ -+ 11, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(0, 0x10280534), -+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), -+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), -+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), -+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), -+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), -+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), -+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), -+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0), -+ -+ 0x80862806, /* Codec Vendor / Device ID: Intel */ -+ 0x80860101, /* Subsystem ID */ -+ 4, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(3, 0x80860101), -+ AZALIA_PIN_CFG(3, 0x05, 0x18560010), -+ AZALIA_PIN_CFG(3, 0x06, 0x18560020), -+ AZALIA_PIN_CFG(3, 0x07, 0x18560030), -+ -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/e6430/mainboard.c b/src/mainboard/dell/e6430/mainboard.c -new file mode 100644 -index 0000000000..31e49802fc ---- /dev/null -+++ b/src/mainboard/dell/e6430/mainboard.c -@@ -0,0 +1,21 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static void mainboard_enable(struct device *dev) -+{ -+ -+ /* FIXME: fix these values. */ -+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, -+ GMA_INT15_PANEL_FIT_DEFAULT, -+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -+} -+ -+struct chip_operations mainboard_ops = { -+ .enable_dev = mainboard_enable, -+}; --- -2.42.0 - diff --git a/config/coreboot/default/target.cfg b/config/coreboot/default/target.cfg index 1de8a3d5..076e7555 100644 --- a/config/coreboot/default/target.cfg +++ b/config/coreboot/default/target.cfg @@ -1,4 +1,4 @@ tree="default" romtype="normal" -rev="d86260a134575b083f35103e1cd5c7c7ad883bce" +rev="d862695f5f432b5c78dada5f16c293a4c3f9fce6" arch="x86_64" -- cgit v1.2.1