From 401c0882aaec059eab62b5ce467d3efbc1472d1f Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 7 Jan 2024 13:25:33 +0000 Subject: NEW MAINBOARD: HP EliteBook 820 G2 This is of Broadwell platform, one generation above Haswell. Of note: this uses HP Sure Start. Although the flash is 16MB, our CBFS section (and IFD configuration) assumes 12MB flash, so the final 4MB will be left unflashed on installation, after blanking the private flash. The coreboot documents have more information about this. Some minor design changes in lbmk were made, to accomodate this port: Support for extracting refcode binaries added (pulled from Google recovery images). The refcode file is an ELF that initialises the MRC and the PCH. It is also responsible for enabling or disabling the Intel GbE device, where Google does not enable it, but lbmk modifies it per the instructions on the coreboot documentation, so as to enable Intel GbE. Google's recovery image stores the refcode as a stage file, but coreboot changed the format (for CBFS files) after 4.13 so coreboot 4.13's cbfstool is used to extract refcode. This realisation made me also change the script logic to use a cbfstool and ifdtool version matching the coreboot tree, for all parts of lbmk, whereas lbmk previously used only the default tree for cbfstool/ifdtool, on insertion and deletion of vendor files - it was 81dc20e744 that broke extraction of refcode on google's recovery images, where google used an older version of cbfstool to insert the files in their coreboot ROMs. A further backported patch has been added, copying coreboot revision f22f408956 which is a build fix from Nico Huber. Iru Cai submitted an ACPI bugfix after the revision lbmk currently uses, for coreboot/default, and this fix is needed for rebooting to work on Linux 6.1 or higher. This patch has been backported to lbmk, while it still uses the same October 2023 revision of coreboot. Broadwell MRC is inserted at the same offset as Haswell, so I didn't need to tweak that. Signed-off-by: Leah Rowe --- ...elitebook_820_g2-do-not-set-EC-SLPT-on-S5.patch | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 config/coreboot/default/patches/0037-mb-hp-elitebook_820_g2-do-not-set-EC-SLPT-on-S5.patch (limited to 'config/coreboot/default') diff --git a/config/coreboot/default/patches/0037-mb-hp-elitebook_820_g2-do-not-set-EC-SLPT-on-S5.patch b/config/coreboot/default/patches/0037-mb-hp-elitebook_820_g2-do-not-set-EC-SLPT-on-S5.patch new file mode 100644 index 00000000..bc584ffe --- /dev/null +++ b/config/coreboot/default/patches/0037-mb-hp-elitebook_820_g2-do-not-set-EC-SLPT-on-S5.patch @@ -0,0 +1,34 @@ +From 6202669b8e8f50837448e2d4c482671abf72f648 Mon Sep 17 00:00:00 2001 +From: Iru Cai +Date: Sun, 5 Nov 2023 17:12:43 +0800 +Subject: [PATCH 1/1] mb/hp/elitebook_820_g2: do not set EC SLPT on S5 + +Setting EC SLPT bit in S5 will make HP EliteBook 820 G2 +fail to reboot under Linux 6.1 and later kernel versions. + +Change-Id: I48f5a35cd78db3b32d9f76cb8e266c738da34e7c +Signed-off-by: Iru Cai +Reviewed-on: https://review.coreboot.org/c/coreboot/+/78907 +Tested-by: build bot (Jenkins) +Reviewed-by: Felix Singer +--- + src/mainboard/hp/elitebook_820_g2/acpi/platform.asl | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/src/mainboard/hp/elitebook_820_g2/acpi/platform.asl b/src/mainboard/hp/elitebook_820_g2/acpi/platform.asl +index 8023ae826c..d17f575c40 100644 +--- a/src/mainboard/hp/elitebook_820_g2/acpi/platform.asl ++++ b/src/mainboard/hp/elitebook_820_g2/acpi/platform.asl +@@ -10,5 +10,8 @@ Method(_WAK,1) + + Method(_PTS,1) + { +- \_SB.PCI0.LPCB.EC0.SLPT = Arg0 ++ If (Arg0 != 5) ++ { ++ \_SB.PCI0.LPCB.EC0.SLPT = Arg0 ++ } + } +-- +2.39.2 + -- cgit v1.2.1