From fedeb6ecd8b5f3ed79dad754e452aecf88cbdde2 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 23 Apr 2026 15:19:44 +0100 Subject: cb/default: use rev 62c8197dd25376cb7b18d272af167cb176d28bcf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit this brings the following changes from upstream, since the previous revision: * 62c8197dd2 mb/google/calypso: Implement ramstage boot logic and QUP firmware loading * 86c6c748ed mainboard/google/calypso: Update board name in board_info.txt * 4298078683 mb/google/calypso: Implement `platform_romstage_main` and `platform_romstage_postram` * 1c79360b44 soc/qualcomm/calypso: Split CPUCP binary into RO and RW regions * fc1ba3d9b3 soc/qualcomm/calypso: Add soc_prepare_bl31_handoff hook * 03aaebef7e soc/qualcomm/calypso: Enable CBFS preloading for BL31 and BL32 * e242958a7d soc/qualcomm/calypso: Add weak mainboard_soc_init hook * 24160f6e3d soc/qualcomm/calypso: Add late init boot state entry * 10a2805216 soc/qualcomm/calypso: Implement cbmem_top_chipset() * 9cb549b4e7 mb/google/calypso: Select SOC_QUALCOMM_CDT * ef4aa128e2 soc/qc/calypso: Introduce CDT_DATA region * d9c36cb483 soc/qualcomm/calypso: Include cdt.c in romstage compilation * e2115d2079 soc/qualcomm/calypso: Update apdp.mbn path to use BLOB_VARIANT * 9fc7c2e3b2 soc/qc/calypso: Implement frequency-based QSPI GPIO drive strength * 6c566de88d soc/qualcomm/calypso: Make SPI bus frequency configurable via Kconfig * ef24143cc4 editorconfig: Explicitly set indent_size * 559eafd2c6 arch/x86/acpi_bert_storage: Add CPER_SEC_PLATFORM_MEM_GUID * 967ac0be68 soc/amd/common/block/cpu/mcax: Fill generic HEST entry * 6395a3f1a2 soc/amd/common/block/cpu/mcax: Add helper to identify bank * 441926d0df soc/amd/common/block/cpu/mcax: Add method to read FRU text from MSR * ff4ce4fa8a cbfstool: Rename COREBOOT_TS to COREBOOT_B * 8a50ec739b nb/intel/gm45: Name IOMMU registers and addresses * 4e56d573ae sb/intel/i82801gx: Drop `SPIBARx` macros * df5e587623 soc/qc/x1p42100:: Select Secure OS options in X1P42100 Kconfig * 8ce11782b3 vc/intel/fsp/fsp2_0/wildcatlake: Expose the VccsaShutdown UPD * a3f7ec15e9 mb/google/nissa/var/pujjoniru: Modify RAM ID table * 8cbaa8d894 mb/google/fatcat/var/ruby: Change fingerprint enable pin power state * bf848a6f80 mb/google/bluey: Configure LID_OPEN_S3 GPIO as input without pull * 0af0b50a3c mainboard/google/fatcat: Disable CPU ratio override on low battery * 6082e79232 sb/intel/wildcatpoint: Use some Lynx Point ME code * 1775f25ccc sb/intel/lynxpoint: Make `intel_me_finalize()` static * 43abc2d1c2 sb/intel/lynxpoint/me.h: Align MKHI macros with Wildcat Point * e357e3c6bb sb/intel/lynxpoint: Add `intel_me_hsio_version()` * fab9b2ad97 sb/intel/lynxpoint/me.h: Move function declarations to bottom * 5d23973369 sb/intel/wildcatpoint: Add parameters to `intel_me_status()` * 5c1bf73ab9 sb/intel/lynxpoint/me_status.c: Better handle unknown values * a66bd85e75 sb/intel/wildcatpoint: Replace ME structs with unions * 7ff29551a4 sb/intel/wildcatpoint/me.h: Align with Lynx Point * 18e29adc30 sb/intel/lynxpoint/early_me.c: Use northbridge defines * 1f376aebde sb/intel/wildcatpoint/cfr.c: Use Lynx Point's file * dccf924a2c sb/intel/lynxpoint: Split a few things off pch.h * 917880c002 broadwell/wildcatpoint: Decouple headers * 7812ceb6dc haswell/lynxpoint: Add `fixed_eq` to USB3 config * 9f90e930cf nb/intel/broadwell: Drop temporary macros * 9a587c54d7 nb/intel/broadwell: Drop `mainboard_fill_pei_data()` * 1c2efb8f2b mb/hp/elitebook_820_g2: Set `ec_present` from devtree * 99affc7f58 nb/intel/broadwell: Separate NB/PCH finalise steps * 165261ba7d nb/intel/haswell: Tidy up includes * f2e24e5230 nb/intel/haswell: Unify more cosmetics with Broadwell * a1af3759cd sb/intel/{lynx,wildcat}point: Drop `SPIBARx` macros * 9a45e0949f util/amdfwtool: Add PSP directory entry type 0x8e (SFDR) * 40eb28ec6b mb/google/ocelot/var/ocicat: Enable UFS inline encryption * 328534098f mb/google/ocelot/var/matsu: Enable UFS inline encryption * 108006e49a sb/intel/*: Centralize BIOS_CNTL macros * a22f97f3ff drivers/intel/touch/chip: Fix typo in *device* in comment * 8121a3dd72 soc/amd/common/block/psp: Add mailbox interface for ROM Armor * 367e323fd0 mb/google/rauru: Implement Priority Mutex for parallel boot alignment * 5b49e6d976 soc/mediatek/common: Implement Shared Resource Mutex for DMA safety * c5f901ba4b fw_config: Always declare fw_config_probe_mainboard_override * c39b0318de mb/google/rauru/sapphire: Override PANEL_ID in fw_config * 104aed9a5c lib/fw_config: Add mainboard override hook * bcfd9a87ee mb/google/bluey: Add is_low_res_panel helper for logo scaling * fd1ad83256 mb/google/bluey: Implement platform_use_secondary_logo * 5b811635e7 lib: Add support for secondary resolution bootsplash logos * a0502589a3 mb/google/bluey/mica: Add vdd and vtsp gpio to depthcharge * 026e1f60b6 drv/i2c/{rv3028c7, rx6110sa}: Use bool for config options where possible * cf7e468d32 payloads/Kconfig: fix dead default for PAYLOAD_FIT_SUPPORT * a7ded1bea6 soc/qualcomm/x1p42100: Use mainboard-specific paths for ADSP blobs * 387c317058 ec/starlabs/merlin: apply settings without enabled PNP devices * c0ca77265b util/lint: fix miniconfig check for CONFIG_MAINBOARD_DIR/HAVE references * 4064b5de37 payloads/external/edk2: build-local FMP cert PCD for capsule updates * 6e95ade0cb nb/intel/haswell/gma.c: Add Broadwell IDs * aa9ff8895f nb/intel/haswell/gma.c: Add Broadwell GT PM init * b75d086f86 nb/intel/haswell/gma.c: Replace GT register tables * 892d68a8c8 nb/intel/haswell/gma.c: Init CDCLK before gfxinit * f7412bf209 nb/intel/haswell/gma.c: Add support for Broadwell CDCLK * 65fdf4754e nb/intel/haswell/gma.c: Enable power well later * 625ba6ed9d nb/intel/haswell: Drop native gfx init leftovers * 8443582672 drivers/intel/gma: Drop unneeded DDI stuff * 6ca4e93632 nb/intel/haswell/gma.c: Update PM init steps * c8320ab9f6 nb/intel/haswell/gma.c: Avoid using invalid GTT resource * a5e124b6d0 nb/intel/haswell/gma.c: Fix PCI driver variable name * 5e0cf0e730 util/cbfstool: don't invalidate MH cache unnecessarily * 1754d90560 cbfstool/bzImage: Fix out-of-bound read with very short input file * df2afe0b22 cbfstool/fv: Fix out-of-bound read with very short input file * 9e600ac8dd cbfstool/fit: Fix out-of-bound read with very short input file * d9085c1a7b cbfstool/elfheaders: Fix out-of-bound read with very short input file * 27cdca23c1 mb/google/ocelot: add alternate clock request support * 5409e52b5f soc/qualcomm/x1p42100: Increase TTB size from to 64K for Bluey * 07c6b36ab3 mb/google/bluey: Add support for PWM-based backlight control * a3011baad1 soc/qualcomm/common: Correct GPIO offset for master PMIC * eaad3ecd4d mainboard/google/bluey: Use generic naming for backlight PMIC GPIO * f457508572 mainboard/google/bluey: Add touchscreen power control via GPIO * bcaaac5804 soc/amd/cezanne/Kconfig: add FSP binaries for V2000A * 5cff8485cb 3rdparty/amd_blobs: advance submodule pointer * 45cc75fe50 soc/amd/common/pci: Add host bridge _PRT method for root-bus devices * 434c92b908 acpi/acpigen_pci: Add devfn-based _PRT entry helpers * 64193f07f6 mb/google/dedede/var/blipper: Add stop_gpio, stop_delays to GTCH7503 * f4b98a0ba3 drivers/amd/ftpm: Disable pre ramstage * 5bbb46481f soc/mediatek: Refactor MT6685 PMIC driver to use lazy initialization * cbd0b52c5e lib/delay: Optimize mdelay and delay in cooperative multitasking * c8ac5953e9 ec/lenovo/h8: Respect H8_HAS_LEDLOGO configuration * 643efabd2a mb/google/ocelot: enable BayHub & Genesys SD Card * 87f9bd1235 Revert "soc/qualcomm/x1p42100: Select APDP and Ramdump configurations" * 3b44256255 soc/amd/common/block/psp: Check backup flash busy flag * c47cbaa3ac lib/cbfs.c: deduplicate checking/querying type on _cbfs*_alloc() * 7f3a299dc8 mb/asus/h61-series: Add Asus P8H61-M LX2 * 054318251c mb/asus/h61m-a_usb3/hda_verb.c: Drop extraneous codec verbs * ae9ffa965d acpi/acpigen_ps2_keybd: Map CONTEXTUAL_INSERT * 0223a54137 include/input-event-codes.h: Update to upstream * c61c56e2da soc/qualcomm/common: Adjust GPIO base for master PMIC * 888d9a4170 mb/google/bluey: Initialize ADSP boot reason in boot * 053ddab917 drv/i2c/{rv3028c7,rx6110sa}: Change date format in final-hook * 4b8bb72cbb mb/siemens/mc_ehl{6,8}: Enable sync of external RTC to CMOS RTC * 91e5644fb0 mb/siemens/mc_rpl1: Enable external RTC RV3028-C7 * baad6487e7 cbfstool: Improve lexer error message * e8a3bb81db treewide: Remove WARNINGS_ARE_ERRORS * a2d386749d soc/amd/glinda: Mark sleep button as control-method only * f7d5afbc18 soc/amd/phoenix: Mark sleep button as control-method only * 5b0dd4933a soc/amd/mendocino: Mark sleep button as control-method only * 81f77fd608 soc/amd/picasso: Set ACPI_FADT_SLEEP_BUTTON flag at SoC level * 30341a6d01 soc/amd/cezanne: Mark sleep button as control-method only * d19104a3ba soc/qc/x1p42100: Implement frequency-based QSPI GPIO drive strength * f75dc1b17c soc/qualcomm/common: Allow SoC override for QSPI GPIO configuration * 48acc27551 mb/google/bluey: Select 75MHz SPI frequency for board models * 4ce87ee626 soc/qualcomm/x1p42100: Make SPI bus frequency configurable via Kconfig * bd89a3df97 soc/qc/x1p42100: Move Display and LPASS initialization to late stage * 3d08ec12df soc/qualcomm/x1p42100: Enable CBFS preloading for BL31 and BL32 * 8e0e61c48f mb/google/bluey: Call setup_usb_late directly in mainboard_soc_init * 1e6e64eeca payloads/ext/.gitignore: Add coreDOOM build directory * be555d8614 payloads/ext/.gitignore: Sort alphabetically * 2942c415db mb/asus: Add ASUS Z87-K (Haswell) * 7721bb3b72 soc/amd/glinda: Pass SMMSTORE region to amdfwtool * 9439a4e6f7 util/amdfwtool: Introduce table granularity * a3bb1d2f21 ifdtool/ifdtool.c: Update FMAP template generation * 246e795b13 amdfwtool: Support directories greater than 4MiB * a8a682b430 mb/google/atria: Enable additional devices * d888458899 mb/google/atria/var/atria: Add initial storage configuration * 18e9062b88 mb/google/ocelot: Move HDMI GPIOs to early bootblock stage * 1b61c8f721 google/fatcat: Provide hook at the entry of BS_DEV_INIT_CHIPS * f40fc7b290 mb/google: Refactor MediaTek boards to use include/baseboard/ namespace * 357f2c8350 mb/google/oak: Rename WRITE_PROTECT macro to GPIO_WP * 63f2426042 mb/google/bluey: Enable DAM sink sensor Z1 optimization for Quartz * b19b4f15d7 mb/google/bluey: Add support for DAM sink sensor Z1 optimization * 8d51c6537a mb/siemens/mc_rpl1: Enable I2C1 bus * 140cb7b6df drv/i2c/rv3028c7: Add feature to sync date and time into CMOS RTC * d7c188f6c2 mb/starlabs/*: expose PS/2 keyboard ACPI node only * 481657b45f mb/starlabs/common: Gate Intel-specific settings * 5eb5f3a9bb mb/google/ocelot: Enable UFS inline encryption * 18b960be65 soc/qualcomm/x1p42100: Remove unused cpucp_prepare() declaration * b7bff5afea mb/amd/crater/devicetree_v2000a.cb: Update GPP port config * b74ab281bd mb/google/fatcat/var/lapis: Disable touchpanel wake-up configuration * 3bc8a9fec1 soc/amd/common/block/spi: Add ROM Armor checks * acd79afe9a soc/amd/glinda: Fill in cache defaults * e18df21852 soc/amd/cezanne/Kconfig: Add 64 Bit support for V2000A * 842b74a0e4 mb/amd/crater/ec.c: Fix calculation of reg in log message * 81de3098f8 mb/amd/crater: Disable PCIe feature programming * 37a1035ddc soc/mediatek/common: Log firmware splash screen status * 586389eafd mb/google/bluey: Skip SoC debug features in recovery mode * 8aa6763cea soc/qualcomm: Allow skipping SoC debug features in recovery * cb51506c64 mb/starlabs/adl: Correct selection of EC_STARLABS_FAN * 8103a5ff9c mainboard/opencellular/elgon/Kconfig: fix dead default for FMDFILE * ec0d1946e7 soc/qualcomm: Remove HAVE_CBFS_FILE_OPTION_BACKEND * f8a7a5c02e mainboard/google/bluey: Move display startup to mainboard_soc_init * 5fc9a1065b soc/qualcomm/x1p42100: Support board-specific SoC initialization * a5fb73a737 soc/intel/pantherlake: Limit active displays for portrait panels * d1c1627ede mb/google/bluey: Update GPIO configuraton for AMP enable pin * 83442b749f mb/google/bluey: Refactor peripheral init and adjust display timing * fb184d4f3d mb/google/bluey: Consolidate peripheral init and fix PCIe timing * 5a24200a97 util/cbfstool: avoid creating an image with only COREBOOT_TS * bf8a8a7aaf mb/google/fatcat: Enable CNVi WWAN coexistence for CELLULAR_PCIE * d9956b0bcf soc/intel/pantherlake: Add CNVi WWAN coexistence support * e71531558e acpi/acpigen_ps2_keybd: Map navigation shortcut keys without numpad * a2bf34ee1c soc/mediatek/mt8196: Relocate FRAMEBUFFER to 0x90200000 * 19e69dde5f vc/intel/fsp/fsp2_0/pantherlake: Update the PTL FSP full headers * 69f0093d54 mb/google/bluey: Optimize NVMe power sequencing in romstage * 2a6b546ca2 soc/qualcomm/x1p42100: Add support to power off PCIe Endpoint * 904aea246f soc/qc/x1p42100: Implement soc_prepare_bl31_handoff to throttle QSPI * fb81f6f6ce arch/arm64: Add soc_prepare_bl31_handoff() hook * 66c68e0168 soc/qualcomm/common: Add qspi_set_bus_clock() helper * 86e45bf52d mb/apple/macbook21: Improve variant name and reintroduce overridetree.cb * 198aabff32 soc/intel/xeon_sp: Add more defines for register SMM_FEATURE_CONTROL * 4c3e63e7fd mb/asus/p8z77-v_lx2: Change super I/O chip to nct5535d * d93eb115b0 util/liveiso: Update nixos to 25.11 * 54b518da64 mb/asus/h61-series: Add P8H61-I R2.0 variant (it8771e) * 74105264e0 util/kconfig/confdata.c: fix -Werror=discarded-qualifiers * ece067d8be util/amdtool/cpu.c: Report SME-HMK state * 14824c7307 util/amdtool/cpu.c: Fix reporting of SEV features * b7dd49d68d security/tpm/tspi/crtm.c: remove superfluous logging * 371ef274f9 lib/cbfs.c: don't skip CBFS verification in SMM * 9e04f49a7a x86: define toolchain for SMM * 98b0fc0e56 mb/google/atria/var/atria: Add TPM configuration * 0eadf8856e mb/google/atria/var/atria: Add initial I2C configuration * 81cdb782f6 mb/google/atria: Add GPE configuration * 7e0e36d412 mb/google/atria: Select configuration for CHROMEOS and VBOOT * 1493066f74 mb/google/atria: Add EC support * df8d6f9a57 mb/google/atria: Add memory initialization support * 7402845e29 mb/google/atria: Add console UART configuration * 3b6f1d3817 mb/google/atria/var/atria: Add initial GPIO configuration * 5d4f18e412 mb/google/atria/var/atria: Add GPIO stub configuration * 9bf6b9096e mb/google/atria: Add atria variant support * f6caf8bf42 mb/google/atria: Add initial mainboard * 6a5f9c8a23 util/intelmetool: Use separate src and build directories * 7d7499449d soc/amd/cezanne: Drop selection of SOC_AMD_COMMON_BLOCK_SPI_DWORD_ACCESS * ff0467b96e mb/google/brya: Set CFR storage default to CBI value on taeko/taniks * 815dc9d445 mb/system76/mtl: Enable EnableTcssCovTypeA configs * 49f9e95c8d util/lint/lint-stable-005-board-status: Add "All-in-One" category * f4df60e306 intel/block/pcie/rtd3: Implement _PR3 * d3b7103c9d .gitignore: ignore extended-junit.xml files * 2d8f4958c5 payloads/ext/.gitignore: match tint tarball * 5ea3c7f7fa payloads/ext/.gitignore: match MemTest86+ new src dir * 53c2fc39ac soc/intel/alderlake: Remove ADL_P_ID_9 from PCH SA device list * 21f79fb69b util/intelmetool: Add Raptor Lake-S PCI ID * b9399443c0 soc/intel/alderlake: Add Raptor Lake-S 8+12 (0xa740) support * c9685501f5 mb/asus/maximus_vi(i)_impact: Update HDA codec name * dfe5b08978 soc/intel/pantherlake: Add UFS inline encryption support * 4e4a2f85bb mb/siemens/{mc_ehl6,mc_ehl7}: Set IccMax IA to 15A * 76be626491 soc/intel/elkhartlake: Expose IccMax IA domain to devicetree * 5267cae13a utils/crossgcc: Update NASM from 2.16.03 to 3.01 * 3ef459a968 utils/crossgcc: Update acpica from 20250807 to 20251212 * e518885dce utils/crossgcc: Update GCC from 14.2.0 to 15.2.0 * a425b57634 soc/qc/x1p42100: Update eDP lane/PHY handling and add BPC selection * a309c042e2 mb/google/bluey: Log firmware splash screen status to BIOS and ELOG * 52da3306cc mb/google/bluey: Refactor and clean up display initialization * ab360c9195 mb/google/bluey: Guard Debug Access Port (DAP) configuration with Kconfig * b11e7b4afa soc/qualcomm/x1p42100: Enable memory chip information filtering * 722f8e630d soc/qualcomm/common: Filter undefined memory chip entries * 4e1d6cee0c soc/qualcomm/x1p42100: Select APDP and Ramdump configurations * 6d73c02606 soc/qualcomm/x1p42100: Use correct path for APDP binary * 7dc8ae735a mb/google/bluey: Move apdp and ramdump regions to RW only * 08bff09608 vc/amd/fsp/renoir/FspUpd.h: Fix comment for FSP signatures * f2f1a5814f mb/amd/crater/Kconfig: Change SOC to V2000A * 661a1aa5a2 mb/google/skywalker: Create R2d2 variant * 9a59f1a5ac mb/asus: Add Maximus VII Ranger (Haswell/Broadwell) * 87af5c2aef mb/asus: Add Maximus VI Hero (Haswell) * ae3bec1c7c soc/amd/cezanne/Kconfig: Enable Cache on S3 resume * ce444c4c76 soc/amd/cezanne: Add V2000A SOC * 621d722ab8 soc/amd/cezanne/Kconfig: Extend bus numbers to 256 for renoir * 0cbc9e9c57 soc/amd/cezanne/Kconfig: Remove ADD_FSP_BINARIES from RENOIR * 4369c463fc soc/amd/common/block/spi: Increase SPI write speed by 27% * 630a6e66c1 mb/asus/maximus_vii_impact: Update comment for USBDEBUG_HCD_INDEX * f89717ecc3 soc/qualcomm/x1p42100: Remove dummy regions around framebuffer * b6ca7755f3 utils/crossgcc: Update binutils from 2.45 to 2.45.1 * 2227096f55 arch/arm64: Add support for COOP_MULTITASKING * e7d4cc6813 lib: Add comprehensive stack checking for cooperative threads * 66cb3e79a4 util/find_usbdebug: Add missing 9 Series PCH rate matching hub IDs * d1da8ec7bb util/autoport: Use official chipset names * 40df3567c6 mb/google/bluey: Avoid using uninitialized EDID data * 02e5c1c39c mb/google/calypso: Add dependency on I2C_TPM for DRIVER_TPM_I2C_ADDR * b8bd5a5639 mb/google/calypso: Add Calypso board variant to Kconfig * 201392d363 mb/google/calypso: Rename mensa mainboard directory to calypso * b1a374e635 mb/google/mensa: Reduce RW_CDT partition size to 4K * eaaa63791a mb/google/mensa: Change fingerprint interface from SPI to USB * e187893fa9 mb/google/mensa: Rename Kconfig symbols from MENSA to CALYPSO * c22ab9f535 mb/google/bluey: Select SOC_QUALCOMM_CDT and shrink RW_CDT partition * a4ee53610f soc/qualcomm/x1p42100: Include cdt.c in romstage compilation * 598504962e soc/qualcomm/common: Read and populate CDT data * f3f8e7f61c memlayout: Introduce CDT_DATA region * b6a87477d7 soc/qualcomm/common: Introduce SOC_QUALCOMM_CDT Kconfig option * 681c5a219b mb/google/bluey: Enable DAP for Quenbi and Mica variants * 8792766e05 mb/google/bluey: Support configurable DAP SMBs Slave IDs * 7d863336bc mb/google/bluey: Increase charging rail stabilization delay to 5s * 6fa8d2c415 mb/google/bluey: Select splash logo based on panel resolution * 7a533becf2 soc/qualcomm/common: Add debug dump for mem_chip_info * f502f316f2 mb/google/*: Add disable_heci1_at_pre_boot to CFR ME options * e3111a3dc2 soc/intel/common/cse: Add CFR override for disabling HECI1 at end of boot * 15529219c9 soc/amd/common/block/cpu: Enable cache on S3 resume * 53561b7903 soc/amd/common/block/spi: Enable SPI_FLASH_SFDP for all SoC * 4e522f49b6 drivers/ck505: Add pre and post hooks * 83977273f1 mb/asus: Add ASUS Maximus VI Impact (Haswell) * 1e49b5c385 mb/starlabs/starfighter: fix touchpad settings not being applied * 1f05ba35b9 mb/starlabs/starfighter: Add missing WiFi and Bluetooth controls * 049a580bbf mb/lenovo/sklkbl_thinkpad: Enable TBT support for T580 * ec6856785d sb/ricoh/rl5c476: Fix building for 64-bit targets * 4a5422fb99 lib/thread: Use standard doubly linked list API * 41d55fae84 commonlib/list: Add list_pop() * 25d3809ea3 payloads/edk2: Update default MrChromebox branch from 2511 to 2603 * 577f30851d util/chromeos/crosfirmware: Update recovery inventory parsing * 7dfe91fe0b soc/intel/cometlake: Always select PMC_IPC_ACPI_INTERFACE * 653e2fee68 mb/amd/crater: add and use APCB recovery file * 7222e5911b acpi/dsdt_top.asl: Add hook to enable routing in APIC mode * 9f65c47ea7 lib/timestamp: Fix get_us_since_boot() * 6bd55cf269 soc/amd/cezanne: Select SOC_AMD_COMMON_BLOCK_HDA * 3cd83d2ce0 mb/google/bluey: Reset eDP and disable backlight on display stop * e5a73dc9e6 mb/google/bluey: Use common APIs to configure PMIC GPIOs * 4c784a6f3a soc/qualcomm/x1p42100: Define PMIC slave IDs * 355658054a soc/qualcomm/x1p42100: Include new PMIC GPIO APIs in ramstage * a3bf18f3b2 soc/qualcomm/common: Add APIs to configure PMIC GPIOs * 1b2c0f8aca mb/google/bluey: Switch fingerprint sensor to USB interface * 3976f8ed0d mb/supermicro/x11-lga1151-series: Enable SATA hotplug * bc2092acd4 mb/google/jecht: Add CFR options for CPU undervolt * 8d2e8295c5 mb/google/jecht: Add CFR PL1/PL2 package power overrides * d1633f5cc1 mb/google/beltino: Add CFR options for CPU undervolt * ef8f4d7ac5 mb/google/beltino: Add CFR PL1/PL2 package power overrides * 32f16591aa mb/google/puff: Add CFR options for CPU undervolt * a612fdce4f mb/google/puff: Add CFR PL1/PL2 package power overrides * faf5f0ea9e mb/google/fizz: Add CFR options for CPU undervolt * e9239d2308 soc/intel/skylake: Add support for OC mailbox programming * 1654e0a1de soc/intel/cannonlake: Add support for OC mailbox programming * aaa396d571 cpu/intel/haswell: Add support for OC mailbox programming * fa68b66686 drivers/intel/oc_mailbox: Add OC_MAILBOX undervolt driver * b137be4d8f soc/amd/cezanne: Fix USB3 port aliases and USB port order * b9e6bc61ce soc/amd/cezanne/acpi: Guard RTC workaround with CONFIG(CHROMEOS) * 912817d316 Revert "mb/google/bluey: Temporarily skip display init in normal mode" * ce74ab0d21 soc/qc/x1p42100: Remove framebuffer from generic MMIO reporting * 889c42c177 device/pciexp_device: Fix SR-IOV detection * 5a3e8f3076 soc/amd/glinda: Use SPI_FLASH_SFDP * 67845716da drivers/spi/spi_flash_sfdp: Parse JEDEC SFDP * a95ee50a7b mb/starlabs/adl/{i5,hz}: increase speaker output power to 2.5W * 601bbd87bd mb/google/zork/vilboz: Set proximity INT as GPI for non-ChromeOS * cbbf961526 arch/x86/acpi_bert_storage: Clear allocated structure * 84c1b81540 Revert "soc/intel/common/power_limit: Raise PsysPL1 when package PL1 is above TDP" * a5941ba5f8 soc/amd/common/psp: add support for early PSP v2 access via SMN * b514b1e671 soc/amd/common/psp/Makefile: make ftpm.c build more conditional * 40e56f2358 soc/qc/x1p42100: Define and reserve framebuffer region * 499ab15def mb/google/bluey: Implement display initialization hooks * 382f5e0cd4 mb/google/bluey: Add support for firmware splash screen * c120e1b9fc mb/google/bluey: Temporarily skip display init in normal mode * c6e0f28814 soc/qualcomm/x1p42100: Add eDP display support * 61706268a6 soc/intel/common: Replace numbers with mask constants in power limits * 38addfb24f mb/google/bluey: Power on NVMe rail earlier in boot * 2f752c6341 util/cbfstool/flashmap/fmap.c: Fix buffer overflow * 96a91bbaf9 mb/siemens/mc_ehl8: Reduce I2C clock rate to 100kHz * 012bf817a9 soc/intel/common/block/power_limit: Remove unnecessary rdmsr * 654f328474 soc/intel/common/power_limit: Don't disable package PL1 in MCHBAR * f7bb12e423 mb/google/bluey: Set GPIO206 as output low on Bluey * f0211870e0 soc/amd/{turin,genoa}_poc: Select SOC_AMD_COMMON_BLOCK_HAS_ESPI1 * f6cd320061 acpi/acpigen_pci_root_resource_producer.c: Report TPM MMIO in domain 0 * bb0e107ebd soc/intel/common: Add hardware limit validation for power overrides * c803ca2ed6 amd/common/block/pci/acpi_prt.c: Add SoC hook to get GSI base * 8e57010d88 mb/google/bluey: Use slow charging if battery is less than 2% * 432703dd7a mb/siemens/mc_ehl7: Deactivate IGD * eda62af9dd mb/google/bluey: Implement slow-to-fast charging transition logic * 1dc346e61e cpu/intel/haswell: Add option-backed PL1/PL2 overrides and package limit lock * 0d95bb5158 mb/google/fizz: Add CFR PL1/PL2 package power overrides * 6c10b07146 mb/google/fizz: Refactor mainboard_set_power_limits() * 976149a2f7 soc/intel/common/power_limit: Raise PsysPL1 when package PL1 is above TDP * bdf757aa86 soc/intel/common/power_limit: Add option-driven PL1/PL2 overrides and locking * f45d6e696a mb/google/bluey: Configure sink sensor for DAM port * 63fc231480 AUTHORS: Update with new authors from the 26.03 release * f67b5ed6fd util/release: add get_new_authors helper * 7bcb90047e mb/google/nissa/var/pujjoniru: Add 2 Micron modules to RAM id table * c683673095 mb/google/nissa/var/yavilla: Add RAM ID H58G56BK8BX068 * 66ed61a73c b/google/brox/var/lotso: Add RAM ID for MT62F1G32D2DS-031RF WT:C * 6d3e13a33a mb/google/bluey: Conditionally enable FP rails in normal boot * 137b9c59ea mb/google/var/fatcat/lapis: adjust 'cirrus,detect-us' property to improve the noise situation * d381d33a39 soc/soc/amd/glinda: Hook up STX VBIOS * 1b284012b8 mb/starlabs/starfighter: add configurable touchpad tuning * 97d616b927 soc/amd/common/block/spi: Add helper functions * 102b9b42ae mb/google/skyrim/var/frostflow: Add non-ChromeOS TBMC support * d012a678e2 mb/google/guybrush/var/dewatt: Add non-ChromeOS TBMC support * 7eb70b259b mb/google/zork: Set correct SYSTEM_TYPE for all variants * dbd05fc2da mb/google/kahlee: Set correct SYSTEM_TYPE for all variants * 45378e6fc2 mb/google/guybrush/dewatt: Mark board as convertible * 227dbbad4a mb/google/skyrim: Use GpioInt wake for touchpad and fingerprint reader * fe445f4b9d mb/google/skyrim: Use level-triggered IRQ for touchpad and touchscreen * 49803f2130 mb/google/guybrush: Use GpioInt wake for touchpad and fingerprint reader * 62abc7aca0 mb/google/guybrush: Switch touchpad IRQ to level triggering * 65858ad5c9 mb/google/zork/var/vilboz: Guard GPIO for SAR sensor * fd5b6323ea mb/google/zork: Use GpioInt wake for touchpad and fingerprint reader * e2c419bc44 mb/google/zork: Use level-triggered IRQ for touchscreens * 30b8524ff5 soc/qualcomm/calypso: Enable basic PCIe support * ba3b83e51e mb/google/mensa: Implement SKU ID retrieval * 888cc7f92a mb/google/mensa: Initialize FP GPIOs in bootblock * a6921f7fb9 soc/qualcomm/calypso: Add placeholder for early clock initialization * 421c21c6cf soc/qualcomm/calypso: Initialize QSPI and QUPv3 in bootblock * 0fc956cd2d mb/google/mensa: Set correct Kconfig defaults for peripherals * 8dbf88a300 soc/qualcomm/calypso: Add QUP Serial Engine (SE) entries * 79b6dde1a5 soc/qualcomm/calypso: Set correct Kconfig defaults for peripherals * dde131c555 mb/google/mensa: Add initial support for Mensa * 38e8eadfa7 soc/qualcomm/calypso: Add initial SoC skeleton for Calypso * c7a7fbbf2c soc/qualcomm: Add support for QUPV3 wrapper 3 * cb05d160d4 soc/qualcomm/x1p42100: Rename SOC_QUALCOMM_BASE to include SoC name * b8ed516097 mb/google/bluey: Defer display initialization based on boot mode * 9bfab15070 docs/mb/hp: fix link to Sure Start whitepaper, add another * e839059435 mainboard/starlabs/common: enable OPAL S3 unlock * 9fc27f4b15 soc/intel/common/pcie/rtd3: Add RTD3 support for OPAL S3 unlock * 468f8131ec security/tcg/opal_s3: hook into default SMI/resume paths * 36a4d92239 util/amdfwtool: Fix APOB_NV quirk * e57478e238 treewide: Apply nonstring attribute to unterminated strings * 492b7c7c09 soc/amd/common/block/psp: Add commands for A/B recovery * cf541343a9 ec/lenovo/h8: Implement LOGO LED * 7609822730 mb/starlabs/*: disable TCO Intruder SMI * 26d005fb30 mb/starlabs/starfighter: use safe shared panel PWM frequency * 25eee46bbc mb/starlabs/starbook/{adl,rpl,tgl}: raise panel PWM frequency * bfaadde071 mb/starlabs/starbook/{adl_n,mtl}: raise panel PWM frequency * d4bfac6564 mb/starlabs/adl/i5: use safe shared panel PWM frequency * 1ca1c60019 mb/starlabs/adl/hz: raise panel PWM frequency to 10kHz * e970b9b0df mb/starlabs/adl/hz: restore panel minimum brightness * 9f6ae2b5a2 mb/starlabs/starbook/{adl,rpl,tgl}: fix panel timings * f13a9cb910 mb/starlabs/adl/i5: fix panel timing values against datasheet * d0e2b5df61 mb/starlabs/starbook/{adl_n,mtl}: fix panel timings * f1bc59e66e mb/starlabs/starfighter: fix panel timing values against datasheet * 040ff1ff39 mb/starlabs/adl/hz: fix panel timing values against datasheet * ed261d5447 mainboard/starlabs/common: include acpi_gnvs.h in gnvs.c * f1505f5e46 mb/google/zork: Add MKBP support * a5b5591d31 mb/google/reef: Add MKBP support * 134b3e050a mb/google/octopus: Add MKBP support * caf980b3fa mb/google/hatch: Add MKBP support * 1a75cd1da2 mb/google/glados: Add MKBP support * f1e95c5536 mb/qemu/riscv: Intialize PCI root bus * c5e905fa21 util/mec152x/Makefile: Include commonlib/bsd/compiler.h * 576515394c util/amdfwtool: Use uint8_t for bitfields * 800d3dbef4 soc/qualcomm/x1p42100: Support separate RO/RW CPUCP binaries * c0e82f6963 3rdparty/amd_blobs: advance submodule pointer * 82de37d171 libpayload: Makefile.mk: Fix unrecognized option '--no-weak' * e021937f35 soc/amd/glinda: Add RAS Kconfig options * e232934f6f mb/google/nissa: Create dirkson variant * 79c98cca80 mb/google/volteer: Add non-ChromeOS TBMC support for 360/flip variants * f867d8f76b mb/google/dedede: Add non-ChromeOS TBMC support for 360/flip variants * 25ad0950a8 mb/google/brya: Add non-ChromeOS TBMC support for 360/flip variants * a8615bed6b mb/google/cyan: Add support for EC mode change event * 8f5477d92d mb/google/volteer: Set correct SYSTEM_TYPE for all variants * 7b87cda615 mb/google/reef: Set correct SYSTEM_TYPE for all variants * 7995a1d3ea mb/google/octopus: Set correct SYSTEM_TYPE for all variants * 14ef332242 mb/google/hatch: Set correct SYSTEM_TYPE for all variants * 3f10068936 mb/google/glados/var/caroline: Mark board as convertible * 025c0edeb2 mb/google/dedede: Set correct SYSTEM_TYPE for all variants * c049dcc271 mb/google/brya: Set correct SYSTEM_TYPE for all variants * ecab793650 ec/chromeec: Add Kconfig and asl for vendor tablet ACPI * 1769b10be0 mb/google/bluey: Lower CPU frequency to 710.4MHz for low-power boot * 710df33471 mb/google/bluey: Signal ADSP to skip Type-C port resets during boot * 521e7949c1 mb/google/bluey: Add support to reduce CPU clock to minimum frequency during OFF‑mode charging * 9a86b9f729 mb/google/bluey: Integrate ADSP load and LPASS bring-up into charging flow * 8beca96470 soc/qualcomm/x1p42100: Add LPASS bring-up sequence for ADSP cold boot * a58f752d0f soc/qualcomm/common: add CBCR disable and config helpers * 2e3e690023 soc/qualcomm/x1p42100: Support to load ADSP Lite firmware * 1c6f4618b6 mb/google/bluey: Allow charger behind DAM * 94dd3f3bba soc/qualcomm/x1p42100: Increase boot CPU frequency to 3.0GHz * da36276955 smbios: Add smbios_cache_speed() implementation * 6f7f27e6c1 soc/qualcomm: Relocate translation tables to DRAM * 4320fe713a mb/google/brask/var/constitution: Generate RAM ID for Samsung K4UBE3D4AA-MGCR * d43421da65 mb/google/nissa/var/quandiso: Generate RAM ID for SL5D32G32C2A-HC0 * 28fbd247f6 spd/lp5x: Generate initial SPD for SL5D32G32C2A-HC0 * d72d7d1ba0 soc/amd/common/block/spi: Check if ROM Armor is enforced * cd8072191d soc/amd/common/block/psp: Get ROM Armor state from HSTI * b42d148171 soc/qualcomm/x1p42100: Define CPUCP region and map in MMU * 92fa2bbd09 soc/qualcomm/x1p42100: Disable compression for CPUCP payload * 6c8a2a6ea1 soc/amd/glinda: Use VBIOS from amd_blobs * ff7bc7d2d1 drivers/amd/ftpm: Fix compilation * ab63331423 mainboard/starlabs/lite: Remove unused header * a19b5b4b17 mainboard/starlabs/starfighter: Remove unused header * c4e44caef8 mainboard/starlabs/starbook: Remove unused headers * b0ff1cdd28 mainboard/starlabs/adl: Remove unused headers * d319b33114 mainboard/starlabs/common: Remove unused headers * b137044a39 ec/starlabs/merlin: Remove unused halt.h * 7bc3561803 ec/starlabs/merlin: Include stdint * e657f5da15 mainboard/starlabs: drop redundant vbt.bin overrides * b7faa4c51a amdfwtool: Allow to set bios entry 0x6d (AMD_BIOS_NV_ST) * 8e04206f28 amdfwtool: mark AMD_BIOS_APOB_NV BIOS directory entry as writable * 8549c6894a amdfwtool: Make NVRAM regions writeable * 1928db74a1 Documentation: Finalize 26.03 release notes * aa27204240 mb/google/fatcat/variants/moonstone: Implement BOE touchscreen power timing * dc41e46b7f google/fatcat: Move mainboard_pre_dev_init_chips hook to BS_ON_EXIT * 3f46d6fd93 mb/google/bluey: Use safe SPMI reads for battery current telemetry * 2f93e4331e soc/qualcomm/common: Add spmi_read8_safe helper with retry logic * 444691603d mb/google/bluey: Support RTC wake-up boot mode * 941597e52f {commonlib, libpayload}: Add RTC_WAKE to boot_mode_t * 34f67580b5 ec/google/chromeec: Add API to check for RTC host event * b00bfdd1e0 mb/google/bluey: Refactor SE firmware loading into early/late stages * 1f2ea3c13e mb/google/bluey: Initiate PCIe link training in romstage * f56a936c54 soc/qualcomm/x1p42100: Allow asynchronous PCIe initialization * f1baed6f79 soc/qualcomm/common: Implement asynchronous PCIe initialization * 8a90e46346 soc/qualcomm/x1p42100: Increase CBFS_MCACHE size to 22K * 4b227a4aa6 arch/arm64: Add debug API to dump MMU page table configuration * 99d409d3ba arch/arm64: Add support for TTB relocation to DRAM * 493770d730 mb/starlabs/starfighter/mtl: add speaker idle CFR option * f3c656b76a soc/intel/common/block/smm: drain sync smi around smmstore * a215e07533 mb/google/nissa/var/craask: Add H58G56CK8BX146 to RAM ID table * a7773d3ab3 mb/google/fatcat: Modifying parameters for AC only * 05246a5934 mb/asus: Add Maximus VII Impact (Haswell/Broadwell) * 0f30eed3e8 Doc/nb/intel/haswell: Fix typo * 5e146277ae Doc/nb/intel/haswell: Drop outdated section about SPD addresses * 86b3901ba5 mb/google/bluey: Monitor thermal sensors during charging * 657bd42548 soc/qualcomm/x1p42100: Define TSENS controllers and thermal zones * 53529b1d93 soc/qualcomm/common: Add Qualcomm TSENS support * 9e7c787f6d soc/qualcomm/x1p42100: Add 806 MHz CPU clock definition * e5c99fe9e0 Documentation: Add coreboot release 26.06 template * 8791c5292d Documentation/releases: Update release notes for 26.03 release * 1063e564e7 Documentation/vboot: Update list of vboot-enabled devices * 8ff1a9a08c vc/tcg/opal: add OPAL packet builder for S3 unlock * 30cd6efc29 util/amdfwtool: rename Faegan SoC to Krackan2e * 1555a1a235 util/amdfwtool: rename Glinda SoC to Strix * dc315c8f51 soc/amd/common/block/psp: Drop send_psp_command_smm * 49f53bbb38 include/acpi/acpi_pld.h: Fix order of colour components * e0bc32ce61 mb/google/brya: Add CFR-based storage selection for taeko/taniks * db3e23d505 lib/fw_config: Add mainboard hook for selective probe override * 225fd5e448 3rdparty/intel-microcode: Update to upstream main * ac5722a66f 3rdparty/fsp: Update to upstream master * 7bfad23a15 mb/google/bluey: Enable GBB_FLAG_ENABLE_ADB for development * a649c82f7a security/vboot: Add option for enabling ADB via GBB flag * 4943cfe4d0 soc/intel/pantherlake: Remove unsupported WCL CPU ID mappings * 9a40f080ac security/tcg/opal_s3: add OPAL NVMe Security Send/Receive helpers * 537f2acc67 vc/intel: add TCG storage core subset for OPAL S3 * fbd755341a security/tcg: add OPAL S3 unlock Kconfig * 42a114e23f mb/google/nissa/var/teliks: Generate RAM ID for BWMYAX32P8A-32G * a6b7fa5474 mb/google/brask/var/moxoe: Disable SAGV * d74cf143fe mb/google/brask/var/kulnex: Disable SAGV * 09d689561a soc/mediatek/common: dsi: Fix CPHY hfp_byte error check * 674000732d drivers/intel/dtbt: Skip mailbox commands on downstream bridges * b03b42285e soc/intel/{mtl,ptl}/fsp_params: Program PcieRpSlotImplemented * e17cc395af soc/intel/alderlake/fsp_params: Drop !! in builtin root port check * 11e9550e0c soc/intel/common/smm: Use cpu/x86 save_state ops * ce1db1f54a cpu/x86/smm: reserve SMRAM for OPAL S3 state * 9422dacdb8 mb/google/brask/var/moxoe: Remove weak symbols for memory config * 53222f1ccb mb/google/brask/var/kulnex: Remove weak symbols for memory config * 5bb8b30c03 nb/intel/haswell: Enable SA clock gating later * a0be26ef5f nb/intel/haswell: Fix IOMMU early init * 60994cf395 nb/intel/haswell/early_peg.c: Simplify implementation * fed6f9494d nb/intel/haswell: Move early PEG stuff to separate file * 76290e8cdc nb/intel/haswell: Move PEG device macros to header * e7cfcec7a7 nb/intel/haswell: Use `report_cpu_info()` from CPU code * f730ec6992 cpu/intel/haswell/report_cpu_info.c: Update CPUID info * f249991e9d cpu/intel/haswell: Fix CPUID macros * 96ab0c9942 nb/intel/broadwell: Move `report_cpu_info()` to CPU code * 7c35218c88 nb/intel/broadwell/report_platform.c: Constify string array * 4ea3450e45 nb/intel/broadwell: Use registers from Haswell * 342d77a0dd nb/intel/broadwell: Rename `MCH_PAIR` to `INTRDIRCTL` * 31f4c30a08 nb/intel/broadwell: Clean up cosmetics * 53bc76856c nb/intel/broadwell/gma.c: Retype some variables * 1172a4e6ee mb/google/brya/var/yavilla: Set LGD touchscreen HID address to 0x01 * 5c20d9ce76 3rdparty/amd_blobs: advance submodule pointer * 817394f12c Makefile.mk: generate EDK2 update capsule * bf037f3961 mb/emu/qemu-sbsa: Add GIC ITS and IORT for PCI MSI support * e69bfef7c0 mb/emu/qemu-sbsa: Set io_port_mmio_base for PCI I/O port support * dc7bf7e3f9 mb/google/bluey: Enable source mode on debug access port * e9e4f7609c mb/google/bluey: Move QUP-GSI init/load to normal boot path * 19e1b5c44b soc/mediatek/mt8196: Change dsi-phy1 & dsi-phy2 control method * e6fb0faf7b soc/qualcomm/x1p42100: Skip redundant MMU toggling for QCLib * deb510afeb cpu/x86/smm: add OPAL S3 CBMEM scratch * 513899c3c8 vc/amd/opensil/phoenix_poc: Adjust headers from Genoa to Phoenix * a616a589a2 vc/amd/opensil: Add Phoenix OpenSIL POC directory as a copy of Genoa * 71effade58 mb/google/eve: Work around CLKREQ# timing erratum * faf12bcacd soc/intel/skl: Allow disabling CLKREQ# independently of SrcClk * 07e4cc0cc3 mb/google/fatcat: Set CPU ratio override in devicetree * 94168f10bc Reland "mb/google/bluey: Configure GPIOs for USB camera" * 975613717a mainboard/starlabs/starfighter: Convert SPD sources to JSON * dda351b895 mainboard/starlabs/adl: Convert SPD sources to JSON * 5202b1371d mainboard/starlabs/adl: Convert i5 SPD sources to JSON * 2c9f1600e0 src/lib: Generate spd.hex from JSON at build time * 9a8d22dcaa util/spd_tools: Improve spd_gen CLI for Make * 3249ad1d7f mb/google/rex: Add SOF chip driver to screebo, kanix, karis * 88eea9da6d vendorcode/amd/opensil/turin_poc: Pass microcode pointer to OpenSIL * 39017d2257 amd/microcode: Add API to obtain address on microcode update block * 6ce607eee4 mb/emu/qemu-sbsa: Add missing PCIe ACPI methods * 5458b34de6 soc/intel/meteorlake: Use Arrow Lake FSP * bd2c7443f3 soc/intel/ptl: Add ISCLK for controlling PCIe clock source * 5e8cf41845 mb/google/bluey/mica: Add MAINBOARD_NO_USB_A_PORT configuration * 2107e48c09 mb/google/nissa/var/telith: Generate RAM ID for BWMYAX32P8A-32G * 1d17c9522f mb/google/trulo/var/kaladin: Add LGD touchscreen * 4d9cb5336f mainboard/starlabs: drop display_native_res VBT toggle * 9bb822dbf8 Update vboot submodule from 2024 to upstream main 2026 * 0be563503a mb/google/rauru: Support new bias IC TPS65130RGER * 5d6061d0ba util/amdfwtool: add support for Strix Halo SoC * 391d5f3cb4 mb/google/ocelot/var/ojal: Enable dtt and ish based on FW config * df470521a7 mb/asus/p8x7x-series: Enable single PS/2 port role control * a402a87405 mb/asus/p8z77-v_le_plus/cmos.layout: Extend checksummed area * bbbc655b15 Revert "mb/google/bluey: Configure GPIOs for USB camera" * fc312590d1 drivers/efi: Derive ESRT version from LOCALVERSION * baae037f25 mb/google/bluey/mica: Add PS8820 re-timer configuration * 40abf7946c mb/starlabs/adl/hz: Add missing cnvi_bt_core parameter * 35dbfac13a mb/google/rex/var/karis: Add H58G56CK8BX146 to RAM ID table * 4734da172b memlayout: Introduce PRERAM and POSTRAM TTB regions * 0be9f20be4 soc/intel/pantherlake: Add icc_max settings for WCL SKU * bf5aa04d8b soc/qc/common: Configure framebuffer as uncacheable * ee3aef1c72 mb/google/bluey: Add AC unplug detection and charging status indication * 0449fb45a6 mb/google/bluey: Refactor and secure low-power charging boot path * b7ca29ba92 mb/google/bluey: Power off if charger applet fails to enable charging * ddac3082ea mb/google/fatcat: Enable ChromeOS EC LED control for variants * a1173d9bc1 mb/google/bluey: Enable ChromeEC LED control for Quartz and Mica * eb5bdf06b9 soc/intel/pantherlake: Add power state thresholds for WCL * bf6b14e4f7 mb/google/ocelot: Add VR_DOMAIN_IA for fast_vmode_i_trip * 026bac6de7 arch/x86/ioapic: Add Kconfig option to keep pre-allocated IOAPIC ID * d251282f2d Kconfig: move IOAPIC option to x86 Kconfig * 1bdfc97c54 lib/cbfs: Enable LZ4 decompression in pre-RAM stages * 1965a8740d mb/google/brox/var/caboc: Set LGD touchscreen HID address to 0x01 * 50ce94d715 Revert "soc/intel/pantherlake: Fix DDR5 channel mapping" * ea58a467f1 Revert "soc/intel/pantherlake: Fill in SPD data on both channels of DDR5 memory" * 92a430baee mb/google/fatcat/var/lapis: Modify parameters to reduce acoustic noise * 4caf5ab903 soc/qualcomm/sc7280: Fix extended EDID read over I2C-over-AUX * fd5f062446 mb/asus/p8x7x-series/*tree.cb: Consolidate gen1_dec into baseboard * 6200d53e31 mb/google/bluey: Use LPASS GPIO configure API for Soundwire GPIOs * 1d8c536d79 soc/qualcomm/x1p42100: Add API to configure LPASS GPIO * 1e1b63c23b commonlib/device_tree: Utilize list_move() in dt_copy_subtree() * 89048780c0 commonlib/list: Add list_move() * 00e3b9989c lib: Rename devtree_update to mb_devtree_update * b1194a838b mb/starlabs: Use common devtree_update mechanism * 346a4ccaef mb/google/fatcat/moonstone: Add Samsung LPDDR5 memory parts * fd6c0aa55b util/scripts: Add spd-decode for LPDDR5 SPD hex * 2ac2df0eda sb/intel/wildcatpoint/pcie.c: Reorder some steps * 59ac2cb2c0 sb/intel/wildcatpoint/pcie.c: Drop redundant write * 44901340bf sb/intel/wildcatpoint/pcie.c: Ensure OBFF is disabled * d74570b01e sb/intel/wildcatpoint/acpi: Use Lynx Point files * 9541171de4 sb/intel/wildcatpoint/acpi: Move platform.asl to mainboards * 762b564f3b mb/google/bluey: Add timeout for charging rail stabilization * 61657cff8f spd/lp5: Add SPD for SK hynix H58G56DK9BX068 * 8aa0ea4062 soc/intel/pantherlake: Keep default values for TdcTimeWindow * c97e740981 mb/google/ocelot: Fix fast_vmode_i_trip indexing in devicetree * aaddb83491 soc/intel/pantherlake: Configure TDC IRMS mode for WCL IA domain * f12d2997fc lib/cbfs: Don't include unused LZ4 code to shrink postcar stage * c772a88b1d configs: Remove starbook/adl option table config * dfc2c45ff4 util/inteltool: Add support for Wellsburg * 23db1b3686 mb/google/bluey/mica: Add mainboard part number * b5a703e5a0 mb/google/skywalker: Add mainboard_prepare_cr50_reset() * 8a4937bf8f soc/mediatek: Add mtk_mipi_panel_poweroff() * a300b135c3 soc/mediatek/mt8196: Call mtk_mmu_disable_l2c_sram via boot state * 510e43d8bd soc/mediatek/mt8196: Move WATCHDOG_TOMBSTONE from SRAM to SRAM_L2C * 2f88fec014 mb/google/bluey/mica: Add TPM I2C and EC SPI configuration * 1b5df51c51 soc/intel: Fix Kconfig select order * b52236fe9e soc/intel/pantherlake: Switch to common finalize implementation * 5c56b9ff72 soc/intel/meteorlake: Switch to common finalize implementation * ae932349bf soc/intel/common/block: Add common finalize implementation * c9ba628d51 soc/intel/elkhartlake: Switch to common global reset implementation * 73e89322ce soc/intel/jasperlake: Switch to common global reset implementation * 0277c75bdd soc/intel/cannonlake: Switch to common global reset implementation * 2ff987f906 soc/intel/tigerlake: Switch to common global reset implementation * 0d4b934726 soc/intel/pantherlake: Switch to common global reset implementation * 5c85dcda7f soc/intel/meteorlake: Switch to common global reset implementation * b2a533c918 soc/intel/alderlake: Switch to common global reset implementation * e4ea840114 soc/intel/common: Add common global reset implementation * 7d8acb88c5 soc/intel/pantherlake: Switch to common PMC lockdown driver * 4da2622964 soc/intel/meteorlake: Switch to common PMC lockdown driver * 19fe81f08f soc/intel/alderlake: Switch to common PMC lockdown driver * e160f3c506 soc/intel/common/feature: Add common PMC lockdown driver * fec793e01d sb/intel/wildcatpoint/acpi: Add CID for GPIO device * bacb55e348 nb/intel/broadwell/acpi.c: Use Haswell's file * 3e89a234ef nb/intel/broadwell/acpi.c: Align with Haswell * 958bc5cdff nb/intel/broadwell: Move `size_of_dnvs()` to southbridge * 35694d2ea4 nb/intel/broadwell: Move device NVS to southbridge * 3d4f2efcf7 nb/intel/broadwell/bootblock.c: Use Haswell's file * 7240bbabe9 nb/intel/broadwell/acpi.c: Drop unneeded includes * 4eb0fd7bea nb/intel/broadwell: Move PCH headers to wildcatpoint * 0bc5746188 soc/intel/broadwell: Move to nb/intel/broadwell * d740cee2d9 soc/intel/broadwell/pch: Move to sb/intel/wildcatpoint * 0d2a0512fd sb/intel/lynxpoint: Configure IOSF Port and Grant Count * 8b69dcccb2 sb/intel/lynxpoint/pcie.c: Add additional disable steps * 381ce51ec4 sb/intel/lynxpoint/acpi: Add HIDs for Wildcat Point * 6953c591ba sb/intel/lynxpoint/acpi/serialio.asl: Add more _PS0/_PS3 methods * 0e9c2f53b0 haswell/broadwell: Move CPU bus ops to CPU code * e0715bc0f9 soc/intel/pantherlake: Disable PCIe PM in compliance test mode * bce8d28a59 MAINTAINERS: Add Nicholas Chin for autoport * b6ebb24a48 util/spd_tools/src/spd_gen/lp5.go: Support LP5X 9600Mbps * 13bf2d9566 mb/google/fatcat: Enable C1 and package C-state auto-demotion * 56e645d942 mb/google/fatcat: Change Gen4 and Gen5 NVMe power sequence * 8998999eb3 Haswell NRI: Add dumping of CAPID registers * 343f439801 util/inteltool: set amb registers dumping error print to stdout * 26006cc217 util/ifdtool: show overlapping region name and range details * 93444a0ce0 mb/emul/qemu-[q35,i440fx]: Create ICQR interrupt resource locally and use defined offset * 036af49b1d mb/emul/qemu-q35: Add a _DIS method for gsi_link devices * f5c9c1c166 mb/google/bluey: Move ADSP QUP-I2C init to normal boot path * 61c69ebfa8 mb/starlabs: Drop PCIe detect-timeout/hotplug workarounds * baadfed999 mb/starlabs/adl: Add NVMe power sequencing * 49a5b949ca mb/starlabs/starbook: Add NVMe/WiFi power sequencing * 279406cd14 mb/starlabs/starfighter: Add NVMe port power sequence * 0306eb0723 mb/starlabs/common: add NVMe power sequencing helper * cfbf8f3953 starlabs: drop CMOS option tables * 9dac2b9e53 ec/starlabs/merlin: persist settings via EFI options * 3fa3818e41 starlabs: add ACPI SMI bridge for EFI options * 484e39c068 mp_init: Pass microcode size to MPinit * ea1a722d2b soc/intel/xeon_sp: Move microcode loading * 08e3ad9e03 mb/google/brox/var/juchi: Add 2 memory parts and generate DRAM IDs * ba6de6c866 mb/google/fatcat/var/ruby: Set ISH GP1 gpio pin to NC * fb2e8b5e1e mainboard/google/bluey: Enable charging debug access in common path * ca9b46d341 soc/mediatek: Add common low battery poweroff handling * c222118cbf soc/qualcomm/x1p42100: Remove redundant VBUS enablement logic * 2c58402339 soc/qualcomm/x1p42100: Configure OTG buck for USB host * 10f0a87824 soc/qualcomm/sc7280: Update console message type non-fatal * 270e84e59f vc/chromeos: Provide inline fallbacks for Chromebook Plus branding * fe506bfe84 ec/google/chromeec: Add Kconfig for AP-controlled LED sync * 12710eafff mb/google/bluey: Implement off-mode charging applet * a1dd5f05b0 ec/google/chromeec: Add interface for offmode heartbeat command * 125d9c8643 soc/qualcomm/x1p42100: Add logic for secure boot blob paths * 6de3d04c4e Kconfig: Add Kconfig for signed secure blobs * 0a6142dfbe soc/amd/turin_poc: Add SPI TPM SoC-specific initialization * dde872911a mainboard/starlabs: drop unused TJ_MAX option * 724176a218 mainboard/starlabs: namespace PL4 powercap setting * 5156ec4533 mainboard/starlabs/adl: move SSDT hook to variant * ffad2454c4 mainboard/starlabs/adl: drop redundant ASPM CFR guard * 14fcb3baf8 mainboard/starlabs/adl: move CFR callbacks to variant * 7f02993393 mainboard/starlabs: move starlite under adl/ * e02dc13b87 mainboard/starlabs: move Byte under adl/ * 3ea94fb2dc mb/starlabs/starfighter: Enable the card reader * 56f588eec6 mb/starlabs/*: Don't consider fan presence for default power profile * 19df8826d7 mb/starlabs/starlite_adl: Disable the card reader by default * c940d20696 soc/intel: Consolidate common code macro definitions in pci_devs.h * d03957e10f soc/intel/tigerlake: Use common PCH client SMI handler * 402da237bc soc/intel/pantherlake: Use common PCH client SMI handler * eb205e379a soc/intel/meteorlake: Use common PCH client SMI handler * f0021f84ec soc/intel/alderlake: Use common PCH client SMI handler * 4b73479c38 soc/intel/common/feature/smihandler: Add common PCH client SMI handler * 2eb37453e5 soc/intel/meteorlake: Use common pmutil driver * f0be882d9f soc/intel/pantherlake: Use common pmutil driver * 2b70ce3fbf soc/intel/alderlake: Use common pmutil driver * cc31cc0ab2 soc/intel/common/feature/pmutil: Add common pmutil driver * 189f8d1a86 soc/intel/elkhartlake: Switch to common eSPI/LPC initialization * aeb9db4467 soc/intel/jasperlake: Switch to common eSPI/LPC initialization * 05006995b6 soc/intel/tigerlake: Switch to common eSPI/LPC initialization * 7278030fa6 soc/intel/pantherlake: Switch to common eSPI/LPC initialization * 4fe7e7fa36 soc/intel/meteorlake: Switch to common eSPI/LPC initialization * 34be3842a1 soc/intel/alderlake: Switch to common eSPI/LPC initialization * 0464f1032a soc/intel/common/feature/espi: Add common eSPI/LPC initialization * f780b7c576 soc/intel/tigerlake: Use common SoundWire driver * 620a33f1c8 soc/intel/pantherlake: Use common SoundWire driver * ffc67b2938 soc/intel/meteorlake: Use common SoundWire driver * ef364d623d soc/intel/alderlake: Use common SoundWire driver * 74d4fac210 soc/intel/common/feature/soundwire: Add common SoundWire driver * 7bee4f5efb mb/starlabs: Drop explicit devtree_update calls * f8494fbeae lib: Add devtree_update bootstate hook * 69242d5bb1 drivers/usb/acpi: Add DSM function 3 support for Intel Bluetooth * 50e92c9cf1 mb/lenovo/m920q: Rename to reflect use for m720q variant as well * e0c26a05d4 ec/starlabs/merlin: fix OSFG suspend comment * ce5c915344 drivers/spi/flashconsole.c: Fix flashconsole * c2eea0c96c mainboard/starlabs/adl: add Bluetooth RTD3 CFR option * 7847a54eed mb/lenovo: Convert PNP device to generic device * 091ae533b9 mb/lenovo/t430: Merge into t430 into t530 * 3a5e4660bb mb/lenovo/t530: Unify GEN_DEC entries * 416875e93e mb/lenovo/t430|t530: Reduces differences in code * 57f96b83fe mb/google/link/hda_verb: Remove presence detect flag from internal sources * 6be9ee7ce4 mb/google/link: Use AZALIA_PIN_DESC macros for pin widgets * 8718db133a mb/google/fatcat/var/lapis: Add 2 Micron modules to RAM id table * f9f43d862d spd/lp5: Add Micron memory part * c57b88d74d mb/google/brox/var/lotso: delete mb_get_channel_disable_mask * 8ba58ef800 mb/samsung/lumpy: Correct NID 0x08 HDA pin config macro usage * 38988a727e util/mediatek: Reduce non-boot related BROM settings * e84415b8f8 mb/google/nissa/var/yaviks: Add micron memory to RAM ID table * 08dcaf404c mb/google/nissa/var/yavilla: Add micron memory to RAM ID table * 523242b2b9 google/bluey: Add RW_CDT region to flash map * 5e46ac1364 mb/google/bluey: Resize WP_RO and add RW_UNUSED region * 08f2f3a21b Haswell NRI: Implement 1D margin training * 098a5cf16e mb/google/ocelot: Configure CDCLK frequency for display * 7b205808e4 mb/google/rauru: Disable CHROMEOS_USE_EC_WATCHDOG_FLAG * b1e8f87b30 mb/google/rauru: Enable MEDIATEK_WDT_RESET_BY_SW * f4825e5c12 soc/amd/common: Add I3C driver * cf5d6f1c88 soc/intel/common/block/gspi: Simplify Makefile using all-$() * 56ede20f10 soc/intel/pantherlake: Use common SPI device function driver * 4bdeb73635 soc/intel/meteorlake: Use common SPI device function driver * 8ecff12528 soc/intel/alderlake: Use common SPI device function driver * 0aea05411d soc/intel/tigerlake: Use common SPI device function driver * 47f3e7e3cc soc/intel/jasperlake: Use common SPI device function driver * 91520ab096 soc/intel/common/feature/spi: Add common SPI device function driver * 0668959a92 soc/intel/skylake: Use common GSPI devfn mapping * 45d3ab84a8 soc/intel/cannonlake: Use common GSPI devfn mapping * 4aae5fb66d soc/intel/elkhartlake: Use common GSPI devfn mapping * 78ef2d0433 soc/intel/jasperlake: Use common GSPI devfn mapping * 66a6c25ef8 soc/intel/tigerlake: Use common GSPI devfn mapping * 3c92c8402a soc/intel/pantherlake: Use common GSPI devfn mapping * 6459039b76 soc/intel/meteorlake: Use common GSPI devfn mapping * 039f21b5e3 soc/intel/alderlake: Use common GSPI devfn mapping * a4bc3131a5 soc/intel/common/feature/gspi: Add common devfn mapping * 253689aebb sb/intel/lynxpoint/acpi/xhci.asl: Guard PCH-LP methods * 72ecebf0c3 soc/intel/broadwell/acpi/xhci.asl: Use macros for constants * 813edbbde8 sb/intel/lynxpoint/acpi/xhci.asl: Use macros for constants * 3cde265c28 sb/intel/lynxpoint/acpi/xhci.asl: Drop redundant writes * a59ddda11e Doc/mb/protectli/fw6: describe revisions and more variants * d5161611a4 soc/intel/pantherlake: Use common I2C devfn mapping * 78e36f8c78 soc/intel/meteorlake: Use common I2C devfn mapping * f703f2800c soc/intel/skylake: Use common I2C devfn mapping * 7f922438be soc/intel/cannonlake: Use common I2C devfn mapping * a0ba812a09 soc/intel/jasperlake: Use common I2C devfn mapping * 83325f354b soc/intel/tigerlake: Use common I2C devfn mapping * fe728d62c9 soc/intel/elkhartlake: Use common I2C devfn mapping * 749bae2f94 soc/intel/alderlake: Use common I2C devfn mapping * b21e861ab5 soc/intel/common/feature/i2c: Add common devfn mapping * 34c156427d soc/intel/common/block/lpc: Fix AMASK decoding in window detection * b50c219557 soc/intel: Use centralized emergency battery shutdown hook * a96f1a464b mb/google/bluey: Use common platform hook for emergency shutdown * 5c44e689ee vc/google/chromeos: Add platform hook for emergency battery shutdown * 086d3a3232 mb/google/fatcat: Enable ChromeOS EC LEDs in romstage * 2a821d8db6 mb/google/bluey: Early enablement of lightbar * d39f406f55 mb/google/bluey: Disable lightbar during low-power charging boot * b68ba24244 ec/google/chromeec: Add API to turn on lightbar * 5f9a1ad962 ec/google/chromeec: Add API to turn off lightbar * 4028996c9d mb/google/nissa/var/pujjoquince: Add support for Micron MT62F1G32D2DS-031RF * 800db242bd {soc,sb}/intel: Drop named object from ASL `GPLD` method * 57e30e6b9d mb/google/brask/var/moxoe: Switch memory to DDR5 * c069dc3eb1 mb/google/fatcat/var/ruby: Add settings for resolving EE noise * 5ac3e40282 mb/google/brox/var/caboc: Probe LGD touchscreen by fw_config * 61ce86ea3e mb/siemens/mc_ehl6: Reduce clock rate for I2C1 * acd8f42410 soc/intel/skylake: Use common UART device list driver * a69d537e61 soc/intel/cannonlake: Use common UART device list driver * e31d32443e Revert "mb/google/fatcat: Fix Gen4 SSD power sequencing" * 7b4fb78e34 soc/intel/elkhartlake: Use common UART device list driver * bb95093b8f soc/intel/jasperlake: Use common UART device list driver * 61dc1e04e0 soc/intel/tigerlake: Use common UART device list driver * 38baf0c5f6 soc/intel/meteorlake: Use common UART device list driver * 44fcbf84b3 soc/intel/snowridge: Move defines to soc/pci_devs.h * dfcd63370d cpu/intel: Use existing defines for MTRR_CAP_MSR * fd2cdf206d cpu/intel/smm/gen1: Optimize cpu_has_alternative_smrr * f96644e774 nb/intel/haswell: Do not print ME status twice * d9bc4740da nb/intel/haswell: Fix DDR frequency reporting * 6a1b016184 nb/intel/haswell: Tidy up memory info prints * f89ac4e6ce soc/mediatek/common: Adjust splash logo bottom margin * f01e11ac5c vc/intel/fsp/fsp2_0/wildcatlake: Update WCL FSP headers to version WCL.3515.03 * 326e33b82d soc/intel/pantherlake: Use common UART device list driver * 3337e56b50 soc/intel/alderlake: Use common UART device list driver * bb941824ca soc/intel/common/feature/uart: Add common UART device list driver * 78295974f8 soc/intel/common: Add feature directory for SoC-specific common code * f691421daf soc/intel/common: Replace CFR enums with booleans * 24870f54e0 soc/intel/skylake: Replace CFR enums with booleans * 666e66800c soc/intel/tigerlake: Replace CFR enums with booleans * 12f99ab067 soc/intel/alderlake: Replace CFR enums with booleans * 47bc0a727c soc/intel/jasperlake: Replace CFR enums with booleans * 1b0147f05b soc/intel/meteorlake: Replace CFR enums with booleans * b935d5b058 soc/intel/cannonlake: Replace CFR enums with booleans * daa32be457 soc/intel/apollolake: Replace CFR enums with booleans * 90f9d9e7c6 mb/google/poppy: Replace CFR enums with booleans * 6b481c73dd mb/google/hatch: Replace CFR enums with booleans * 9a58dc7fee mb/google/auron: Replace CFR enums with booleans * e7c05d666c mb/google/volteer: Replace CFR enums with booleans * 71b7167396 mb/lenovo/sklkbl_thinkpad: Replace CFR enums with booleans * ed10b36edf ec/google/chromeec: Replace CFR enums with booleans * d19e5d2550 ec/lenovo/pmh7: Replace CFR enums with booleans * 0ff3c3d2ec ec/lenovo/h8: Replace CFR enums with booleans * f9f81e4839 mb/lenovo/x220: Replace CFR enums with booleans * 7e8850a862 mb/google/*/cfr.c: Drop initial empty line * 220669643b soc/qualcomm: Add Kconfig to skip redundant MMU toggling * c9578eac24 mb/google/ocelot: Add THC-SPI Touchscreen support in fw_config * d88e98cf49 mb/google/fatcat/lapis: Remove RTD3 config for SSD * 24866fefef mb/google/fatcat/var/lapis: Add UFSC bit of new FP MCU * 33d873324e mb/lenovo/*: Drop unused ACPI code * 571dbbe345 mb/lenovo/t430: Move TPM in devicetree.cb * 06446dd0ac dram/ddr3: Add speed in MT/s * bf148cae0a lib/dimm_info_util.c: Handle 16-bit memory bus extension for ECC * a3923d678f ec/starlabs/merlin: fix ITE CMOS index mapping * e47952c3a7 mb/asus/p8x7x-series: Enable common SIO ASL code * e82ecc739d sio/nuvoton/nct6776: Switch to common init code * e72a325c40 sio/nuvoton/nct{5535,6779}d: Use new common init code * 65c4ea0bfb superio/acpi/pnp_kbc.asl: Allow changing device and PNP IDs * 2de0c9575d sio/nuvoton/nct6776: Switch to common Nuvoton ASL code * 94a356e0c8 sio/nuvoton/nct5535d: Use common ASL code * 4cee52e457 sio/nuvoton/nct6791d: Enable common ASL code * c30802d6fb sio/nuvoton/nct6779d: Enable common ASL code * 7876bcaa86 sio/nuvoton: Implement common ramstage keyboard/ACPI init routines * afeca9f422 mb/starlabs: disable TCO INTRUDER# SMI by default * c996684f40 intel/smm: make TCO INTRUDER# SMI optional * 339ef9b5c9 soc/intel/common/block/lpc: Improve automatic window opening * f1e4de7fbf mb/google/dedede/var/galtic: Add fw_config option for touchpad type * 08b05f56a6 Revert "mb/google/dedede/galtic: Add CFR option for touchpad type" * ed5a993f0f mb/google/fatcat/lapis: Enable eSOL feature Signed-off-by: Leah Rowe --- ...01-add-c3-and-clockgen-to-apple-macbook21.patch | 44 +- ...-mb-lenovo-t430-Merge-into-t430-into-t530.patch | 1097 ++++++++++++++ .../0002-lenovo-t400-Enable-all-SATA-ports.patch | 34 - .../0003-lenovo-t400-Enable-all-SATA-ports.patch | 34 + ...230-set-me_state-Disabled-in-cmos.default.patch | 37 - ...230-set-me_state-Disabled-in-cmos.default.patch | 37 + ..._state-Disabled-on-all-cmos.default-files.patch | 124 -- ..._state-Disabled-on-all-cmos.default-files.patch | 124 ++ ...-ifdtool-add-nuke-flag-all-0xFF-on-region.patch | 207 --- ...00-Enable-01.0-device-in-devicetree-for-d.patch | 28 - ...-ifdtool-add-nuke-flag-all-0xFF-on-region.patch | 207 +++ ...ing-for-coreboot-images-built-without-a-p.patch | 39 - ...00-Enable-01.0-device-in-devicetree-for-d.patch | 28 + ...CK-Disable-coreboot-related-BL31-features.patch | 28 - ...ing-for-coreboot-images-built-without-a-p.patch | 39 + ...CK-Disable-coreboot-related-BL31-features.patch | 28 + ...-dell-e6430-use-ME-Soft-Temporary-Disable.patch | 30 - ...-dell-e6430-use-ME-Soft-Temporary-Disable.patch | 30 + ...0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch | 872 ----------- ...0011-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch | 872 +++++++++++ ...intel-haswell-make-IOMMU-a-runtime-option.patch | 292 ---- ...ll-optiplex_9020-Disable-IOMMU-by-default.patch | 29 - ...intel-haswell-make-IOMMU-a-runtime-option.patch | 293 ++++ ...ll-optiplex_9020-Disable-IOMMU-by-default.patch | 29 + ...well-Fully-disable-iGPU-when-dGPU-is-used.patch | 51 - ...c-dell-mec5035-Add-S3-suspend-SMI-handler.patch | 147 -- ...well-Fully-disable-iGPU-when-dGPU-is-used.patch | 51 + ...c-dell-mec5035-Add-S3-suspend-SMI-handler.patch | 147 ++ ...ell-lock-policy-regs-when-disabling-IOMMU.patch | 55 - ...ell-lock-policy-regs-when-disabling-IOMMU.patch | 54 + ...0016-nb-intel-gm45-Make-DDR2-raminit-work.patch | 223 --- ...Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch | 240 --- ...0017-nb-intel-gm45-Make-DDR2-raminit-work.patch | 223 +++ ...00-Use-100-MHz-reference-clock-for-displa.patch | 51 - ...Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch | 240 +++ ...00-Use-100-MHz-reference-clock-for-displa.patch | 51 + ...019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch | 52 - ...-mb-dell-gm45_latitudes-Add-E4300-variant.patch | 332 ----- ...020-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch | 52 + ...ell-Add-S3-SMI-handler-for-Dell-Latitudes.patch | 70 - ...-mb-dell-gm45_latitudes-Add-E4300-variant.patch | 332 +++++ ...-Disable-compression-on-refcode-insertion.patch | 31 - ...ell-Add-S3-SMI-handler-for-Dell-Latitudes.patch | 70 + ...-Disable-compression-on-refcode-insertion.patch | 31 + ...ntel-Disable-stack-overflow-debug-options.patch | 187 --- ...024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch | 708 --------- ...ntel-Disable-stack-overflow-debug-options.patch | 187 +++ ...025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch | 708 +++++++++ ...025-mb-dell-optiplex_780-Add-USFF-variant.patch | 326 ----- ...026-mb-dell-optiplex_780-Add-USFF-variant.patch | 326 +++++ ...rc-intel-x4x-Disable-stack-overflow-debug.patch | 33 - ...p-8300cmt-remove-xhci_overcurrent_mapping.patch | 42 - ...rc-intel-x4x-Disable-stack-overflow-debug.patch | 33 + .../0028-dell-3050micro-disable-nvme-hotplug.patch | 47 - ...p-8300cmt-remove-xhci_overcurrent_mapping.patch | 42 + .../0029-dell-3050micro-disable-nvme-hotplug.patch | 47 + ...kylake-Disable-stack-overflow-debug-optio.patch | 61 - ...30-soc-intel-skylake-Don-t-compress-FSP-S.patch | 36 - ...kylake-Disable-stack-overflow-debug-optio.patch | 61 + ...Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch | 78 - ...31-soc-intel-skylake-Don-t-compress-FSP-S.patch | 36 + ...ional-TBFW-setting-for-kabylake-thinkpads.patch | 37 - ...Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch | 78 + ...ional-TBFW-setting-for-kabylake-thinkpads.patch | 37 + ...lderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch | 30 - ...PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch | 76 - ...lderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch | 30 + ...PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch | 76 + ...-soc-intel-alderlake-Don-t-compress-FSP-S.patch | 35 - ...e-don-t-require-full-fsp-repo-for-fd-path.patch | 33 - ...-soc-intel-alderlake-Don-t-compress-FSP-S.patch | 35 + ...e-don-t-require-full-fsp-repo-for-fd-path.patch | 33 + ...rlake-disable-stack-overflow-debug-option.patch | 46 - ...5035-Add-command-to-disable-EC-initiated-.patch | 92 -- ...rlake-disable-stack-overflow-debug-option.patch | 46 + ...5035-Add-command-to-disable-EC-initiated-.patch | 92 ++ ..._ivb_latitude-Disable-EC-initiated-shutdo.patch | 36 - .../default/patches/0040-fix-ifdtool-build.patch | 28 - ..._ivb_latitude-Disable-EC-initiated-shutdo.patch | 36 + .../default/patches/0041-fix-ifdtool-build.patch | 28 + ...akefile.mk-use-3rdparty-cmocka-by-default.patch | 30 - ...ll-optiplex_780-use-legacy-HDA-verb-table.patch | 51 - ...akefile.mk-use-3rdparty-cmocka-by-default.patch | 30 + .../0043-hp8300cmt-use-legacy-verb-table.patch | 30 - ...ll-optiplex_780-use-legacy-HDA-verb-table.patch | 51 + .../0044-hp8300cmt-use-legacy-verb-table.patch | 30 + .../patches/0044-topton-x2e-n150-use-old-fsp.patch | 34 - ...ro-x11-lga1151-series-Disable-ME-HECI-in-.patch | 31 - .../patches/0045-topton-x2e-n150-use-old-fsp.patch | 34 + ...ro-x11-lga1151-series-Disable-ME-HECI-in-.patch | 31 + ...l-ifdtool-option-to-allow-region-override.patch | 60 - ...0047-me_cleaner-don-t-modify-if-k-is-used.patch | 44 - ...l-ifdtool-option-to-allow-region-override.patch | 68 + ...klkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch | 600 -------- ...0048-me_cleaner-don-t-modify-if-k-is-used.patch | 44 + ...klkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch | 600 ++++++++ ...ovo-x270-Provide-correct-vbt-and-hda_verb.patch | 132 -- ...0050-mb-dell-Add-OptiPlex-3040-Micro-port.patch | 1528 ------------------- ...ovo-x270-Provide-correct-vbt-and-hda_verb.patch | 129 ++ ...-OptiPlex-3040-Micro-port-upstream-compat.patch | 1530 ++++++++++++++++++++ ...ro-x11-lga1151-series-Enable-SATA-hotplug.patch | 46 - 101 files changed, 8569 insertions(+), 7511 deletions(-) create mode 100644 config/coreboot/default/patches/0002-Revert-mb-lenovo-t430-Merge-into-t430-into-t530.patch delete mode 100644 config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch create mode 100644 config/coreboot/default/patches/0003-lenovo-t400-Enable-all-SATA-ports.patch delete mode 100644 config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch create mode 100644 config/coreboot/default/patches/0004-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch delete mode 100644 config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch create mode 100644 config/coreboot/default/patches/0005-set-me_state-Disabled-on-all-cmos.default-files.patch delete mode 100644 config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch delete mode 100644 config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch create mode 100644 config/coreboot/default/patches/0006-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch delete mode 100644 config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch create mode 100644 config/coreboot/default/patches/0007-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch delete mode 100644 config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch create mode 100644 config/coreboot/default/patches/0008-Remove-warning-for-coreboot-images-built-without-a-p.patch create mode 100644 config/coreboot/default/patches/0009-HACK-Disable-coreboot-related-BL31-features.patch delete mode 100644 config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch create mode 100644 config/coreboot/default/patches/0010-dell-e6430-use-ME-Soft-Temporary-Disable.patch delete mode 100644 config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch create mode 100644 config/coreboot/default/patches/0011-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch delete mode 100644 config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch delete mode 100644 config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch create mode 100644 config/coreboot/default/patches/0012-nb-intel-haswell-make-IOMMU-a-runtime-option.patch create mode 100644 config/coreboot/default/patches/0013-dell-optiplex_9020-Disable-IOMMU-by-default.patch delete mode 100644 config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch delete mode 100644 config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch create mode 100644 config/coreboot/default/patches/0014-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch create mode 100644 config/coreboot/default/patches/0015-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch delete mode 100644 config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch create mode 100644 config/coreboot/default/patches/0016-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch delete mode 100644 config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch delete mode 100644 config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch create mode 100644 config/coreboot/default/patches/0017-nb-intel-gm45-Make-DDR2-raminit-work.patch delete mode 100644 config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch create mode 100644 config/coreboot/default/patches/0018-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch create mode 100644 config/coreboot/default/patches/0019-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch delete mode 100644 config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch delete mode 100644 config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch create mode 100644 config/coreboot/default/patches/0020-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch delete mode 100644 config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch create mode 100644 config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch delete mode 100644 config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch create mode 100644 config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch create mode 100644 config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch delete mode 100644 config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch delete mode 100644 config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch create mode 100644 config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch create mode 100644 config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch delete mode 100644 config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch create mode 100644 config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch delete mode 100644 config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch delete mode 100644 config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch create mode 100644 config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch delete mode 100644 config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch create mode 100644 config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch create mode 100644 config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch delete mode 100644 config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch delete mode 100644 config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch create mode 100644 config/coreboot/default/patches/0030-src-intel-skylake-Disable-stack-overflow-debug-optio.patch delete mode 100644 config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch create mode 100644 config/coreboot/default/patches/0031-soc-intel-skylake-Don-t-compress-FSP-S.patch delete mode 100644 config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch create mode 100644 config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch create mode 100644 config/coreboot/default/patches/0033-Conditional-TBFW-setting-for-kabylake-thinkpads.patch delete mode 100644 config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch delete mode 100644 config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch create mode 100644 config/coreboot/default/patches/0034-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch create mode 100644 config/coreboot/default/patches/0035-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch delete mode 100644 config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch delete mode 100644 config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch create mode 100644 config/coreboot/default/patches/0036-soc-intel-alderlake-Don-t-compress-FSP-S.patch create mode 100644 config/coreboot/default/patches/0037-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch delete mode 100644 config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch delete mode 100644 config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch create mode 100644 config/coreboot/default/patches/0038-soc-alderlake-disable-stack-overflow-debug-option.patch create mode 100644 config/coreboot/default/patches/0039-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch delete mode 100644 config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch delete mode 100644 config/coreboot/default/patches/0040-fix-ifdtool-build.patch create mode 100644 config/coreboot/default/patches/0040-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch create mode 100644 config/coreboot/default/patches/0041-fix-ifdtool-build.patch delete mode 100644 config/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch delete mode 100644 config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch create mode 100644 config/coreboot/default/patches/0042-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch delete mode 100644 config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch create mode 100644 config/coreboot/default/patches/0043-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch create mode 100644 config/coreboot/default/patches/0044-hp8300cmt-use-legacy-verb-table.patch delete mode 100644 config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch delete mode 100644 config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch create mode 100644 config/coreboot/default/patches/0045-topton-x2e-n150-use-old-fsp.patch create mode 100644 config/coreboot/default/patches/0046-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch delete mode 100644 config/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch delete mode 100644 config/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch create mode 100644 config/coreboot/default/patches/0047-util-ifdtool-option-to-allow-region-override.patch delete mode 100644 config/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch create mode 100644 config/coreboot/default/patches/0048-me_cleaner-don-t-modify-if-k-is-used.patch create mode 100644 config/coreboot/default/patches/0049-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch delete mode 100644 config/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch delete mode 100644 config/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port.patch create mode 100644 config/coreboot/default/patches/0050-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch create mode 100644 config/coreboot/default/patches/0051-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch delete mode 100644 config/coreboot/default/patches/0051-mb-supermicro-x11-lga1151-series-Enable-SATA-hotplug.patch (limited to 'config/coreboot/default/patches') diff --git a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch index b654b32c..5fc4b8b5 100644 --- a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch +++ b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch @@ -1,30 +1,30 @@ -From 03e8f5f33723fd291e30c5305fa2f5eb22bdf656 Mon Sep 17 00:00:00 2001 +From 11f759cb05a4d9f4656982a8afea40d7dadfb93e Mon Sep 17 00:00:00 2001 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> Date: Wed, 27 Oct 2021 13:36:01 +0200 -Subject: [PATCH 01/48] add c3 and clockgen to apple/macbook21 +Subject: [PATCH 01/51] add c3 and clockgen to apple/macbook21 --- - src/mainboard/apple/macbook21/Kconfig | 1 + - src/mainboard/apple/macbook21/cstates.c | 13 +++++++++++++ - src/mainboard/apple/macbook21/devicetree.cb | 6 ++++++ + src/mainboard/apple/i945_macs/Kconfig | 1 + + src/mainboard/apple/i945_macs/cstates.c | 13 +++++++++++++ + src/mainboard/apple/i945_macs/devicetree.cb | 6 ++++++ 3 files changed, 20 insertions(+) -diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig -index 330d8efae2..cf10343554 100644 ---- a/src/mainboard/apple/macbook21/Kconfig -+++ b/src/mainboard/apple/macbook21/Kconfig -@@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS - select HAVE_ACPI_TABLES - select HAVE_ACPI_RESUME +diff --git a/src/mainboard/apple/i945_macs/Kconfig b/src/mainboard/apple/i945_macs/Kconfig +index 42774e484a..cd5155e81a 100644 +--- a/src/mainboard/apple/i945_macs/Kconfig ++++ b/src/mainboard/apple/i945_macs/Kconfig +@@ -20,6 +20,7 @@ config BOARD_APPLE_MACBOOK11 + bool + select BOARD_APPLE_I945_MACS_COMMON select I945_LVDS + select DRIVERS_I2C_CK505 - config MAINBOARD_DIR - default "apple/macbook21" -diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c + config BOARD_APPLE_MACBOOK21 + bool +diff --git a/src/mainboard/apple/i945_macs/cstates.c b/src/mainboard/apple/i945_macs/cstates.c index 13d06f0839..88b8669c61 100644 ---- a/src/mainboard/apple/macbook21/cstates.c -+++ b/src/mainboard/apple/macbook21/cstates.c +--- a/src/mainboard/apple/i945_macs/cstates.c ++++ b/src/mainboard/apple/i945_macs/cstates.c @@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = { .addrh = 0, } @@ -45,11 +45,11 @@ index 13d06f0839..88b8669c61 100644 }; int get_cst_entries(const acpi_cstate_t **entries) -diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb -index fd86e939b9..263fbabcd1 100644 ---- a/src/mainboard/apple/macbook21/devicetree.cb -+++ b/src/mainboard/apple/macbook21/devicetree.cb -@@ -100,7 +100,13 @@ chip northbridge/intel/i945 +diff --git a/src/mainboard/apple/i945_macs/devicetree.cb b/src/mainboard/apple/i945_macs/devicetree.cb +index b17f8ae529..18731b067f 100644 +--- a/src/mainboard/apple/i945_macs/devicetree.cb ++++ b/src/mainboard/apple/i945_macs/devicetree.cb +@@ -89,7 +89,13 @@ chip northbridge/intel/i945 end device pci 1f.3 on # SMBUS subsystemid 0x8086 0x7270 diff --git a/config/coreboot/default/patches/0002-Revert-mb-lenovo-t430-Merge-into-t430-into-t530.patch b/config/coreboot/default/patches/0002-Revert-mb-lenovo-t430-Merge-into-t430-into-t530.patch new file mode 100644 index 00000000..d905e5cf --- /dev/null +++ b/config/coreboot/default/patches/0002-Revert-mb-lenovo-t430-Merge-into-t430-into-t530.patch @@ -0,0 +1,1097 @@ +From 3c5b15f0aa0ba2c9e7d4db6f893e13978c045032 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Thu, 23 Apr 2026 20:00:33 +0100 +Subject: [PATCH 02/51] Revert "mb/lenovo/t430: Merge into t430 into t530" + +This reverts commit 091ae533b9fdb5b78a5edbc2b68c2faee083f1dd. +--- + src/mainboard/lenovo/t430/Kconfig | 80 +++++++++ + src/mainboard/lenovo/t430/Kconfig.name | 4 + + src/mainboard/lenovo/t430/Makefile.mk | 8 + + src/mainboard/lenovo/t430/acpi/ec.asl | 4 + + src/mainboard/lenovo/t430/acpi/platform.asl | 23 +++ + src/mainboard/lenovo/t430/acpi/superio.asl | 3 + + src/mainboard/lenovo/t430/acpi_tables.c | 15 ++ + src/mainboard/lenovo/t430/board_info.txt | 6 + + src/mainboard/lenovo/t430/cmos.default | 20 +++ + src/mainboard/lenovo/t430/cmos.layout | 108 ++++++++++++ + .../lenovo/{t530/variants => }/t430/data.vbt | Bin + src/mainboard/lenovo/t430/devicetree.cb | 166 ++++++++++++++++++ + src/mainboard/lenovo/t430/dsdt.asl | 39 ++++ + src/mainboard/lenovo/t430/early_init.c | 40 +++++ + src/mainboard/lenovo/t430/gma-mainboard.ads | 22 +++ + .../lenovo/{t530/variants => }/t430/gpio.c | 0 + .../{t530/variants => }/t430/hda_verb.c | 0 + src/mainboard/lenovo/t430/mainboard.c | 15 ++ + src/mainboard/lenovo/t430/smihandler.c | 68 +++++++ + .../lenovo/t430/vboot-ro-me_clean.fmd | 21 +++ + src/mainboard/lenovo/t430/vboot-ro.fmd | 21 +++ + src/mainboard/lenovo/t430/vboot-rwab.fmd | 35 ++++ + src/mainboard/lenovo/t530/Kconfig | 7 - + src/mainboard/lenovo/t530/Kconfig.name | 3 - + src/mainboard/lenovo/t530/Makefile.mk | 1 - + .../t530/{variants/t530 => }/hda_verb.c | 0 + .../lenovo/t530/variants/t430/overridetree.cb | 58 ------ + .../lenovo/t530/variants/w530/hda_verb.c | 75 -------- + 28 files changed, 698 insertions(+), 144 deletions(-) + create mode 100644 src/mainboard/lenovo/t430/Kconfig + create mode 100644 src/mainboard/lenovo/t430/Kconfig.name + create mode 100644 src/mainboard/lenovo/t430/Makefile.mk + create mode 100644 src/mainboard/lenovo/t430/acpi/ec.asl + create mode 100644 src/mainboard/lenovo/t430/acpi/platform.asl + create mode 100644 src/mainboard/lenovo/t430/acpi/superio.asl + create mode 100644 src/mainboard/lenovo/t430/acpi_tables.c + create mode 100644 src/mainboard/lenovo/t430/board_info.txt + create mode 100644 src/mainboard/lenovo/t430/cmos.default + create mode 100644 src/mainboard/lenovo/t430/cmos.layout + rename src/mainboard/lenovo/{t530/variants => }/t430/data.vbt (100%) + create mode 100644 src/mainboard/lenovo/t430/devicetree.cb + create mode 100644 src/mainboard/lenovo/t430/dsdt.asl + create mode 100644 src/mainboard/lenovo/t430/early_init.c + create mode 100644 src/mainboard/lenovo/t430/gma-mainboard.ads + rename src/mainboard/lenovo/{t530/variants => }/t430/gpio.c (100%) + rename src/mainboard/lenovo/{t530/variants => }/t430/hda_verb.c (100%) + create mode 100644 src/mainboard/lenovo/t430/mainboard.c + create mode 100644 src/mainboard/lenovo/t430/smihandler.c + create mode 100644 src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd + create mode 100644 src/mainboard/lenovo/t430/vboot-ro.fmd + create mode 100644 src/mainboard/lenovo/t430/vboot-rwab.fmd + rename src/mainboard/lenovo/t530/{variants/t530 => }/hda_verb.c (100%) + delete mode 100644 src/mainboard/lenovo/t530/variants/t430/overridetree.cb + delete mode 100644 src/mainboard/lenovo/t530/variants/w530/hda_verb.c + +diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig +new file mode 100644 +index 0000000000..2b6eb17e9c +--- /dev/null ++++ b/src/mainboard/lenovo/t430/Kconfig +@@ -0,0 +1,80 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++if BOARD_LENOVO_THINKPAD_T430 ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ select AZALIA_USE_LEGACY_VERB_TABLE ++ select BOARD_ROMSIZE_KB_12288 ++ select DRIVERS_LENOVO_HYBRID_GRAPHICS ++ select DRIVER_LENOVO_SERIALS ++ select DRIVER_LENOVO_SERIALS_EARLY_LOCK ++ select DRIVERS_RICOH_RCE822 ++ select EC_LENOVO_H8 ++ select EC_LENOVO_PMH7 ++ select GFX_GMA_PANEL_1_ON_LVDS ++ select H8_HAS_BAT_THRESHOLDS_IMPL ++ select H8_HAS_BDC_GPIO_DETECTION ++ select H8_HAS_WWAN_GPIO_DETECTION ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ select INTEL_GMA_HAVE_VBT ++ select INTEL_INT15 ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_HAS_TPM1 ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select MEMORY_MAPPED_TPM ++ select NO_UART_ON_SUPERIO ++ select NORTHBRIDGE_INTEL_SANDYBRIDGE ++ select SERIRQ_CONTINUOUS_MODE ++ select SOUTHBRIDGE_INTEL_C216 ++ select SYSTEM_TYPE_LAPTOP ++ select USE_NATIVE_RAMINIT ++ ++config VBOOT ++ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC ++ select GBB_FLAG_DISABLE_FWMP ++ select GBB_FLAG_DISABLE_LID_SHUTDOWN ++ select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC ++ select HAS_RECOVERY_MRC_CACHE ++ select VBOOT_VBNV_FLASH ++ ++config VBOOT_SLOTS_RW_AB ++ default y ++ ++config CBFS_SIZE ++ default 0x700000 ++ ++config FMDFILE ++ default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT ++ ++config MAINBOARD_DIR ++ default "lenovo/t430" ++ ++config MAINBOARD_PART_NUMBER ++ default "ThinkPad T430" ++ ++config VGA_BIOS_ID ++ string ++ default "8086,0166" ++ ++config DRAM_RESET_GATE_GPIO ++ int ++ default 10 ++ ++config USBDEBUG_HCD_INDEX ++ int ++ default 2 ++ ++config PS2K_EISAID ++ default "PNP0303" ++ ++config PS2M_EISAID ++ default "LEN0015" ++ ++config THINKPADEC_HKEY_EISAID ++ default "LEN0068" ++ ++endif +diff --git a/src/mainboard/lenovo/t430/Kconfig.name b/src/mainboard/lenovo/t430/Kconfig.name +new file mode 100644 +index 0000000000..f14a1a2d78 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/Kconfig.name +@@ -0,0 +1,4 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_LENOVO_THINKPAD_T430 ++ bool "ThinkPad T430" +diff --git a/src/mainboard/lenovo/t430/Makefile.mk b/src/mainboard/lenovo/t430/Makefile.mk +new file mode 100644 +index 0000000000..e4b6fbf0f0 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/Makefile.mk +@@ -0,0 +1,8 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++bootblock-y += gpio.c ++romstage-y += gpio.c ++ ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads ++bootblock-y += early_init.c ++romstage-y += early_init.c +diff --git a/src/mainboard/lenovo/t430/acpi/ec.asl b/src/mainboard/lenovo/t430/acpi/ec.asl +new file mode 100644 +index 0000000000..987593e919 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/acpi/ec.asl +@@ -0,0 +1,4 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include +diff --git a/src/mainboard/lenovo/t430/acpi/platform.asl b/src/mainboard/lenovo/t430/acpi/platform.asl +new file mode 100644 +index 0000000000..9dee90edc3 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/acpi/platform.asl +@@ -0,0 +1,23 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* The _PTS method (Prepare To Sleep) is called before the OS is ++ * entering a sleep state. The sleep state number is passed in Arg0 ++ */ ++ ++Method(_PTS,1) ++{ ++ \_SB.PCI0.LPCB.EC.MUTE(1) ++ \_SB.PCI0.LPCB.EC.USBP(0) ++ \_SB.PCI0.LPCB.EC.RADI(0) ++} ++ ++/* The _WAK method is called on system wakeup */ ++ ++Method(_WAK,1) ++{ ++ /* Wake the HKEY to init BT/WWAN */ ++ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) ++ ++ /* Not implemented. */ ++ Return(Package(){0,0}) ++} +diff --git a/src/mainboard/lenovo/t430/acpi/superio.asl b/src/mainboard/lenovo/t430/acpi/superio.asl +new file mode 100644 +index 0000000000..ee2eabeb75 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/acpi/superio.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include +diff --git a/src/mainboard/lenovo/t430/acpi_tables.c b/src/mainboard/lenovo/t430/acpi_tables.c +new file mode 100644 +index 0000000000..36d3e85c1e +--- /dev/null ++++ b/src/mainboard/lenovo/t430/acpi_tables.c +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_fill_gnvs(struct global_nvs *gnvs) ++{ ++ /* The lid is open by default */ ++ gnvs->lids = 1; ++ ++ /* Temperature at which OS will shutdown */ ++ gnvs->tcrt = 100; ++ /* Temperature at which OS will throttle CPU */ ++ gnvs->tpsv = 90; ++} +diff --git a/src/mainboard/lenovo/t430/board_info.txt b/src/mainboard/lenovo/t430/board_info.txt +new file mode 100644 +index 0000000000..09ddde1f85 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/board_info.txt +@@ -0,0 +1,6 @@ ++Category: laptop ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: n ++Release year: 2012 +diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default +new file mode 100644 +index 0000000000..4857f92f67 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/cmos.default +@@ -0,0 +1,20 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Disable ++nmi=Enable ++volume=0x3 ++first_battery=Primary ++bluetooth=Enable ++wwan=Enable ++wlan=Enable ++touchpad=Enable ++sata_mode=AHCI ++fn_ctrl_swap=Disable ++sticky_fn=Disable ++trackpoint=Enable ++backlight=Both ++hybrid_graphics_mode=Integrated Only ++usb_always_on=Disable ++me_state=Normal +diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout +new file mode 100644 +index 0000000000..d109a61b4e +--- /dev/null ++++ b/src/mainboard/lenovo/t430/cmos.layout +@@ -0,0 +1,108 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++ ++#400 8 r 0 reserved for century byte ++ ++# coreboot config options: southbridge ++408 1 e 1 nmi ++409 2 e 7 power_on_after_fail ++ ++# coreboot config options: EC ++411 1 e 8 first_battery ++412 1 e 1 bluetooth ++413 1 e 1 wwan ++414 1 e 1 touchpad ++415 1 e 1 wlan ++416 1 e 1 trackpoint ++417 1 e 1 fn_ctrl_swap ++418 1 e 1 sticky_fn ++419 2 e 13 usb_always_on ++421 1 e 9 sata_mode ++422 2 e 10 backlight ++ ++# coreboot config options: ME ++424 1 e 14 me_state ++425 2 h 0 me_state_prev ++ ++# coreboot config options: northbridge ++432 3 e 11 gfx_uma_size ++435 2 e 12 hybrid_graphics_mode ++ ++440 8 h 0 volume ++ ++# VBOOT ++448 128 r 0 vbnv ++ ++# SandyBridge MRC Scrambler Seed values ++896 32 r 0 mrc_scrambler_seed ++928 32 r 0 mrc_scrambler_seed_s3 ++960 16 r 0 mrc_scrambler_seed_chk ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++2 0 Enable ++2 1 Disable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++8 0 Secondary ++8 1 Primary ++9 0 AHCI ++9 1 Compatible ++10 0 Both ++10 1 Keyboard only ++10 2 Thinklight only ++10 3 None ++11 0 32M ++11 1 64M ++11 2 96M ++11 3 128M ++11 4 160M ++11 5 192M ++11 6 224M ++12 0 Integrated Only ++12 1 Discrete Only ++12 2 Dual Graphics ++13 0 Disable ++13 1 AC and battery ++13 2 AC only ++14 0 Normal ++14 1 Disabled ++ ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 447 984 +diff --git a/src/mainboard/lenovo/t530/variants/t430/data.vbt b/src/mainboard/lenovo/t430/data.vbt +similarity index 100% +rename from src/mainboard/lenovo/t530/variants/t430/data.vbt +rename to src/mainboard/lenovo/t430/data.vbt +diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb +new file mode 100644 +index 0000000000..198900b399 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/devicetree.cb +@@ -0,0 +1,166 @@ ++chip northbridge/intel/sandybridge ++ register "gfx" = "GMA_STATIC_DISPLAYS(1)" ++ ++ # Enable DisplayPort Hotplug with 6ms pulse ++ register "gpu_dp_d_hotplug" = "0x06" ++ ++ # Enable Panel as LVDS and configure power delays ++ register "gpu_panel_port_select" = "PANEL_PORT_LVDS" ++ register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms ++ register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms ++ register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms ++ register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms ++ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms ++ register "gpu_cpu_backlight" = "0x1155" ++ register "gpu_pch_backlight" = "0x11551155" ++ ++ register "spd_addresses" = "{0x50, 0, 0x51, 0}" ++ ++ device domain 0 on ++ subsystemid 0x17aa 0x21f3 inherit ++ ++ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH ++ register "docking_supported" = "true" ++ register "gen1_dec" = "0x000c15e1" ++ register "gen2_dec" = "0x007c1601" ++ register "gen3_dec" = "0x000c06a1" ++ register "gpi13_routing" = "2" ++ register "gpi1_routing" = "2" ++ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" ++ register "pcie_port_coalesce" = "true" ++ register "sata_interface_speed_support" = "0x3" ++ register "sata_port_map" = "0x17" ++ ++ # Do not enable xHCI Port 4 since WWAN USB is EHCI-only ++ register "superspeed_capable_ports" = "0x7" ++ register "xhci_switchable_ports" = "0x7" ++ register "usb_port_config" = "{ ++ { 1, 1, 0 }, ++ { 1, 1, 1 }, ++ { 1, 2, 3 }, ++ { 1, 1, -1 }, ++ { 1, 1, 2 }, ++ { 1, 0, -1 }, ++ { 0, 0, -1 }, ++ { 1, 2, -1 }, ++ { 1, 0, -1 }, ++ { 1, 1, 5 }, ++ { 1, 0, -1 }, ++ { 1, 0, -1 }, ++ { 1, 3, -1 }, ++ { 1, 1, -1 } ++ }" ++ ++ # device specific SPI configuration ++ register "spi_uvscc" = "0x2005" ++ register "spi_lvscc" = "0x2005" ++ ++ device ref xhci on end # USB 3.0 Controller ++ device ref mei1 on end # Management Engine Interface 1 ++ device ref mei2 off end # Management Engine Interface 2 ++ device ref me_ide_r off end # Management Engine IDE-R ++ device ref me_kt off end # Management Engine KT ++ device ref gbe on end # Intel Gigabit Ethernet ++ device ref ehci2 on end # USB2 EHCI #2 ++ device ref hda on end # High Definition Audio controller ++ device ref pcie_rp1 on # PCIe Port #1 ++ chip drivers/ricoh/rce822 # Ricoh cardreader ++ register "disable_mask" = "0x87" ++ register "sdwppol" = "1" ++ device pci 00.0 on end # Ricoh SD card reader ++ end ++ end ++ device ref pcie_rp2 on end # PCIe Port #2 ++ device ref pcie_rp3 on # PCIe Port #3 ++ smbios_slot_desc "7" "3" "ExpressCard Slot" "8" ++ end ++ device ref pcie_rp4 off end # PCIe Port #4 ++ device ref pcie_rp5 off end # PCIe Port #5 ++ device ref pcie_rp6 off end # PCIe Port #6 ++ device ref pcie_rp7 off end # PCIe Port #7 ++ device ref pcie_rp8 off end # PCIe Port #8 ++ device ref ehci1 on end # USB2 EHCI #1 ++ device ref pci_bridge off end # PCI bridge ++ device ref lpc on # LPC bridge PCI-LPC bridge ++ chip ec/lenovo/pmh7 ++ register "backlight_enable" = "true" ++ register "dock_event_enable" = "true" ++ device pnp ff.1 on end # dummy ++ end ++ chip drivers/pc80/tpm ++ device pnp 0c31.0 on end ++ end ++ chip ec/lenovo/h8 ++ device pnp ff.2 on # dummy ++ io 0x60 = 0x62 ++ io 0x62 = 0x66 ++ io 0x64 = 0x1600 ++ io 0x66 = 0x1604 ++ end ++ register "config0" = "0xa7" ++ register "config1" = "0x01" ++ register "config2" = "0xa0" ++ register "config3" = "0xe2" ++ ++ register "has_keyboard_backlight" = "0" ++ ++ register "beepmask0" = "0x02" ++ register "beepmask1" = "0x86" ++ register "has_power_management_beeps" = "1" ++ register "event2_enable" = "0xff" ++ register "event3_enable" = "0xff" ++ register "event4_enable" = "0xf0" ++ register "event5_enable" = "0x3c" ++ register "event6_enable" = "0x00" ++ register "event7_enable" = "0xa1" ++ register "event8_enable" = "0x7b" ++ register "event9_enable" = "0xff" ++ register "eventa_enable" = "0x00" ++ register "eventb_enable" = "0x00" ++ register "eventc_enable" = "0xff" ++ register "eventd_enable" = "0xff" ++ register "evente_enable" = "0x0d" ++ ++ register "bdc_gpio_num" = "54" ++ register "bdc_gpio_lvl" = "0" ++ ++ register "wwan_gpio_num" = "70" ++ register "wwan_gpio_lvl" = "0" ++ end ++ chip drivers/lenovo/hybrid_graphics ++ device pnp ff.f on end # dummy ++ ++ register "detect_gpio" = "21" ++ ++ register "has_panel_hybrid_gpio" = "true" ++ register "panel_hybrid_gpio" = "52" ++ register "panel_integrated_lvl" = "true" ++ ++ register "has_backlight_gpio" = "false" ++ register "has_dgpu_power_gpio" = "false" ++ ++ register "has_thinker1" = "true" ++ end ++ end ++ device ref sata1 on end # SATA Controller 1 ++ device ref smbus on # SMBus ++ chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip ++ device i2c 54 on end ++ device i2c 55 on end ++ device i2c 56 on end ++ device i2c 57 on end ++ device i2c 5c on end ++ device i2c 5d on end ++ device i2c 5e on end ++ device i2c 5f on end ++ end ++ end ++ device ref sata2 off end # SATA Controller 2 ++ device ref thermal off end # Thermal ++ end ++ device ref host_bridge on end # Host bridge Host bridge ++ device ref peg10 on end # PCIe Bridge for discrete graphics ++ device ref igd on end # Internal graphics VGA controller ++ device ref dev4 off end # Signal processing controller ++ end ++end +diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl +new file mode 100644 +index 0000000000..1134782675 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/dsdt.asl +@@ -0,0 +1,39 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#define THINKPAD_EC_GPE 17 ++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB ++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB ++ ++#include ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20110725 // OEM revision ++) ++{ ++ #include ++ #include ++ ++ #include "acpi/platform.asl" ++ ++ // global NVS and variables ++ #include ++ ++ #include ++ ++ Scope (\_SB) { ++ Device (PCI0) ++ { ++ #include ++ #include ++ ++ #include ++ } ++ } ++ ++ #include ++ #include ++} +diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c +new file mode 100644 +index 0000000000..d982660856 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/early_init.c +@@ -0,0 +1,40 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static void hybrid_graphics_init(void) ++{ ++ bool peg, igd; ++ u32 reg32; ++ ++ early_hybrid_graphics(&igd, &peg); ++ ++ if (peg && igd) ++ return; ++ ++ /* Hide disabled devices */ ++ reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); ++ reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); ++ ++ if (peg) ++ reg32 |= DEVEN_PEG10; ++ ++ if (igd) ++ reg32 |= DEVEN_IGD; ++ else ++ /* Disable IGD VGA decode, no GTT or GFX stolen */ ++ pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); ++ ++ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); ++} ++ ++void mainboard_early_init(bool s3resume) ++{ ++ hybrid_graphics_init(); ++ lenovo_mainboard_eeprom_lock(); ++} +diff --git a/src/mainboard/lenovo/t430/gma-mainboard.ads b/src/mainboard/lenovo/t430/gma-mainboard.ads +new file mode 100644 +index 0000000000..3df1e37f3e +--- /dev/null ++++ b/src/mainboard/lenovo/t430/gma-mainboard.ads +@@ -0,0 +1,22 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (DP1, ++ DP2, ++ DP3, ++ HDMI1, ++ HDMI2, ++ HDMI3, ++ Analog, ++ LVDS, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/lenovo/t530/variants/t430/gpio.c b/src/mainboard/lenovo/t430/gpio.c +similarity index 100% +rename from src/mainboard/lenovo/t530/variants/t430/gpio.c +rename to src/mainboard/lenovo/t430/gpio.c +diff --git a/src/mainboard/lenovo/t530/variants/t430/hda_verb.c b/src/mainboard/lenovo/t430/hda_verb.c +similarity index 100% +rename from src/mainboard/lenovo/t530/variants/t430/hda_verb.c +rename to src/mainboard/lenovo/t430/hda_verb.c +diff --git a/src/mainboard/lenovo/t430/mainboard.c b/src/mainboard/lenovo/t430/mainboard.c +new file mode 100644 +index 0000000000..50c944e341 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/mainboard.c +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++static void mainboard_enable(struct device *dev) ++{ ++ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, ++ GMA_INT15_PANEL_FIT_DEFAULT, ++ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); ++} ++ ++struct chip_operations mainboard_ops = { ++ .enable_dev = mainboard_enable, ++}; +diff --git a/src/mainboard/lenovo/t430/smihandler.c b/src/mainboard/lenovo/t430/smihandler.c +new file mode 100644 +index 0000000000..03c899e0d9 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/smihandler.c +@@ -0,0 +1,68 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define GPE_EC_SCI 1 ++#define GPE_EC_WAKE 13 ++ ++static void mainboard_smi_handle_ec_sci(void) ++{ ++ u8 status = inb(EC_SC); ++ u8 event; ++ ++ if (!(status & EC_SCI_EVT)) ++ return; ++ ++ event = ec_query(); ++ printk(BIOS_DEBUG, "EC event %#02x\n", event); ++} ++ ++void mainboard_smi_gpi(u32 gpi_sts) ++{ ++ if (gpi_sts & (1 << GPE_EC_SCI)) ++ mainboard_smi_handle_ec_sci(); ++} ++ ++int mainboard_smi_apmc(u8 data) ++{ ++ switch (data) { ++ case APM_CNT_ACPI_ENABLE: ++ /* use 0x1600/0x1604 to prevent races with userspace */ ++ ec_set_ports(0x1604, 0x1600); ++ /* route EC_SCI to SCI */ ++ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); ++ /* discard all events, and enable attention */ ++ ec_write(0x80, 0x01); ++ break; ++ case APM_CNT_ACPI_DISABLE: ++ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't ++ provide a EC query function */ ++ ec_set_ports(0x66, 0x62); ++ /* route EC_SCI to SMI */ ++ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); ++ /* discard all events, and enable attention */ ++ ec_write(0x80, 0x01); ++ break; ++ default: ++ break; ++ } ++ return 0; ++} ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ if (slp_typ == 3) { ++ u8 ec_wake = ec_read(0x32); ++ /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ ++ if (ec_wake & 0x14) { ++ /* Redirect EC WAKE GPE to SCI. */ ++ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); ++ } ++ } ++} +diff --git a/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd +new file mode 100644 +index 0000000000..5101caa59c +--- /dev/null ++++ b/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd +@@ -0,0 +1,21 @@ ++FLASH 0xc00000 { ++ SI_ALL 0x20000 { ++ SI_DESC 0x1000 ++ SI_GBE 0x2000 ++ SI_ME ++ } ++ SI_BIOS 0xbe0000 { ++ UNIFIED_MRC_CACHE 0x20000 { ++ RECOVERY_MRC_CACHE 0x10000 ++ RW_MRC_CACHE 0x10000 ++ } ++ ++ WP_RO { ++ FMAP 0x800 ++ RO_FRID 0x40 ++ RO_PADDING 0x7c0 ++ GBB 0x1e000 ++ COREBOOT(CBFS) ++ } ++ } ++} +diff --git a/src/mainboard/lenovo/t430/vboot-ro.fmd b/src/mainboard/lenovo/t430/vboot-ro.fmd +new file mode 100644 +index 0000000000..027849bfe9 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/vboot-ro.fmd +@@ -0,0 +1,21 @@ ++FLASH 0xc00000 { ++ SI_ALL 0x500000 { ++ SI_DESC 0x1000 ++ SI_GBE 0x2000 ++ SI_ME ++ } ++ SI_BIOS 0x700000 { ++ UNIFIED_MRC_CACHE 0x20000 { ++ RECOVERY_MRC_CACHE 0x10000 ++ RW_MRC_CACHE 0x10000 ++ } ++ ++ WP_RO { ++ FMAP 0x800 ++ RO_FRID 0x40 ++ RO_PADDING 0x7c0 ++ GBB 0x1e000 ++ COREBOOT(CBFS) ++ } ++ } ++} +diff --git a/src/mainboard/lenovo/t430/vboot-rwab.fmd b/src/mainboard/lenovo/t430/vboot-rwab.fmd +new file mode 100644 +index 0000000000..8819959dfe +--- /dev/null ++++ b/src/mainboard/lenovo/t430/vboot-rwab.fmd +@@ -0,0 +1,35 @@ ++FLASH 0xc00000 { ++ SI_ALL@0x0 0x500000 { ++ SI_DESC@0x0 0x1000 ++ SI_GBE@0x1000 0x2000 ++ SI_ME ++ } ++ SI_BIOS@0x500000 0x700000 { ++ RW_SECTION_A 0x280000 { ++ VBLOCK_A 0x10000 ++ FW_MAIN_A(CBFS) ++ RW_FWID_A 0x40 ++ } ++ RW_SECTION_B 0x280000 { ++ VBLOCK_B 0x10000 ++ FW_MAIN_B(CBFS) ++ RW_FWID_B 0x40 ++ } ++ UNIFIED_MRC_CACHE@0x500000 0x20000 { ++ RECOVERY_MRC_CACHE@0x0 0x10000 ++ RW_MRC_CACHE@0x10000 0x10000 ++ } ++ RW_VPD(PRESERVE) 0x1000 ++ SMMSTORE(PRESERVE)@0x521000 0x40000 ++ RW_NVRAM(PRESERVE)@0x561000 0x2000 ++ ++ WP_RO { ++ FMAP 0x800 ++ RO_FRID 0x40 ++ RO_PADDING 0x7c0 ++ RO_VPD(PRESERVE) 0x1000 ++ GBB 0x1e000 ++ COREBOOT(CBFS) ++ } ++ } ++} +diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig +index 4f0002f536..8830c39301 100644 +--- a/src/mainboard/lenovo/t530/Kconfig ++++ b/src/mainboard/lenovo/t530/Kconfig +@@ -38,10 +38,6 @@ config BOARD_LENOVO_W530 + select BOARD_LENOVO_BASEBOARD_T530 + select DRIVERS_RICOH_RCE822 + +-config BOARD_LENOVO_T430 +- select BOARD_LENOVO_BASEBOARD_T530 +- select DRIVERS_RICOH_RCE822 +- + if BOARD_LENOVO_BASEBOARD_T530 + + config VBOOT +@@ -64,7 +60,6 @@ config FMDFILE + config VARIANT_DIR + default "t530" if BOARD_LENOVO_T530 + default "w530" if BOARD_LENOVO_W530 +- default "t430" if BOARD_LENOVO_T430 + + config MAINBOARD_DIR + default "lenovo/t530" +@@ -75,7 +70,6 @@ config OVERRIDE_DEVICETREE + config MAINBOARD_PART_NUMBER + default "ThinkPad T530" if BOARD_LENOVO_T530 + default "ThinkPad W530" if BOARD_LENOVO_W530 +- default "ThinkPad T430" if BOARD_LENOVO_T430 + + config USBDEBUG_HCD_INDEX + int +@@ -90,7 +84,6 @@ config VGA_BIOS_ID + default "8086,0166" + + config PS2K_EISAID +- default "PNP0303" if BOARD_LENOVO_T430 + default "LEN0071" + + config PS2M_EISAID +diff --git a/src/mainboard/lenovo/t530/Kconfig.name b/src/mainboard/lenovo/t530/Kconfig.name +index 5b42bd2f89..d8b1925f65 100644 +--- a/src/mainboard/lenovo/t530/Kconfig.name ++++ b/src/mainboard/lenovo/t530/Kconfig.name +@@ -5,6 +5,3 @@ config BOARD_LENOVO_T530 + + config BOARD_LENOVO_W530 + bool "ThinkPad W530" +- +-config BOARD_LENOVO_T430 +- bool "ThinkPad T430" +diff --git a/src/mainboard/lenovo/t530/Makefile.mk b/src/mainboard/lenovo/t530/Makefile.mk +index 1c72bfe045..69ef08873b 100644 +--- a/src/mainboard/lenovo/t530/Makefile.mk ++++ b/src/mainboard/lenovo/t530/Makefile.mk +@@ -5,4 +5,3 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + bootblock-y += early_init.c + romstage-y += early_init.c +-ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +diff --git a/src/mainboard/lenovo/t530/variants/t530/hda_verb.c b/src/mainboard/lenovo/t530/hda_verb.c +similarity index 100% +rename from src/mainboard/lenovo/t530/variants/t530/hda_verb.c +rename to src/mainboard/lenovo/t530/hda_verb.c +diff --git a/src/mainboard/lenovo/t530/variants/t430/overridetree.cb b/src/mainboard/lenovo/t530/variants/t430/overridetree.cb +deleted file mode 100644 +index 72cc6b54e1..0000000000 +--- a/src/mainboard/lenovo/t530/variants/t430/overridetree.cb ++++ /dev/null +@@ -1,58 +0,0 @@ +-chip northbridge/intel/sandybridge +- register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms +- register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms +- +- register "spd_addresses" = "{0x50, 0, 0x51, 0}" +- device domain 0 on +- subsystemid 0x17aa 0x21f3 inherit +- chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH +- register "sata_interface_speed_support" = "0x3" +- register "sata_port_map" = "0x17" +- +- # Do not enable xHCI Port 4 since WWAN USB is EHCI-only +- register "superspeed_capable_ports" = "0x7" +- register "xhci_switchable_ports" = "0x7" +- register "usb_port_config" = "{ +- { 1, 1, 0 }, +- { 1, 1, 1 }, +- { 1, 2, 3 }, +- { 1, 1, -1 }, +- { 1, 1, 2 }, +- { 1, 0, -1 }, +- { 0, 0, -1 }, +- { 1, 2, -1 }, +- { 1, 0, -1 }, +- { 1, 1, 5 }, +- { 1, 0, -1 }, +- { 1, 0, -1 }, +- { 1, 3, -1 }, +- { 1, 1, -1 } +- }" +- +- device ref pcie_rp1 on # PCIe Port #1 +- chip drivers/ricoh/rce822 # Ricoh cardreader +- register "disable_mask" = "0x87" +- register "sdwppol" = "1" +- device pci 00.0 on end # Ricoh SD card reader +- end +- end +- device ref lpc on +- chip ec/lenovo/h8 +- device pnp ff.2 on end # dummy +- register "wwan_gpio_num" = "70" +- register "wwan_gpio_lvl" = "0" +- register "config1" = "0x01" +- register "config3" = "0xe2" +- register "has_keyboard_backlight" = "0" +- register "beepmask0" = "0x02" +- register "has_power_management_beeps" = "1" +- register "event4_enable" = "0xf0" +- register "event5_enable" = "0x3c" +- register "event7_enable" = "0xa1" +- register "eventa_enable" = "0x00" +- end +- end +- device ref thermal off end # Thermal +- end +- end +-end +diff --git a/src/mainboard/lenovo/t530/variants/w530/hda_verb.c b/src/mainboard/lenovo/t530/variants/w530/hda_verb.c +deleted file mode 100644 +index 564aff2d77..0000000000 +--- a/src/mainboard/lenovo/t530/variants/w530/hda_verb.c ++++ /dev/null +@@ -1,75 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +- +-/* Bits 31:28 - Codec Address */ +-/* Bits 27:20 - NID */ +-/* Bits 19:8 - Verb ID */ +-/* Bits 7:0 - Payload */ +- +-#include +- +-const u32 cim_verb_data[] = { +- 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269VC */ +- 0x17aa21fa, /* Subsystem ID */ +- 18, /* Number of 4 dword sets */ +- AZALIA_SUBVENDOR(0, 0x17aa21fa), +- +- /* Ext. Microphone Connector: External,Right; MicIn,3.5mm; Black,JD; DA,Seq */ +- AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), +- +- /* Headphones Connector: External,Right; HP,3.5mm; Black,JD; DA,Seq */ +- AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), +- +- /* Not connected: N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq */ +- AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0), +- +- /* Internal Speakers Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq */ +- AZALIA_PIN_CFG(0, 0x0d, 0x90170110), +- +- /* Not connected */ +- AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), +- +- /* Internal Microphone: Fixed,Int,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq */ +- AZALIA_PIN_CFG(0, 0x11, 0xd5a30140), +- AZALIA_PIN_CFG(0, 0x12, 0x90a60140), +- AZALIA_PIN_CFG(0, 0x14, 0x90170110), +- AZALIA_PIN_CFG(0, 0x15, 0x03211020), +- AZALIA_PIN_CFG(0, 0x18, 0x03a11830), +- AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), +- +- 0x01970804, +- 0x01870803, +- 0x01470740, +- 0x00970600, +- +- AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), +- AZALIA_PIN_CFG(0, 0x1d, 0x40138205), +- AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), +- +- /* Misc entries */ +- 0x00370600, +- 0x00270600, +- 0x00b707C0, /* Enable PortB as Output with HP amp */ +- 0x00d70740, /* Enable PortD as Output */ +- 0x0017a200, /* Disable ClkEn of PortSenseTst */ +- 0x0017c621, /* Slave Port - Port A used as microphone input for +- combo Jack +- Master Port - Port B used for Jack Presence Detect +- Enable Combo Jack Detection */ +- 0x0017a208, /* Enable ClkEn of PortSenseTst */ +- 0x00170500, /* Set power state to D0 */ +- +- /* --- Codec #3 --- */ +- 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ +- 0x80860101, /* Subsystem ID */ +- 4, /* Number of 4 dword sets */ +- AZALIA_SUBVENDOR(3, 0x80860101), +- AZALIA_PIN_CFG(3, 0x05, 0x18560010), +- AZALIA_PIN_CFG(3, 0x06, 0x18560020), +- AZALIA_PIN_CFG(3, 0x07, 0x18560030), +-}; +- +-const u32 pc_beep_verbs[] = { +- 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +-}; +- +-AZALIA_ARRAY_SIZES; +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch deleted file mode 100644 index 20fff9eb..00000000 --- a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch +++ /dev/null @@ -1,34 +0,0 @@ -From da742084f51bb7e97472605d6eff0726fd7a5863 Mon Sep 17 00:00:00 2001 -From: persmule -Date: Sun, 31 Oct 2021 23:33:26 +0000 -Subject: [PATCH 02/48] lenovo/t400: Enable all SATA ports - -There are 2 SATA ports on the chassis of t400(s), but at least one dock for -t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its -chassis, and another one on its dock. - -They have to be unmasked via device tree to use. - -This patch unmasked all SATA ports found within t400s with factory firmware. ---- - src/mainboard/lenovo/t400/devicetree.cb | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb -index 9e056772e9..9361f330d2 100644 ---- a/src/mainboard/lenovo/t400/devicetree.cb -+++ b/src/mainboard/lenovo/t400/devicetree.cb -@@ -46,8 +46,8 @@ chip northbridge/intel/gm45 - register "gpe0_en" = "0x01000000" - register "gpi1_routing" = "2" - -- # Set AHCI mode, enable ports 1 and 2. -- register "sata_port_map" = "0x03" -+ # Set AHCI mode, enable ports 1, 2, 5 and 6. -+ register "sata_port_map" = "0x33" - register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0" - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0003-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0003-lenovo-t400-Enable-all-SATA-ports.patch new file mode 100644 index 00000000..bad82d0f --- /dev/null +++ b/config/coreboot/default/patches/0003-lenovo-t400-Enable-all-SATA-ports.patch @@ -0,0 +1,34 @@ +From 33b89af06765839c0f9a6e599789c520e794a22a Mon Sep 17 00:00:00 2001 +From: persmule +Date: Sun, 31 Oct 2021 23:33:26 +0000 +Subject: [PATCH 03/51] lenovo/t400: Enable all SATA ports + +There are 2 SATA ports on the chassis of t400(s), but at least one dock for +t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its +chassis, and another one on its dock. + +They have to be unmasked via device tree to use. + +This patch unmasked all SATA ports found within t400s with factory firmware. +--- + src/mainboard/lenovo/t400/devicetree.cb | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb +index 9e056772e9..9361f330d2 100644 +--- a/src/mainboard/lenovo/t400/devicetree.cb ++++ b/src/mainboard/lenovo/t400/devicetree.cb +@@ -46,8 +46,8 @@ chip northbridge/intel/gm45 + register "gpe0_en" = "0x01000000" + register "gpi1_routing" = "2" + +- # Set AHCI mode, enable ports 1 and 2. +- register "sata_port_map" = "0x03" ++ # Set AHCI mode, enable ports 1, 2, 5 and 6. ++ register "sata_port_map" = "0x33" + register "sata_clock_request" = "0" + register "sata_traffic_monitor" = "0" + +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch deleted file mode 100644 index 8e814be3..00000000 --- a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 278c2a989c025c1b3a097966968c8d253c973a3e Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 3 Jan 2022 19:06:22 +0000 -Subject: [PATCH 03/48] lenovo/x230: set me_state=Disabled in cmos.default - -I only recently found out about this. It's possible to use me_cleaner to -do the same thing, but some people might just flash coreboot and not do -anything with the ME region - -With this change, the ME is set to disabled. It's my understanding that this -will accomplish more or less the same thing as me_cleaner, without actually -using that. Of course, I still recommend using me_cleaner - -I saw this when I audited coreboot's git history, and saw this: - -commit 833e9bad4762e0dca6c867d3a18dbaf6d5166be8 -Author: Evgeny Zinoviev -Date: Thu Nov 21 21:47:31 2019 +0300 - - sb/intel/bd82x6x: Support ME Soft Temporary Disable Mode ---- - src/mainboard/lenovo/x230/cmos.default | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default -index 732e214b32..8454f0eac0 100644 ---- a/src/mainboard/lenovo/x230/cmos.default -+++ b/src/mainboard/lenovo/x230/cmos.default -@@ -17,4 +17,4 @@ trackpoint=Enable - backlight=Both - usb_always_on=Disable - f1_to_f12_as_primary=Enable --me_state=Normal -+me_state=Disabled --- -2.47.3 - diff --git a/config/coreboot/default/patches/0004-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0004-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch new file mode 100644 index 00000000..2d4b145c --- /dev/null +++ b/config/coreboot/default/patches/0004-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -0,0 +1,37 @@ +From 6bf8a87bdea4b7d5876e20f734821e6496b51cb9 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 3 Jan 2022 19:06:22 +0000 +Subject: [PATCH 04/51] lenovo/x230: set me_state=Disabled in cmos.default + +I only recently found out about this. It's possible to use me_cleaner to +do the same thing, but some people might just flash coreboot and not do +anything with the ME region + +With this change, the ME is set to disabled. It's my understanding that this +will accomplish more or less the same thing as me_cleaner, without actually +using that. Of course, I still recommend using me_cleaner + +I saw this when I audited coreboot's git history, and saw this: + +commit 833e9bad4762e0dca6c867d3a18dbaf6d5166be8 +Author: Evgeny Zinoviev +Date: Thu Nov 21 21:47:31 2019 +0300 + + sb/intel/bd82x6x: Support ME Soft Temporary Disable Mode +--- + src/mainboard/lenovo/x230/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default +index 732e214b32..8454f0eac0 100644 +--- a/src/mainboard/lenovo/x230/cmos.default ++++ b/src/mainboard/lenovo/x230/cmos.default +@@ -17,4 +17,4 @@ trackpoint=Enable + backlight=Both + usb_always_on=Disable + f1_to_f12_as_primary=Enable +-me_state=Normal ++me_state=Disabled +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch deleted file mode 100644 index 43830448..00000000 --- a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch +++ /dev/null @@ -1,124 +0,0 @@ -From 63357b7f8c9da3a8d644542c70f50fc9bc77a8fc Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Wed, 2 Mar 2022 21:50:01 +0000 -Subject: [PATCH 04/48] set me_state=Disabled on all cmos.default files! - -yeah. why the hell isn't this the default - -Signed-off-by: Leah Rowe ---- - src/mainboard/lenovo/l520/cmos.default | 2 +- - src/mainboard/lenovo/t420/cmos.default | 2 +- - src/mainboard/lenovo/t420s/cmos.default | 2 +- - src/mainboard/lenovo/t430/cmos.default | 2 +- - src/mainboard/lenovo/t430s/cmos.default | 2 +- - src/mainboard/lenovo/t520/cmos.default | 2 +- - src/mainboard/lenovo/t530/cmos.default | 2 +- - src/mainboard/lenovo/x220/cmos.default | 2 +- - src/mainboard/protectli/vault_cml/cmos.default | 2 +- - src/mainboard/system76/tgl-u/cmos.default | 2 +- - 10 files changed, 10 insertions(+), 10 deletions(-) - -diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default -index be08e0a342..b8970efa46 100644 ---- a/src/mainboard/lenovo/l520/cmos.default -+++ b/src/mainboard/lenovo/l520/cmos.default -@@ -16,4 +16,4 @@ sticky_fn=Disable - trackpoint=Enable - backlight=Both - usb_always_on=Disable --me_state=Normal -+me_state=Disabled -diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default -index 6fd26c5fe3..27a62d07b3 100644 ---- a/src/mainboard/lenovo/t420/cmos.default -+++ b/src/mainboard/lenovo/t420/cmos.default -@@ -16,4 +16,4 @@ sticky_fn=Disable - trackpoint=Enable - hybrid_graphics_mode=Integrated Only - usb_always_on=Disable --me_state=Normal -+me_state=Disabled -diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default -index 6fd26c5fe3..27a62d07b3 100644 ---- a/src/mainboard/lenovo/t420s/cmos.default -+++ b/src/mainboard/lenovo/t420s/cmos.default -@@ -16,4 +16,4 @@ sticky_fn=Disable - trackpoint=Enable - hybrid_graphics_mode=Integrated Only - usb_always_on=Disable --me_state=Normal -+me_state=Disabled -diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default -index c896eadec1..6d1e172056 100644 ---- a/src/mainboard/lenovo/t430/cmos.default -+++ b/src/mainboard/lenovo/t430/cmos.default -@@ -17,4 +17,4 @@ trackpoint=Enable - backlight=Both - usb_always_on=Disable - hybrid_graphics_mode=Integrated Only --me_state=Normal -+me_state=Disabled -diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default -index 286fb0ae8c..5a05c73721 100644 ---- a/src/mainboard/lenovo/t430s/cmos.default -+++ b/src/mainboard/lenovo/t430s/cmos.default -@@ -18,4 +18,4 @@ backlight=Both - enable_dual_graphics=Disable - usb_always_on=Disable - f1_to_f12_as_primary=Enable --me_state=Normal -+me_state=Disabled -diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default -index 4857f92f67..ab1be1a678 100644 ---- a/src/mainboard/lenovo/t520/cmos.default -+++ b/src/mainboard/lenovo/t520/cmos.default -@@ -17,4 +17,4 @@ trackpoint=Enable - backlight=Both - hybrid_graphics_mode=Integrated Only - usb_always_on=Disable --me_state=Normal -+me_state=Disabled -diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default -index 4857f92f67..ab1be1a678 100644 ---- a/src/mainboard/lenovo/t530/cmos.default -+++ b/src/mainboard/lenovo/t530/cmos.default -@@ -17,4 +17,4 @@ trackpoint=Enable - backlight=Both - hybrid_graphics_mode=Integrated Only - usb_always_on=Disable --me_state=Normal -+me_state=Disabled -diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default -index ef706c1303..b318ab9772 100644 ---- a/src/mainboard/lenovo/x220/cmos.default -+++ b/src/mainboard/lenovo/x220/cmos.default -@@ -15,4 +15,4 @@ usb_always_on=Disable - fn_ctrl_swap=Disable - sticky_fn=Disable - trackpoint=Enable --me_state=Normal -+me_state=Disabled -diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default -index d61046df6b..8c793fd1c3 100644 ---- a/src/mainboard/protectli/vault_cml/cmos.default -+++ b/src/mainboard/protectli/vault_cml/cmos.default -@@ -2,4 +2,4 @@ - - boot_option=Fallback - debug_level=Debug --me_state=Enable -+me_state=Disabled -diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default -index d61046df6b..8c793fd1c3 100644 ---- a/src/mainboard/system76/tgl-u/cmos.default -+++ b/src/mainboard/system76/tgl-u/cmos.default -@@ -2,4 +2,4 @@ - - boot_option=Fallback - debug_level=Debug --me_state=Enable -+me_state=Disabled --- -2.47.3 - diff --git a/config/coreboot/default/patches/0005-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0005-set-me_state-Disabled-on-all-cmos.default-files.patch new file mode 100644 index 00000000..5ada54ef --- /dev/null +++ b/config/coreboot/default/patches/0005-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -0,0 +1,124 @@ +From 05f20d18bf572ebe80875d506dd686efd3eb7e4e Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Wed, 2 Mar 2022 21:50:01 +0000 +Subject: [PATCH 05/51] set me_state=Disabled on all cmos.default files! + +yeah. why the hell isn't this the default + +Signed-off-by: Leah Rowe +--- + src/mainboard/lenovo/l520/cmos.default | 2 +- + src/mainboard/lenovo/t420/cmos.default | 2 +- + src/mainboard/lenovo/t420s/cmos.default | 2 +- + src/mainboard/lenovo/t430/cmos.default | 2 +- + src/mainboard/lenovo/t430s/cmos.default | 2 +- + src/mainboard/lenovo/t520/cmos.default | 2 +- + src/mainboard/lenovo/t530/cmos.default | 2 +- + src/mainboard/lenovo/x220/cmos.default | 2 +- + src/mainboard/protectli/vault_cml/cmos.default | 2 +- + src/mainboard/system76/tgl-u/cmos.default | 2 +- + 10 files changed, 10 insertions(+), 10 deletions(-) + +diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default +index be08e0a342..b8970efa46 100644 +--- a/src/mainboard/lenovo/l520/cmos.default ++++ b/src/mainboard/lenovo/l520/cmos.default +@@ -16,4 +16,4 @@ sticky_fn=Disable + trackpoint=Enable + backlight=Both + usb_always_on=Disable +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default +index 6fd26c5fe3..27a62d07b3 100644 +--- a/src/mainboard/lenovo/t420/cmos.default ++++ b/src/mainboard/lenovo/t420/cmos.default +@@ -16,4 +16,4 @@ sticky_fn=Disable + trackpoint=Enable + hybrid_graphics_mode=Integrated Only + usb_always_on=Disable +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default +index 6fd26c5fe3..27a62d07b3 100644 +--- a/src/mainboard/lenovo/t420s/cmos.default ++++ b/src/mainboard/lenovo/t420s/cmos.default +@@ -16,4 +16,4 @@ sticky_fn=Disable + trackpoint=Enable + hybrid_graphics_mode=Integrated Only + usb_always_on=Disable +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default +index 4857f92f67..ab1be1a678 100644 +--- a/src/mainboard/lenovo/t430/cmos.default ++++ b/src/mainboard/lenovo/t430/cmos.default +@@ -17,4 +17,4 @@ trackpoint=Enable + backlight=Both + hybrid_graphics_mode=Integrated Only + usb_always_on=Disable +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default +index 286fb0ae8c..5a05c73721 100644 +--- a/src/mainboard/lenovo/t430s/cmos.default ++++ b/src/mainboard/lenovo/t430s/cmos.default +@@ -18,4 +18,4 @@ backlight=Both + enable_dual_graphics=Disable + usb_always_on=Disable + f1_to_f12_as_primary=Enable +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default +index 4857f92f67..ab1be1a678 100644 +--- a/src/mainboard/lenovo/t520/cmos.default ++++ b/src/mainboard/lenovo/t520/cmos.default +@@ -17,4 +17,4 @@ trackpoint=Enable + backlight=Both + hybrid_graphics_mode=Integrated Only + usb_always_on=Disable +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default +index 4857f92f67..ab1be1a678 100644 +--- a/src/mainboard/lenovo/t530/cmos.default ++++ b/src/mainboard/lenovo/t530/cmos.default +@@ -17,4 +17,4 @@ trackpoint=Enable + backlight=Both + hybrid_graphics_mode=Integrated Only + usb_always_on=Disable +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default +index ef706c1303..b318ab9772 100644 +--- a/src/mainboard/lenovo/x220/cmos.default ++++ b/src/mainboard/lenovo/x220/cmos.default +@@ -15,4 +15,4 @@ usb_always_on=Disable + fn_ctrl_swap=Disable + sticky_fn=Disable + trackpoint=Enable +-me_state=Normal ++me_state=Disabled +diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default +index d61046df6b..8c793fd1c3 100644 +--- a/src/mainboard/protectli/vault_cml/cmos.default ++++ b/src/mainboard/protectli/vault_cml/cmos.default +@@ -2,4 +2,4 @@ + + boot_option=Fallback + debug_level=Debug +-me_state=Enable ++me_state=Disabled +diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default +index d61046df6b..8c793fd1c3 100644 +--- a/src/mainboard/system76/tgl-u/cmos.default ++++ b/src/mainboard/system76/tgl-u/cmos.default +@@ -2,4 +2,4 @@ + + boot_option=Fallback + debug_level=Debug +-me_state=Enable ++me_state=Disabled +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch deleted file mode 100644 index 8490157a..00000000 --- a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ /dev/null @@ -1,207 +0,0 @@ -From 434136e0aca4839e449e3841a5e993688b4586f0 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 05/48] util/ifdtool: add --nuke flag (all 0xFF on region) - -When this option is used, the region's contents are overwritten -with all ones (0xFF). - -Example: - -./ifdtool --nuke gbe coreboot.rom -./ifdtool --nuke bios coreboot.com -./ifdtool --nuke me coreboot.com - -Rebased since the last revision update in lbmk. - -Signed-off-by: Leah Rowe ---- - util/ifdtool/ifdtool.c | 116 +++++++++++++++++++++++++++++------------ - 1 file changed, 84 insertions(+), 32 deletions(-) - -diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index 0592785bf6..cab934c3a5 100644 ---- a/util/ifdtool/ifdtool.c -+++ b/util/ifdtool/ifdtool.c -@@ -2240,6 +2240,7 @@ static void print_usage(const char *name) - " tgl - Tiger Lake\n" - " wbg - Wellsburg\n" - " -S | --setpchstrap Write a PCH strap\n" -+ " -N | --nuke Overwrite the specified region with 0xFF (all ones)\n" - " -V | --newvalue The new value to write into PCH strap specified by -S\n" - " -T | --topswapsize Set the Top Swap Block Size PCH strap value\n" - " Possible values: 0x10000, 0x20000, 0x40000, 0x80000,\n" -@@ -2251,6 +2252,60 @@ static void print_usage(const char *name) - "\n"); - } - -+static int -+get_region_type_string(const char *region_type_string) -+{ -+ if (!strcasecmp("Descriptor", region_type_string)) -+ return 0; -+ else if (!strcasecmp("BIOS", region_type_string)) -+ return 1; -+ else if (!strcasecmp("ME", region_type_string)) -+ return 2; -+ else if (!strcasecmp("GbE", region_type_string)) -+ return 3; -+ else if (!strcasecmp("Platform Data", region_type_string)) -+ return 4; -+ else if (!strcasecmp("Device Exp1", region_type_string)) -+ return 5; -+ else if (!strcasecmp("Secondary BIOS", region_type_string)) -+ return 6; -+ else if (!strcasecmp("Reserved", region_type_string)) -+ return 7; -+ else if (!strcasecmp("EC", region_type_string)) -+ return 8; -+ else if (!strcasecmp("Device Exp2", region_type_string)) -+ return 9; -+ else if (!strcasecmp("IE", region_type_string)) -+ return 10; -+ else if (!strcasecmp("10GbE_0", region_type_string)) -+ return 11; -+ else if (!strcasecmp("10GbE_1", region_type_string)) -+ return 12; -+ else if (!strcasecmp("PTT", region_type_string)) -+ return 15; -+ return -1; -+} -+ -+static void -+nuke(const char *filename, char *image, int size, int region_type) -+{ -+ int i; -+ struct region region; -+ const struct frba *frba = find_frba(image, size); -+ if (!frba) -+ exit(EXIT_FAILURE); -+ -+ region = get_region(frba, region_type); -+ if (region.size > 0) { -+ for (i = region.base; i <= region.limit; i++) { -+ if ((i + 1) > (size)) -+ break; -+ image[i] = 0xFF; -+ } -+ write_image(filename, image, size); -+ } -+} -+ - int main(int argc, char *argv[]) - { - int opt, option_index = 0; -@@ -2258,6 +2313,7 @@ int main(int argc, char *argv[]) - int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; - int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; - int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; -+ int mode_nuke = 0; - int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0; - int mode_settopswapsize = 0; - char *region_type_string = NULL, *region_fname = NULL, *layout_fname = NULL; -@@ -2294,6 +2350,7 @@ int main(int argc, char *argv[]) - {"setpchstrap", 1, NULL, 'S'}, - {"newvalue", 1, NULL, 'V'}, - {"topswapsize", 1, NULL, 'T'}, -+ {"nuke", 1, NULL, 'N'}, - {0, 0, 0, 0} - }; - -@@ -2343,35 +2400,8 @@ int main(int argc, char *argv[]) - region_fname++; - // Descriptor, BIOS, ME, GbE, Platform - // valid type? -- if (!strcasecmp("Descriptor", region_type_string)) -- region_type = 0; -- else if (!strcasecmp("BIOS", region_type_string)) -- region_type = 1; -- else if (!strcasecmp("ME", region_type_string)) -- region_type = 2; -- else if (!strcasecmp("GbE", region_type_string)) -- region_type = 3; -- else if (!strcasecmp("Platform Data", region_type_string)) -- region_type = 4; -- else if (!strcasecmp("Device Exp1", region_type_string)) -- region_type = 5; -- else if (!strcasecmp("Secondary BIOS", region_type_string)) -- region_type = 6; -- else if (!strcasecmp("Reserved", region_type_string)) -- region_type = 7; -- else if (!strcasecmp("EC", region_type_string)) -- region_type = 8; -- else if (!strcasecmp("Device Exp2", region_type_string)) -- region_type = 9; -- else if (!strcasecmp("IE", region_type_string)) -- region_type = 10; -- else if (!strcasecmp("10GbE_0", region_type_string)) -- region_type = 11; -- else if (!strcasecmp("10GbE_1", region_type_string)) -- region_type = 12; -- else if (!strcasecmp("PTT", region_type_string)) -- region_type = 15; -- if (region_type == -1) { -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { - fprintf(stderr, "No such region type: '%s'\n\n", - region_type_string); - fprintf(stderr, "run '%s -h' for usage\n", argv[0]); -@@ -2552,7 +2582,23 @@ int main(int argc, char *argv[]) - mode_settopswapsize = 1; - top_swap_size_arg = optarg; - break; -- case 'v': -+ case 'N': -+ region_type_string = strdup(optarg); -+ if (!region_type_string) { -+ fprintf(stderr, "No region specified\n"); -+ print_usage(argv[0]); -+ exit(EXIT_FAILURE); -+ } -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { -+ fprintf(stderr, "No such region type: '%s'\n\n", -+ region_type_string); -+ print_usage(argv[0]); -+ exit(EXIT_FAILURE); -+ } -+ mode_nuke = 1; -+ break; -+ Case 'v': - print_version(); - exit(EXIT_SUCCESS); - break; -@@ -2571,7 +2617,8 @@ int main(int argc, char *argv[]) - if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + - mode_setstrap + mode_settopswapsize + mode_newlayout + (mode_spifreq | mode_em100 | - mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + -- (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) { -+ (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status + -+ mode_nuke) > 1) { - fprintf(stderr, "You may not specify more than one mode.\n\n"); - fprintf(stderr, "run '%s -h' for usage\n", argv[0]); - exit(EXIT_FAILURE); -@@ -2580,7 +2627,8 @@ int main(int argc, char *argv[]) - if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + - mode_setstrap + mode_settopswapsize + mode_newlayout + mode_spifreq + mode_em100 + - mode_locked + mode_unlocked + mode_density + mode_altmedisable + -- mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) { -+ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status + -+ mode_nuke) == 0) { - fprintf(stderr, "You need to specify a mode.\n\n"); - fprintf(stderr, "run '%s -h' for usage\n", argv[0]); - exit(EXIT_FAILURE); -@@ -2746,6 +2794,10 @@ int main(int argc, char *argv[]) - write_image(new_filename, image, size); - } - -+ if (mode_nuke) { -+ nuke(new_filename, image, size, region_type); -+ } -+ - if (mode_altmedisable) { - struct fpsba *fpsba = find_fpsba(image, size); - struct fmsba *fmsba = find_fmsba(image, size); --- -2.47.3 - diff --git a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch deleted file mode 100644 index 725c6380..00000000 --- a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 91e4334541da6522d5a0bf5277ac478c891e7117 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 06/48] mb/dell/e6400: Enable 01.0 device in devicetree for - dGPU models - -Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/gm45_latitude/devicetree.cb | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/dell/gm45_latitude/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb -index 5919803be2..76dae87153 100644 ---- a/src/mainboard/dell/gm45_latitude/devicetree.cb -+++ b/src/mainboard/dell/gm45_latitude/devicetree.cb -@@ -18,7 +18,7 @@ chip northbridge/intel/gm45 - ops gm45_pci_domain_ops - - device pci 00.0 on end # host bridge -- device pci 01.0 off end -+ device pci 01.0 on end - device pci 02.0 on end # VGA - device pci 02.1 on end # Display - device pci 03.0 on end # ME --- -2.47.3 - diff --git a/config/coreboot/default/patches/0006-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0006-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch new file mode 100644 index 00000000..7b5c1a3d --- /dev/null +++ b/config/coreboot/default/patches/0006-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -0,0 +1,207 @@ +From 68e1738c5a46181b1fd1fcd44fe314da297b95d0 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sun, 19 Feb 2023 18:21:43 +0000 +Subject: [PATCH 06/51] util/ifdtool: add --nuke flag (all 0xFF on region) + +When this option is used, the region's contents are overwritten +with all ones (0xFF). + +Example: + +./ifdtool --nuke gbe coreboot.rom +./ifdtool --nuke bios coreboot.com +./ifdtool --nuke me coreboot.com + +Rebased since the last revision update in lbmk. + +Signed-off-by: Leah Rowe +--- + util/ifdtool/ifdtool.c | 116 +++++++++++++++++++++++++++++------------ + 1 file changed, 84 insertions(+), 32 deletions(-) + +diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c +index 0b75db54bd..7f0c10bd0b 100644 +--- a/util/ifdtool/ifdtool.c ++++ b/util/ifdtool/ifdtool.c +@@ -2252,6 +2252,7 @@ static void print_usage(const char *name) + " tgl - Tiger Lake\n" + " wbg - Wellsburg\n" + " -S | --setpchstrap Write a PCH strap\n" ++ " -N | --nuke Overwrite the specified region with 0xFF (all ones)\n" + " -V | --newvalue The new value to write into PCH strap specified by -S\n" + " -T | --topswapsize Set the Top Swap Block Size PCH strap value\n" + " Possible values: 0x10000, 0x20000, 0x40000, 0x80000,\n" +@@ -2263,6 +2264,60 @@ static void print_usage(const char *name) + "\n"); + } + ++static int ++get_region_type_string(const char *region_type_string) ++{ ++ if (!strcasecmp("Descriptor", region_type_string)) ++ return 0; ++ else if (!strcasecmp("BIOS", region_type_string)) ++ return 1; ++ else if (!strcasecmp("ME", region_type_string)) ++ return 2; ++ else if (!strcasecmp("GbE", region_type_string)) ++ return 3; ++ else if (!strcasecmp("Platform Data", region_type_string)) ++ return 4; ++ else if (!strcasecmp("Device Exp1", region_type_string)) ++ return 5; ++ else if (!strcasecmp("Secondary BIOS", region_type_string)) ++ return 6; ++ else if (!strcasecmp("Reserved", region_type_string)) ++ return 7; ++ else if (!strcasecmp("EC", region_type_string)) ++ return 8; ++ else if (!strcasecmp("Device Exp2", region_type_string)) ++ return 9; ++ else if (!strcasecmp("IE", region_type_string)) ++ return 10; ++ else if (!strcasecmp("10GbE_0", region_type_string)) ++ return 11; ++ else if (!strcasecmp("10GbE_1", region_type_string)) ++ return 12; ++ else if (!strcasecmp("PTT", region_type_string)) ++ return 15; ++ return -1; ++} ++ ++static void ++nuke(const char *filename, char *image, int size, int region_type) ++{ ++ int i; ++ struct region region; ++ const struct frba *frba = find_frba(image, size); ++ if (!frba) ++ exit(EXIT_FAILURE); ++ ++ region = get_region(frba, region_type); ++ if (region.size > 0) { ++ for (i = region.base; i <= region.limit; i++) { ++ if ((i + 1) > (size)) ++ break; ++ image[i] = 0xFF; ++ } ++ write_image(filename, image, size); ++ } ++} ++ + int main(int argc, char *argv[]) + { + int opt, option_index = 0; +@@ -2270,6 +2325,7 @@ int main(int argc, char *argv[]) + int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; + int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; + int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; ++ int mode_nuke = 0; + int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0; + int mode_settopswapsize = 0; + char *region_type_string = NULL, *region_fname = NULL, *layout_fname = NULL; +@@ -2306,6 +2362,7 @@ int main(int argc, char *argv[]) + {"setpchstrap", 1, NULL, 'S'}, + {"newvalue", 1, NULL, 'V'}, + {"topswapsize", 1, NULL, 'T'}, ++ {"nuke", 1, NULL, 'N'}, + {0, 0, 0, 0} + }; + +@@ -2355,35 +2412,8 @@ int main(int argc, char *argv[]) + region_fname++; + // Descriptor, BIOS, ME, GbE, Platform + // valid type? +- if (!strcasecmp("Descriptor", region_type_string)) +- region_type = 0; +- else if (!strcasecmp("BIOS", region_type_string)) +- region_type = 1; +- else if (!strcasecmp("ME", region_type_string)) +- region_type = 2; +- else if (!strcasecmp("GbE", region_type_string)) +- region_type = 3; +- else if (!strcasecmp("Platform Data", region_type_string)) +- region_type = 4; +- else if (!strcasecmp("Device Exp1", region_type_string)) +- region_type = 5; +- else if (!strcasecmp("Secondary BIOS", region_type_string)) +- region_type = 6; +- else if (!strcasecmp("Reserved", region_type_string)) +- region_type = 7; +- else if (!strcasecmp("EC", region_type_string)) +- region_type = 8; +- else if (!strcasecmp("Device Exp2", region_type_string)) +- region_type = 9; +- else if (!strcasecmp("IE", region_type_string)) +- region_type = 10; +- else if (!strcasecmp("10GbE_0", region_type_string)) +- region_type = 11; +- else if (!strcasecmp("10GbE_1", region_type_string)) +- region_type = 12; +- else if (!strcasecmp("PTT", region_type_string)) +- region_type = 15; +- if (region_type == -1) { ++ if ((region_type = ++ get_region_type_string(region_type_string)) == -1) { + fprintf(stderr, "No such region type: '%s'\n\n", + region_type_string); + fprintf(stderr, "run '%s -h' for usage\n", argv[0]); +@@ -2564,7 +2594,23 @@ int main(int argc, char *argv[]) + mode_settopswapsize = 1; + top_swap_size_arg = optarg; + break; +- case 'v': ++ case 'N': ++ region_type_string = strdup(optarg); ++ if (!region_type_string) { ++ fprintf(stderr, "No region specified\n"); ++ print_usage(argv[0]); ++ exit(EXIT_FAILURE); ++ } ++ if ((region_type = ++ get_region_type_string(region_type_string)) == -1) { ++ fprintf(stderr, "No such region type: '%s'\n\n", ++ region_type_string); ++ print_usage(argv[0]); ++ exit(EXIT_FAILURE); ++ } ++ mode_nuke = 1; ++ break; ++ Case 'v': + print_version(); + exit(EXIT_SUCCESS); + break; +@@ -2583,7 +2629,8 @@ int main(int argc, char *argv[]) + if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + + mode_setstrap + mode_settopswapsize + mode_newlayout + (mode_spifreq | mode_em100 | + mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + +- (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) { ++ (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status + ++ mode_nuke) > 1) { + fprintf(stderr, "You may not specify more than one mode.\n\n"); + fprintf(stderr, "run '%s -h' for usage\n", argv[0]); + exit(EXIT_FAILURE); +@@ -2592,7 +2639,8 @@ int main(int argc, char *argv[]) + if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + + mode_setstrap + mode_settopswapsize + mode_newlayout + mode_spifreq + mode_em100 + + mode_locked + mode_unlocked + mode_density + mode_altmedisable + +- mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) { ++ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status + ++ mode_nuke) == 0) { + fprintf(stderr, "You need to specify a mode.\n\n"); + fprintf(stderr, "run '%s -h' for usage\n", argv[0]); + exit(EXIT_FAILURE); +@@ -2758,6 +2806,10 @@ int main(int argc, char *argv[]) + write_image(new_filename, image, size); + } + ++ if (mode_nuke) { ++ nuke(new_filename, image, size, region_type); ++ } ++ + if (mode_altmedisable) { + struct fpsba *fpsba = find_fpsba(image, size); + struct fmsba *fmsba = find_fmsba(image, size); +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch deleted file mode 100644 index e583accc..00000000 --- a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 3ebe9e03ec563e5adb43337340fe973aa66a984a Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 07/48] Remove warning for coreboot images built without a - payload - -I added this in upstream to prevent people from accidentally flashing -roms without a payload resulting in a no boot situation, but in -libreboot lbmk handles the payload and thus this warning always comes -up. This has caused confusion and concern so just patch it out. ---- - payloads/Makefile.mk | 13 +------------ - 1 file changed, 1 insertion(+), 12 deletions(-) - -diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk -index 5f988dac1b..516133880f 100644 ---- a/payloads/Makefile.mk -+++ b/payloads/Makefile.mk -@@ -50,16 +50,5 @@ distclean-payloads: - print-repo-info-payloads: - -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) - --ifeq ($(CONFIG_PAYLOAD_NONE),y) --show_notices:: warn_no_payload --endif -- --warn_no_payload: -- printf "\n\t** WARNING **\n" -- printf "coreboot has been built without a payload. Writing\n" -- printf "a coreboot image without a payload to your board's\n" -- printf "flash chip will result in a non-booting system. You\n" -- printf "can use cbfstool to add a payload to the image.\n\n" -- - .PHONY: force-payload coreinfo nvramcui --.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload -+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads --- -2.47.3 - diff --git a/config/coreboot/default/patches/0007-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0007-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch new file mode 100644 index 00000000..bdab3fa6 --- /dev/null +++ b/config/coreboot/default/patches/0007-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -0,0 +1,28 @@ +From 6c626f71a4ec9f887d1b82da071011423a3fd24e Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Sat, 6 May 2023 15:53:41 -0600 +Subject: [PATCH 07/51] mb/dell/e6400: Enable 01.0 device in devicetree for + dGPU models + +Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/gm45_latitude/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/gm45_latitude/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb +index 5919803be2..76dae87153 100644 +--- a/src/mainboard/dell/gm45_latitude/devicetree.cb ++++ b/src/mainboard/dell/gm45_latitude/devicetree.cb +@@ -18,7 +18,7 @@ chip northbridge/intel/gm45 + ops gm45_pci_domain_ops + + device pci 00.0 on end # host bridge +- device pci 01.0 off end ++ device pci 01.0 on end + device pci 02.0 on end # VGA + device pci 02.1 on end # Display + device pci 03.0 on end # ME +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch deleted file mode 100644 index a450cb4e..00000000 --- a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 0e2fa472354b2e68ffbfc01d5bb225ca9d8973f0 Mon Sep 17 00:00:00 2001 -From: Alper Nebi Yasak -Date: Thu, 22 Jun 2023 16:44:27 +0300 -Subject: [PATCH 08/48] HACK: Disable coreboot related BL31 features - -I don't know why, but removing this BL31 make argument lets gru-kevin -power off properly when shut down from Linux. Needs investigation. ---- - src/arch/arm64/Makefile.mk | 3 --- - 1 file changed, 3 deletions(-) - -diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk -index efd628fee7..6c4f3d702e 100644 ---- a/src/arch/arm64/Makefile.mk -+++ b/src/arch/arm64/Makefile.mk -@@ -156,9 +156,6 @@ BL31_MAKEARGS += LOG_LEVEL=40 - # Always enable crash reporting, even on a release build - BL31_MAKEARGS += CRASH_REPORTING=1 - --# Enable coreboot-specific features like CBMEM console support --BL31_MAKEARGS += COREBOOT=1 -- - # Avoid build/release|build/debug distinction by overriding BUILD_PLAT directly - BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)" - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0008-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0008-Remove-warning-for-coreboot-images-built-without-a-p.patch new file mode 100644 index 00000000..03401a8b --- /dev/null +++ b/config/coreboot/default/patches/0008-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -0,0 +1,39 @@ +From bd349e86429cd0e83bbd6251ec507f3273b80854 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Fri, 12 May 2023 19:55:15 -0600 +Subject: [PATCH 08/51] Remove warning for coreboot images built without a + payload + +I added this in upstream to prevent people from accidentally flashing +roms without a payload resulting in a no boot situation, but in +libreboot lbmk handles the payload and thus this warning always comes +up. This has caused confusion and concern so just patch it out. +--- + payloads/Makefile.mk | 13 +------------ + 1 file changed, 1 insertion(+), 12 deletions(-) + +diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk +index 5f988dac1b..516133880f 100644 +--- a/payloads/Makefile.mk ++++ b/payloads/Makefile.mk +@@ -50,16 +50,5 @@ distclean-payloads: + print-repo-info-payloads: + -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) + +-ifeq ($(CONFIG_PAYLOAD_NONE),y) +-show_notices:: warn_no_payload +-endif +- +-warn_no_payload: +- printf "\n\t** WARNING **\n" +- printf "coreboot has been built without a payload. Writing\n" +- printf "a coreboot image without a payload to your board's\n" +- printf "flash chip will result in a non-booting system. You\n" +- printf "can use cbfstool to add a payload to the image.\n\n" +- + .PHONY: force-payload coreinfo nvramcui +-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload ++.PHONY: clean-payloads distclean-payloads print-repo-info-payloads +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0009-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0009-HACK-Disable-coreboot-related-BL31-features.patch new file mode 100644 index 00000000..158ff60b --- /dev/null +++ b/config/coreboot/default/patches/0009-HACK-Disable-coreboot-related-BL31-features.patch @@ -0,0 +1,28 @@ +From bd98f54b50b66d291641f88ec3169b9518855862 Mon Sep 17 00:00:00 2001 +From: Alper Nebi Yasak +Date: Thu, 22 Jun 2023 16:44:27 +0300 +Subject: [PATCH 09/51] HACK: Disable coreboot related BL31 features + +I don't know why, but removing this BL31 make argument lets gru-kevin +power off properly when shut down from Linux. Needs investigation. +--- + src/arch/arm64/Makefile.mk | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk +index 7310ce1c1f..b0a6ed1f84 100644 +--- a/src/arch/arm64/Makefile.mk ++++ b/src/arch/arm64/Makefile.mk +@@ -158,9 +158,6 @@ BL31_MAKEARGS += LOG_LEVEL=40 + # Always enable crash reporting, even on a release build + BL31_MAKEARGS += CRASH_REPORTING=1 + +-# Enable coreboot-specific features like CBMEM console support +-BL31_MAKEARGS += COREBOOT=1 +- + # Avoid build/release|build/debug distinction by overriding BUILD_PLAT directly + BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)" + +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch deleted file mode 100644 index d67bdf03..00000000 --- a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch +++ /dev/null @@ -1,30 +0,0 @@ -From f692cd96a4484b8e60bd112454d1bdbc3c689017 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sun, 5 Nov 2023 11:41:41 +0000 -Subject: [PATCH 09/48] dell/e6430: use ME Soft Temporary Disable - -i overlooked this. it's set on other boards. - -we use me_cleaner anyway, and we set the hap bit, but -this additional setting takes effect even if the ME -region is unaltered. it's just another layer of -disablement, to absolutely ensure Intel ME is not alive - -Signed-off-by: Leah Rowe ---- - src/mainboard/dell/snb_ivb_latitude/cmos.default | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/dell/snb_ivb_latitude/cmos.default b/src/mainboard/dell/snb_ivb_latitude/cmos.default -index 2a5b30f2b7..279415dfd1 100644 ---- a/src/mainboard/dell/snb_ivb_latitude/cmos.default -+++ b/src/mainboard/dell/snb_ivb_latitude/cmos.default -@@ -6,4 +6,4 @@ bluetooth=Enable - wwan=Enable - wlan=Enable - sata_mode=AHCI --me_state=Normal -+me_state=Disabled --- -2.47.3 - diff --git a/config/coreboot/default/patches/0010-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0010-dell-e6430-use-ME-Soft-Temporary-Disable.patch new file mode 100644 index 00000000..3451cc67 --- /dev/null +++ b/config/coreboot/default/patches/0010-dell-e6430-use-ME-Soft-Temporary-Disable.patch @@ -0,0 +1,30 @@ +From ae01730cad059bb3707b6d938a082dee9494bde5 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sun, 5 Nov 2023 11:41:41 +0000 +Subject: [PATCH 10/51] dell/e6430: use ME Soft Temporary Disable + +i overlooked this. it's set on other boards. + +we use me_cleaner anyway, and we set the hap bit, but +this additional setting takes effect even if the ME +region is unaltered. it's just another layer of +disablement, to absolutely ensure Intel ME is not alive + +Signed-off-by: Leah Rowe +--- + src/mainboard/dell/snb_ivb_latitude/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/snb_ivb_latitude/cmos.default b/src/mainboard/dell/snb_ivb_latitude/cmos.default +index 2a5b30f2b7..279415dfd1 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/cmos.default ++++ b/src/mainboard/dell/snb_ivb_latitude/cmos.default +@@ -6,4 +6,4 @@ bluetooth=Enable + wwan=Enable + wlan=Enable + sata_mode=AHCI +-me_state=Normal ++me_state=Disabled +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch deleted file mode 100644 index e01800af..00000000 --- a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch +++ /dev/null @@ -1,872 +0,0 @@ -From 78db6c595ff816ad4344d541688605ae720a83c4 Mon Sep 17 00:00:00 2001 -From: Riku Viitanen -Date: Sat, 23 Dec 2023 19:02:10 +0200 -Subject: [PATCH 10/48] mb/hp: Add Compaq Elite 8300 CMT port - -Based on autoport and Z220 SuperIO code. - -With SeaBIOS and Nouveau on Debian, only nomodeset works with GTX 780 -(must use proprietary driver instead). - -Tested by xilynx / spot_ on #libreboot: -- i3-3220, native raminit 2x2GB, M378B5773DH0-CH9 + MT8JTF25664AZ-1G6M1 -- Celeron G1620, native raminit 1x4GB, MT8JTF51264AZ-1G6E1 -- Booting Debian with Linux 6.1.0-16-amd64 via SeaBIOS -- All SATA ports -- Audio: internal speaker, headphone and microphone plugs -- Rebooting -- S3 suspend and wake -- libgfxinit: VGA, DisplayPort -- Ethernet -- Super I/O: fan speeds stay in control -- GPU in PEG slot - -Untested: -- EHCI debugging -- Other PCI/PCIe slots -- PS/2 -- Serial, parallel ports - -Change-Id: Ie6ec60d2f4ee50d5e3fa2847c19fa4cf0ab73363 -Signed-off-by: Riku Viitanen ---- - .../hp/compaq_elite_8300_cmt/Kconfig | 39 ++++ - .../hp/compaq_elite_8300_cmt/Kconfig.name | 2 + - .../hp/compaq_elite_8300_cmt/Makefile.mk | 7 + - .../hp/compaq_elite_8300_cmt/acpi/ec.asl | 1 + - .../compaq_elite_8300_cmt/acpi/platform.asl | 10 + - .../hp/compaq_elite_8300_cmt/acpi/superio.asl | 29 +++ - .../hp/compaq_elite_8300_cmt/acpi_tables.c | 12 ++ - .../hp/compaq_elite_8300_cmt/board_info.txt | 5 + - .../hp/compaq_elite_8300_cmt/cmos.default | 7 + - .../hp/compaq_elite_8300_cmt/cmos.layout | 74 +++++++ - .../hp/compaq_elite_8300_cmt/data.vbt | Bin 0 -> 3902 bytes - .../hp/compaq_elite_8300_cmt/devicetree.cb | 177 ++++++++++++++++ - .../hp/compaq_elite_8300_cmt/dsdt.asl | 26 +++ - .../hp/compaq_elite_8300_cmt/early_init.c | 14 ++ - .../compaq_elite_8300_cmt/gma-mainboard.ads | 17 ++ - src/mainboard/hp/compaq_elite_8300_cmt/gpio.c | 191 ++++++++++++++++++ - .../hp/compaq_elite_8300_cmt/hda_verb.c | 33 +++ - .../hp/compaq_elite_8300_cmt/mainboard.c | 16 ++ - 18 files changed, 660 insertions(+) - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/cmos.default - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/data.vbt - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/early_init.c - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/gpio.c - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c - create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c - -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig -new file mode 100644 -index 0000000000..d2bfd35dc4 ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig -@@ -0,0 +1,39 @@ -+if BOARD_HP_COMPAQ_ELITE_8300_CMT -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ select BOARD_ROMSIZE_KB_16384 -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ select INTEL_GMA_HAVE_VBT -+ select INTEL_INT15 -+ select MAINBOARD_HAS_TPM1 -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_USES_IFD_GBE_REGION -+ select MEMORY_MAPPED_TPM -+ select NORTHBRIDGE_INTEL_SANDYBRIDGE -+ select SERIRQ_CONTINUOUS_MODE -+ select SOUTHBRIDGE_INTEL_C216 -+ select SUPERIO_NUVOTON_NPCD378 -+ select USE_NATIVE_RAMINIT -+ -+config CBFS_SIZE -+ default 0x570000 -+ -+config MAINBOARD_DIR -+ default "hp/compaq_elite_8300_cmt" -+ -+config MAINBOARD_PART_NUMBER -+ default "HP Compaq Elite 8300 CMT" -+ -+config VGA_BIOS_ID -+ default "8086,0152" -+ -+config DRAM_RESET_GATE_GPIO -+ default 60 -+ -+config USBDEBUG_HCD_INDEX # FIXME: check this -+ default 2 -+endif -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name -new file mode 100644 -index 0000000000..bd399b1e76 ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name -@@ -0,0 +1,2 @@ -+config BOARD_HP_COMPAQ_ELITE_8300_CMT -+ bool "Compaq Elite 8300 CMT" -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk -new file mode 100644 -index 0000000000..fb492d3583 ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk -@@ -0,0 +1,7 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+bootblock-y += early_init.c -+bootblock-y += gpio.c -+romstage-y += early_init.c -+romstage-y += gpio.c -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl -new file mode 100644 -index 0000000000..73fa78ef14 ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl -@@ -0,0 +1 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl -new file mode 100644 -index 0000000000..aff432b6f4 ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl -@@ -0,0 +1,10 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+Method(_WAK, 1) -+{ -+ Return(Package() {0, 0}) -+} -+ -+Method(_PTS, 1) -+{ -+} -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl -new file mode 100644 -index 0000000000..54f8e3fe95 ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl -@@ -0,0 +1,29 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+/* Copied over from compaq_8200_elite_sff/acpi/superio.asl */ -+ -+#include -+ -+Scope (\_GPE) -+{ -+ Method (_L0D, 0, NotSerialized) -+ { -+ Notify (\_SB.PCI0.EHC1, 0x02) -+ Notify (\_SB.PCI0.EHC2, 0x02) -+ //FIXME: Add GBE device -+ //Notify (\_SB.PCI0.GBE, 0x02) -+ } -+ -+ Method (_L09, 0, NotSerialized) -+ { -+ Notify (\_SB.PCI0.RP01, 0x02) -+ Notify (\_SB.PCI0.RP02, 0x02) -+ Notify (\_SB.PCI0.RP03, 0x02) -+ Notify (\_SB.PCI0.RP04, 0x02) -+ Notify (\_SB.PCI0.RP05, 0x02) -+ Notify (\_SB.PCI0.RP06, 0x02) -+ Notify (\_SB.PCI0.RP07, 0x02) -+ Notify (\_SB.PCI0.RP08, 0x02) -+ Notify (\_SB.PCI0.PEGP, 0x02) -+ } -+} -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c b/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c -new file mode 100644 -index 0000000000..8f4f83b826 ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c -@@ -0,0 +1,12 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+ -+void mainboard_fill_gnvs(struct global_nvs *gnvs) -+{ -+ /* Temperature at which OS will shutdown */ -+ gnvs->tcrt = 100; -+ /* Temperature at which OS will throttle CPU */ -+ gnvs->tpsv = 90; -+} -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt b/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt -new file mode 100644 -index 0000000000..16c29e82d8 ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt -@@ -0,0 +1,5 @@ -+Category: desktop -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2012 -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default -new file mode 100644 -index 0000000000..6d27a79c66 ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default -@@ -0,0 +1,7 @@ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Enable -+nmi=Enable -+sata_mode=AHCI -+gfx_uma_size=32M -+psu_fan_lvl=3 -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout -new file mode 100644 -index 0000000000..1fc83b1a55 ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout -@@ -0,0 +1,74 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+400 3 h 0 psu_fan_lvl -+ -+# coreboot config options: southbridge -+408 1 e 1 nmi -+409 2 e 7 power_on_after_fail -+ -+421 1 e 9 sata_mode -+ -+# coreboot config options: northbridge -+432 3 e 11 gfx_uma_size -+ -+448 128 r 0 vbnv -+ -+# SandyBridge MRC Scrambler Seed values -+896 32 r 0 mrc_scrambler_seed -+928 32 r 0 mrc_scrambler_seed_s3 -+960 16 r 0 mrc_scrambler_seed_chk -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+2 0 Enable -+2 1 Disable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+9 0 AHCI -+9 1 IDE -+11 0 32M -+11 1 64M -+11 2 96M -+11 3 128M -+11 4 160M -+11 5 192M -+11 6 224M -+ -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 415 984 -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/data.vbt b/src/mainboard/hp/compaq_elite_8300_cmt/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..ba627e152b65d779a80529d3811ec4d21c1b1e54 -GIT binary patch -literal 3902 -zcmdT{U2GIp6h5;vvp;uc+U>N$b}h{<64)*MnJ%?9P1V_-)?HZIZFkwM#K;zQp(Lf0 -zb69XhyYd$H6Fo9yU(vE~()R;1j?k!Dq(D1|r9o2pI)6wGoV(Cz^&><0>;1cWR7zP*~YL5XE -z{3`?=k6Yy2an&85Zl2-7jM~D`7^g}MH^6WOPE9askfBLVUBl5fj(Wi%F%Ax(<(|k= -zUH4c9hXO|5?0UW22lb}G1;Fb@mzSZ8u5fTU59si@;V}EXTQ}(rl%Wn?F&a92X)&+> -zPTj@>Ls7r4(ffK2={zn6t_hS-cTaC$zZ!`R#y2KYqnT`O>nqx^H{P7_!|gKQVi}A& -z)G!L9*Z>@59dMlOh4owoes{Vd$kl1)tt1cJZseb2!YSsO`J_8jQ^hAhROmRyl4au@8tDixs`{k^Dwd%=Z -zH-yjQdy~%q^YKYth;}v$r!Z-pnAN<1I)+#R``=|huU|*W1ew~tpBFsG0q;_jCFT6Ulxt*TNv8# -z2{`>`$JM`Jd{F+EzpU7VIlvml?AFW1Xv$0tKyom(Ej2b-oERG0Q?%Jx8HYk6s9{*E -z_)hegWIm-8PLF`1DpU2QrTKj4;VUElwQBD4f+hZZbggj@JDLYbjpK69X2PaAVr^Xn{6e+%i&oRk>LBlzUQG|c;s(9FFjhafiyq*GToK^@07@tL{CZbd5K(*L<3rb71Ew* -zhn0l-*|a>v(n`=1+Du-&m2f&k|07qiv~u)9FuttfVcu_x;V>QXdsXjZ?db(%oNhK5 -zme#7yVBD-k)j4Zp4ohoWFJ0rv5wpCVNbYROUKoL9Ww31Rg%2ZHHV$2!ik&#T)={qH -z{mrUEty8JFXPPS;w@^`Y*;z%PU#m>bK7$Oci}}Epjc<@x;b&~*!Op}BgEe0X$iI{Gx1p1;4R>1E3jwQUCw| - -literal 0 -HcmV?d00001 - -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -new file mode 100644 -index 0000000000..3d21739b72 ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -@@ -0,0 +1,177 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+chip northbridge/intel/sandybridge -+ register "gfx.use_spread_spectrum_clock" = "0" -+ register "gpu_dp_b_hotplug" = "0" -+ register "gpu_dp_c_hotplug" = "0" -+ register "gpu_dp_d_hotplug" = "0" -+ # BTX mainboard: Reversed mapping -+ register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}" -+ device domain 0 on -+ subsystemid 0x103c 0x3396 inherit -+ -+ device ref host_bridge on end # Host bridge Host bridge -+ device ref peg10 on end # PEG -+ device ref igd on end # iGPU -+ -+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH -+ register "docking_supported" = "0" -+ register "gen1_dec" = "0x00fc0a01" -+ register "gen2_dec" = "0x00fc0801" -+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" -+ register "pcie_port_coalesce" = "1" -+ register "sata_interface_speed_support" = "0x3" -+ register "sata_port_map" = "0x1f" -+ register "spi_lvscc" = "0x2005" -+ register "spi_uvscc" = "0x2005" -+ register "superspeed_capable_ports" = "0x0000000f" -+ register "xhci_overcurrent_mapping" = "0x00000c03" -+ register "xhci_switchable_ports" = "0x0000000f" -+ register "usb_port_config" = "{ -+ { 1, 0, 0 }, -+ { 1, 0, 0 }, -+ { 1, 0, 1 }, -+ { 1, 0, 1 }, -+ { 1, 0, 2 }, -+ { 1, 0, 2 }, -+ { 1, 0, 3 }, -+ { 1, 0, 3 }, -+ { 1, 0, 4 }, -+ { 1, 0, 4 }, -+ { 1, 0, 6 }, -+ { 1, 0, 5 }, -+ { 1, 0, 5 }, -+ { 1, 0, 6 } -+ }" -+ -+ device ref xhci on end # USB 3.0 Controller -+ device ref mei1 off end # Management Engine Interface 1 -+ device ref mei2 off end -+ device ref me_ide_r off end -+ device ref me_kt off end -+ device ref gbe on end # Intel Gigabit Ethernet -+ device ref ehci1 on end # USB2 EHCI #1 -+ device ref ehci2 on end # USB2 EHCI #2 -+ device ref hda on end # High Definition Audio -+ device ref sata1 on end # SATA Controller 1 -+ device ref sata2 off end # SATA Controller 2 -+ device ref smbus on end # SMBus -+ -+ device ref pcie_rp1 on end -+ device ref pcie_rp2 on end -+ device ref pcie_rp3 on end -+ device ref pcie_rp4 on end -+ device ref pcie_rp5 on end -+ device ref pcie_rp6 on end -+ device ref pcie_rp7 on end -+ device ref pcie_rp8 on end -+ -+ device ref pci_bridge on end -+ device ref lpc on # LPC bridge -+ chip superio/common # copied from Z220 -+ device pnp 2e.ff on # passes SIO base addr to SSDT gen -+ chip superio/nuvoton/npcd378 -+ device pnp 2e.0 off end # Floppy -+ device pnp 2e.1 on # Parallel port -+ # global -+ -+ # serialice: Vendor writes: -+ irq 0x14 = 0x9c -+ irq 0x1c = 0xa8 -+ irq 0x1d = 0x08 -+ irq 0x22 = 0x3f -+ irq 0x1a = 0xb0 -+ # dumped from superiotool: -+ irq 0x1b = 0x1e -+ irq 0x27 = 0x08 -+ irq 0x2a = 0x20 -+ irq 0x2d = 0x01 -+ # parallel port -+ io 0x60 = 0x378 -+ irq 0x70 = 0x07 -+ drq 0x74 = 0x01 -+ end -+ device pnp 2e.2 off # COM1 -+ io 0x60 = 0x2f8 -+ irq 0x70 = 3 -+ end -+ device pnp 2e.3 on # COM2, IR -+ io 0x60 = 0x3f8 -+ irq 0x70 = 4 -+ end -+ device pnp 2e.4 on # LED control -+ io 0x60 = 0x600 -+ # IOBASE[0h] = bit0 LED red / green -+ # IOBASE[0h] = bit1-4 LED PWM duty cycle -+ # IOBASE[1h] = bit6 SWCC -+ -+ io 0x62 = 0x610 -+ # IOBASE [0h] = GPES -+ # IOBASE [1h] = GPEE -+ # IOBASE [4h:7h] = 32bit upcounter at 1Mhz -+ # IOBASE [8h:bh] = GPS -+ # IOBASE [ch:fh] = GPE -+ end -+ device pnp 2e.5 on # Mouse -+ irq 0x70 = 0xc -+ end -+ device pnp 2e.6 on # Keyboard -+ io 0x60 = 0x0060 -+ io 0x62 = 0x0064 -+ irq 0x70 = 0x01 -+ # serialice: Vendor writes: -+ drq 0xf0 = 0x40 -+ end -+ device pnp 2e.7 on # WDT ? -+ io 0x60 = 0x620 -+ end -+ device pnp 2e.8 on # HWM -+ io 0x60 = 0x800 -+ # IOBASE[0h:feh] HWM page -+ # IOBASE[ffh] bit0-bit3 page selector -+ -+ drq 0xf0 = 0x20 -+ drq 0xf1 = 0x01 -+ drq 0xf2 = 0x40 -+ drq 0xf3 = 0x01 -+ -+ drq 0xf4 = 0x66 -+ drq 0xf5 = 0x67 -+ drq 0xf6 = 0x66 -+ drq 0xf7 = 0x01 -+ end -+ device pnp 2e.f on # GPIO OD ? -+ drq 0xf1 = 0x97 -+ drq 0xf2 = 0x01 -+ drq 0xf5 = 0x08 -+ drq 0xfe = 0x80 -+ end -+ device pnp 2e.15 on # BUS ? -+ io 0x60 = 0x0680 -+ io 0x62 = 0x0690 -+ end -+ device pnp 2e.1c on # Suspend Control ? -+ io 0x60 = 0x640 -+ # writing to IOBASE[5h] -+ # 0x0: Power off -+ # 0x9: Power off and bricked until CMOS battery removed -+ end -+ device pnp 2e.1e on # GPIO ? -+ io 0x60 = 0x660 -+ drq 0xf4 = 0x01 -+ # skip the following, as it -+ # looks like remapped registers -+ #drq 0xf5 = 0x06 -+ #drq 0xf6 = 0x60 -+ #drq 0xfe = 0x03 -+ end -+ end -+ end -+ end -+ chip drivers/pc80/tpm -+ device pnp 4e.0 on end # TPM module -+ end -+ end -+ end -+ end -+end -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl b/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl -new file mode 100644 -index 0000000000..e8e2b3a3e5 ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20141018 /* OEM revision */ -+) -+{ -+ #include -+ #include "acpi/platform.asl" -+ #include -+ #include -+ #include -+ #include -+ -+ Device (\_SB.PCI0) -+ { -+ #include -+ #include -+ } -+} -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c -new file mode 100644 -index 0000000000..8d10c6317c ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c -@@ -0,0 +1,14 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include -+ -+#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2) -+ -+void bootblock_mainboard_early_init(void) -+{ -+ if (CONFIG(CONSOLE_SERIAL)) -+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -+} -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads b/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads -new file mode 100644 -index 0000000000..686f7d44db ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads -@@ -0,0 +1,17 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ (DP2, -+ HDMI2, -+ Analog, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c b/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c -new file mode 100644 -index 0000000000..2ae852ae51 ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c -@@ -0,0 +1,191 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_GPIO, -+ .gpio1 = GPIO_MODE_GPIO, -+ .gpio2 = GPIO_MODE_NATIVE, -+ .gpio3 = GPIO_MODE_NATIVE, -+ .gpio4 = GPIO_MODE_NATIVE, -+ .gpio5 = GPIO_MODE_NATIVE, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_GPIO, -+ .gpio8 = GPIO_MODE_GPIO, -+ .gpio9 = GPIO_MODE_NATIVE, -+ .gpio10 = GPIO_MODE_NATIVE, -+ .gpio11 = GPIO_MODE_GPIO, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_NATIVE, -+ .gpio15 = GPIO_MODE_GPIO, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_GPIO, -+ .gpio18 = GPIO_MODE_NATIVE, -+ .gpio19 = GPIO_MODE_NATIVE, -+ .gpio20 = GPIO_MODE_NATIVE, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_NATIVE, -+ .gpio31 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio0 = GPIO_DIR_INPUT, -+ .gpio1 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio7 = GPIO_DIR_INPUT, -+ .gpio8 = GPIO_DIR_INPUT, -+ .gpio11 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio15 = GPIO_DIR_OUTPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio17 = GPIO_DIR_OUTPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_OUTPUT, -+ .gpio29 = GPIO_DIR_OUTPUT, -+ .gpio31 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio15 = GPIO_LEVEL_LOW, -+ .gpio17 = GPIO_LEVEL_LOW, -+ .gpio28 = GPIO_LEVEL_LOW, -+ .gpio29 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_reset = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio0 = GPIO_INVERT, -+ .gpio1 = GPIO_INVERT, -+ .gpio6 = GPIO_INVERT, -+ .gpio11 = GPIO_INVERT, -+ .gpio13 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_GPIO, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_GPIO, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_NATIVE, -+ .gpio46 = GPIO_MODE_GPIO, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_NATIVE, -+ .gpio52 = GPIO_MODE_NATIVE, -+ .gpio53 = GPIO_MODE_NATIVE, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_NATIVE, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_NATIVE, -+ .gpio61 = GPIO_MODE_GPIO, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio32 = GPIO_DIR_INPUT, -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_INPUT, -+ .gpio35 = GPIO_DIR_INPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio43 = GPIO_DIR_INPUT, -+ .gpio46 = GPIO_DIR_INPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_INPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio61 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_reset = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_NATIVE, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_NATIVE, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_GPIO, -+ .gpio69 = GPIO_MODE_GPIO, -+ .gpio70 = GPIO_MODE_GPIO, -+ .gpio71 = GPIO_MODE_GPIO, -+ .gpio72 = GPIO_MODE_GPIO, -+ .gpio73 = GPIO_MODE_NATIVE, -+ .gpio74 = GPIO_MODE_NATIVE, -+ .gpio75 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio68 = GPIO_DIR_INPUT, -+ .gpio69 = GPIO_DIR_INPUT, -+ .gpio70 = GPIO_DIR_INPUT, -+ .gpio71 = GPIO_DIR_OUTPUT, -+ .gpio72 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+ .gpio71 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_reset = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ .reset = &pch_gpio_set1_reset, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ .reset = &pch_gpio_set2_reset, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ .reset = &pch_gpio_set3_reset, -+ }, -+}; -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c b/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c -new file mode 100644 -index 0000000000..a1eafcda68 ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c -@@ -0,0 +1,33 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ 0x10ec0221, /* Codec Vendor / Device ID: Realtek */ -+ 0x103c3396, /* Subsystem ID */ -+ 11, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(0, 0x103c3396), -+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0), -+ AZALIA_PIN_CFG(0, 0x14, 0x01014020), -+ AZALIA_PIN_CFG(0, 0x17, 0x90170110), -+ AZALIA_PIN_CFG(0, 0x18, 0x411111f0), -+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0), -+ AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f), -+ AZALIA_PIN_CFG(0, 0x1b, 0x01813c30), -+ AZALIA_PIN_CFG(0, 0x1d, 0x415901f0), -+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), -+ AZALIA_PIN_CFG(0, 0x21, 0x0221102f), -+ -+ 0x80862806, /* Codec Vendor / Device ID: Intel */ -+ 0x80860101, /* Subsystem ID */ -+ 4, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(3, 0x80860101), -+ AZALIA_PIN_CFG(3, 0x05, 0x58560010), -+ AZALIA_PIN_CFG(3, 0x06, 0x18560020), -+ AZALIA_PIN_CFG(3, 0x07, 0x58560030), -+ -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c b/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c -new file mode 100644 -index 0000000000..8dbd95ef96 ---- /dev/null -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+ -+static void mainboard_enable(struct device *dev) -+{ -+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, -+ GMA_INT15_PANEL_FIT_DEFAULT, -+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -+} -+ -+struct chip_operations mainboard_ops = { -+ .enable_dev = mainboard_enable, -+}; --- -2.47.3 - diff --git a/config/coreboot/default/patches/0011-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0011-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch new file mode 100644 index 00000000..c3fee8c7 --- /dev/null +++ b/config/coreboot/default/patches/0011-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch @@ -0,0 +1,872 @@ +From ae7d23355be8efbbe3a1216d8e28c30a07e2e0ef Mon Sep 17 00:00:00 2001 +From: Riku Viitanen +Date: Sat, 23 Dec 2023 19:02:10 +0200 +Subject: [PATCH 11/51] mb/hp: Add Compaq Elite 8300 CMT port + +Based on autoport and Z220 SuperIO code. + +With SeaBIOS and Nouveau on Debian, only nomodeset works with GTX 780 +(must use proprietary driver instead). + +Tested by xilynx / spot_ on #libreboot: +- i3-3220, native raminit 2x2GB, M378B5773DH0-CH9 + MT8JTF25664AZ-1G6M1 +- Celeron G1620, native raminit 1x4GB, MT8JTF51264AZ-1G6E1 +- Booting Debian with Linux 6.1.0-16-amd64 via SeaBIOS +- All SATA ports +- Audio: internal speaker, headphone and microphone plugs +- Rebooting +- S3 suspend and wake +- libgfxinit: VGA, DisplayPort +- Ethernet +- Super I/O: fan speeds stay in control +- GPU in PEG slot + +Untested: +- EHCI debugging +- Other PCI/PCIe slots +- PS/2 +- Serial, parallel ports + +Change-Id: Ie6ec60d2f4ee50d5e3fa2847c19fa4cf0ab73363 +Signed-off-by: Riku Viitanen +--- + .../hp/compaq_elite_8300_cmt/Kconfig | 39 ++++ + .../hp/compaq_elite_8300_cmt/Kconfig.name | 2 + + .../hp/compaq_elite_8300_cmt/Makefile.mk | 7 + + .../hp/compaq_elite_8300_cmt/acpi/ec.asl | 1 + + .../compaq_elite_8300_cmt/acpi/platform.asl | 10 + + .../hp/compaq_elite_8300_cmt/acpi/superio.asl | 29 +++ + .../hp/compaq_elite_8300_cmt/acpi_tables.c | 12 ++ + .../hp/compaq_elite_8300_cmt/board_info.txt | 5 + + .../hp/compaq_elite_8300_cmt/cmos.default | 7 + + .../hp/compaq_elite_8300_cmt/cmos.layout | 74 +++++++ + .../hp/compaq_elite_8300_cmt/data.vbt | Bin 0 -> 3902 bytes + .../hp/compaq_elite_8300_cmt/devicetree.cb | 177 ++++++++++++++++ + .../hp/compaq_elite_8300_cmt/dsdt.asl | 26 +++ + .../hp/compaq_elite_8300_cmt/early_init.c | 14 ++ + .../compaq_elite_8300_cmt/gma-mainboard.ads | 17 ++ + src/mainboard/hp/compaq_elite_8300_cmt/gpio.c | 191 ++++++++++++++++++ + .../hp/compaq_elite_8300_cmt/hda_verb.c | 33 +++ + .../hp/compaq_elite_8300_cmt/mainboard.c | 16 ++ + 18 files changed, 660 insertions(+) + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/cmos.default + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/data.vbt + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/early_init.c + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/gpio.c + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c + +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig +new file mode 100644 +index 0000000000..d2bfd35dc4 +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig +@@ -0,0 +1,39 @@ ++if BOARD_HP_COMPAQ_ELITE_8300_CMT ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ select BOARD_ROMSIZE_KB_16384 ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ select INTEL_GMA_HAVE_VBT ++ select INTEL_INT15 ++ select MAINBOARD_HAS_TPM1 ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select MEMORY_MAPPED_TPM ++ select NORTHBRIDGE_INTEL_SANDYBRIDGE ++ select SERIRQ_CONTINUOUS_MODE ++ select SOUTHBRIDGE_INTEL_C216 ++ select SUPERIO_NUVOTON_NPCD378 ++ select USE_NATIVE_RAMINIT ++ ++config CBFS_SIZE ++ default 0x570000 ++ ++config MAINBOARD_DIR ++ default "hp/compaq_elite_8300_cmt" ++ ++config MAINBOARD_PART_NUMBER ++ default "HP Compaq Elite 8300 CMT" ++ ++config VGA_BIOS_ID ++ default "8086,0152" ++ ++config DRAM_RESET_GATE_GPIO ++ default 60 ++ ++config USBDEBUG_HCD_INDEX # FIXME: check this ++ default 2 ++endif +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name +new file mode 100644 +index 0000000000..bd399b1e76 +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name +@@ -0,0 +1,2 @@ ++config BOARD_HP_COMPAQ_ELITE_8300_CMT ++ bool "Compaq Elite 8300 CMT" +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk +new file mode 100644 +index 0000000000..fb492d3583 +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk +@@ -0,0 +1,7 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++bootblock-y += early_init.c ++bootblock-y += gpio.c ++romstage-y += early_init.c ++romstage-y += gpio.c ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl +new file mode 100644 +index 0000000000..73fa78ef14 +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl +@@ -0,0 +1 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl +new file mode 100644 +index 0000000000..aff432b6f4 +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl +@@ -0,0 +1,10 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++Method(_WAK, 1) ++{ ++ Return(Package() {0, 0}) ++} ++ ++Method(_PTS, 1) ++{ ++} +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl +new file mode 100644 +index 0000000000..54f8e3fe95 +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl +@@ -0,0 +1,29 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* Copied over from compaq_8200_elite_sff/acpi/superio.asl */ ++ ++#include ++ ++Scope (\_GPE) ++{ ++ Method (_L0D, 0, NotSerialized) ++ { ++ Notify (\_SB.PCI0.EHC1, 0x02) ++ Notify (\_SB.PCI0.EHC2, 0x02) ++ //FIXME: Add GBE device ++ //Notify (\_SB.PCI0.GBE, 0x02) ++ } ++ ++ Method (_L09, 0, NotSerialized) ++ { ++ Notify (\_SB.PCI0.RP01, 0x02) ++ Notify (\_SB.PCI0.RP02, 0x02) ++ Notify (\_SB.PCI0.RP03, 0x02) ++ Notify (\_SB.PCI0.RP04, 0x02) ++ Notify (\_SB.PCI0.RP05, 0x02) ++ Notify (\_SB.PCI0.RP06, 0x02) ++ Notify (\_SB.PCI0.RP07, 0x02) ++ Notify (\_SB.PCI0.RP08, 0x02) ++ Notify (\_SB.PCI0.PEGP, 0x02) ++ } ++} +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c b/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c +new file mode 100644 +index 0000000000..8f4f83b826 +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c +@@ -0,0 +1,12 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_fill_gnvs(struct global_nvs *gnvs) ++{ ++ /* Temperature at which OS will shutdown */ ++ gnvs->tcrt = 100; ++ /* Temperature at which OS will throttle CPU */ ++ gnvs->tpsv = 90; ++} +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt b/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt +new file mode 100644 +index 0000000000..16c29e82d8 +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt +@@ -0,0 +1,5 @@ ++Category: desktop ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y ++Release year: 2012 +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default +new file mode 100644 +index 0000000000..6d27a79c66 +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default +@@ -0,0 +1,7 @@ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Enable ++nmi=Enable ++sata_mode=AHCI ++gfx_uma_size=32M ++psu_fan_lvl=3 +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout +new file mode 100644 +index 0000000000..1fc83b1a55 +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout +@@ -0,0 +1,74 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++400 3 h 0 psu_fan_lvl ++ ++# coreboot config options: southbridge ++408 1 e 1 nmi ++409 2 e 7 power_on_after_fail ++ ++421 1 e 9 sata_mode ++ ++# coreboot config options: northbridge ++432 3 e 11 gfx_uma_size ++ ++448 128 r 0 vbnv ++ ++# SandyBridge MRC Scrambler Seed values ++896 32 r 0 mrc_scrambler_seed ++928 32 r 0 mrc_scrambler_seed_s3 ++960 16 r 0 mrc_scrambler_seed_chk ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++2 0 Enable ++2 1 Disable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++9 0 AHCI ++9 1 IDE ++11 0 32M ++11 1 64M ++11 2 96M ++11 3 128M ++11 4 160M ++11 5 192M ++11 6 224M ++ ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 415 984 +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/data.vbt b/src/mainboard/hp/compaq_elite_8300_cmt/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..ba627e152b65d779a80529d3811ec4d21c1b1e54 +GIT binary patch +literal 3902 +zcmdT{U2GIp6h5;vvp;uc+U>N$b}h{<64)*MnJ%?9P1V_-)?HZIZFkwM#K;zQp(Lf0 +zb69XhyYd$H6Fo9yU(vE~()R;1j?k!Dq(D1|r9o2pI)6wGoV(Cz^&><0>;1cWR7zP*~YL5XE +z{3`?=k6Yy2an&85Zl2-7jM~D`7^g}MH^6WOPE9askfBLVUBl5fj(Wi%F%Ax(<(|k= +zUH4c9hXO|5?0UW22lb}G1;Fb@mzSZ8u5fTU59si@;V}EXTQ}(rl%Wn?F&a92X)&+> +zPTj@>Ls7r4(ffK2={zn6t_hS-cTaC$zZ!`R#y2KYqnT`O>nqx^H{P7_!|gKQVi}A& +z)G!L9*Z>@59dMlOh4owoes{Vd$kl1)tt1cJZseb2!YSsO`J_8jQ^hAhROmRyl4au@8tDixs`{k^Dwd%=Z +zH-yjQdy~%q^YKYth;}v$r!Z-pnAN<1I)+#R``=|huU|*W1ew~tpBFsG0q;_jCFT6Ulxt*TNv8# +z2{`>`$JM`Jd{F+EzpU7VIlvml?AFW1Xv$0tKyom(Ej2b-oERG0Q?%Jx8HYk6s9{*E +z_)hegWIm-8PLF`1DpU2QrTKj4;VUElwQBD4f+hZZbggj@JDLYbjpK69X2PaAVr^Xn{6e+%i&oRk>LBlzUQG|c;s(9FFjhafiyq*GToK^@07@tL{CZbd5K(*L<3rb71Ew* +zhn0l-*|a>v(n`=1+Du-&m2f&k|07qiv~u)9FuttfVcu_x;V>QXdsXjZ?db(%oNhK5 +zme#7yVBD-k)j4Zp4ohoWFJ0rv5wpCVNbYROUKoL9Ww31Rg%2ZHHV$2!ik&#T)={qH +z{mrUEty8JFXPPS;w@^`Y*;z%PU#m>bK7$Oci}}Epjc<@x;b&~*!Op}BgEe0X$iI{Gx1p1;4R>1E3jwQUCw| + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb +new file mode 100644 +index 0000000000..3d21739b72 +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb +@@ -0,0 +1,177 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++chip northbridge/intel/sandybridge ++ register "gfx.use_spread_spectrum_clock" = "0" ++ register "gpu_dp_b_hotplug" = "0" ++ register "gpu_dp_c_hotplug" = "0" ++ register "gpu_dp_d_hotplug" = "0" ++ # BTX mainboard: Reversed mapping ++ register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}" ++ device domain 0 on ++ subsystemid 0x103c 0x3396 inherit ++ ++ device ref host_bridge on end # Host bridge Host bridge ++ device ref peg10 on end # PEG ++ device ref igd on end # iGPU ++ ++ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH ++ register "docking_supported" = "0" ++ register "gen1_dec" = "0x00fc0a01" ++ register "gen2_dec" = "0x00fc0801" ++ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" ++ register "pcie_port_coalesce" = "1" ++ register "sata_interface_speed_support" = "0x3" ++ register "sata_port_map" = "0x1f" ++ register "spi_lvscc" = "0x2005" ++ register "spi_uvscc" = "0x2005" ++ register "superspeed_capable_ports" = "0x0000000f" ++ register "xhci_overcurrent_mapping" = "0x00000c03" ++ register "xhci_switchable_ports" = "0x0000000f" ++ register "usb_port_config" = "{ ++ { 1, 0, 0 }, ++ { 1, 0, 0 }, ++ { 1, 0, 1 }, ++ { 1, 0, 1 }, ++ { 1, 0, 2 }, ++ { 1, 0, 2 }, ++ { 1, 0, 3 }, ++ { 1, 0, 3 }, ++ { 1, 0, 4 }, ++ { 1, 0, 4 }, ++ { 1, 0, 6 }, ++ { 1, 0, 5 }, ++ { 1, 0, 5 }, ++ { 1, 0, 6 } ++ }" ++ ++ device ref xhci on end # USB 3.0 Controller ++ device ref mei1 off end # Management Engine Interface 1 ++ device ref mei2 off end ++ device ref me_ide_r off end ++ device ref me_kt off end ++ device ref gbe on end # Intel Gigabit Ethernet ++ device ref ehci1 on end # USB2 EHCI #1 ++ device ref ehci2 on end # USB2 EHCI #2 ++ device ref hda on end # High Definition Audio ++ device ref sata1 on end # SATA Controller 1 ++ device ref sata2 off end # SATA Controller 2 ++ device ref smbus on end # SMBus ++ ++ device ref pcie_rp1 on end ++ device ref pcie_rp2 on end ++ device ref pcie_rp3 on end ++ device ref pcie_rp4 on end ++ device ref pcie_rp5 on end ++ device ref pcie_rp6 on end ++ device ref pcie_rp7 on end ++ device ref pcie_rp8 on end ++ ++ device ref pci_bridge on end ++ device ref lpc on # LPC bridge ++ chip superio/common # copied from Z220 ++ device pnp 2e.ff on # passes SIO base addr to SSDT gen ++ chip superio/nuvoton/npcd378 ++ device pnp 2e.0 off end # Floppy ++ device pnp 2e.1 on # Parallel port ++ # global ++ ++ # serialice: Vendor writes: ++ irq 0x14 = 0x9c ++ irq 0x1c = 0xa8 ++ irq 0x1d = 0x08 ++ irq 0x22 = 0x3f ++ irq 0x1a = 0xb0 ++ # dumped from superiotool: ++ irq 0x1b = 0x1e ++ irq 0x27 = 0x08 ++ irq 0x2a = 0x20 ++ irq 0x2d = 0x01 ++ # parallel port ++ io 0x60 = 0x378 ++ irq 0x70 = 0x07 ++ drq 0x74 = 0x01 ++ end ++ device pnp 2e.2 off # COM1 ++ io 0x60 = 0x2f8 ++ irq 0x70 = 3 ++ end ++ device pnp 2e.3 on # COM2, IR ++ io 0x60 = 0x3f8 ++ irq 0x70 = 4 ++ end ++ device pnp 2e.4 on # LED control ++ io 0x60 = 0x600 ++ # IOBASE[0h] = bit0 LED red / green ++ # IOBASE[0h] = bit1-4 LED PWM duty cycle ++ # IOBASE[1h] = bit6 SWCC ++ ++ io 0x62 = 0x610 ++ # IOBASE [0h] = GPES ++ # IOBASE [1h] = GPEE ++ # IOBASE [4h:7h] = 32bit upcounter at 1Mhz ++ # IOBASE [8h:bh] = GPS ++ # IOBASE [ch:fh] = GPE ++ end ++ device pnp 2e.5 on # Mouse ++ irq 0x70 = 0xc ++ end ++ device pnp 2e.6 on # Keyboard ++ io 0x60 = 0x0060 ++ io 0x62 = 0x0064 ++ irq 0x70 = 0x01 ++ # serialice: Vendor writes: ++ drq 0xf0 = 0x40 ++ end ++ device pnp 2e.7 on # WDT ? ++ io 0x60 = 0x620 ++ end ++ device pnp 2e.8 on # HWM ++ io 0x60 = 0x800 ++ # IOBASE[0h:feh] HWM page ++ # IOBASE[ffh] bit0-bit3 page selector ++ ++ drq 0xf0 = 0x20 ++ drq 0xf1 = 0x01 ++ drq 0xf2 = 0x40 ++ drq 0xf3 = 0x01 ++ ++ drq 0xf4 = 0x66 ++ drq 0xf5 = 0x67 ++ drq 0xf6 = 0x66 ++ drq 0xf7 = 0x01 ++ end ++ device pnp 2e.f on # GPIO OD ? ++ drq 0xf1 = 0x97 ++ drq 0xf2 = 0x01 ++ drq 0xf5 = 0x08 ++ drq 0xfe = 0x80 ++ end ++ device pnp 2e.15 on # BUS ? ++ io 0x60 = 0x0680 ++ io 0x62 = 0x0690 ++ end ++ device pnp 2e.1c on # Suspend Control ? ++ io 0x60 = 0x640 ++ # writing to IOBASE[5h] ++ # 0x0: Power off ++ # 0x9: Power off and bricked until CMOS battery removed ++ end ++ device pnp 2e.1e on # GPIO ? ++ io 0x60 = 0x660 ++ drq 0xf4 = 0x01 ++ # skip the following, as it ++ # looks like remapped registers ++ #drq 0xf5 = 0x06 ++ #drq 0xf6 = 0x60 ++ #drq 0xfe = 0x03 ++ end ++ end ++ end ++ end ++ chip drivers/pc80/tpm ++ device pnp 4e.0 on end # TPM module ++ end ++ end ++ end ++ end ++end +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl b/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl +new file mode 100644 +index 0000000000..e8e2b3a3e5 +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20141018 /* OEM revision */ ++) ++{ ++ #include ++ #include "acpi/platform.asl" ++ #include ++ #include ++ #include ++ #include ++ ++ Device (\_SB.PCI0) ++ { ++ #include ++ #include ++ } ++} +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c +new file mode 100644 +index 0000000000..8d10c6317c +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++ ++#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2) ++ ++void bootblock_mainboard_early_init(void) ++{ ++ if (CONFIG(CONSOLE_SERIAL)) ++ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ++} +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads b/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads +new file mode 100644 +index 0000000000..686f7d44db +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads +@@ -0,0 +1,17 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (DP2, ++ HDMI2, ++ Analog, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c b/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c +new file mode 100644 +index 0000000000..2ae852ae51 +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c +@@ -0,0 +1,191 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_GPIO, ++ .gpio2 = GPIO_MODE_NATIVE, ++ .gpio3 = GPIO_MODE_NATIVE, ++ .gpio4 = GPIO_MODE_NATIVE, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_GPIO, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_NATIVE, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_NATIVE, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_NATIVE, ++ .gpio31 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio1 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio11 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_OUTPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_OUTPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_OUTPUT, ++ .gpio31 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio15 = GPIO_LEVEL_LOW, ++ .gpio17 = GPIO_LEVEL_LOW, ++ .gpio28 = GPIO_LEVEL_LOW, ++ .gpio29 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio0 = GPIO_INVERT, ++ .gpio1 = GPIO_INVERT, ++ .gpio6 = GPIO_INVERT, ++ .gpio11 = GPIO_INVERT, ++ .gpio13 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_GPIO, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_GPIO, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_GPIO, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_NATIVE, ++ .gpio52 = GPIO_MODE_NATIVE, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_NATIVE, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_NATIVE, ++ .gpio61 = GPIO_MODE_GPIO, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio32 = GPIO_DIR_INPUT, ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio43 = GPIO_DIR_INPUT, ++ .gpio46 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_INPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio61 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_GPIO, ++ .gpio69 = GPIO_MODE_GPIO, ++ .gpio70 = GPIO_MODE_GPIO, ++ .gpio71 = GPIO_MODE_GPIO, ++ .gpio72 = GPIO_MODE_GPIO, ++ .gpio73 = GPIO_MODE_NATIVE, ++ .gpio74 = GPIO_MODE_NATIVE, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio68 = GPIO_DIR_INPUT, ++ .gpio69 = GPIO_DIR_INPUT, ++ .gpio70 = GPIO_DIR_INPUT, ++ .gpio71 = GPIO_DIR_OUTPUT, ++ .gpio72 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++ .gpio71 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c b/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c +new file mode 100644 +index 0000000000..a1eafcda68 +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c +@@ -0,0 +1,33 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ 0x10ec0221, /* Codec Vendor / Device ID: Realtek */ ++ 0x103c3396, /* Subsystem ID */ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x103c3396), ++ AZALIA_PIN_CFG(0, 0x12, 0x411111f0), ++ AZALIA_PIN_CFG(0, 0x14, 0x01014020), ++ AZALIA_PIN_CFG(0, 0x17, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x18, 0x411111f0), ++ AZALIA_PIN_CFG(0, 0x19, 0x411111f0), ++ AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f), ++ AZALIA_PIN_CFG(0, 0x1b, 0x01813c30), ++ AZALIA_PIN_CFG(0, 0x1d, 0x415901f0), ++ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), ++ AZALIA_PIN_CFG(0, 0x21, 0x0221102f), ++ ++ 0x80862806, /* Codec Vendor / Device ID: Intel */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(3, 0x80860101), ++ AZALIA_PIN_CFG(3, 0x05, 0x58560010), ++ AZALIA_PIN_CFG(3, 0x06, 0x18560020), ++ AZALIA_PIN_CFG(3, 0x07, 0x58560030), ++ ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c b/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c +new file mode 100644 +index 0000000000..8dbd95ef96 +--- /dev/null ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c +@@ -0,0 +1,16 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++ ++static void mainboard_enable(struct device *dev) ++{ ++ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, ++ GMA_INT15_PANEL_FIT_DEFAULT, ++ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); ++} ++ ++struct chip_operations mainboard_ops = { ++ .enable_dev = mainboard_enable, ++}; +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch deleted file mode 100644 index 235ee880..00000000 --- a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch +++ /dev/null @@ -1,292 +0,0 @@ -From beb9b1650fb3aec96544b683fbe53ee16584f3d8 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 2 Mar 2024 22:51:09 +0000 -Subject: [PATCH 11/48] nb/intel/haswell: make IOMMU a runtime option - -When I tested graphics cards on a coreboot port for Dell -OptiPlex 9020 SFF, I could not use a graphics card unless -I set iommu=off on the Linux cmdline. - -Coreboot's current behaviour is to check whether the CPU -has vt-d support and, if it does, initialise the IOMMU. - -This patch maintains the current behaviour by default, but -allows the user to turn *off* the IOMMU, even if vt-d is -supported by the host CPU. - -If iommu=Disable is specified, the check will not be -performed, and the IOMMU will be left disabled. This option -has been added to all current Haswell boards, though it is -recommended to leave the IOMMU turned on in most setups. - -Signed-off-by: Leah Rowe ---- - src/mainboard/asrock/b85m_pro4/cmos.default | 1 + - src/mainboard/asrock/b85m_pro4/cmos.layout | 3 +++ - src/mainboard/asrock/h81m-hds/cmos.default | 1 + - src/mainboard/asrock/h81m-hds/cmos.layout | 6 ++++++ - src/mainboard/dell/optiplex_9020/cmos.default | 1 + - src/mainboard/dell/optiplex_9020/cmos.layout | 6 ++++++ - src/mainboard/google/beltino/cmos.layout | 5 +++++ - src/mainboard/google/slippy/cmos.layout | 5 +++++ - src/mainboard/intel/baskingridge/cmos.layout | 4 ++++ - src/mainboard/lenovo/haswell/cmos.default | 1 + - src/mainboard/lenovo/haswell/cmos.layout | 3 +++ - src/mainboard/supermicro/x10slm-f/cmos.default | 1 + - src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++ - src/northbridge/intel/haswell/early_init.c | 5 +++++ - 14 files changed, 48 insertions(+) - -diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default -index 01bf20ad16..dfc8b80fb0 100644 ---- a/src/mainboard/asrock/b85m_pro4/cmos.default -+++ b/src/mainboard/asrock/b85m_pro4/cmos.default -@@ -4,3 +4,4 @@ boot_option=Fallback - debug_level=Debug - nmi=Enable - power_on_after_fail=Disable -+iommu=Enable -diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout -index efdc333fc2..c9883ea71d 100644 ---- a/src/mainboard/asrock/b85m_pro4/cmos.layout -+++ b/src/mainboard/asrock/b85m_pro4/cmos.layout -@@ -11,6 +11,7 @@ - 395 4 e 4 debug_level - 408 1 e 1 nmi - 409 2 e 5 power_on_after_fail -+ 412 1 e 6 iommu - 984 16 h 0 check_sum - # ----------------------------------------------------------------- - -@@ -38,6 +39,8 @@ - 5 0 Disable - 5 1 Enable - 5 2 Keep -+ 6 0 Disable -+ 6 1 Enable - # ----------------------------------------------------------------- - - # ----------------------------------------------------------------- -diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default -index 01bf20ad16..dfc8b80fb0 100644 ---- a/src/mainboard/asrock/h81m-hds/cmos.default -+++ b/src/mainboard/asrock/h81m-hds/cmos.default -@@ -4,3 +4,4 @@ boot_option=Fallback - debug_level=Debug - nmi=Enable - power_on_after_fail=Disable -+iommu=Enable -diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout -index c9ba76c78f..95ee3d36fb 100644 ---- a/src/mainboard/asrock/h81m-hds/cmos.layout -+++ b/src/mainboard/asrock/h81m-hds/cmos.layout -@@ -21,6 +21,9 @@ entries - 408 1 e 1 nmi - 409 2 e 5 power_on_after_fail - -+# enable or disable iommu -+412 1 e 6 iommu -+ - # coreboot config options: check sums - 984 16 h 0 check_sum - -@@ -52,6 +55,9 @@ enumerations - 5 1 Enable - 5 2 Keep - -+6 0 Disable -+6 1 Enable -+ - # ----------------------------------------------------------------- - checksums - -diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default -index 6c4a2a1be7..8000eea8c0 100644 ---- a/src/mainboard/dell/optiplex_9020/cmos.default -+++ b/src/mainboard/dell/optiplex_9020/cmos.default -@@ -4,3 +4,4 @@ debug_level=Debug - nmi=Disable - power_on_after_fail=Disable - fan_full_speed=Disable -+iommu=Enable -diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout -index d10ad95b23..4a1496a878 100644 ---- a/src/mainboard/dell/optiplex_9020/cmos.layout -+++ b/src/mainboard/dell/optiplex_9020/cmos.layout -@@ -21,6 +21,9 @@ entries - 408 1 e 1 nmi - 409 2 e 5 power_on_after_fail - -+# turn iommu on or off -+411 1 e 6 iommu -+ - # coreboot config options: EC - 412 1 e 1 fan_full_speed - -@@ -55,6 +58,9 @@ enumerations - 5 1 Enable - 5 2 Keep - -+6 0 Disable -+6 1 Enable -+ - # ----------------------------------------------------------------- - checksums - -diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout -index 78d44c1415..c143979ae1 100644 ---- a/src/mainboard/google/beltino/cmos.layout -+++ b/src/mainboard/google/beltino/cmos.layout -@@ -19,6 +19,9 @@ entries - 408 1 e 1 nmi - 409 2 e 7 power_on_after_fail - -+# enable or disable iommu -+412 1 e 8 iommu -+ - # coreboot config options: bootloader - #Used by ChromeOS: - 416 128 r 0 vbnv -@@ -47,6 +50,8 @@ enumerations - 7 0 Disable - 7 1 Enable - 7 2 Keep -+8 0 Disable -+8 1 Enable - # ----------------------------------------------------------------- - checksums - -diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout -index 78d44c1415..c143979ae1 100644 ---- a/src/mainboard/google/slippy/cmos.layout -+++ b/src/mainboard/google/slippy/cmos.layout -@@ -19,6 +19,9 @@ entries - 408 1 e 1 nmi - 409 2 e 7 power_on_after_fail - -+# enable or disable iommu -+412 1 e 8 iommu -+ - # coreboot config options: bootloader - #Used by ChromeOS: - 416 128 r 0 vbnv -@@ -47,6 +50,8 @@ enumerations - 7 0 Disable - 7 1 Enable - 7 2 Keep -+8 0 Disable -+8 1 Enable - # ----------------------------------------------------------------- - checksums - -diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout -index 78d44c1415..f2c602f541 100644 ---- a/src/mainboard/intel/baskingridge/cmos.layout -+++ b/src/mainboard/intel/baskingridge/cmos.layout -@@ -19,6 +19,8 @@ entries - 408 1 e 1 nmi - 409 2 e 7 power_on_after_fail - -+412 1 e 8 iommu -+ - # coreboot config options: bootloader - #Used by ChromeOS: - 416 128 r 0 vbnv -@@ -47,6 +49,8 @@ enumerations - 7 0 Disable - 7 1 Enable - 7 2 Keep -+8 0 Disable -+8 1 Enable - # ----------------------------------------------------------------- - checksums - -diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default -index 08db97c5a9..cc6b363cd9 100644 ---- a/src/mainboard/lenovo/haswell/cmos.default -+++ b/src/mainboard/lenovo/haswell/cmos.default -@@ -14,3 +14,4 @@ trackpoint=Enable - backlight=Keyboard - enable_dual_graphics=Disable - usb_always_on=Disable -+iommu=Enable -diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout -index 27915d3ab7..59df76b64c 100644 ---- a/src/mainboard/lenovo/haswell/cmos.layout -+++ b/src/mainboard/lenovo/haswell/cmos.layout -@@ -23,6 +23,7 @@ entries - - # coreboot config options: EC - 411 1 e 8 first_battery -+413 1 e 14 iommu - 415 1 e 1 wlan - 416 1 e 1 trackpoint - 417 1 e 1 fn_ctrl_swap -@@ -72,6 +73,8 @@ enumerations - 13 0 Disable - 13 1 AC and battery - 13 2 AC only -+14 0 Disable -+14 1 Enable - - # ----------------------------------------------------------------- - checksums -diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default -index 7ce38fb5d7..6049e7938a 100644 ---- a/src/mainboard/supermicro/x10slm-f/cmos.default -+++ b/src/mainboard/supermicro/x10slm-f/cmos.default -@@ -5,3 +5,4 @@ debug_level=Debug - nmi=Enable - power_on_after_fail=Keep - hide_ast2400=Disable -+iommu=Enable -diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout -index 38ba87aa45..24d39e97ee 100644 ---- a/src/mainboard/supermicro/x10slm-f/cmos.layout -+++ b/src/mainboard/supermicro/x10slm-f/cmos.layout -@@ -21,6 +21,9 @@ entries - 408 1 e 1 nmi - 409 2 e 5 power_on_after_fail - -+# enable or disable iommu -+412 1 e 6 iommu -+ - # coreboot config options: mainboard - 416 1 e 1 hide_ast2400 - -@@ -55,6 +58,9 @@ enumerations - 5 1 Enable - 5 2 Keep - -+6 0 Disable -+6 1 Enable -+ - # ----------------------------------------------------------------- - checksums - -diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c -index e47deb5da6..1a7e0b1076 100644 ---- a/src/northbridge/intel/haswell/early_init.c -+++ b/src/northbridge/intel/haswell/early_init.c -@@ -5,6 +5,7 @@ - #include - #include - #include -+#include - - #include "haswell.h" - -@@ -157,6 +158,10 @@ static void haswell_setup_misc(void) - static void haswell_setup_iommu(void) - { - const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); -+ u8 enable_iommu = get_uint_option("iommu", 1); -+ -+ if (!enable_iommu) -+ return; - - if (capid0_a & VTD_DISABLE) - return; --- -2.47.3 - diff --git a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch deleted file mode 100644 index 3e6b8085..00000000 --- a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 0f76a919522c9624c2b5df2a9c17525ab21bd6b9 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 2 Mar 2024 23:00:09 +0000 -Subject: [PATCH 12/48] dell/optiplex_9020: Disable IOMMU by default - -Needed to make graphics cards work. Turning it on is -recommended if only using iGPU, otherwise leave it off -by default. The IOMMU is extremely buggy when a graphics -card is used. Leaving it off by default will ensure that -the default ROM images in Libreboot will work on any setup. - -Signed-off-by: Leah Rowe ---- - src/mainboard/dell/optiplex_9020/cmos.default | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default -index 8000eea8c0..0700f971ee 100644 ---- a/src/mainboard/dell/optiplex_9020/cmos.default -+++ b/src/mainboard/dell/optiplex_9020/cmos.default -@@ -4,4 +4,4 @@ debug_level=Debug - nmi=Disable - power_on_after_fail=Disable - fan_full_speed=Disable --iommu=Enable -+iommu=Disable --- -2.47.3 - diff --git a/config/coreboot/default/patches/0012-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0012-nb-intel-haswell-make-IOMMU-a-runtime-option.patch new file mode 100644 index 00000000..883590fc --- /dev/null +++ b/config/coreboot/default/patches/0012-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -0,0 +1,293 @@ +From 0d418d44f61dda7670cfe02226150c2e5d3d6308 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 2 Mar 2024 22:51:09 +0000 +Subject: [PATCH 12/51] nb/intel/haswell: make IOMMU a runtime option + +When I tested graphics cards on a coreboot port for Dell +OptiPlex 9020 SFF, I could not use a graphics card unless +I set iommu=off on the Linux cmdline. + +Coreboot's current behaviour is to check whether the CPU +has vt-d support and, if it does, initialise the IOMMU. + +This patch maintains the current behaviour by default, but +allows the user to turn *off* the IOMMU, even if vt-d is +supported by the host CPU. + +If iommu=Disable is specified, the check will not be +performed, and the IOMMU will be left disabled. This option +has been added to all current Haswell boards, though it is +recommended to leave the IOMMU turned on in most setups. + +Signed-off-by: Leah Rowe +--- + src/mainboard/asrock/b85m_pro4/cmos.default | 1 + + src/mainboard/asrock/b85m_pro4/cmos.layout | 3 +++ + src/mainboard/asrock/h81m-hds/cmos.default | 1 + + src/mainboard/asrock/h81m-hds/cmos.layout | 6 ++++++ + src/mainboard/dell/optiplex_9020/cmos.default | 1 + + src/mainboard/dell/optiplex_9020/cmos.layout | 6 ++++++ + src/mainboard/google/beltino/cmos.layout | 5 +++++ + src/mainboard/google/slippy/cmos.layout | 5 +++++ + src/mainboard/intel/baskingridge/cmos.layout | 4 ++++ + src/mainboard/lenovo/haswell/cmos.default | 1 + + src/mainboard/lenovo/haswell/cmos.layout | 3 +++ + src/mainboard/supermicro/x10slm-f/cmos.default | 1 + + src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++ + src/northbridge/intel/haswell/early_init.c | 6 ++++++ + 14 files changed, 49 insertions(+) + +diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default +index 01bf20ad16..dfc8b80fb0 100644 +--- a/src/mainboard/asrock/b85m_pro4/cmos.default ++++ b/src/mainboard/asrock/b85m_pro4/cmos.default +@@ -4,3 +4,4 @@ boot_option=Fallback + debug_level=Debug + nmi=Enable + power_on_after_fail=Disable ++iommu=Enable +diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout +index efdc333fc2..c9883ea71d 100644 +--- a/src/mainboard/asrock/b85m_pro4/cmos.layout ++++ b/src/mainboard/asrock/b85m_pro4/cmos.layout +@@ -11,6 +11,7 @@ + 395 4 e 4 debug_level + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail ++ 412 1 e 6 iommu + 984 16 h 0 check_sum + # ----------------------------------------------------------------- + +@@ -38,6 +39,8 @@ + 5 0 Disable + 5 1 Enable + 5 2 Keep ++ 6 0 Disable ++ 6 1 Enable + # ----------------------------------------------------------------- + + # ----------------------------------------------------------------- +diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default +index 01bf20ad16..dfc8b80fb0 100644 +--- a/src/mainboard/asrock/h81m-hds/cmos.default ++++ b/src/mainboard/asrock/h81m-hds/cmos.default +@@ -4,3 +4,4 @@ boot_option=Fallback + debug_level=Debug + nmi=Enable + power_on_after_fail=Disable ++iommu=Enable +diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout +index c9ba76c78f..95ee3d36fb 100644 +--- a/src/mainboard/asrock/h81m-hds/cmos.layout ++++ b/src/mainboard/asrock/h81m-hds/cmos.layout +@@ -21,6 +21,9 @@ entries + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail + ++# enable or disable iommu ++412 1 e 6 iommu ++ + # coreboot config options: check sums + 984 16 h 0 check_sum + +@@ -52,6 +55,9 @@ enumerations + 5 1 Enable + 5 2 Keep + ++6 0 Disable ++6 1 Enable ++ + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default +index 6c4a2a1be7..8000eea8c0 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.default ++++ b/src/mainboard/dell/optiplex_9020/cmos.default +@@ -4,3 +4,4 @@ debug_level=Debug + nmi=Disable + power_on_after_fail=Disable + fan_full_speed=Disable ++iommu=Enable +diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout +index d10ad95b23..4a1496a878 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.layout ++++ b/src/mainboard/dell/optiplex_9020/cmos.layout +@@ -21,6 +21,9 @@ entries + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail + ++# turn iommu on or off ++411 1 e 6 iommu ++ + # coreboot config options: EC + 412 1 e 1 fan_full_speed + +@@ -55,6 +58,9 @@ enumerations + 5 1 Enable + 5 2 Keep + ++6 0 Disable ++6 1 Enable ++ + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout +index 78d44c1415..c143979ae1 100644 +--- a/src/mainboard/google/beltino/cmos.layout ++++ b/src/mainboard/google/beltino/cmos.layout +@@ -19,6 +19,9 @@ entries + 408 1 e 1 nmi + 409 2 e 7 power_on_after_fail + ++# enable or disable iommu ++412 1 e 8 iommu ++ + # coreboot config options: bootloader + #Used by ChromeOS: + 416 128 r 0 vbnv +@@ -47,6 +50,8 @@ enumerations + 7 0 Disable + 7 1 Enable + 7 2 Keep ++8 0 Disable ++8 1 Enable + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout +index 78d44c1415..c143979ae1 100644 +--- a/src/mainboard/google/slippy/cmos.layout ++++ b/src/mainboard/google/slippy/cmos.layout +@@ -19,6 +19,9 @@ entries + 408 1 e 1 nmi + 409 2 e 7 power_on_after_fail + ++# enable or disable iommu ++412 1 e 8 iommu ++ + # coreboot config options: bootloader + #Used by ChromeOS: + 416 128 r 0 vbnv +@@ -47,6 +50,8 @@ enumerations + 7 0 Disable + 7 1 Enable + 7 2 Keep ++8 0 Disable ++8 1 Enable + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout +index 78d44c1415..f2c602f541 100644 +--- a/src/mainboard/intel/baskingridge/cmos.layout ++++ b/src/mainboard/intel/baskingridge/cmos.layout +@@ -19,6 +19,8 @@ entries + 408 1 e 1 nmi + 409 2 e 7 power_on_after_fail + ++412 1 e 8 iommu ++ + # coreboot config options: bootloader + #Used by ChromeOS: + 416 128 r 0 vbnv +@@ -47,6 +49,8 @@ enumerations + 7 0 Disable + 7 1 Enable + 7 2 Keep ++8 0 Disable ++8 1 Enable + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default +index 08db97c5a9..cc6b363cd9 100644 +--- a/src/mainboard/lenovo/haswell/cmos.default ++++ b/src/mainboard/lenovo/haswell/cmos.default +@@ -14,3 +14,4 @@ trackpoint=Enable + backlight=Keyboard + enable_dual_graphics=Disable + usb_always_on=Disable ++iommu=Enable +diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout +index 27915d3ab7..59df76b64c 100644 +--- a/src/mainboard/lenovo/haswell/cmos.layout ++++ b/src/mainboard/lenovo/haswell/cmos.layout +@@ -23,6 +23,7 @@ entries + + # coreboot config options: EC + 411 1 e 8 first_battery ++413 1 e 14 iommu + 415 1 e 1 wlan + 416 1 e 1 trackpoint + 417 1 e 1 fn_ctrl_swap +@@ -72,6 +73,8 @@ enumerations + 13 0 Disable + 13 1 AC and battery + 13 2 AC only ++14 0 Disable ++14 1 Enable + + # ----------------------------------------------------------------- + checksums +diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default +index 7ce38fb5d7..6049e7938a 100644 +--- a/src/mainboard/supermicro/x10slm-f/cmos.default ++++ b/src/mainboard/supermicro/x10slm-f/cmos.default +@@ -5,3 +5,4 @@ debug_level=Debug + nmi=Enable + power_on_after_fail=Keep + hide_ast2400=Disable ++iommu=Enable +diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout +index 38ba87aa45..24d39e97ee 100644 +--- a/src/mainboard/supermicro/x10slm-f/cmos.layout ++++ b/src/mainboard/supermicro/x10slm-f/cmos.layout +@@ -21,6 +21,9 @@ entries + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail + ++# enable or disable iommu ++412 1 e 6 iommu ++ + # coreboot config options: mainboard + 416 1 e 1 hide_ast2400 + +@@ -55,6 +58,9 @@ enumerations + 5 1 Enable + 5 2 Keep + ++6 0 Disable ++6 1 Enable ++ + # ----------------------------------------------------------------- + checksums + +diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c +index 6a5ce53a40..5f07fa0b17 100644 +--- a/src/northbridge/intel/haswell/early_init.c ++++ b/src/northbridge/intel/haswell/early_init.c +@@ -6,6 +6,7 @@ + #include + #include + #include ++#include + + #include "haswell.h" + +@@ -80,6 +81,11 @@ static void haswell_setup_misc(void) + static void northbridge_setup_iommu(void) + { + const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); ++ u8 enable_iommu = get_uint_option("iommu", 1); ++ ++ if (!enable_iommu) ++ return; ++ + if (capid0_a & VTD_DISABLE) + return; + +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0013-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0013-dell-optiplex_9020-Disable-IOMMU-by-default.patch new file mode 100644 index 00000000..a5eb5de2 --- /dev/null +++ b/config/coreboot/default/patches/0013-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -0,0 +1,29 @@ +From 2bd978a08ffee969bbf61af8f145b9e6b050d321 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 2 Mar 2024 23:00:09 +0000 +Subject: [PATCH 13/51] dell/optiplex_9020: Disable IOMMU by default + +Needed to make graphics cards work. Turning it on is +recommended if only using iGPU, otherwise leave it off +by default. The IOMMU is extremely buggy when a graphics +card is used. Leaving it off by default will ensure that +the default ROM images in Libreboot will work on any setup. + +Signed-off-by: Leah Rowe +--- + src/mainboard/dell/optiplex_9020/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default +index 8000eea8c0..0700f971ee 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.default ++++ b/src/mainboard/dell/optiplex_9020/cmos.default +@@ -4,4 +4,4 @@ debug_level=Debug + nmi=Disable + power_on_after_fail=Disable + fan_full_speed=Disable +-iommu=Enable ++iommu=Disable +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch deleted file mode 100644 index 56b61882..00000000 --- a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch +++ /dev/null @@ -1,51 +0,0 @@ -From df64f2825157226b98e002e746114e25b0047438 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 6 Apr 2024 01:22:47 +0100 -Subject: [PATCH 13/48] nb/haswell: Fully disable iGPU when dGPU is used - -My earlier patch disabled decode *and* disabled the iGPU itself, but -a subsequent revision disabled only VGA decode. Upon revisiting, I -found that, actually, yes, you also need to disable the iGPU entirely. - -Tested on Dell 9020 SFF using broadwell MRC, with both iGPU and dGPU. -With this patch, the iGPU is completely disabled when you install a -graphics card, but the iGPU is available to use when no graphics card -is present. - -For more context, see: - -Author: Leah Rowe -Date: Fri Feb 23 13:33:31 2024 +0000 - - nb/haswell: Disable iGPU when dGPU is used - -And look at the Gerrit comments: - -https://review.coreboot.org/c/coreboot/+/80717/ - -So, my original submission on change 80717 was actually correct. -This patch fixes the issue. I tested on iGPU and dGPU, with both -broadwell and haswell mrc.bin. - -Signed-off-by: Leah Rowe ---- - src/northbridge/intel/haswell/gma.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c -index f7fad3183d..1b188e92e1 100644 ---- a/src/northbridge/intel/haswell/gma.c -+++ b/src/northbridge/intel/haswell/gma.c -@@ -466,6 +466,9 @@ static void gma_func0_disable(struct device *dev) - { - /* Disable VGA decode */ - pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1); -+ -+ /* Required or else the graphics card doesn't work */ -+ dev->enabled = 0; - } - - static struct device_operations gma_func0_ops = { --- -2.47.3 - diff --git a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch deleted file mode 100644 index 722e895d..00000000 --- a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch +++ /dev/null @@ -1,147 +0,0 @@ -From fdf4774a6e80b1f94079abb346049113dfbf5241 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Fri, 3 May 2024 11:03:32 -0600 -Subject: [PATCH 14/48] ec/dell/mec5035: Add S3 suspend SMI handler - -This is necessary for S3 resume to work on SNB and newer Dell Latitude -laptops. If a command isn't sent, the EC cuts power to the DIMMs, -preventing the system from resuming. These commands were found using an -FPGA to log all LPC bus transactions between the host and the EC and -then narrowing down which ones were actually necessary. - -Interestingly, the command IDs appear to be identical to those in -ec/google/wilco, the EC used on Dell Latitude Chromebooks, and that EC -implements a similar S3 SMI handler as the one implemented in this -commit. The Wilco EC Kconfig does suggest that its firmware is a -modified version of Dell's usual Latitude EC firmware, so the -similarities seem to be intentional. - -These similarities also identified a command to enable or disable wake -sources like the power button and lid switch, and this was added to the -SMI handler to disable lid wake as the system does not yet resume -properly from a like wake with coreboot. - -Tested on the Latitude E6430 (Ivy Bridge) and the Precision M6800 -(Haswell, not yet pushed). - -Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070 -Signed-off-by: Nicholas Chin ---- - src/ec/dell/mec5035/Makefile.mk | 1 + - src/ec/dell/mec5035/mec5035.c | 13 +++++++++++++ - src/ec/dell/mec5035/mec5035.h | 22 ++++++++++++++++++++++ - src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++ - 4 files changed, 53 insertions(+) - create mode 100644 src/ec/dell/mec5035/smihandler.c - -diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk -index 4ebdd811f9..be557e4599 100644 ---- a/src/ec/dell/mec5035/Makefile.mk -+++ b/src/ec/dell/mec5035/Makefile.mk -@@ -5,5 +5,6 @@ ifeq ($(CONFIG_EC_DELL_MEC5035),y) - bootblock-y += mec5035.c - romstage-y += mec5035.c - ramstage-y += mec5035.c -+smm-y += mec5035.c smihandler.c - - endif -diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index 17ac2c1dab..c5067c16f6 100644 ---- a/src/ec/dell/mec5035/mec5035.c -+++ b/src/ec/dell/mec5035/mec5035.c -@@ -100,6 +100,19 @@ static void mec5035_power_button_route(enum ec_power_button_route target) - write_mailbox_regs(&buf, 2, 1); - ec_command(CMD_POWER_BUTTON_TO_HOST); - } -+void mec5035_change_wake(u8 source, enum ec_wake_change change) -+{ -+ u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40}; -+ write_mailbox_regs(buf, 2, ACPI_WAKEUP_NUM_ARGS); -+ ec_command(CMD_ACPI_WAKEUP_CHANGE); -+} -+ -+void mec5035_sleep_enable(void) -+{ -+ u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0}; -+ write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS); -+ ec_command(CMD_SLEEP_ENABLE); -+} - - void mec5035_early_init(void) - { -diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h -index 5fdf56631b..5cd907bf71 100644 ---- a/src/ec/dell/mec5035/mec5035.h -+++ b/src/ec/dell/mec5035/mec5035.h -@@ -4,6 +4,7 @@ - #define _EC_DELL_MEC5035_H_ - - #include -+#include - - #define NUM_REGISTERS 32 - -@@ -11,6 +12,8 @@ enum mec5035_cmd { - CMD_MOUSE_TP = 0x1a, - CMD_RADIO_CTRL = 0x2b, - CMD_POWER_BUTTON_TO_HOST = 0x3e, -+ CMD_ACPI_WAKEUP_CHANGE = 0x4a, -+ CMD_SLEEP_ENABLE = 0x64, - CMD_CPU_OK = 0xc2, - }; - -@@ -39,9 +42,28 @@ enum ec_power_button_route { - HOST - }; - -+#define ACPI_WAKEUP_NUM_ARGS 4 -+enum ec_wake_change { -+ WAKE_OFF = 0, -+ WAKE_ON -+}; -+ -+/* Copied from ec/google/wilco/commands.h. Not sure if these all apply */ -+enum ec_acpi_wake_events { -+ EC_ACPI_WAKE_PWRB = BIT(0), /* Wake up by power button */ -+ EC_ACPI_WAKE_LID = BIT(1), /* Wake up by lid switch */ -+ EC_ACPI_WAKE_RTC = BIT(5), /* Wake up by RTC */ -+}; -+ -+#define SLEEP_EN_NUM_ARGS 2 -+ - u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting); - void mec5035_cpu_ok(void); - void mec5035_early_init(void); - void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state); -+void mec5035_change_wake(u8 source, enum ec_wake_change change); -+void mec5035_sleep_enable(void); -+ -+void mec5035_smi_sleep(int slp_type); - - #endif /* _EC_DELL_MEC5035_H_ */ -diff --git a/src/ec/dell/mec5035/smihandler.c b/src/ec/dell/mec5035/smihandler.c -new file mode 100644 -index 0000000000..958733bf97 ---- /dev/null -+++ b/src/ec/dell/mec5035/smihandler.c -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include "mec5035.h" -+ -+void mec5035_smi_sleep(int slp_type) -+{ -+ switch (slp_type) { -+ case ACPI_S3: -+ /* System does not yet resume properly if woken by lid */ -+ mec5035_change_wake(EC_ACPI_WAKE_LID, WAKE_OFF); -+ mec5035_sleep_enable(); -+ break; -+ } -+} --- -2.47.3 - diff --git a/config/coreboot/default/patches/0014-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0014-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch new file mode 100644 index 00000000..aa5483c8 --- /dev/null +++ b/config/coreboot/default/patches/0014-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -0,0 +1,51 @@ +From 1179f45055fffb383fffe806e313a315de7c4205 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 6 Apr 2024 01:22:47 +0100 +Subject: [PATCH 14/51] nb/haswell: Fully disable iGPU when dGPU is used + +My earlier patch disabled decode *and* disabled the iGPU itself, but +a subsequent revision disabled only VGA decode. Upon revisiting, I +found that, actually, yes, you also need to disable the iGPU entirely. + +Tested on Dell 9020 SFF using broadwell MRC, with both iGPU and dGPU. +With this patch, the iGPU is completely disabled when you install a +graphics card, but the iGPU is available to use when no graphics card +is present. + +For more context, see: + +Author: Leah Rowe +Date: Fri Feb 23 13:33:31 2024 +0000 + + nb/haswell: Disable iGPU when dGPU is used + +And look at the Gerrit comments: + +https://review.coreboot.org/c/coreboot/+/80717/ + +So, my original submission on change 80717 was actually correct. +This patch fixes the issue. I tested on iGPU and dGPU, with both +broadwell and haswell mrc.bin. + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/haswell/gma.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c +index fc44a98a57..451147d082 100644 +--- a/src/northbridge/intel/haswell/gma.c ++++ b/src/northbridge/intel/haswell/gma.c +@@ -655,6 +655,9 @@ static void gma_func0_disable(struct device *dev) + { + /* Disable VGA decode */ + pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1); ++ ++ /* Required or else the graphics card doesn't work */ ++ dev->enabled = 0; + } + + static struct device_operations gma_func0_ops = { +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0015-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0015-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch new file mode 100644 index 00000000..7cadcb56 --- /dev/null +++ b/config/coreboot/default/patches/0015-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch @@ -0,0 +1,147 @@ +From 59b741bf1b74a2c4e108755fbfd1580894c7d783 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Fri, 3 May 2024 11:03:32 -0600 +Subject: [PATCH 15/51] ec/dell/mec5035: Add S3 suspend SMI handler + +This is necessary for S3 resume to work on SNB and newer Dell Latitude +laptops. If a command isn't sent, the EC cuts power to the DIMMs, +preventing the system from resuming. These commands were found using an +FPGA to log all LPC bus transactions between the host and the EC and +then narrowing down which ones were actually necessary. + +Interestingly, the command IDs appear to be identical to those in +ec/google/wilco, the EC used on Dell Latitude Chromebooks, and that EC +implements a similar S3 SMI handler as the one implemented in this +commit. The Wilco EC Kconfig does suggest that its firmware is a +modified version of Dell's usual Latitude EC firmware, so the +similarities seem to be intentional. + +These similarities also identified a command to enable or disable wake +sources like the power button and lid switch, and this was added to the +SMI handler to disable lid wake as the system does not yet resume +properly from a like wake with coreboot. + +Tested on the Latitude E6430 (Ivy Bridge) and the Precision M6800 +(Haswell, not yet pushed). + +Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070 +Signed-off-by: Nicholas Chin +--- + src/ec/dell/mec5035/Makefile.mk | 1 + + src/ec/dell/mec5035/mec5035.c | 13 +++++++++++++ + src/ec/dell/mec5035/mec5035.h | 22 ++++++++++++++++++++++ + src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++ + 4 files changed, 53 insertions(+) + create mode 100644 src/ec/dell/mec5035/smihandler.c + +diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk +index 4ebdd811f9..be557e4599 100644 +--- a/src/ec/dell/mec5035/Makefile.mk ++++ b/src/ec/dell/mec5035/Makefile.mk +@@ -5,5 +5,6 @@ ifeq ($(CONFIG_EC_DELL_MEC5035),y) + bootblock-y += mec5035.c + romstage-y += mec5035.c + ramstage-y += mec5035.c ++smm-y += mec5035.c smihandler.c + + endif +diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c +index 17ac2c1dab..c5067c16f6 100644 +--- a/src/ec/dell/mec5035/mec5035.c ++++ b/src/ec/dell/mec5035/mec5035.c +@@ -100,6 +100,19 @@ static void mec5035_power_button_route(enum ec_power_button_route target) + write_mailbox_regs(&buf, 2, 1); + ec_command(CMD_POWER_BUTTON_TO_HOST); + } ++void mec5035_change_wake(u8 source, enum ec_wake_change change) ++{ ++ u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40}; ++ write_mailbox_regs(buf, 2, ACPI_WAKEUP_NUM_ARGS); ++ ec_command(CMD_ACPI_WAKEUP_CHANGE); ++} ++ ++void mec5035_sleep_enable(void) ++{ ++ u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0}; ++ write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS); ++ ec_command(CMD_SLEEP_ENABLE); ++} + + void mec5035_early_init(void) + { +diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h +index 5fdf56631b..5cd907bf71 100644 +--- a/src/ec/dell/mec5035/mec5035.h ++++ b/src/ec/dell/mec5035/mec5035.h +@@ -4,6 +4,7 @@ + #define _EC_DELL_MEC5035_H_ + + #include ++#include + + #define NUM_REGISTERS 32 + +@@ -11,6 +12,8 @@ enum mec5035_cmd { + CMD_MOUSE_TP = 0x1a, + CMD_RADIO_CTRL = 0x2b, + CMD_POWER_BUTTON_TO_HOST = 0x3e, ++ CMD_ACPI_WAKEUP_CHANGE = 0x4a, ++ CMD_SLEEP_ENABLE = 0x64, + CMD_CPU_OK = 0xc2, + }; + +@@ -39,9 +42,28 @@ enum ec_power_button_route { + HOST + }; + ++#define ACPI_WAKEUP_NUM_ARGS 4 ++enum ec_wake_change { ++ WAKE_OFF = 0, ++ WAKE_ON ++}; ++ ++/* Copied from ec/google/wilco/commands.h. Not sure if these all apply */ ++enum ec_acpi_wake_events { ++ EC_ACPI_WAKE_PWRB = BIT(0), /* Wake up by power button */ ++ EC_ACPI_WAKE_LID = BIT(1), /* Wake up by lid switch */ ++ EC_ACPI_WAKE_RTC = BIT(5), /* Wake up by RTC */ ++}; ++ ++#define SLEEP_EN_NUM_ARGS 2 ++ + u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting); + void mec5035_cpu_ok(void); + void mec5035_early_init(void); + void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state); ++void mec5035_change_wake(u8 source, enum ec_wake_change change); ++void mec5035_sleep_enable(void); ++ ++void mec5035_smi_sleep(int slp_type); + + #endif /* _EC_DELL_MEC5035_H_ */ +diff --git a/src/ec/dell/mec5035/smihandler.c b/src/ec/dell/mec5035/smihandler.c +new file mode 100644 +index 0000000000..958733bf97 +--- /dev/null ++++ b/src/ec/dell/mec5035/smihandler.c +@@ -0,0 +1,17 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include "mec5035.h" ++ ++void mec5035_smi_sleep(int slp_type) ++{ ++ switch (slp_type) { ++ case ACPI_S3: ++ /* System does not yet resume properly if woken by lid */ ++ mec5035_change_wake(EC_ACPI_WAKE_LID, WAKE_OFF); ++ mec5035_sleep_enable(); ++ break; ++ } ++} +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch deleted file mode 100644 index ac672295..00000000 --- a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 18216387e5c40ec3c80c63ec25e9b0c55a009cff Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 4 May 2024 02:00:53 +0100 -Subject: [PATCH 15/48] nb/haswell: lock policy regs when disabling IOMMU - -Angel Pons told me I should do it. See comments here: -https://review.coreboot.org/c/coreboot/+/81016 - -I see no harm in complying with the request. I'll merge -this into the main patch at a later date and try to -get this upstreamed. - -Just a reminder: on Optiplex 9020 variants, Xorg locks up -under Linux when tested with a graphics card; disabling -IOMMU works around the issue. Intel graphics work just fine -with IOMMU turned on. Libreboot disables IOMMU by default, -on the 9020, so that users can install graphics cards easily. - -Signed-off-by: Leah Rowe ---- - src/northbridge/intel/haswell/early_init.c | 15 +++++++-------- - 1 file changed, 7 insertions(+), 8 deletions(-) - -diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c -index 1a7e0b1076..e9506ee830 100644 ---- a/src/northbridge/intel/haswell/early_init.c -+++ b/src/northbridge/intel/haswell/early_init.c -@@ -160,17 +160,16 @@ static void haswell_setup_iommu(void) - const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); - u8 enable_iommu = get_uint_option("iommu", 1); - -- if (!enable_iommu) -- return; -- - if (capid0_a & VTD_DISABLE) - return; - -- /* Setup BARs: zeroize top 32 bits; set enable bit */ -- mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); -- mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); -- mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); -- mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); -+ if (enable_iommu) { -+ /* Setup BARs: zeroize top 32 bits; set enable bit */ -+ mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); -+ mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); -+ mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); -+ mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); -+ } - - /* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */ - u32 reg32; --- -2.47.3 - diff --git a/config/coreboot/default/patches/0016-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0016-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch new file mode 100644 index 00000000..17cfdac2 --- /dev/null +++ b/config/coreboot/default/patches/0016-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch @@ -0,0 +1,54 @@ +From 3c1416797f2deafbd6b56774d890706aaea3614f Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 4 May 2024 02:00:53 +0100 +Subject: [PATCH 16/51] nb/haswell: lock policy regs when disabling IOMMU + +Angel Pons told me I should do it. See comments here: +https://review.coreboot.org/c/coreboot/+/81016 + +I see no harm in complying with the request. I'll merge +this into the main patch at a later date and try to +get this upstreamed. + +Just a reminder: on Optiplex 9020 variants, Xorg locks up +under Linux when tested with a graphics card; disabling +IOMMU works around the issue. Intel graphics work just fine +with IOMMU turned on. Libreboot disables IOMMU by default, +on the 9020, so that users can install graphics cards easily. + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/haswell/early_init.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) + +diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c +index 5f07fa0b17..30660e3903 100644 +--- a/src/northbridge/intel/haswell/early_init.c ++++ b/src/northbridge/intel/haswell/early_init.c +@@ -86,15 +86,17 @@ static void northbridge_setup_iommu(void) + if (!enable_iommu) + return; + ++ if (enable_iommu) { ++ /* Setup BARs: zeroize top 32 bits; set enable bit */ ++ mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); ++ mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); ++ mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); ++ mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); ++ } ++ + if (capid0_a & VTD_DISABLE) + return; + +- /* Setup BARs: zeroize top 32 bits; set enable bit */ +- mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); +- mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); +- mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); +- mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); +- + if (cpu_is_haswell()) { + /* + * Intel Document 492662 (Haswell System Agent BIOS Spec), Rev 1.6.0 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch deleted file mode 100644 index e7c8d0a9..00000000 --- a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch +++ /dev/null @@ -1,223 +0,0 @@ -From d797b9d19c6bc3224897000756caef29e98dd266 Mon Sep 17 00:00:00 2001 -From: Angel Pons -Date: Mon, 10 May 2021 22:40:59 +0200 -Subject: [PATCH 16/48] nb/intel/gm45: Make DDR2 raminit work - -List of changes: - - Update some timing and ODT values - - Patch RCOMP calibration to better match what MRC binaries do - - Replay a hardcoded list of RCOMP codes after RcvEn - -This makes raminit work at DDR2-800 speeds and fixes S3 resume as well. -Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs. - -Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c -Signed-off-by: Angel Pons ---- - src/northbridge/intel/gm45/gm45.h | 2 +- - src/northbridge/intel/gm45/raminit.c | 90 +++++++++++++++++-- - .../intel/gm45/raminit_rcomp_calibration.c | 27 ++++-- - 3 files changed, 106 insertions(+), 13 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h -index f68bfdee7a..b76117bc3a 100644 ---- a/src/northbridge/intel/gm45/gm45.h -+++ b/src/northbridge/intel/gm45/gm45.h -@@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo); - int raminit_read_vco_index(void); - u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank); - --void raminit_rcomp_calibration(stepping_t stepping); -+void raminit_rcomp_calibration(int ddr_type, stepping_t stepping); - void raminit_reset_readwrite_pointers(void); - void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *); - void raminit_write_training(const mem_clock_t, const dimminfo_t *, bool s3resume); -diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c -index def9e1e331..7b091cc567 100644 ---- a/src/northbridge/intel/gm45/raminit.c -+++ b/src/northbridge/intel/gm45/raminit.c -@@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping, - } - - /* Perform RCOMP calibration for DDR3. */ -- raminit_rcomp_calibration(stepping); -+ raminit_rcomp_calibration(spd_type, stepping); - - /* Run initial RCOMP. */ - mchbar_setbits32(0x418, 1 << 17); -@@ -1117,7 +1117,7 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi - reg = (reg & ~(0xf << 10)) | (2 << 10); - else - reg = (reg & ~(0xf << 10)) | (3 << 10); -- reg = (reg & ~(0x7 << 5)) | (3 << 5); -+ reg = (reg & ~(0x7 << 5)) | (2 << 5); - } else if (timings->mem_clock != MEM_CLOCK_1067MT) { - reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); - reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); -@@ -1286,11 +1286,11 @@ static void ddr2_odt_setup(const timings_t *const timings, const int sff) - reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32)); - reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32)); - if (timings->mem_clock == MEM_CLOCK_667MT) { -- reg = (reg & ~(0xf << (36 - 32))) | (4 << (36 - 32)); -- reg = (reg & ~(0xf << (32 - 32))) | (4 << (32 - 32)); -+ reg = (reg & ~(0xf << (36 - 32))) | (8 << (36 - 32)); -+ reg = (reg & ~(0xf << (32 - 32))) | (8 << (32 - 32)); - } else { -- reg = (reg & ~(0xf << (36 - 32))) | (5 << (36 - 32)); -- reg = (reg & ~(0xf << (32 - 32))) | (5 << (32 - 32)); -+ reg = (reg & ~(0xf << (36 - 32))) | (9 << (36 - 32)); -+ reg = (reg & ~(0xf << (32 - 32))) | (9 << (32 - 32)); - } - mchbar_write32(CxODT_HIGH(ch), reg); - -@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume) - raminit_write_training(timings->mem_clock, dimms, s3resume); - } - -+ /* -+ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done -+ * after receiver enable calibration, otherwise raminit sometimes -+ * completes with non-working memory. -+ */ -+ mchbar_write32(0x0530, 0x06060005); -+ mchbar_write32(0x0680, 0x06060606); -+ mchbar_write32(0x0684, 0x08070606); -+ mchbar_write32(0x0688, 0x0e0e0c0a); -+ mchbar_write32(0x068c, 0x0e0e0e0e); -+ mchbar_write32(0x0698, 0x06060606); -+ mchbar_write32(0x069c, 0x08070606); -+ mchbar_write32(0x06a0, 0x0c0c0b0a); -+ mchbar_write32(0x06a4, 0x0c0c0c0c); -+ -+ mchbar_write32(0x06c0, 0x02020202); -+ mchbar_write32(0x06c4, 0x03020202); -+ mchbar_write32(0x06c8, 0x04040403); -+ mchbar_write32(0x06cc, 0x04040404); -+ mchbar_write32(0x06d8, 0x02020202); -+ mchbar_write32(0x06dc, 0x03020202); -+ mchbar_write32(0x06e0, 0x04040403); -+ mchbar_write32(0x06e4, 0x04040404); -+ -+ mchbar_write32(0x0700, 0x02020202); -+ mchbar_write32(0x0704, 0x03020202); -+ mchbar_write32(0x0708, 0x04040403); -+ mchbar_write32(0x070c, 0x04040404); -+ mchbar_write32(0x0718, 0x02020202); -+ mchbar_write32(0x071c, 0x03020202); -+ mchbar_write32(0x0720, 0x04040403); -+ mchbar_write32(0x0724, 0x04040404); -+ -+ mchbar_write32(0x0740, 0x02020202); -+ mchbar_write32(0x0744, 0x03020202); -+ mchbar_write32(0x0748, 0x04040403); -+ mchbar_write32(0x074c, 0x04040404); -+ mchbar_write32(0x0758, 0x02020202); -+ mchbar_write32(0x075c, 0x03020202); -+ mchbar_write32(0x0760, 0x04040403); -+ mchbar_write32(0x0764, 0x04040404); -+ -+ mchbar_write32(0x0780, 0x06060606); -+ mchbar_write32(0x0784, 0x09070606); -+ mchbar_write32(0x0788, 0x0e0e0c0b); -+ mchbar_write32(0x078c, 0x0e0e0e0e); -+ mchbar_write32(0x0798, 0x06060606); -+ mchbar_write32(0x079c, 0x09070606); -+ mchbar_write32(0x07a0, 0x0d0d0c0b); -+ mchbar_write32(0x07a4, 0x0d0d0d0d); -+ -+ mchbar_write32(0x07c0, 0x06060606); -+ mchbar_write32(0x07c4, 0x09070606); -+ mchbar_write32(0x07c8, 0x0e0e0c0b); -+ mchbar_write32(0x07cc, 0x0e0e0e0e); -+ mchbar_write32(0x07d8, 0x06060606); -+ mchbar_write32(0x07dc, 0x09070606); -+ mchbar_write32(0x07e0, 0x0d0d0c0b); -+ mchbar_write32(0x07e4, 0x0d0d0d0d); -+ -+ mchbar_write32(0x0840, 0x06060606); -+ mchbar_write32(0x0844, 0x08070606); -+ mchbar_write32(0x0848, 0x0e0e0c0a); -+ mchbar_write32(0x084c, 0x0e0e0e0e); -+ mchbar_write32(0x0858, 0x06060606); -+ mchbar_write32(0x085c, 0x08070606); -+ mchbar_write32(0x0860, 0x0c0c0b0a); -+ mchbar_write32(0x0864, 0x0c0c0c0c); -+ -+ mchbar_write32(0x0880, 0x02020202); -+ mchbar_write32(0x0884, 0x03020202); -+ mchbar_write32(0x0888, 0x04040403); -+ mchbar_write32(0x088c, 0x04040404); -+ mchbar_write32(0x0898, 0x02020202); -+ mchbar_write32(0x089c, 0x03020202); -+ mchbar_write32(0x08a0, 0x04040403); -+ mchbar_write32(0x08a4, 0x04040404); -+ - igd_compute_ggc(sysinfo); - - /* Program final memory map (with real values). */ -diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -index aef863f05a..b74765fd9c 100644 ---- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -@@ -161,11 +161,13 @@ static void lookup_and_write(const int a1step, - mchbar += 4; - } - } --void raminit_rcomp_calibration(const stepping_t stepping) { -+void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { - const int a1step = stepping >= STEPPING_CONVERSION_A1; - - int i; - -+ char magic_comp[2] = {0}; -+ - enum { - PULL_UP = 0, - PULL_DOWN = 1, -@@ -196,6 +198,10 @@ void raminit_rcomp_calibration(const stepping_t stepping) { - reg = mchbar_read32(0x518); - lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f; - lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f; -+ if (i == 1) { -+ magic_comp[0] = (reg >> 8) & 0x3f; -+ magic_comp[1] = (reg >> 0) & 0x3f; -+ } - } - /* Cleanup? */ - mchbar_setbits32(0x400, 1 << 3); -@@ -216,13 +222,19 @@ void raminit_rcomp_calibration(const stepping_t stepping) { - for (channel = 0; channel < 2; ++channel) { - for (group = 0; group < 6; ++group) { - for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) { -- lookup_and_write( -- a1step, -- lut_idx[channel][group][pu_pd] - 7, -- ddr3_lookup_schedule[group][pu_pd], -- mchbar); -+ if (ddr_type == DDR3) { -+ lookup_and_write( -+ a1step, -+ lut_idx[channel][group][pu_pd] - 7, -+ ddr3_lookup_schedule[group][pu_pd], -+ mchbar); -+ } - mchbar += 0x0018; - } -+ if (ddr_type == DDR2) { -+ mchbar_clrsetbits32(mchbar + 0, 0x7f << 24, lut_idx[channel][group][PULL_DOWN] << 24); -+ mchbar_clrsetbits32(mchbar + 4, 0x7f << 0, lut_idx[channel][group][PULL_UP] << 0); -+ } - mchbar += 0x0010; - /* Channel B knows only the first two groups. */ - if ((1 == channel) && (1 == group)) -@@ -230,4 +242,7 @@ void raminit_rcomp_calibration(const stepping_t stepping) { - } - mchbar += 0x0040; - } -+ -+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); -+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); - } --- -2.47.3 - diff --git a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch deleted file mode 100644 index 51ba3ae7..00000000 --- a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch +++ /dev/null @@ -1,240 +0,0 @@ -From e573065ac900d4decfd4dbd0a1464d82501ac3c5 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 6 Aug 2024 00:50:24 +0100 -Subject: [PATCH 17/48] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards - -We add this patch: - -commit commit_id_here -Author: Angel Pons -Date: Mon May 10 22:40:59 2021 +0200 - - nb/intel/gm45: Make DDR2 raminit work - -This patch was original applied, in lbmk, only on coreboot/dell, -separately from coreboot/default, which was wasteful because it -meant having an entire coreboot tree just for a single board. We -did this, because the DDR2 RCOMP fix happened to break DDR3 init -on other boards. - -What *this* new patch does on top of Angel's patch, is make sure -that their changes only apply to DDR2, while DDR3 behaviour remains -unchanged. This means that the Dell Latitude E6400 can be supported -in the main coreboot tree, within lbmk. - -Essentially, this patch restores the old behaviour, prior to applying -Angel's patch, only when DDR3 memory is used. - -Signed-off-by: Leah Rowe ---- - src/northbridge/intel/gm45/raminit.c | 161 +++++++++--------- - .../intel/gm45/raminit_rcomp_calibration.c | 9 +- - 2 files changed, 88 insertions(+), 82 deletions(-) - -diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c -index 7b091cc567..478898564a 100644 ---- a/src/northbridge/intel/gm45/raminit.c -+++ b/src/northbridge/intel/gm45/raminit.c -@@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi - reg = (reg & ~(0xf << 10)) | (2 << 10); - else - reg = (reg & ~(0xf << 10)) | (3 << 10); -- reg = (reg & ~(0x7 << 5)) | (2 << 5); -+ if (spd_type == DDR2) -+ reg = (reg & ~(0x7 << 5)) | (2 << 5); -+ else -+ reg = (reg & ~(0x7 << 5)) | (3 << 5); - } else if (timings->mem_clock != MEM_CLOCK_1067MT) { - reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); - reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); -@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume) - raminit_write_training(timings->mem_clock, dimms, s3resume); - } - -- /* -- * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done -- * after receiver enable calibration, otherwise raminit sometimes -- * completes with non-working memory. -- */ -- mchbar_write32(0x0530, 0x06060005); -- mchbar_write32(0x0680, 0x06060606); -- mchbar_write32(0x0684, 0x08070606); -- mchbar_write32(0x0688, 0x0e0e0c0a); -- mchbar_write32(0x068c, 0x0e0e0e0e); -- mchbar_write32(0x0698, 0x06060606); -- mchbar_write32(0x069c, 0x08070606); -- mchbar_write32(0x06a0, 0x0c0c0b0a); -- mchbar_write32(0x06a4, 0x0c0c0c0c); -- -- mchbar_write32(0x06c0, 0x02020202); -- mchbar_write32(0x06c4, 0x03020202); -- mchbar_write32(0x06c8, 0x04040403); -- mchbar_write32(0x06cc, 0x04040404); -- mchbar_write32(0x06d8, 0x02020202); -- mchbar_write32(0x06dc, 0x03020202); -- mchbar_write32(0x06e0, 0x04040403); -- mchbar_write32(0x06e4, 0x04040404); -- -- mchbar_write32(0x0700, 0x02020202); -- mchbar_write32(0x0704, 0x03020202); -- mchbar_write32(0x0708, 0x04040403); -- mchbar_write32(0x070c, 0x04040404); -- mchbar_write32(0x0718, 0x02020202); -- mchbar_write32(0x071c, 0x03020202); -- mchbar_write32(0x0720, 0x04040403); -- mchbar_write32(0x0724, 0x04040404); -- -- mchbar_write32(0x0740, 0x02020202); -- mchbar_write32(0x0744, 0x03020202); -- mchbar_write32(0x0748, 0x04040403); -- mchbar_write32(0x074c, 0x04040404); -- mchbar_write32(0x0758, 0x02020202); -- mchbar_write32(0x075c, 0x03020202); -- mchbar_write32(0x0760, 0x04040403); -- mchbar_write32(0x0764, 0x04040404); -- -- mchbar_write32(0x0780, 0x06060606); -- mchbar_write32(0x0784, 0x09070606); -- mchbar_write32(0x0788, 0x0e0e0c0b); -- mchbar_write32(0x078c, 0x0e0e0e0e); -- mchbar_write32(0x0798, 0x06060606); -- mchbar_write32(0x079c, 0x09070606); -- mchbar_write32(0x07a0, 0x0d0d0c0b); -- mchbar_write32(0x07a4, 0x0d0d0d0d); -- -- mchbar_write32(0x07c0, 0x06060606); -- mchbar_write32(0x07c4, 0x09070606); -- mchbar_write32(0x07c8, 0x0e0e0c0b); -- mchbar_write32(0x07cc, 0x0e0e0e0e); -- mchbar_write32(0x07d8, 0x06060606); -- mchbar_write32(0x07dc, 0x09070606); -- mchbar_write32(0x07e0, 0x0d0d0c0b); -- mchbar_write32(0x07e4, 0x0d0d0d0d); -- -- mchbar_write32(0x0840, 0x06060606); -- mchbar_write32(0x0844, 0x08070606); -- mchbar_write32(0x0848, 0x0e0e0c0a); -- mchbar_write32(0x084c, 0x0e0e0e0e); -- mchbar_write32(0x0858, 0x06060606); -- mchbar_write32(0x085c, 0x08070606); -- mchbar_write32(0x0860, 0x0c0c0b0a); -- mchbar_write32(0x0864, 0x0c0c0c0c); -- -- mchbar_write32(0x0880, 0x02020202); -- mchbar_write32(0x0884, 0x03020202); -- mchbar_write32(0x0888, 0x04040403); -- mchbar_write32(0x088c, 0x04040404); -- mchbar_write32(0x0898, 0x02020202); -- mchbar_write32(0x089c, 0x03020202); -- mchbar_write32(0x08a0, 0x04040403); -- mchbar_write32(0x08a4, 0x04040404); -+ if (sysinfo->spd_type == DDR2) { -+ /* -+ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done -+ * after receiver enable calibration, otherwise raminit sometimes -+ * completes with non-working memory. -+ */ -+ mchbar_write32(0x0530, 0x06060005); -+ mchbar_write32(0x0680, 0x06060606); -+ mchbar_write32(0x0684, 0x08070606); -+ mchbar_write32(0x0688, 0x0e0e0c0a); -+ mchbar_write32(0x068c, 0x0e0e0e0e); -+ mchbar_write32(0x0698, 0x06060606); -+ mchbar_write32(0x069c, 0x08070606); -+ mchbar_write32(0x06a0, 0x0c0c0b0a); -+ mchbar_write32(0x06a4, 0x0c0c0c0c); -+ -+ mchbar_write32(0x06c0, 0x02020202); -+ mchbar_write32(0x06c4, 0x03020202); -+ mchbar_write32(0x06c8, 0x04040403); -+ mchbar_write32(0x06cc, 0x04040404); -+ mchbar_write32(0x06d8, 0x02020202); -+ mchbar_write32(0x06dc, 0x03020202); -+ mchbar_write32(0x06e0, 0x04040403); -+ mchbar_write32(0x06e4, 0x04040404); -+ -+ mchbar_write32(0x0700, 0x02020202); -+ mchbar_write32(0x0704, 0x03020202); -+ mchbar_write32(0x0708, 0x04040403); -+ mchbar_write32(0x070c, 0x04040404); -+ mchbar_write32(0x0718, 0x02020202); -+ mchbar_write32(0x071c, 0x03020202); -+ mchbar_write32(0x0720, 0x04040403); -+ mchbar_write32(0x0724, 0x04040404); -+ -+ mchbar_write32(0x0740, 0x02020202); -+ mchbar_write32(0x0744, 0x03020202); -+ mchbar_write32(0x0748, 0x04040403); -+ mchbar_write32(0x074c, 0x04040404); -+ mchbar_write32(0x0758, 0x02020202); -+ mchbar_write32(0x075c, 0x03020202); -+ mchbar_write32(0x0760, 0x04040403); -+ mchbar_write32(0x0764, 0x04040404); -+ -+ mchbar_write32(0x0780, 0x06060606); -+ mchbar_write32(0x0784, 0x09070606); -+ mchbar_write32(0x0788, 0x0e0e0c0b); -+ mchbar_write32(0x078c, 0x0e0e0e0e); -+ mchbar_write32(0x0798, 0x06060606); -+ mchbar_write32(0x079c, 0x09070606); -+ mchbar_write32(0x07a0, 0x0d0d0c0b); -+ mchbar_write32(0x07a4, 0x0d0d0d0d); -+ -+ mchbar_write32(0x07c0, 0x06060606); -+ mchbar_write32(0x07c4, 0x09070606); -+ mchbar_write32(0x07c8, 0x0e0e0c0b); -+ mchbar_write32(0x07cc, 0x0e0e0e0e); -+ mchbar_write32(0x07d8, 0x06060606); -+ mchbar_write32(0x07dc, 0x09070606); -+ mchbar_write32(0x07e0, 0x0d0d0c0b); -+ mchbar_write32(0x07e4, 0x0d0d0d0d); -+ -+ mchbar_write32(0x0840, 0x06060606); -+ mchbar_write32(0x0844, 0x08070606); -+ mchbar_write32(0x0848, 0x0e0e0c0a); -+ mchbar_write32(0x084c, 0x0e0e0e0e); -+ mchbar_write32(0x0858, 0x06060606); -+ mchbar_write32(0x085c, 0x08070606); -+ mchbar_write32(0x0860, 0x0c0c0b0a); -+ mchbar_write32(0x0864, 0x0c0c0c0c); -+ -+ mchbar_write32(0x0880, 0x02020202); -+ mchbar_write32(0x0884, 0x03020202); -+ mchbar_write32(0x0888, 0x04040403); -+ mchbar_write32(0x088c, 0x04040404); -+ mchbar_write32(0x0898, 0x02020202); -+ mchbar_write32(0x089c, 0x03020202); -+ mchbar_write32(0x08a0, 0x04040403); -+ mchbar_write32(0x08a4, 0x04040404); -+ } - - igd_compute_ggc(sysinfo); - -diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -index b74765fd9c..5d4505e063 100644 ---- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -@@ -198,7 +198,7 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { - reg = mchbar_read32(0x518); - lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f; - lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f; -- if (i == 1) { -+ if ((i == 1) && (ddr_type == DDR2)) { - magic_comp[0] = (reg >> 8) & 0x3f; - magic_comp[1] = (reg >> 0) & 0x3f; - } -@@ -242,7 +242,8 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { - } - mchbar += 0x0040; - } -- -- mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); -- mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); -+ if (ddr_type == DDR2) { -+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); -+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); -+ } - } --- -2.47.3 - diff --git a/config/coreboot/default/patches/0017-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0017-nb-intel-gm45-Make-DDR2-raminit-work.patch new file mode 100644 index 00000000..6161d4f8 --- /dev/null +++ b/config/coreboot/default/patches/0017-nb-intel-gm45-Make-DDR2-raminit-work.patch @@ -0,0 +1,223 @@ +From 4347eae3a819dff7b6715630208d4be74b8245e4 Mon Sep 17 00:00:00 2001 +From: Angel Pons +Date: Mon, 10 May 2021 22:40:59 +0200 +Subject: [PATCH 17/51] nb/intel/gm45: Make DDR2 raminit work + +List of changes: + - Update some timing and ODT values + - Patch RCOMP calibration to better match what MRC binaries do + - Replay a hardcoded list of RCOMP codes after RcvEn + +This makes raminit work at DDR2-800 speeds and fixes S3 resume as well. +Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs. + +Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c +Signed-off-by: Angel Pons +--- + src/northbridge/intel/gm45/gm45.h | 2 +- + src/northbridge/intel/gm45/raminit.c | 90 +++++++++++++++++-- + .../intel/gm45/raminit_rcomp_calibration.c | 27 ++++-- + 3 files changed, 106 insertions(+), 13 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h +index 90ab570524..d537ef82af 100644 +--- a/src/northbridge/intel/gm45/gm45.h ++++ b/src/northbridge/intel/gm45/gm45.h +@@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo); + int raminit_read_vco_index(void); + u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank); + +-void raminit_rcomp_calibration(stepping_t stepping); ++void raminit_rcomp_calibration(int ddr_type, stepping_t stepping); + void raminit_reset_readwrite_pointers(void); + void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *); + void raminit_write_training(const mem_clock_t, const dimminfo_t *, bool s3resume); +diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c +index def9e1e331..7b091cc567 100644 +--- a/src/northbridge/intel/gm45/raminit.c ++++ b/src/northbridge/intel/gm45/raminit.c +@@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping, + } + + /* Perform RCOMP calibration for DDR3. */ +- raminit_rcomp_calibration(stepping); ++ raminit_rcomp_calibration(spd_type, stepping); + + /* Run initial RCOMP. */ + mchbar_setbits32(0x418, 1 << 17); +@@ -1117,7 +1117,7 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi + reg = (reg & ~(0xf << 10)) | (2 << 10); + else + reg = (reg & ~(0xf << 10)) | (3 << 10); +- reg = (reg & ~(0x7 << 5)) | (3 << 5); ++ reg = (reg & ~(0x7 << 5)) | (2 << 5); + } else if (timings->mem_clock != MEM_CLOCK_1067MT) { + reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); + reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); +@@ -1286,11 +1286,11 @@ static void ddr2_odt_setup(const timings_t *const timings, const int sff) + reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32)); + reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32)); + if (timings->mem_clock == MEM_CLOCK_667MT) { +- reg = (reg & ~(0xf << (36 - 32))) | (4 << (36 - 32)); +- reg = (reg & ~(0xf << (32 - 32))) | (4 << (32 - 32)); ++ reg = (reg & ~(0xf << (36 - 32))) | (8 << (36 - 32)); ++ reg = (reg & ~(0xf << (32 - 32))) | (8 << (32 - 32)); + } else { +- reg = (reg & ~(0xf << (36 - 32))) | (5 << (36 - 32)); +- reg = (reg & ~(0xf << (32 - 32))) | (5 << (32 - 32)); ++ reg = (reg & ~(0xf << (36 - 32))) | (9 << (36 - 32)); ++ reg = (reg & ~(0xf << (32 - 32))) | (9 << (32 - 32)); + } + mchbar_write32(CxODT_HIGH(ch), reg); + +@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume) + raminit_write_training(timings->mem_clock, dimms, s3resume); + } + ++ /* ++ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done ++ * after receiver enable calibration, otherwise raminit sometimes ++ * completes with non-working memory. ++ */ ++ mchbar_write32(0x0530, 0x06060005); ++ mchbar_write32(0x0680, 0x06060606); ++ mchbar_write32(0x0684, 0x08070606); ++ mchbar_write32(0x0688, 0x0e0e0c0a); ++ mchbar_write32(0x068c, 0x0e0e0e0e); ++ mchbar_write32(0x0698, 0x06060606); ++ mchbar_write32(0x069c, 0x08070606); ++ mchbar_write32(0x06a0, 0x0c0c0b0a); ++ mchbar_write32(0x06a4, 0x0c0c0c0c); ++ ++ mchbar_write32(0x06c0, 0x02020202); ++ mchbar_write32(0x06c4, 0x03020202); ++ mchbar_write32(0x06c8, 0x04040403); ++ mchbar_write32(0x06cc, 0x04040404); ++ mchbar_write32(0x06d8, 0x02020202); ++ mchbar_write32(0x06dc, 0x03020202); ++ mchbar_write32(0x06e0, 0x04040403); ++ mchbar_write32(0x06e4, 0x04040404); ++ ++ mchbar_write32(0x0700, 0x02020202); ++ mchbar_write32(0x0704, 0x03020202); ++ mchbar_write32(0x0708, 0x04040403); ++ mchbar_write32(0x070c, 0x04040404); ++ mchbar_write32(0x0718, 0x02020202); ++ mchbar_write32(0x071c, 0x03020202); ++ mchbar_write32(0x0720, 0x04040403); ++ mchbar_write32(0x0724, 0x04040404); ++ ++ mchbar_write32(0x0740, 0x02020202); ++ mchbar_write32(0x0744, 0x03020202); ++ mchbar_write32(0x0748, 0x04040403); ++ mchbar_write32(0x074c, 0x04040404); ++ mchbar_write32(0x0758, 0x02020202); ++ mchbar_write32(0x075c, 0x03020202); ++ mchbar_write32(0x0760, 0x04040403); ++ mchbar_write32(0x0764, 0x04040404); ++ ++ mchbar_write32(0x0780, 0x06060606); ++ mchbar_write32(0x0784, 0x09070606); ++ mchbar_write32(0x0788, 0x0e0e0c0b); ++ mchbar_write32(0x078c, 0x0e0e0e0e); ++ mchbar_write32(0x0798, 0x06060606); ++ mchbar_write32(0x079c, 0x09070606); ++ mchbar_write32(0x07a0, 0x0d0d0c0b); ++ mchbar_write32(0x07a4, 0x0d0d0d0d); ++ ++ mchbar_write32(0x07c0, 0x06060606); ++ mchbar_write32(0x07c4, 0x09070606); ++ mchbar_write32(0x07c8, 0x0e0e0c0b); ++ mchbar_write32(0x07cc, 0x0e0e0e0e); ++ mchbar_write32(0x07d8, 0x06060606); ++ mchbar_write32(0x07dc, 0x09070606); ++ mchbar_write32(0x07e0, 0x0d0d0c0b); ++ mchbar_write32(0x07e4, 0x0d0d0d0d); ++ ++ mchbar_write32(0x0840, 0x06060606); ++ mchbar_write32(0x0844, 0x08070606); ++ mchbar_write32(0x0848, 0x0e0e0c0a); ++ mchbar_write32(0x084c, 0x0e0e0e0e); ++ mchbar_write32(0x0858, 0x06060606); ++ mchbar_write32(0x085c, 0x08070606); ++ mchbar_write32(0x0860, 0x0c0c0b0a); ++ mchbar_write32(0x0864, 0x0c0c0c0c); ++ ++ mchbar_write32(0x0880, 0x02020202); ++ mchbar_write32(0x0884, 0x03020202); ++ mchbar_write32(0x0888, 0x04040403); ++ mchbar_write32(0x088c, 0x04040404); ++ mchbar_write32(0x0898, 0x02020202); ++ mchbar_write32(0x089c, 0x03020202); ++ mchbar_write32(0x08a0, 0x04040403); ++ mchbar_write32(0x08a4, 0x04040404); ++ + igd_compute_ggc(sysinfo); + + /* Program final memory map (with real values). */ +diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +index aef863f05a..b74765fd9c 100644 +--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c ++++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +@@ -161,11 +161,13 @@ static void lookup_and_write(const int a1step, + mchbar += 4; + } + } +-void raminit_rcomp_calibration(const stepping_t stepping) { ++void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { + const int a1step = stepping >= STEPPING_CONVERSION_A1; + + int i; + ++ char magic_comp[2] = {0}; ++ + enum { + PULL_UP = 0, + PULL_DOWN = 1, +@@ -196,6 +198,10 @@ void raminit_rcomp_calibration(const stepping_t stepping) { + reg = mchbar_read32(0x518); + lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f; + lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f; ++ if (i == 1) { ++ magic_comp[0] = (reg >> 8) & 0x3f; ++ magic_comp[1] = (reg >> 0) & 0x3f; ++ } + } + /* Cleanup? */ + mchbar_setbits32(0x400, 1 << 3); +@@ -216,13 +222,19 @@ void raminit_rcomp_calibration(const stepping_t stepping) { + for (channel = 0; channel < 2; ++channel) { + for (group = 0; group < 6; ++group) { + for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) { +- lookup_and_write( +- a1step, +- lut_idx[channel][group][pu_pd] - 7, +- ddr3_lookup_schedule[group][pu_pd], +- mchbar); ++ if (ddr_type == DDR3) { ++ lookup_and_write( ++ a1step, ++ lut_idx[channel][group][pu_pd] - 7, ++ ddr3_lookup_schedule[group][pu_pd], ++ mchbar); ++ } + mchbar += 0x0018; + } ++ if (ddr_type == DDR2) { ++ mchbar_clrsetbits32(mchbar + 0, 0x7f << 24, lut_idx[channel][group][PULL_DOWN] << 24); ++ mchbar_clrsetbits32(mchbar + 4, 0x7f << 0, lut_idx[channel][group][PULL_UP] << 0); ++ } + mchbar += 0x0010; + /* Channel B knows only the first two groups. */ + if ((1 == channel) && (1 == group)) +@@ -230,4 +242,7 @@ void raminit_rcomp_calibration(const stepping_t stepping) { + } + mchbar += 0x0040; + } ++ ++ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); ++ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); + } +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch deleted file mode 100644 index fdb225e8..00000000 --- a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 130a5ca25fbedb58e49b613e4a7cece715b545ae Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Mon, 20 May 2024 10:24:16 -0600 -Subject: [PATCH 18/48] mb/dell/e6400: Use 100 MHz reference clock for display - -The E6400 uses a 100 MHz reference clock for spread spectrum support on -LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For -the more common 1280 x 800 display panels, the numerical error was not -large enough to cause noticable issues, but the actual pixel clock -frequency derived from a 100 MHz reference using PLL configs calculated -assuming a 96 MHz reference was not close enough for 1440 x 900 panels, -which require a much higher pixel clock. This resulted in a garbled -display in the pre-OS graphics environment provided by libgfxinit. - -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/gm45_latitude/Kconfig | 2 ++ - src/northbridge/intel/gm45/Kconfig | 4 ++++ - 2 files changed, 6 insertions(+) - -diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig -index edc79b0d43..5020744990 100644 ---- a/src/mainboard/dell/gm45_latitude/Kconfig -+++ b/src/mainboard/dell/gm45_latitude/Kconfig -@@ -22,6 +22,8 @@ config BOARD_DELL_E6400 - select BOARD_DELL_GM45_LATITUDE_COMMON - - if BOARD_DELL_GM45_LATITUDE_COMMON -+config INTEL_GMA_DPLL_REF_FREQ -+ default 100000000 - - config MAINBOARD_DIR - default "dell/gm45_latitude" -diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig -index a776217475..35e89b0c88 100644 ---- a/src/northbridge/intel/gm45/Kconfig -+++ b/src/northbridge/intel/gm45/Kconfig -@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45 - - if NORTHBRIDGE_INTEL_GM45 - -+config INTEL_GMA_DPLL_REF_FREQ -+ int -+ default 96000000 -+ - config VBOOT - select VBOOT_STARTS_IN_BOOTBLOCK - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0018-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0018-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch new file mode 100644 index 00000000..04b00c86 --- /dev/null +++ b/config/coreboot/default/patches/0018-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch @@ -0,0 +1,240 @@ +From 8effb91216e331655ab64bc0aa114a3b38baec9c Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 6 Aug 2024 00:50:24 +0100 +Subject: [PATCH 18/51] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards + +We add this patch: + +commit commit_id_here +Author: Angel Pons +Date: Mon May 10 22:40:59 2021 +0200 + + nb/intel/gm45: Make DDR2 raminit work + +This patch was original applied, in lbmk, only on coreboot/dell, +separately from coreboot/default, which was wasteful because it +meant having an entire coreboot tree just for a single board. We +did this, because the DDR2 RCOMP fix happened to break DDR3 init +on other boards. + +What *this* new patch does on top of Angel's patch, is make sure +that their changes only apply to DDR2, while DDR3 behaviour remains +unchanged. This means that the Dell Latitude E6400 can be supported +in the main coreboot tree, within lbmk. + +Essentially, this patch restores the old behaviour, prior to applying +Angel's patch, only when DDR3 memory is used. + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/gm45/raminit.c | 161 +++++++++--------- + .../intel/gm45/raminit_rcomp_calibration.c | 9 +- + 2 files changed, 88 insertions(+), 82 deletions(-) + +diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c +index 7b091cc567..478898564a 100644 +--- a/src/northbridge/intel/gm45/raminit.c ++++ b/src/northbridge/intel/gm45/raminit.c +@@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi + reg = (reg & ~(0xf << 10)) | (2 << 10); + else + reg = (reg & ~(0xf << 10)) | (3 << 10); +- reg = (reg & ~(0x7 << 5)) | (2 << 5); ++ if (spd_type == DDR2) ++ reg = (reg & ~(0x7 << 5)) | (2 << 5); ++ else ++ reg = (reg & ~(0x7 << 5)) | (3 << 5); + } else if (timings->mem_clock != MEM_CLOCK_1067MT) { + reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); + reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); +@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume) + raminit_write_training(timings->mem_clock, dimms, s3resume); + } + +- /* +- * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done +- * after receiver enable calibration, otherwise raminit sometimes +- * completes with non-working memory. +- */ +- mchbar_write32(0x0530, 0x06060005); +- mchbar_write32(0x0680, 0x06060606); +- mchbar_write32(0x0684, 0x08070606); +- mchbar_write32(0x0688, 0x0e0e0c0a); +- mchbar_write32(0x068c, 0x0e0e0e0e); +- mchbar_write32(0x0698, 0x06060606); +- mchbar_write32(0x069c, 0x08070606); +- mchbar_write32(0x06a0, 0x0c0c0b0a); +- mchbar_write32(0x06a4, 0x0c0c0c0c); +- +- mchbar_write32(0x06c0, 0x02020202); +- mchbar_write32(0x06c4, 0x03020202); +- mchbar_write32(0x06c8, 0x04040403); +- mchbar_write32(0x06cc, 0x04040404); +- mchbar_write32(0x06d8, 0x02020202); +- mchbar_write32(0x06dc, 0x03020202); +- mchbar_write32(0x06e0, 0x04040403); +- mchbar_write32(0x06e4, 0x04040404); +- +- mchbar_write32(0x0700, 0x02020202); +- mchbar_write32(0x0704, 0x03020202); +- mchbar_write32(0x0708, 0x04040403); +- mchbar_write32(0x070c, 0x04040404); +- mchbar_write32(0x0718, 0x02020202); +- mchbar_write32(0x071c, 0x03020202); +- mchbar_write32(0x0720, 0x04040403); +- mchbar_write32(0x0724, 0x04040404); +- +- mchbar_write32(0x0740, 0x02020202); +- mchbar_write32(0x0744, 0x03020202); +- mchbar_write32(0x0748, 0x04040403); +- mchbar_write32(0x074c, 0x04040404); +- mchbar_write32(0x0758, 0x02020202); +- mchbar_write32(0x075c, 0x03020202); +- mchbar_write32(0x0760, 0x04040403); +- mchbar_write32(0x0764, 0x04040404); +- +- mchbar_write32(0x0780, 0x06060606); +- mchbar_write32(0x0784, 0x09070606); +- mchbar_write32(0x0788, 0x0e0e0c0b); +- mchbar_write32(0x078c, 0x0e0e0e0e); +- mchbar_write32(0x0798, 0x06060606); +- mchbar_write32(0x079c, 0x09070606); +- mchbar_write32(0x07a0, 0x0d0d0c0b); +- mchbar_write32(0x07a4, 0x0d0d0d0d); +- +- mchbar_write32(0x07c0, 0x06060606); +- mchbar_write32(0x07c4, 0x09070606); +- mchbar_write32(0x07c8, 0x0e0e0c0b); +- mchbar_write32(0x07cc, 0x0e0e0e0e); +- mchbar_write32(0x07d8, 0x06060606); +- mchbar_write32(0x07dc, 0x09070606); +- mchbar_write32(0x07e0, 0x0d0d0c0b); +- mchbar_write32(0x07e4, 0x0d0d0d0d); +- +- mchbar_write32(0x0840, 0x06060606); +- mchbar_write32(0x0844, 0x08070606); +- mchbar_write32(0x0848, 0x0e0e0c0a); +- mchbar_write32(0x084c, 0x0e0e0e0e); +- mchbar_write32(0x0858, 0x06060606); +- mchbar_write32(0x085c, 0x08070606); +- mchbar_write32(0x0860, 0x0c0c0b0a); +- mchbar_write32(0x0864, 0x0c0c0c0c); +- +- mchbar_write32(0x0880, 0x02020202); +- mchbar_write32(0x0884, 0x03020202); +- mchbar_write32(0x0888, 0x04040403); +- mchbar_write32(0x088c, 0x04040404); +- mchbar_write32(0x0898, 0x02020202); +- mchbar_write32(0x089c, 0x03020202); +- mchbar_write32(0x08a0, 0x04040403); +- mchbar_write32(0x08a4, 0x04040404); ++ if (sysinfo->spd_type == DDR2) { ++ /* ++ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done ++ * after receiver enable calibration, otherwise raminit sometimes ++ * completes with non-working memory. ++ */ ++ mchbar_write32(0x0530, 0x06060005); ++ mchbar_write32(0x0680, 0x06060606); ++ mchbar_write32(0x0684, 0x08070606); ++ mchbar_write32(0x0688, 0x0e0e0c0a); ++ mchbar_write32(0x068c, 0x0e0e0e0e); ++ mchbar_write32(0x0698, 0x06060606); ++ mchbar_write32(0x069c, 0x08070606); ++ mchbar_write32(0x06a0, 0x0c0c0b0a); ++ mchbar_write32(0x06a4, 0x0c0c0c0c); ++ ++ mchbar_write32(0x06c0, 0x02020202); ++ mchbar_write32(0x06c4, 0x03020202); ++ mchbar_write32(0x06c8, 0x04040403); ++ mchbar_write32(0x06cc, 0x04040404); ++ mchbar_write32(0x06d8, 0x02020202); ++ mchbar_write32(0x06dc, 0x03020202); ++ mchbar_write32(0x06e0, 0x04040403); ++ mchbar_write32(0x06e4, 0x04040404); ++ ++ mchbar_write32(0x0700, 0x02020202); ++ mchbar_write32(0x0704, 0x03020202); ++ mchbar_write32(0x0708, 0x04040403); ++ mchbar_write32(0x070c, 0x04040404); ++ mchbar_write32(0x0718, 0x02020202); ++ mchbar_write32(0x071c, 0x03020202); ++ mchbar_write32(0x0720, 0x04040403); ++ mchbar_write32(0x0724, 0x04040404); ++ ++ mchbar_write32(0x0740, 0x02020202); ++ mchbar_write32(0x0744, 0x03020202); ++ mchbar_write32(0x0748, 0x04040403); ++ mchbar_write32(0x074c, 0x04040404); ++ mchbar_write32(0x0758, 0x02020202); ++ mchbar_write32(0x075c, 0x03020202); ++ mchbar_write32(0x0760, 0x04040403); ++ mchbar_write32(0x0764, 0x04040404); ++ ++ mchbar_write32(0x0780, 0x06060606); ++ mchbar_write32(0x0784, 0x09070606); ++ mchbar_write32(0x0788, 0x0e0e0c0b); ++ mchbar_write32(0x078c, 0x0e0e0e0e); ++ mchbar_write32(0x0798, 0x06060606); ++ mchbar_write32(0x079c, 0x09070606); ++ mchbar_write32(0x07a0, 0x0d0d0c0b); ++ mchbar_write32(0x07a4, 0x0d0d0d0d); ++ ++ mchbar_write32(0x07c0, 0x06060606); ++ mchbar_write32(0x07c4, 0x09070606); ++ mchbar_write32(0x07c8, 0x0e0e0c0b); ++ mchbar_write32(0x07cc, 0x0e0e0e0e); ++ mchbar_write32(0x07d8, 0x06060606); ++ mchbar_write32(0x07dc, 0x09070606); ++ mchbar_write32(0x07e0, 0x0d0d0c0b); ++ mchbar_write32(0x07e4, 0x0d0d0d0d); ++ ++ mchbar_write32(0x0840, 0x06060606); ++ mchbar_write32(0x0844, 0x08070606); ++ mchbar_write32(0x0848, 0x0e0e0c0a); ++ mchbar_write32(0x084c, 0x0e0e0e0e); ++ mchbar_write32(0x0858, 0x06060606); ++ mchbar_write32(0x085c, 0x08070606); ++ mchbar_write32(0x0860, 0x0c0c0b0a); ++ mchbar_write32(0x0864, 0x0c0c0c0c); ++ ++ mchbar_write32(0x0880, 0x02020202); ++ mchbar_write32(0x0884, 0x03020202); ++ mchbar_write32(0x0888, 0x04040403); ++ mchbar_write32(0x088c, 0x04040404); ++ mchbar_write32(0x0898, 0x02020202); ++ mchbar_write32(0x089c, 0x03020202); ++ mchbar_write32(0x08a0, 0x04040403); ++ mchbar_write32(0x08a4, 0x04040404); ++ } + + igd_compute_ggc(sysinfo); + +diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +index b74765fd9c..5d4505e063 100644 +--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c ++++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +@@ -198,7 +198,7 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { + reg = mchbar_read32(0x518); + lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f; + lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f; +- if (i == 1) { ++ if ((i == 1) && (ddr_type == DDR2)) { + magic_comp[0] = (reg >> 8) & 0x3f; + magic_comp[1] = (reg >> 0) & 0x3f; + } +@@ -242,7 +242,8 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { + } + mchbar += 0x0040; + } +- +- mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); +- mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); ++ if (ddr_type == DDR2) { ++ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); ++ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); ++ } + } +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0019-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0019-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch new file mode 100644 index 00000000..8ed6a3f4 --- /dev/null +++ b/config/coreboot/default/patches/0019-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch @@ -0,0 +1,51 @@ +From c7b85347f892432b31000c67efccc02c84d9394a Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Mon, 20 May 2024 10:24:16 -0600 +Subject: [PATCH 19/51] mb/dell/e6400: Use 100 MHz reference clock for display + +The E6400 uses a 100 MHz reference clock for spread spectrum support on +LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For +the more common 1280 x 800 display panels, the numerical error was not +large enough to cause noticable issues, but the actual pixel clock +frequency derived from a 100 MHz reference using PLL configs calculated +assuming a 96 MHz reference was not close enough for 1440 x 900 panels, +which require a much higher pixel clock. This resulted in a garbled +display in the pre-OS graphics environment provided by libgfxinit. + +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/gm45_latitude/Kconfig | 2 ++ + src/northbridge/intel/gm45/Kconfig | 4 ++++ + 2 files changed, 6 insertions(+) + +diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig +index edc79b0d43..5020744990 100644 +--- a/src/mainboard/dell/gm45_latitude/Kconfig ++++ b/src/mainboard/dell/gm45_latitude/Kconfig +@@ -22,6 +22,8 @@ config BOARD_DELL_E6400 + select BOARD_DELL_GM45_LATITUDE_COMMON + + if BOARD_DELL_GM45_LATITUDE_COMMON ++config INTEL_GMA_DPLL_REF_FREQ ++ default 100000000 + + config MAINBOARD_DIR + default "dell/gm45_latitude" +diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig +index a776217475..35e89b0c88 100644 +--- a/src/northbridge/intel/gm45/Kconfig ++++ b/src/northbridge/intel/gm45/Kconfig +@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45 + + if NORTHBRIDGE_INTEL_GM45 + ++config INTEL_GMA_DPLL_REF_FREQ ++ int ++ default 96000000 ++ + config VBOOT + select VBOOT_STARTS_IN_BOOTBLOCK + +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch deleted file mode 100644 index b7af55b4..00000000 --- a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 7641a4b9b91c385223026cd566e0ffc2a2aa0d8f Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 12 Aug 2024 02:15:24 +0100 -Subject: [PATCH 19/48] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ - -set it to 96MHz. fixes the following build error when -building for x4x boards e.g. gigabyte ga-g41m-es2l: - -hw-gfx-gma-plls.adb:465:46: error: "INTEL_GMA_DPLL_REF_FREQ" not declared in "Config" -make: *** [Makefile:423: build/ramstage/libgfxinit/common/g45/hw-gfx-gma-plls.o] Error 1 - -this error was introduced when merging coreboot/dell -into coreboot/default in lbmk. nicholas chin's fix in lbmk -was as follows: - -commit 8629873a6043067affc137be275b7aa69cb1f10c -Author: Nicholas Chin -Date: Mon May 20 10:46:25 2024 -0600 - - Fix E6400 display issue with 1440 x 900 panel - -this currently corresponds to the patch in lbmk, -as of 12 august 2024: - -0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch - -The assumption prior to Nicholas's fix was 96MHz, so set -it accordingly on x4x northbridge. - -Signed-off-by: Leah Rowe ---- - src/northbridge/intel/x4x/Kconfig | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 6fa4551957..646af3510b 100644 ---- a/src/northbridge/intel/x4x/Kconfig -+++ b/src/northbridge/intel/x4x/Kconfig -@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X - - if NORTHBRIDGE_INTEL_X4X - -+config INTEL_GMA_DPLL_REF_FREQ -+ int -+ default 96000000 -+ - config CBFS_SIZE - default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch deleted file mode 100644 index c9603f71..00000000 --- a/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch +++ /dev/null @@ -1,332 +0,0 @@ -From 36126c093a9b9e01d41f0a68977cd09070c3c276 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Thu, 26 Sep 2024 19:51:25 -0600 -Subject: [PATCH 20/48] mb/dell/gm45_latitudes: Add E4300 variant - -Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2 -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/gm45_latitude/Kconfig | 5 + - src/mainboard/dell/gm45_latitude/Kconfig.name | 3 + - .../gm45_latitude/variants/e4300/data.vbt | Bin 0 -> 3881 bytes - .../variants/e4300/gma-mainboard.ads | 17 +++ - .../dell/gm45_latitude/variants/e4300/gpio.c | 138 ++++++++++++++++++ - .../gm45_latitude/variants/e4300/hda_verb.c | 37 +++++ - .../variants/e4300/overridetree.cb | 10 ++ - 7 files changed, 210 insertions(+) - create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt - create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads - create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c - create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c - create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb - -diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig -index 5020744990..d27d5728a8 100644 ---- a/src/mainboard/dell/gm45_latitude/Kconfig -+++ b/src/mainboard/dell/gm45_latitude/Kconfig -@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON - config BOARD_DELL_E6400 - select BOARD_DELL_GM45_LATITUDE_COMMON - -+config BOARD_DELL_E4300 -+ select BOARD_DELL_GM45_LATITUDE_COMMON -+ - if BOARD_DELL_GM45_LATITUDE_COMMON - config INTEL_GMA_DPLL_REF_FREQ - default 100000000 -@@ -30,12 +33,14 @@ config MAINBOARD_DIR - - config MAINBOARD_PART_NUMBER - default "Latitude E6400" if BOARD_DELL_E6400 -+ default "Latitude E4300" if BOARD_DELL_E4300 - - config OVERRIDE_DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" - - config VARIANT_DIR - default "e6400" if BOARD_DELL_E6400 -+ default "e4300" if BOARD_DELL_E4300 - - config USBDEBUG_HCD_INDEX - default 1 -diff --git a/src/mainboard/dell/gm45_latitude/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name -index aefe777109..4dc95f46be 100644 ---- a/src/mainboard/dell/gm45_latitude/Kconfig.name -+++ b/src/mainboard/dell/gm45_latitude/Kconfig.name -@@ -1,4 +1,7 @@ - ## SPDX-License-Identifier: GPL-2.0-only - -+config BOARD_DELL_E4300 -+ bool "Latitude E4300" -+ - config BOARD_DELL_E6400 - bool "Latitude E6400" -diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..fa2f3db13f688b5687df16a155781d8674ea26f3 -GIT binary patch -literal 3881 -zcmdT`eQXp(6#wnV-R;foUbovquV-n84`GWGmlkRzXWaG>Td6>yG#51CN?M@?>DeM+ -zBI$}GlK6F+nD{}Y|ClJzh>3}Rm=N?2Y5aNhx3i7B*>RjEs#PQ-s5C6@#q~ze8SUuLOHbzw$htxKlQYWCt9NZmC -zVLO$_s2tQZ9MvqmM&%tUr>K0RF`T3FGnHSdOj6O}3>K9-D$(bpDh$)OQqAIh6jOwCxuw)qvS0N+Nk!? -zI~I-~3&u$!iZQuCQ3;=xYZQ&}1^JS!6aFCSvPt-}q{`KV7o=aLI=_ERh8gM+`g(-E -z9-*&C=<5;sdVc?y{2iwmrKs|~Kw5}Heji&vYYqJOG&As1`1?G0hsr2Y&r%2qq-H)u -z>=c836bj~sR4T<{m@IvjLaC(P1v(j%W}uLfs)L~qi^ -z4yaW6zjKK*SSa$dvbC#eRZDAgQ@dDEfr?l)G{1I8}OhGtOw#1e$Fn9wsUmbC8g}vF{$V$Y~rFp!qRJP)Z!2NYEhIpf^PzD_^ptxacQ#R+9@(N>ibe6 -z@|mz|d=bjIxSe3u0>+jxdmFQMG4?34k2C9i#y(>91!n!pSR`S$B&>T9Y*WHMl(1e% -zuvZiInS^yV!G28GmAbW9XHB~OfNnjavje*Qrfz+xvyXNAl5R-`OBnW@hPA<9+YI|D -z!+P0Z#|`^S!}`Hs7Yw^5X*DKUOVaL7TBAv}d|dV9^O8rYn%=4o&5GjdSWeb`yeyf7 -zk&0z-2#I*9^ljWL^79K!Ex#yORz2-nxRYGT$+NdKUcs>{SI2Fyx@<{2w?w*#&%hG* -zeY&DumV{4Nw4(1*^g5r`avbR44Nj-miiQs;Ii;O}*rL^|oYl8hQ9P@{Qf5}Gn;uRg -zI{c?gKNv~R$&eHj8!uus22Br_GkCD$Q)pf! -zGh%f}_&(hXOZrW-WCWJVw`DdrczV_sXGaOvzjt%F!O;{7J-K`tJBTNGZHe^T`VrkY0pv~u^?l~DG9UD8p8(692 Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c -new file mode 100644 -index 0000000000..b50f8da0b5 ---- /dev/null -+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c -@@ -0,0 +1,138 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_NATIVE, -+ .gpio1 = GPIO_MODE_GPIO, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_GPIO, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_GPIO, -+ .gpio8 = GPIO_MODE_GPIO, -+ .gpio9 = GPIO_MODE_NATIVE, -+ .gpio10 = GPIO_MODE_NATIVE, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_NATIVE, -+ .gpio16 = GPIO_MODE_NATIVE, -+ .gpio17 = GPIO_MODE_GPIO, -+ .gpio18 = GPIO_MODE_GPIO, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_GPIO, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_NATIVE, -+ .gpio30 = GPIO_MODE_NATIVE, -+ .gpio31 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio1 = GPIO_DIR_INPUT, -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio5 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio7 = GPIO_DIR_INPUT, -+ .gpio8 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio17 = GPIO_DIR_INPUT, -+ .gpio18 = GPIO_DIR_INPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio20 = GPIO_DIR_INPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio1 = GPIO_INVERT, -+ .gpio7 = GPIO_INVERT, -+ .gpio8 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_NATIVE, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_NATIVE, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_NATIVE, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_NATIVE, -+ .gpio52 = GPIO_MODE_GPIO, -+ .gpio53 = GPIO_MODE_GPIO, -+ .gpio54 = GPIO_MODE_NATIVE, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_GPIO, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_INPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_INPUT, -+ .gpio52 = GPIO_DIR_INPUT, -+ .gpio53 = GPIO_DIR_INPUT, -+ .gpio56 = GPIO_DIR_INPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ }, -+}; -diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c -new file mode 100644 -index 0000000000..a9948a93dd ---- /dev/null -+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c -@@ -0,0 +1,37 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ /* coreboot specific header */ -+ 0x111d76b2, /* IDT 92HD71B7X */ -+ 0x1028024d, /* Subsystem ID */ -+ 13, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ -+ AZALIA_PIN_CFG(0, 0x0a, 0x0421101f), -+ AZALIA_PIN_CFG(0, 0x0b, 0x04a11021), -+ AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0), -+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), -+ AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e), -+ AZALIA_PIN_CFG(0, 0x0f, 0x23011050), -+ AZALIA_PIN_CFG(0, 0x14, 0x40f000f2), -+ AZALIA_PIN_CFG(0, 0x18, 0x90a601a0), -+ AZALIA_PIN_CFG(0, 0x19, 0x40f000f4), -+ AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5), -+ AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6), -+ AZALIA_PIN_CFG(0, 0x20, 0x40f000f7), -+ AZALIA_PIN_CFG(0, 0x27, 0x40f000f0), -+}; -+ -+const u32 pc_beep_verbs[] = { -+ 0x00170500, /* power up codec */ -+ 0x00d70500, /* power up speakers */ -+ 0x00d70102, /* select mixer (input 0x2) for speakers */ -+ 0x00d70740, /* enable speakers output */ -+ 0x02770720, /* enable beep input */ -+ 0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */ -+ 0x00d37000, /* unmute speakers */ -+}; -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb -new file mode 100644 -index 0000000000..20dfa245fb ---- /dev/null -+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb -@@ -0,0 +1,10 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/gm45 -+ device domain 0 on -+ subsystemid 0x1028 0x024d inherit -+ chip southbridge/intel/i82801ix -+ device pci 1c.2 off end # PCIe Port #3 -+ end -+ end -+end --- -2.47.3 - diff --git a/config/coreboot/default/patches/0020-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0020-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch new file mode 100644 index 00000000..753e8c6f --- /dev/null +++ b/config/coreboot/default/patches/0020-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch @@ -0,0 +1,52 @@ +From 6d1cbaedc747afe4acd8b13240c56232ba870639 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 12 Aug 2024 02:15:24 +0100 +Subject: [PATCH 20/51] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ + +set it to 96MHz. fixes the following build error when +building for x4x boards e.g. gigabyte ga-g41m-es2l: + +hw-gfx-gma-plls.adb:465:46: error: "INTEL_GMA_DPLL_REF_FREQ" not declared in "Config" +make: *** [Makefile:423: build/ramstage/libgfxinit/common/g45/hw-gfx-gma-plls.o] Error 1 + +this error was introduced when merging coreboot/dell +into coreboot/default in lbmk. nicholas chin's fix in lbmk +was as follows: + +commit 8629873a6043067affc137be275b7aa69cb1f10c +Author: Nicholas Chin +Date: Mon May 20 10:46:25 2024 -0600 + + Fix E6400 display issue with 1440 x 900 panel + +this currently corresponds to the patch in lbmk, +as of 12 august 2024: + +0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch + +The assumption prior to Nicholas's fix was 96MHz, so set +it accordingly on x4x northbridge. + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/x4x/Kconfig | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig +index 6fa4551957..646af3510b 100644 +--- a/src/northbridge/intel/x4x/Kconfig ++++ b/src/northbridge/intel/x4x/Kconfig +@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X + + if NORTHBRIDGE_INTEL_X4X + ++config INTEL_GMA_DPLL_REF_FREQ ++ int ++ default 96000000 ++ + config CBFS_SIZE + default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX + +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch deleted file mode 100644 index 238e4799..00000000 --- a/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 4caca6e6e349fa1913df622081025ea53bfd136f Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Fri, 3 May 2024 16:31:12 -0600 -Subject: [PATCH 21/48] mb/dell: Add S3 SMI handler for Dell Latitudes - -Integrate the previously added mec5035_smi_sleep() function into -mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240. -The E6400 does not require the EC command to sucessfully suspend and -resume from S3, though sending it does enable the breathing effect on -the power LED while in S3. Without it, all LEDs turn off during S3. - -Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283 -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/gm45_latitude/smihandler.c | 9 +++++++++ - src/mainboard/dell/haswell_latitude/smihandler.c | 9 +++++++++ - src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++ - 3 files changed, 27 insertions(+) - create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c - create mode 100644 src/mainboard/dell/haswell_latitude/smihandler.c - create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c - -diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c -new file mode 100644 -index 0000000000..00e55b51db ---- /dev/null -+++ b/src/mainboard/dell/gm45_latitude/smihandler.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+ -+void mainboard_smi_sleep(u8 slp_typ) -+{ -+ mec5035_smi_sleep(slp_typ); -+} -diff --git a/src/mainboard/dell/haswell_latitude/smihandler.c b/src/mainboard/dell/haswell_latitude/smihandler.c -new file mode 100644 -index 0000000000..00e55b51db ---- /dev/null -+++ b/src/mainboard/dell/haswell_latitude/smihandler.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+ -+void mainboard_smi_sleep(u8 slp_typ) -+{ -+ mec5035_smi_sleep(slp_typ); -+} -diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c -new file mode 100644 -index 0000000000..00e55b51db ---- /dev/null -+++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+ -+void mainboard_smi_sleep(u8 slp_typ) -+{ -+ mec5035_smi_sleep(slp_typ); -+} --- -2.47.3 - diff --git a/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch new file mode 100644 index 00000000..7266646e --- /dev/null +++ b/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch @@ -0,0 +1,332 @@ +From bd1594c9025dbd84cdce4aac02152b809b67b108 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Thu, 26 Sep 2024 19:51:25 -0600 +Subject: [PATCH 21/51] mb/dell/gm45_latitudes: Add E4300 variant + +Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2 +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/gm45_latitude/Kconfig | 5 + + src/mainboard/dell/gm45_latitude/Kconfig.name | 3 + + .../gm45_latitude/variants/e4300/data.vbt | Bin 0 -> 3881 bytes + .../variants/e4300/gma-mainboard.ads | 17 +++ + .../dell/gm45_latitude/variants/e4300/gpio.c | 138 ++++++++++++++++++ + .../gm45_latitude/variants/e4300/hda_verb.c | 37 +++++ + .../variants/e4300/overridetree.cb | 10 ++ + 7 files changed, 210 insertions(+) + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb + +diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig +index 5020744990..d27d5728a8 100644 +--- a/src/mainboard/dell/gm45_latitude/Kconfig ++++ b/src/mainboard/dell/gm45_latitude/Kconfig +@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON + config BOARD_DELL_E6400 + select BOARD_DELL_GM45_LATITUDE_COMMON + ++config BOARD_DELL_E4300 ++ select BOARD_DELL_GM45_LATITUDE_COMMON ++ + if BOARD_DELL_GM45_LATITUDE_COMMON + config INTEL_GMA_DPLL_REF_FREQ + default 100000000 +@@ -30,12 +33,14 @@ config MAINBOARD_DIR + + config MAINBOARD_PART_NUMBER + default "Latitude E6400" if BOARD_DELL_E6400 ++ default "Latitude E4300" if BOARD_DELL_E4300 + + config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + + config VARIANT_DIR + default "e6400" if BOARD_DELL_E6400 ++ default "e4300" if BOARD_DELL_E4300 + + config USBDEBUG_HCD_INDEX + default 1 +diff --git a/src/mainboard/dell/gm45_latitude/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name +index aefe777109..4dc95f46be 100644 +--- a/src/mainboard/dell/gm45_latitude/Kconfig.name ++++ b/src/mainboard/dell/gm45_latitude/Kconfig.name +@@ -1,4 +1,7 @@ + ## SPDX-License-Identifier: GPL-2.0-only + ++config BOARD_DELL_E4300 ++ bool "Latitude E4300" ++ + config BOARD_DELL_E6400 + bool "Latitude E6400" +diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..fa2f3db13f688b5687df16a155781d8674ea26f3 +GIT binary patch +literal 3881 +zcmdT`eQXp(6#wnV-R;foUbovquV-n84`GWGmlkRzXWaG>Td6>yG#51CN?M@?>DeM+ +zBI$}GlK6F+nD{}Y|ClJzh>3}Rm=N?2Y5aNhx3i7B*>RjEs#PQ-s5C6@#q~ze8SUuLOHbzw$htxKlQYWCt9NZmC +zVLO$_s2tQZ9MvqmM&%tUr>K0RF`T3FGnHSdOj6O}3>K9-D$(bpDh$)OQqAIh6jOwCxuw)qvS0N+Nk!? +zI~I-~3&u$!iZQuCQ3;=xYZQ&}1^JS!6aFCSvPt-}q{`KV7o=aLI=_ERh8gM+`g(-E +z9-*&C=<5;sdVc?y{2iwmrKs|~Kw5}Heji&vYYqJOG&As1`1?G0hsr2Y&r%2qq-H)u +z>=c836bj~sR4T<{m@IvjLaC(P1v(j%W}uLfs)L~qi^ +z4yaW6zjKK*SSa$dvbC#eRZDAgQ@dDEfr?l)G{1I8}OhGtOw#1e$Fn9wsUmbC8g}vF{$V$Y~rFp!qRJP)Z!2NYEhIpf^PzD_^ptxacQ#R+9@(N>ibe6 +z@|mz|d=bjIxSe3u0>+jxdmFQMG4?34k2C9i#y(>91!n!pSR`S$B&>T9Y*WHMl(1e% +zuvZiInS^yV!G28GmAbW9XHB~OfNnjavje*Qrfz+xvyXNAl5R-`OBnW@hPA<9+YI|D +z!+P0Z#|`^S!}`Hs7Yw^5X*DKUOVaL7TBAv}d|dV9^O8rYn%=4o&5GjdSWeb`yeyf7 +zk&0z-2#I*9^ljWL^79K!Ex#yORz2-nxRYGT$+NdKUcs>{SI2Fyx@<{2w?w*#&%hG* +zeY&DumV{4Nw4(1*^g5r`avbR44Nj-miiQs;Ii;O}*rL^|oYl8hQ9P@{Qf5}Gn;uRg +zI{c?gKNv~R$&eHj8!uus22Br_GkCD$Q)pf! +zGh%f}_&(hXOZrW-WCWJVw`DdrczV_sXGaOvzjt%F!O;{7J-K`tJBTNGZHe^T`VrkY0pv~u^?l~DG9UD8p8(692 Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c +new file mode 100644 +index 0000000000..b50f8da0b5 +--- /dev/null ++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c +@@ -0,0 +1,138 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_NATIVE, ++ .gpio1 = GPIO_MODE_GPIO, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_GPIO, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_NATIVE, ++ .gpio16 = GPIO_MODE_NATIVE, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_GPIO, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_GPIO, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_NATIVE, ++ .gpio30 = GPIO_MODE_NATIVE, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio1 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio5 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio18 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio20 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio1 = GPIO_INVERT, ++ .gpio7 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_NATIVE, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_NATIVE, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_GPIO, ++ .gpio54 = GPIO_MODE_NATIVE, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_INPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio53 = GPIO_DIR_INPUT, ++ .gpio56 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ }, ++}; +diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c +new file mode 100644 +index 0000000000..a9948a93dd +--- /dev/null ++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c +@@ -0,0 +1,37 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header */ ++ 0x111d76b2, /* IDT 92HD71B7X */ ++ 0x1028024d, /* Subsystem ID */ ++ 13, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ ++ AZALIA_PIN_CFG(0, 0x0a, 0x0421101f), ++ AZALIA_PIN_CFG(0, 0x0b, 0x04a11021), ++ AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x14, 0x40f000f2), ++ AZALIA_PIN_CFG(0, 0x18, 0x90a601a0), ++ AZALIA_PIN_CFG(0, 0x19, 0x40f000f4), ++ AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5), ++ AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6), ++ AZALIA_PIN_CFG(0, 0x20, 0x40f000f7), ++ AZALIA_PIN_CFG(0, 0x27, 0x40f000f0), ++}; ++ ++const u32 pc_beep_verbs[] = { ++ 0x00170500, /* power up codec */ ++ 0x00d70500, /* power up speakers */ ++ 0x00d70102, /* select mixer (input 0x2) for speakers */ ++ 0x00d70740, /* enable speakers output */ ++ 0x02770720, /* enable beep input */ ++ 0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */ ++ 0x00d37000, /* unmute speakers */ ++}; ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb +new file mode 100644 +index 0000000000..20dfa245fb +--- /dev/null ++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb +@@ -0,0 +1,10 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/gm45 ++ device domain 0 on ++ subsystemid 0x1028 0x024d inherit ++ chip southbridge/intel/i82801ix ++ device pci 1c.2 off end # PCIe Port #3 ++ end ++ end ++end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch deleted file mode 100644 index deaefbfd..00000000 --- a/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 669ef0d2c72326134f64a4fe70f67220ec690c5e Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 31 Dec 2024 14:42:24 +0000 -Subject: [PATCH 22/48] Disable compression on refcode insertion - -Compression is not reliably reproducible. In an lbmk release -context, this means we cannot rely on vendorfile insertion. - -Therefore, use uncompressed refcode. - -Signed-off-by: Leah Rowe ---- - Makefile.mk | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/Makefile.mk b/Makefile.mk -index 5fccb4a52d..c40e06c453 100644 ---- a/Makefile.mk -+++ b/Makefile.mk -@@ -1414,7 +1414,7 @@ endif - cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode - $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB) - $(CONFIG_CBFS_PREFIX)/refcode-type := stage --$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG) -+$(CONFIG_CBFS_PREFIX)/refcode-compression := none - - cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin - vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE) --- -2.47.3 - diff --git a/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch new file mode 100644 index 00000000..cc67346f --- /dev/null +++ b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch @@ -0,0 +1,70 @@ +From 7fda207316f80a5bdffe428309df32a278d13c93 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Fri, 3 May 2024 16:31:12 -0600 +Subject: [PATCH 22/51] mb/dell: Add S3 SMI handler for Dell Latitudes + +Integrate the previously added mec5035_smi_sleep() function into +mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240. +The E6400 does not require the EC command to sucessfully suspend and +resume from S3, though sending it does enable the breathing effect on +the power LED while in S3. Without it, all LEDs turn off during S3. + +Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283 +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/gm45_latitude/smihandler.c | 9 +++++++++ + src/mainboard/dell/haswell_latitude/smihandler.c | 9 +++++++++ + src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++ + 3 files changed, 27 insertions(+) + create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c + create mode 100644 src/mainboard/dell/haswell_latitude/smihandler.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c + +diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c +new file mode 100644 +index 0000000000..00e55b51db +--- /dev/null ++++ b/src/mainboard/dell/gm45_latitude/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_smi_sleep(slp_typ); ++} +diff --git a/src/mainboard/dell/haswell_latitude/smihandler.c b/src/mainboard/dell/haswell_latitude/smihandler.c +new file mode 100644 +index 0000000000..00e55b51db +--- /dev/null ++++ b/src/mainboard/dell/haswell_latitude/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_smi_sleep(slp_typ); ++} +diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c +new file mode 100644 +index 0000000000..00e55b51db +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_smi_sleep(slp_typ); ++} +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch new file mode 100644 index 00000000..1205b3bf --- /dev/null +++ b/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch @@ -0,0 +1,31 @@ +From 8f5399ac24599f6d0f1912d46f253a91d67536cf Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 31 Dec 2024 14:42:24 +0000 +Subject: [PATCH 23/51] Disable compression on refcode insertion + +Compression is not reliably reproducible. In an lbmk release +context, this means we cannot rely on vendorfile insertion. + +Therefore, use uncompressed refcode. + +Signed-off-by: Leah Rowe +--- + Makefile.mk | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/Makefile.mk b/Makefile.mk +index dbad313911..8f541ad187 100644 +--- a/Makefile.mk ++++ b/Makefile.mk +@@ -1432,7 +1432,7 @@ endif + cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode + $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB) + $(CONFIG_CBFS_PREFIX)/refcode-type := stage +-$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG) ++$(CONFIG_CBFS_PREFIX)/refcode-compression := none + + cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin + vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE) +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch deleted file mode 100644 index 3bb55c37..00000000 --- a/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch +++ /dev/null @@ -1,187 +0,0 @@ -From c7b136f1f4fa2bc1a783711b5a1ee82c5d9ce69f Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 21 Apr 2025 02:58:47 +0100 -Subject: [PATCH 23/48] nb/intel/*: Disable stack overflow debug options - -Signed-off-by: Leah Rowe ---- - src/northbridge/intel/e7505/Kconfig | 9 +++++++++ - src/northbridge/intel/gm45/Kconfig | 9 +++++++++ - src/northbridge/intel/haswell/Kconfig | 9 +++++++++ - src/northbridge/intel/i440bx/Kconfig | 13 +++++++++++++ - src/northbridge/intel/i945/Kconfig | 9 +++++++++ - src/northbridge/intel/ironlake/Kconfig | 9 +++++++++ - src/northbridge/intel/pineview/Kconfig | 9 +++++++++ - src/northbridge/intel/sandybridge/Kconfig | 9 +++++++++ - src/northbridge/intel/x4x/Kconfig | 9 +++++++++ - 9 files changed, 85 insertions(+) - -diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig -index 039a7396f8..ddcb986f10 100644 ---- a/src/northbridge/intel/e7505/Kconfig -+++ b/src/northbridge/intel/e7505/Kconfig -@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505 - select NO_CBFS_MCACHE - select SMM_TSEG - select NEED_SMALL_2MB_PAGE_TABLES -+ -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig -index 35e89b0c88..c5456d0ddf 100644 ---- a/src/northbridge/intel/gm45/Kconfig -+++ b/src/northbridge/intel/gm45/Kconfig -@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE - config FIXED_EPBAR_MMIO_BASE - default 0xfed19000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig -index c57f1ec380..0a5181b183 100644 ---- a/src/northbridge/intel/haswell/Kconfig -+++ b/src/northbridge/intel/haswell/Kconfig -@@ -10,6 +10,15 @@ config NORTHBRIDGE_INTEL_HASWELL - - if NORTHBRIDGE_INTEL_HASWELL - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - config USE_NATIVE_RAMINIT - bool "[NOT COMPLETE] Use native raminit" - default n -diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig -index dbb2d7436b..5e9418b6a9 100644 ---- a/src/northbridge/intel/i440bx/Kconfig -+++ b/src/northbridge/intel/i440bx/Kconfig -@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM - If your board has 4 DIMM slots, you must use select this option, in - your Kconfig file of the board. On boards with 3 DIMM slots, - do _not_ select this option. -+ -+if NORTHBRIDGE_INTEL_I440BX -+ -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ -+endif -diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig -index c4e17f90bf..b12f5be091 100644 ---- a/src/northbridge/intel/i945/Kconfig -+++ b/src/northbridge/intel/i945/Kconfig -@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE - config FIXED_EPBAR_MMIO_BASE - default 0xfed19000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig -index 39566a6e5f..f46acf6937 100644 ---- a/src/northbridge/intel/ironlake/Kconfig -+++ b/src/northbridge/intel/ironlake/Kconfig -@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE - config FIXED_EPBAR_MMIO_BASE - default 0xfed19000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig -index a05b866dad..50e3a7cdb9 100644 ---- a/src/northbridge/intel/pineview/Kconfig -+++ b/src/northbridge/intel/pineview/Kconfig -@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE - config DOMAIN_RESOURCE_32BIT_LIMIT - default 0xfec00000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig -index 9972a43da0..fe4ac5106c 100644 ---- a/src/northbridge/intel/sandybridge/Kconfig -+++ b/src/northbridge/intel/sandybridge/Kconfig -@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX - default 2 if IGD_DEFAULT_UMA_SIZE_96MB - default 3 if IGD_DEFAULT_UMA_SIZE_128MB - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 646af3510b..069fa0244d 100644 ---- a/src/northbridge/intel/x4x/Kconfig -+++ b/src/northbridge/intel/x4x/Kconfig -@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE - config FIXED_EPBAR_MMIO_BASE - default 0xfed19000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif --- -2.47.3 - diff --git a/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch deleted file mode 100644 index 22061393..00000000 --- a/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch +++ /dev/null @@ -1,708 +0,0 @@ -From c15a0ef9b964e9df9a5578ed271af4f1c0419f38 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Mon, 30 Sep 2024 20:44:38 -0400 -Subject: [PATCH 24/48] mb/dell: Add Optiplex 780 MT (x4x/ICH10) - -Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/optiplex_780/Kconfig | 40 ++++ - src/mainboard/dell/optiplex_780/Kconfig.name | 4 + - src/mainboard/dell/optiplex_780/Makefile.mk | 10 + - src/mainboard/dell/optiplex_780/acpi/ec.asl | 5 + - .../dell/optiplex_780/acpi/ich10_pci_irqs.asl | 32 ++++ - .../dell/optiplex_780/acpi/superio.asl | 18 ++ - .../dell/optiplex_780/board_info.txt | 6 + - src/mainboard/dell/optiplex_780/cmos.default | 8 + - src/mainboard/dell/optiplex_780/cmos.layout | 72 ++++++++ - src/mainboard/dell/optiplex_780/cstates.c | 8 + - src/mainboard/dell/optiplex_780/devicetree.cb | 63 +++++++ - src/mainboard/dell/optiplex_780/dsdt.asl | 26 +++ - .../dell/optiplex_780/gma-mainboard.ads | 16 ++ - .../optiplex_780/variants/780_mt/data.vbt | Bin 0 -> 1917 bytes - .../optiplex_780/variants/780_mt/early_init.c | 12 ++ - .../dell/optiplex_780/variants/780_mt/gpio.c | 174 ++++++++++++++++++ - .../optiplex_780/variants/780_mt/hda_verb.c | 26 +++ - .../variants/780_mt/overridetree.cb | 10 + - 18 files changed, 530 insertions(+) - create mode 100644 src/mainboard/dell/optiplex_780/Kconfig - create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name - create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk - create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl - create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl - create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl - create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt - create mode 100644 src/mainboard/dell/optiplex_780/cmos.default - create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout - create mode 100644 src/mainboard/dell/optiplex_780/cstates.c - create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb - create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl - create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb - -diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig -new file mode 100644 -index 0000000000..2d06c75c9a ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/Kconfig -@@ -0,0 +1,40 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_DELL_OPTIPLEX_780_COMMON -+ def_bool n -+ select BOARD_ROMSIZE_KB_8192 -+ select CPU_INTEL_SOCKET_LGA775 -+ select DRIVERS_I2C_CK505 -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ select INTEL_GMA_HAVE_VBT -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_USES_IFD_GBE_REGION -+ select NORTHBRIDGE_INTEL_X4X -+ select PCIEXP_ASPM -+ select PCIEXP_CLK_PM -+ select SOUTHBRIDGE_INTEL_I82801JX -+ -+config BOARD_DELL_OPTIPLEX_780_MT -+ select BOARD_DELL_OPTIPLEX_780_COMMON -+ -+if BOARD_DELL_OPTIPLEX_780_COMMON -+ -+config VGA_BIOS_ID -+ default "8086,2e22" -+ -+config MAINBOARD_DIR -+ default "dell/optiplex_780" -+ -+config MAINBOARD_PART_NUMBER -+ default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT -+ -+config OVERRIDE_DEVICETREE -+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -+ -+config VARIANT_DIR -+ default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT -+ -+endif # BOARD_DELL_OPTIPLEX_780_COMMON -diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name -new file mode 100644 -index 0000000000..db7f2e8fe3 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/Kconfig.name -@@ -0,0 +1,4 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_DELL_OPTIPLEX_780_MT -+ bool "OptiPlex 780 MT" -diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk -new file mode 100644 -index 0000000000..d462995d75 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/Makefile.mk -@@ -0,0 +1,10 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+ramstage-y += cstates.c -+romstage-y += variants/$(VARIANT_DIR)/gpio.c -+ -+bootblock-y += variants/$(VARIANT_DIR)/early_init.c -+romstage-y += variants/$(VARIANT_DIR)/early_init.c -+ -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c -diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl -new file mode 100644 -index 0000000000..479296cb76 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl -@@ -0,0 +1,5 @@ -+/* SPDX-License-Identifier: CC-PDDC */ -+ -+/* Please update the license if adding licensable material. */ -+ -+/* dummy */ -diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl -new file mode 100644 -index 0000000000..b7588dcc41 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl -@@ -0,0 +1,32 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+/* This is board specific information: -+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 -+ */ -+ -+If (PICM) { -+ Return (Package() { -+ /* PCI slot */ -+ Package() { 0x0001ffff, 0, 0, 0x14}, -+ Package() { 0x0001ffff, 1, 0, 0x15}, -+ Package() { 0x0001ffff, 2, 0, 0x16}, -+ Package() { 0x0001ffff, 3, 0, 0x17}, -+ -+ Package() { 0x0002ffff, 0, 0, 0x15}, -+ Package() { 0x0002ffff, 1, 0, 0x16}, -+ Package() { 0x0002ffff, 2, 0, 0x17}, -+ Package() { 0x0002ffff, 3, 0, 0x14}, -+ }) -+} Else { -+ Return (Package() { -+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, -+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, -+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, -+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, -+ -+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, -+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, -+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, -+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, -+ }) -+} -diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl -new file mode 100644 -index 0000000000..9f3900b86c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl -@@ -0,0 +1,18 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#undef SUPERIO_DEV -+#undef SUPERIO_PNP_BASE -+#undef IT8720F_SHOW_SP1 -+#undef IT8720F_SHOW_SP2 -+#undef IT8720F_SHOW_EC -+#undef IT8720F_SHOW_KBCK -+#undef IT8720F_SHOW_KBCM -+#undef IT8720F_SHOW_GPIO -+#undef IT8720F_SHOW_CIR -+#define SUPERIO_DEV SIO0 -+#define SUPERIO_PNP_BASE 0x2e -+#define IT8720F_SHOW_EC 1 -+#define IT8720F_SHOW_KBCK 1 -+#define IT8720F_SHOW_KBCM 1 -+#define IT8720F_SHOW_GPIO 1 -+#include -diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt -new file mode 100644 -index 0000000000..aaf657b583 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/board_info.txt -@@ -0,0 +1,6 @@ -+Category: desktop -+Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1 -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default -new file mode 100644 -index 0000000000..23f0e55f3e ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/cmos.default -@@ -0,0 +1,8 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -+nmi=Enable -+sata_mode=AHCI -+gfx_uma_size=64M -diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout -new file mode 100644 -index 0000000000..9f5012adb4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/cmos.layout -@@ -0,0 +1,72 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+# coreboot config options: southbridge -+408 1 e 10 sata_mode -+409 2 e 7 power_on_after_fail -+411 1 e 1 nmi -+ -+# coreboot config options: cpu -+ -+# coreboot config options: northbridge -+432 4 e 11 gfx_uma_size -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+2 0 Enable -+2 1 Disable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+10 0 AHCI -+10 1 Compatible -+11 1 4M -+11 2 8M -+11 3 16M -+11 4 32M -+11 5 48M -+11 6 64M -+11 7 128M -+11 8 256M -+11 9 96M -+11 10 160M -+11 11 224M -+11 12 352M -+ -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 983 984 -diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c -new file mode 100644 -index 0000000000..4adf0edc63 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/cstates.c -@@ -0,0 +1,8 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+int get_cst_entries(const acpi_cstate_t **entries) -+{ -+ return 0; -+} -diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb -new file mode 100644 -index 0000000000..95e3bd517c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/devicetree.cb -@@ -0,0 +1,63 @@ -+# SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/x4x -+ device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster -+ device domain 0 on -+ ops x4x_pci_domain_ops # PCI domain -+ subsystemid 0x8086 0x0028 inherit -+ device pci 0.0 on end # Host Bridge -+ device pci 1.0 on end # PCIe x16 2.0 slot -+ device pci 2.0 on end # Integrated graphics controller -+ device pci 2.1 on end # Integrated graphics controller 2 -+ device pci 3.0 off end # ME -+ device pci 3.1 off end # ME -+ chip southbridge/intel/i82801jx # ICH10 -+ register "gpe0_en" = "0x40" -+ -+ # Set AHCI mode. -+ register "sata_port_map" = "0x3f" -+ register "sata_clock_request" = "1" -+ -+ # Enable PCIe ports 0,1 as slots. -+ register "pcie_slot_implemented" = "0x3" -+ -+ device pci 19.0 on end # GBE -+ device pci 1a.0 on end # USB -+ device pci 1a.1 on end # USB -+ device pci 1a.2 on end # USB -+ device pci 1a.7 on end # USB -+ device pci 1b.0 on end # Audio -+ device pci 1c.0 off end # PCIe 1 -+ device pci 1c.1 off end # PCIe 2 -+ device pci 1c.2 off end # PCIe 3 -+ device pci 1c.3 off end # PCIe 4 -+ device pci 1c.4 off end # PCIe 5 -+ device pci 1c.5 off end # PCIe 6 -+ device pci 1d.0 on end # USB -+ device pci 1d.1 on end # USB -+ device pci 1d.2 on end # USB -+ device pci 1d.7 on end # USB -+ device pci 1e.0 on end # PCI bridge -+ device pci 1f.0 on end # LPC bridge -+ device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5) -+ device pci 1f.3 on # SMBus -+ chip drivers/i2c/ck505 # IDT CV194 -+ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff }" -+ register "regs" = "{ 0x15, 0x82, 0xff, 0xff, -+ 0xff, 0x00, 0x00, 0x95, -+ 0x00, 0x65, 0x7d, 0x56, -+ 0x13, 0xc0, 0x00, 0x07, -+ 0x01, 0x0a, 0x64 }" -+ device i2c 69 on end -+ end -+ end -+ device pci 1f.4 off end -+ device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode) -+ device pci 1f.6 off end # Thermal Subsystem -+ end -+ end -+end -diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl -new file mode 100644 -index 0000000000..9ad70469de ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/dsdt.asl -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20090811 // OEM revision -+) -+{ -+ #include -+ -+ OSYS = 2002 -+ // global NVS and variables -+ #include -+ -+ Device (\_SB.PCI0) -+ { -+ #include -+ #include -+ } -+ -+ #include -+} -diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads -new file mode 100644 -index 0000000000..bc81cf4a40 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads -@@ -0,0 +1,16 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ (DP2, -+ Analog, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..fefda9d6f226b88ab67c5b044de30a707df22fbf -GIT binary patch -literal 1917 -zcmd6nO>7%Q6vzLwGv0Mv$FUpJ*ik4iQd_wnX*X`M0y3~p?8a$~>ZXxZMU`4dc9RGb -zTXq_i1Bwd~aNr{c4i)r(goF^M-nek+sY0sMa}Sk>xFFy_FTEfX^Y+7unt+OgkeJbX -zznS;`v-5V=o{ZwwmnN>gY?}>{`7^JBpP$l`EBIwbi0*k&aU)n@v)E -znI_A1T57efS5MGNN5_ut -zt=x`G)EjR#mlhURC^2!A3p33TcBg4-d8JyTiF&hfk}|a#&Dfe2%~V^}=4!QavNzBh -z0Pae^5`gfb?7Q)c(LsP)8 -zQy)2gwgG1S^>aw&0D}Z+-SCcJJF;s)yXJeQ|4N{SU?$I`#$HZa9dWBuxA$6X;VK;%W?Y>I;0P`|*vwAK$S(VB2JSq6g4n -z>oEf8XCt;_Y-iYBWz#3T9EmJ -z2x?*GPeN%?=Fj3+fv~4%I(nv~XF7VOqi5RsAt%13JtW>q=<<;0IkLPSUGL%_1h)2kjaZzuV;`43yCV;I=#Jcyyw@xKE8GGX39@am|0GKhH` -zawsKv^FvHqm+c8*FfFsu??w)Oed@;Mg~21%rCZ%d{x!>-zmv4AyWL1E -xfz+CGUnQ7Y^TD}&c_cQRYlBC+`?m?k6Nuw??s04gg4@4`<@FO{XEbO( -+ -+void mb_get_spd_map(u8 spd_map[4]) -+{ -+ // BTX form factor -+ spd_map[0] = 0x53; -+ spd_map[1] = 0x52; -+ spd_map[2] = 0x51; -+ spd_map[3] = 0x50; -+} -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c -new file mode 100644 -index 0000000000..9993f17c55 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c -@@ -0,0 +1,174 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_NATIVE, -+ .gpio1 = GPIO_MODE_NATIVE, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_GPIO, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_NATIVE, -+ .gpio8 = GPIO_MODE_NATIVE, -+ .gpio9 = GPIO_MODE_GPIO, -+ .gpio10 = GPIO_MODE_GPIO, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_NATIVE, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_NATIVE, -+ .gpio18 = GPIO_MODE_GPIO, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_GPIO, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_GPIO, -+ .gpio31 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio5 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio9 = GPIO_DIR_OUTPUT, -+ .gpio10 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio18 = GPIO_DIR_OUTPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio20 = GPIO_DIR_OUTPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_OUTPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+ .gpio30 = GPIO_DIR_INPUT, -+ .gpio31 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio9 = GPIO_LEVEL_HIGH, -+ .gpio18 = GPIO_LEVEL_HIGH, -+ .gpio20 = GPIO_LEVEL_HIGH, -+ .gpio28 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio13 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_GPIO, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_NATIVE, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_NATIVE, -+ .gpio52 = GPIO_MODE_NATIVE, -+ .gpio53 = GPIO_MODE_NATIVE, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_GPIO, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio32 = GPIO_DIR_INPUT, -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_INPUT, -+ .gpio35 = GPIO_DIR_OUTPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_OUTPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio56 = GPIO_DIR_OUTPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio35 = GPIO_LEVEL_LOW, -+ .gpio49 = GPIO_LEVEL_HIGH, -+ .gpio56 = GPIO_LEVEL_HIGH, -+ .gpio60 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_NATIVE, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_NATIVE, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_NATIVE, -+ .gpio69 = GPIO_MODE_NATIVE, -+ .gpio70 = GPIO_MODE_NATIVE, -+ .gpio71 = GPIO_MODE_NATIVE, -+ .gpio72 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio72 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ }, -+}; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c -new file mode 100644 -index 0000000000..4158bcf899 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ /* coreboot specific header */ -+ 0x11d4194a, /* Analog Devices AD1984A */ -+ 0xbfd40000, /* Subsystem ID */ -+ 10, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ AZALIA_PIN_CFG(0, 0x11, 0x032140f0), -+ AZALIA_PIN_CFG(0, 0x12, 0x21214010), -+ AZALIA_PIN_CFG(0, 0x13, 0x901701f0), -+ AZALIA_PIN_CFG(0, 0x14, 0x03a190f0), -+ AZALIA_PIN_CFG(0, 0x15, 0xb7a70121), -+ AZALIA_PIN_CFG(0, 0x16, 0x9933012e), -+ AZALIA_PIN_CFG(0, 0x17, 0x97a601f0), -+ AZALIA_PIN_CFG(0, 0x1a, 0x90f301f0), -+ AZALIA_PIN_CFG(0, 0x1b, 0x014510f0), -+ AZALIA_PIN_CFG(0, 0x1c, 0x21a19020), -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb -new file mode 100644 -index 0000000000..555b1c1f5c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb -@@ -0,0 +1,10 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/x4x -+ device domain 0 on -+ chip southbridge/intel/i82801jx -+ device pci 1c.0 on end # PCIe 1 -+ device pci 1c.1 on end # PCIe 2 -+ end -+ end -+end --- -2.47.3 - diff --git a/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch new file mode 100644 index 00000000..2d4b8dad --- /dev/null +++ b/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch @@ -0,0 +1,187 @@ +From 1e3e9ea40f4b43b9ffbb390222d8c4a4a67dd332 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 21 Apr 2025 02:58:47 +0100 +Subject: [PATCH 24/51] nb/intel/*: Disable stack overflow debug options + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/e7505/Kconfig | 9 +++++++++ + src/northbridge/intel/gm45/Kconfig | 9 +++++++++ + src/northbridge/intel/haswell/Kconfig | 9 +++++++++ + src/northbridge/intel/i440bx/Kconfig | 13 +++++++++++++ + src/northbridge/intel/i945/Kconfig | 9 +++++++++ + src/northbridge/intel/ironlake/Kconfig | 9 +++++++++ + src/northbridge/intel/pineview/Kconfig | 9 +++++++++ + src/northbridge/intel/sandybridge/Kconfig | 9 +++++++++ + src/northbridge/intel/x4x/Kconfig | 9 +++++++++ + 9 files changed, 85 insertions(+) + +diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig +index 039a7396f8..ddcb986f10 100644 +--- a/src/northbridge/intel/e7505/Kconfig ++++ b/src/northbridge/intel/e7505/Kconfig +@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505 + select NO_CBFS_MCACHE + select SMM_TSEG + select NEED_SMALL_2MB_PAGE_TABLES ++ ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n +diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig +index 35e89b0c88..c5456d0ddf 100644 +--- a/src/northbridge/intel/gm45/Kconfig ++++ b/src/northbridge/intel/gm45/Kconfig +@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE + config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig +index d67cc14660..fa22e35ccb 100644 +--- a/src/northbridge/intel/haswell/Kconfig ++++ b/src/northbridge/intel/haswell/Kconfig +@@ -9,6 +9,15 @@ config NORTHBRIDGE_INTEL_HASWELL + + if NORTHBRIDGE_INTEL_HASWELL + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + config USE_NATIVE_RAMINIT + bool "[NOT COMPLETE] Use native raminit" + default n +diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig +index dbb2d7436b..5e9418b6a9 100644 +--- a/src/northbridge/intel/i440bx/Kconfig ++++ b/src/northbridge/intel/i440bx/Kconfig +@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM + If your board has 4 DIMM slots, you must use select this option, in + your Kconfig file of the board. On boards with 3 DIMM slots, + do _not_ select this option. ++ ++if NORTHBRIDGE_INTEL_I440BX ++ ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ ++endif +diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig +index c4e17f90bf..b12f5be091 100644 +--- a/src/northbridge/intel/i945/Kconfig ++++ b/src/northbridge/intel/i945/Kconfig +@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE + config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig +index 39566a6e5f..f46acf6937 100644 +--- a/src/northbridge/intel/ironlake/Kconfig ++++ b/src/northbridge/intel/ironlake/Kconfig +@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE + config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig +index a05b866dad..50e3a7cdb9 100644 +--- a/src/northbridge/intel/pineview/Kconfig ++++ b/src/northbridge/intel/pineview/Kconfig +@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE + config DOMAIN_RESOURCE_32BIT_LIMIT + default 0xfec00000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig +index 9972a43da0..fe4ac5106c 100644 +--- a/src/northbridge/intel/sandybridge/Kconfig ++++ b/src/northbridge/intel/sandybridge/Kconfig +@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX + default 2 if IGD_DEFAULT_UMA_SIZE_96MB + default 3 if IGD_DEFAULT_UMA_SIZE_128MB + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig +index 646af3510b..069fa0244d 100644 +--- a/src/northbridge/intel/x4x/Kconfig ++++ b/src/northbridge/intel/x4x/Kconfig +@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE + config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch new file mode 100644 index 00000000..28df4126 --- /dev/null +++ b/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch @@ -0,0 +1,708 @@ +From d83715448c0f7467ddf94e5c0a53560c5ff3b86b Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Mon, 30 Sep 2024 20:44:38 -0400 +Subject: [PATCH 25/51] mb/dell: Add Optiplex 780 MT (x4x/ICH10) + +Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/optiplex_780/Kconfig | 40 ++++ + src/mainboard/dell/optiplex_780/Kconfig.name | 4 + + src/mainboard/dell/optiplex_780/Makefile.mk | 10 + + src/mainboard/dell/optiplex_780/acpi/ec.asl | 5 + + .../dell/optiplex_780/acpi/ich10_pci_irqs.asl | 32 ++++ + .../dell/optiplex_780/acpi/superio.asl | 18 ++ + .../dell/optiplex_780/board_info.txt | 6 + + src/mainboard/dell/optiplex_780/cmos.default | 8 + + src/mainboard/dell/optiplex_780/cmos.layout | 72 ++++++++ + src/mainboard/dell/optiplex_780/cstates.c | 8 + + src/mainboard/dell/optiplex_780/devicetree.cb | 63 +++++++ + src/mainboard/dell/optiplex_780/dsdt.asl | 26 +++ + .../dell/optiplex_780/gma-mainboard.ads | 16 ++ + .../optiplex_780/variants/780_mt/data.vbt | Bin 0 -> 1917 bytes + .../optiplex_780/variants/780_mt/early_init.c | 12 ++ + .../dell/optiplex_780/variants/780_mt/gpio.c | 174 ++++++++++++++++++ + .../optiplex_780/variants/780_mt/hda_verb.c | 26 +++ + .../variants/780_mt/overridetree.cb | 10 + + 18 files changed, 530 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_780/Kconfig + create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name + create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk + create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl + create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl + create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl + create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt + create mode 100644 src/mainboard/dell/optiplex_780/cmos.default + create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout + create mode 100644 src/mainboard/dell/optiplex_780/cstates.c + create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb + create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl + create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb + +diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig +new file mode 100644 +index 0000000000..2d06c75c9a +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/Kconfig +@@ -0,0 +1,40 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_DELL_OPTIPLEX_780_COMMON ++ def_bool n ++ select BOARD_ROMSIZE_KB_8192 ++ select CPU_INTEL_SOCKET_LGA775 ++ select DRIVERS_I2C_CK505 ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ select INTEL_GMA_HAVE_VBT ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select NORTHBRIDGE_INTEL_X4X ++ select PCIEXP_ASPM ++ select PCIEXP_CLK_PM ++ select SOUTHBRIDGE_INTEL_I82801JX ++ ++config BOARD_DELL_OPTIPLEX_780_MT ++ select BOARD_DELL_OPTIPLEX_780_COMMON ++ ++if BOARD_DELL_OPTIPLEX_780_COMMON ++ ++config VGA_BIOS_ID ++ default "8086,2e22" ++ ++config MAINBOARD_DIR ++ default "dell/optiplex_780" ++ ++config MAINBOARD_PART_NUMBER ++ default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT ++ ++config OVERRIDE_DEVICETREE ++ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" ++ ++config VARIANT_DIR ++ default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT ++ ++endif # BOARD_DELL_OPTIPLEX_780_COMMON +diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name +new file mode 100644 +index 0000000000..db7f2e8fe3 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/Kconfig.name +@@ -0,0 +1,4 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_DELL_OPTIPLEX_780_MT ++ bool "OptiPlex 780 MT" +diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk +new file mode 100644 +index 0000000000..d462995d75 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/Makefile.mk +@@ -0,0 +1,10 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++ramstage-y += cstates.c ++romstage-y += variants/$(VARIANT_DIR)/gpio.c ++ ++bootblock-y += variants/$(VARIANT_DIR)/early_init.c ++romstage-y += variants/$(VARIANT_DIR)/early_init.c ++ ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads ++ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl +new file mode 100644 +index 0000000000..479296cb76 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl +@@ -0,0 +1,5 @@ ++/* SPDX-License-Identifier: CC-PDDC */ ++ ++/* Please update the license if adding licensable material. */ ++ ++/* dummy */ +diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl +new file mode 100644 +index 0000000000..b7588dcc41 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* This is board specific information: ++ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 ++ */ ++ ++If (PICM) { ++ Return (Package() { ++ /* PCI slot */ ++ Package() { 0x0001ffff, 0, 0, 0x14}, ++ Package() { 0x0001ffff, 1, 0, 0x15}, ++ Package() { 0x0001ffff, 2, 0, 0x16}, ++ Package() { 0x0001ffff, 3, 0, 0x17}, ++ ++ Package() { 0x0002ffff, 0, 0, 0x15}, ++ Package() { 0x0002ffff, 1, 0, 0x16}, ++ Package() { 0x0002ffff, 2, 0, 0x17}, ++ Package() { 0x0002ffff, 3, 0, 0x14}, ++ }) ++} Else { ++ Return (Package() { ++ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, ++ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, ++ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, ++ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, ++ ++ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, ++ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, ++ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, ++ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, ++ }) ++} +diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl +new file mode 100644 +index 0000000000..9f3900b86c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl +@@ -0,0 +1,18 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#undef SUPERIO_DEV ++#undef SUPERIO_PNP_BASE ++#undef IT8720F_SHOW_SP1 ++#undef IT8720F_SHOW_SP2 ++#undef IT8720F_SHOW_EC ++#undef IT8720F_SHOW_KBCK ++#undef IT8720F_SHOW_KBCM ++#undef IT8720F_SHOW_GPIO ++#undef IT8720F_SHOW_CIR ++#define SUPERIO_DEV SIO0 ++#define SUPERIO_PNP_BASE 0x2e ++#define IT8720F_SHOW_EC 1 ++#define IT8720F_SHOW_KBCK 1 ++#define IT8720F_SHOW_KBCM 1 ++#define IT8720F_SHOW_GPIO 1 ++#include +diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt +new file mode 100644 +index 0000000000..aaf657b583 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/board_info.txt +@@ -0,0 +1,6 @@ ++Category: desktop ++Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1 ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y +diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default +new file mode 100644 +index 0000000000..23f0e55f3e +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/cmos.default +@@ -0,0 +1,8 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Disable ++nmi=Enable ++sata_mode=AHCI ++gfx_uma_size=64M +diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout +new file mode 100644 +index 0000000000..9f5012adb4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/cmos.layout +@@ -0,0 +1,72 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++ ++# coreboot config options: southbridge ++408 1 e 10 sata_mode ++409 2 e 7 power_on_after_fail ++411 1 e 1 nmi ++ ++# coreboot config options: cpu ++ ++# coreboot config options: northbridge ++432 4 e 11 gfx_uma_size ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++2 0 Enable ++2 1 Disable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++10 0 AHCI ++10 1 Compatible ++11 1 4M ++11 2 8M ++11 3 16M ++11 4 32M ++11 5 48M ++11 6 64M ++11 7 128M ++11 8 256M ++11 9 96M ++11 10 160M ++11 11 224M ++11 12 352M ++ ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 983 984 +diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c +new file mode 100644 +index 0000000000..4adf0edc63 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/cstates.c +@@ -0,0 +1,8 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++int get_cst_entries(const acpi_cstate_t **entries) ++{ ++ return 0; ++} +diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb +new file mode 100644 +index 0000000000..95e3bd517c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/devicetree.cb +@@ -0,0 +1,63 @@ ++# SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster ++ device domain 0 on ++ ops x4x_pci_domain_ops # PCI domain ++ subsystemid 0x8086 0x0028 inherit ++ device pci 0.0 on end # Host Bridge ++ device pci 1.0 on end # PCIe x16 2.0 slot ++ device pci 2.0 on end # Integrated graphics controller ++ device pci 2.1 on end # Integrated graphics controller 2 ++ device pci 3.0 off end # ME ++ device pci 3.1 off end # ME ++ chip southbridge/intel/i82801jx # ICH10 ++ register "gpe0_en" = "0x40" ++ ++ # Set AHCI mode. ++ register "sata_port_map" = "0x3f" ++ register "sata_clock_request" = "1" ++ ++ # Enable PCIe ports 0,1 as slots. ++ register "pcie_slot_implemented" = "0x3" ++ ++ device pci 19.0 on end # GBE ++ device pci 1a.0 on end # USB ++ device pci 1a.1 on end # USB ++ device pci 1a.2 on end # USB ++ device pci 1a.7 on end # USB ++ device pci 1b.0 on end # Audio ++ device pci 1c.0 off end # PCIe 1 ++ device pci 1c.1 off end # PCIe 2 ++ device pci 1c.2 off end # PCIe 3 ++ device pci 1c.3 off end # PCIe 4 ++ device pci 1c.4 off end # PCIe 5 ++ device pci 1c.5 off end # PCIe 6 ++ device pci 1d.0 on end # USB ++ device pci 1d.1 on end # USB ++ device pci 1d.2 on end # USB ++ device pci 1d.7 on end # USB ++ device pci 1e.0 on end # PCI bridge ++ device pci 1f.0 on end # LPC bridge ++ device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5) ++ device pci 1f.3 on # SMBus ++ chip drivers/i2c/ck505 # IDT CV194 ++ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff }" ++ register "regs" = "{ 0x15, 0x82, 0xff, 0xff, ++ 0xff, 0x00, 0x00, 0x95, ++ 0x00, 0x65, 0x7d, 0x56, ++ 0x13, 0xc0, 0x00, 0x07, ++ 0x01, 0x0a, 0x64 }" ++ device i2c 69 on end ++ end ++ end ++ device pci 1f.4 off end ++ device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode) ++ device pci 1f.6 off end # Thermal Subsystem ++ end ++ end ++end +diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl +new file mode 100644 +index 0000000000..9ad70469de +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/dsdt.asl +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20090811 // OEM revision ++) ++{ ++ #include ++ ++ OSYS = 2002 ++ // global NVS and variables ++ #include ++ ++ Device (\_SB.PCI0) ++ { ++ #include ++ #include ++ } ++ ++ #include ++} +diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads +new file mode 100644 +index 0000000000..bc81cf4a40 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads +@@ -0,0 +1,16 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (DP2, ++ Analog, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..fefda9d6f226b88ab67c5b044de30a707df22fbf +GIT binary patch +literal 1917 +zcmd6nO>7%Q6vzLwGv0Mv$FUpJ*ik4iQd_wnX*X`M0y3~p?8a$~>ZXxZMU`4dc9RGb +zTXq_i1Bwd~aNr{c4i)r(goF^M-nek+sY0sMa}Sk>xFFy_FTEfX^Y+7unt+OgkeJbX +zznS;`v-5V=o{ZwwmnN>gY?}>{`7^JBpP$l`EBIwbi0*k&aU)n@v)E +znI_A1T57efS5MGNN5_ut +zt=x`G)EjR#mlhURC^2!A3p33TcBg4-d8JyTiF&hfk}|a#&Dfe2%~V^}=4!QavNzBh +z0Pae^5`gfb?7Q)c(LsP)8 +zQy)2gwgG1S^>aw&0D}Z+-SCcJJF;s)yXJeQ|4N{SU?$I`#$HZa9dWBuxA$6X;VK;%W?Y>I;0P`|*vwAK$S(VB2JSq6g4n +z>oEf8XCt;_Y-iYBWz#3T9EmJ +z2x?*GPeN%?=Fj3+fv~4%I(nv~XF7VOqi5RsAt%13JtW>q=<<;0IkLPSUGL%_1h)2kjaZzuV;`43yCV;I=#Jcyyw@xKE8GGX39@am|0GKhH` +zawsKv^FvHqm+c8*FfFsu??w)Oed@;Mg~21%rCZ%d{x!>-zmv4AyWL1E +xfz+CGUnQ7Y^TD}&c_cQRYlBC+`?m?k6Nuw??s04gg4@4`<@FO{XEbO( ++ ++void mb_get_spd_map(u8 spd_map[4]) ++{ ++ // BTX form factor ++ spd_map[0] = 0x53; ++ spd_map[1] = 0x52; ++ spd_map[2] = 0x51; ++ spd_map[3] = 0x50; ++} +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c +new file mode 100644 +index 0000000000..9993f17c55 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c +@@ -0,0 +1,174 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_NATIVE, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_GPIO, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_NATIVE, ++ .gpio8 = GPIO_MODE_NATIVE, ++ .gpio9 = GPIO_MODE_GPIO, ++ .gpio10 = GPIO_MODE_GPIO, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_NATIVE, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_NATIVE, ++ .gpio18 = GPIO_MODE_GPIO, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_GPIO, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio5 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio9 = GPIO_DIR_OUTPUT, ++ .gpio10 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio18 = GPIO_DIR_OUTPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio20 = GPIO_DIR_OUTPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_INPUT, ++ .gpio31 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio9 = GPIO_LEVEL_HIGH, ++ .gpio18 = GPIO_LEVEL_HIGH, ++ .gpio20 = GPIO_LEVEL_HIGH, ++ .gpio28 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio13 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_GPIO, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_NATIVE, ++ .gpio52 = GPIO_MODE_NATIVE, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio32 = GPIO_DIR_INPUT, ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio35 = GPIO_DIR_OUTPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio56 = GPIO_DIR_OUTPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio35 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_HIGH, ++ .gpio56 = GPIO_LEVEL_HIGH, ++ .gpio60 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_NATIVE, ++ .gpio69 = GPIO_MODE_NATIVE, ++ .gpio70 = GPIO_MODE_NATIVE, ++ .gpio71 = GPIO_MODE_NATIVE, ++ .gpio72 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio72 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ }, ++}; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c +new file mode 100644 +index 0000000000..4158bcf899 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header */ ++ 0x11d4194a, /* Analog Devices AD1984A */ ++ 0xbfd40000, /* Subsystem ID */ ++ 10, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ AZALIA_PIN_CFG(0, 0x11, 0x032140f0), ++ AZALIA_PIN_CFG(0, 0x12, 0x21214010), ++ AZALIA_PIN_CFG(0, 0x13, 0x901701f0), ++ AZALIA_PIN_CFG(0, 0x14, 0x03a190f0), ++ AZALIA_PIN_CFG(0, 0x15, 0xb7a70121), ++ AZALIA_PIN_CFG(0, 0x16, 0x9933012e), ++ AZALIA_PIN_CFG(0, 0x17, 0x97a601f0), ++ AZALIA_PIN_CFG(0, 0x1a, 0x90f301f0), ++ AZALIA_PIN_CFG(0, 0x1b, 0x014510f0), ++ AZALIA_PIN_CFG(0, 0x1c, 0x21a19020), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb +new file mode 100644 +index 0000000000..555b1c1f5c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb +@@ -0,0 +1,10 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device domain 0 on ++ chip southbridge/intel/i82801jx ++ device pci 1c.0 on end # PCIe 1 ++ device pci 1c.1 on end # PCIe 2 ++ end ++ end ++end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch deleted file mode 100644 index c126ee58..00000000 --- a/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch +++ /dev/null @@ -1,326 +0,0 @@ -From bfd5f6628a69d8704a84b30c4027149fe1b21efa Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Wed, 30 Oct 2024 20:55:25 -0600 -Subject: [PATCH 25/48] mb/dell/optiplex_780: Add USFF variant - -Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/optiplex_780/Kconfig | 5 + - src/mainboard/dell/optiplex_780/Kconfig.name | 3 + - .../optiplex_780/variants/780_usff/data.vbt | Bin 0 -> 1917 bytes - .../variants/780_usff/early_init.c | 9 + - .../optiplex_780/variants/780_usff/gpio.c | 166 ++++++++++++++++++ - .../optiplex_780/variants/780_usff/hda_verb.c | 26 +++ - .../variants/780_usff/overridetree.cb | 10 ++ - 7 files changed, 219 insertions(+) - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb - -diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig -index 2d06c75c9a..fc649e35d5 100644 ---- a/src/mainboard/dell/optiplex_780/Kconfig -+++ b/src/mainboard/dell/optiplex_780/Kconfig -@@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON - config BOARD_DELL_OPTIPLEX_780_MT - select BOARD_DELL_OPTIPLEX_780_COMMON - -+config BOARD_DELL_OPTIPLEX_780_USFF -+ select BOARD_DELL_OPTIPLEX_780_COMMON -+ - if BOARD_DELL_OPTIPLEX_780_COMMON - - config VGA_BIOS_ID -@@ -30,11 +33,13 @@ config MAINBOARD_DIR - - config MAINBOARD_PART_NUMBER - default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT -+ default "OptiPlex 780 USFF" if BOARD_DELL_OPTIPLEX_780_USFF - - config OVERRIDE_DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" - - config VARIANT_DIR - default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT -+ default "780_usff" if BOARD_DELL_OPTIPLEX_780_USFF - - endif # BOARD_DELL_OPTIPLEX_780_COMMON -diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name -index db7f2e8fe3..bc84c82a79 100644 ---- a/src/mainboard/dell/optiplex_780/Kconfig.name -+++ b/src/mainboard/dell/optiplex_780/Kconfig.name -@@ -2,3 +2,6 @@ - - config BOARD_DELL_OPTIPLEX_780_MT - bool "OptiPlex 780 MT" -+ -+config BOARD_DELL_OPTIPLEX_780_USFF -+ bool "OptiPlex 780 USFF" -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..dbd764f285ed18f7ee9c54bc777560138bd9b5f7 -GIT binary patch -literal 1917 -zcmd6nO>7%Q6vzLwGv3{}j$^l`v7@w1q*9sEq+2(b3K>`@c5#TSx@iP+W+B10OwbsGtX=N(gc4jSGjKDkP+yIUo^nsel8$^ny^9H?td8Ra=EiCEn=G -z@6DV4?!2AdojnUv^Rirgvs$heXUkGs9S+{Jc2WPhP0buTak^BTFP@&N9-E$(UtuSX -zS{r`=b+EX|Ig`2a*^5oDdG>8jE-1BBxs`*jgrf_sj_fP;%L|PwURRcCFBMCroNRQv -zmp$2TUhc}qJMB(u#jDG@x6(N85thC4%Z=8hiN}lj&zb2~``u3C;?lCrPQOTnInFqB -zhvdwqWv?lxTb=fVEH;~RPHDPw&g*&|s$pU7!7x2mLBtAF!g>K`zPnkx!DpPHuk6{_zc*0qi7)Aet$T -z1ks@8hWS#+6cI5)j1oD86{5PX8Zu2(^OC6M`xo)V)Ow=U6P12c -z=U0uNC9T9v{)-|#h(mSX*hSA8)ZeocL7l4J&!{RSO{6~oTtyn535j!RQh#GA*wTF8 -zvasRbO~d!?*FbM3K`W?lHx=v*(jiARIhWyh4^io|;n?@1H>uqJy>0sjV-Dt)_=%bE -zgNO3D@uE5m+7aqi?Y8b+inye%Z=HUmgBtaZ3Lc%OLt+bo+)5BjVwT<{mxT`nde$vb -zV99s{>`r76L#Hr6XW6r|>HT47I`**Q#Vu0QW!^VP-9S{xXzpq_zS#9k-;aXz?b+S!Ne$Kkk6dq&Hj-x+kx1W-4#E&beDT*S)=&NoSE?<-w!G@~aW()0ZN4O&=Q+nZa)p%Vd$k-_$a= -T#w3FFBiyj -+ -+void mb_get_spd_map(u8 spd_map[4]) -+{ -+ spd_map[0] = 0x50; -+ spd_map[2] = 0x52; -+} -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c -new file mode 100644 -index 0000000000..389f4077d7 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c -@@ -0,0 +1,166 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_NATIVE, -+ .gpio1 = GPIO_MODE_NATIVE, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_GPIO, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_NATIVE, -+ .gpio8 = GPIO_MODE_NATIVE, -+ .gpio9 = GPIO_MODE_GPIO, -+ .gpio10 = GPIO_MODE_GPIO, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_NATIVE, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_NATIVE, -+ .gpio18 = GPIO_MODE_GPIO, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_GPIO, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_GPIO, -+ .gpio31 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio5 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio9 = GPIO_DIR_OUTPUT, -+ .gpio10 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio18 = GPIO_DIR_OUTPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio20 = GPIO_DIR_OUTPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_OUTPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+ .gpio30 = GPIO_DIR_INPUT, -+ .gpio31 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio9 = GPIO_LEVEL_HIGH, -+ .gpio18 = GPIO_LEVEL_HIGH, -+ .gpio20 = GPIO_LEVEL_HIGH, -+ .gpio28 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio13 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_GPIO, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_NATIVE, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_NATIVE, -+ .gpio52 = GPIO_MODE_NATIVE, -+ .gpio53 = GPIO_MODE_NATIVE, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_GPIO, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio32 = GPIO_DIR_INPUT, -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_INPUT, -+ .gpio35 = GPIO_DIR_OUTPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_OUTPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio56 = GPIO_DIR_OUTPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio35 = GPIO_LEVEL_LOW, -+ .gpio49 = GPIO_LEVEL_HIGH, -+ .gpio56 = GPIO_LEVEL_HIGH, -+ .gpio60 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio72 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio72 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ }, -+}; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c -new file mode 100644 -index 0000000000..c94e06b156 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ /* coreboot specific header */ -+ 0x11d4194a, /* Analog Devices AD1984A */ -+ 0x10280420, /* Subsystem ID */ -+ 10, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ AZALIA_PIN_CFG(0, 0x11, 0x02214040), -+ AZALIA_PIN_CFG(0, 0x12, 0x01014010), -+ AZALIA_PIN_CFG(0, 0x13, 0x991301f0), -+ AZALIA_PIN_CFG(0, 0x14, 0x02a19020), -+ AZALIA_PIN_CFG(0, 0x15, 0x01813030), -+ AZALIA_PIN_CFG(0, 0x16, 0x413301f0), -+ AZALIA_PIN_CFG(0, 0x17, 0x41a601f0), -+ AZALIA_PIN_CFG(0, 0x1a, 0x41f301f0), -+ AZALIA_PIN_CFG(0, 0x1b, 0x414501f0), -+ AZALIA_PIN_CFG(0, 0x1c, 0x413301f0), -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb -new file mode 100644 -index 0000000000..555b1c1f5c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb -@@ -0,0 +1,10 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/x4x -+ device domain 0 on -+ chip southbridge/intel/i82801jx -+ device pci 1c.0 on end # PCIe 1 -+ device pci 1c.1 on end # PCIe 2 -+ end -+ end -+end --- -2.47.3 - diff --git a/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch new file mode 100644 index 00000000..8948aee7 --- /dev/null +++ b/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch @@ -0,0 +1,326 @@ +From 3a5fa257c1b74c6e9e3556147114fc7691dc9e49 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Wed, 30 Oct 2024 20:55:25 -0600 +Subject: [PATCH 26/51] mb/dell/optiplex_780: Add USFF variant + +Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/optiplex_780/Kconfig | 5 + + src/mainboard/dell/optiplex_780/Kconfig.name | 3 + + .../optiplex_780/variants/780_usff/data.vbt | Bin 0 -> 1917 bytes + .../variants/780_usff/early_init.c | 9 + + .../optiplex_780/variants/780_usff/gpio.c | 166 ++++++++++++++++++ + .../optiplex_780/variants/780_usff/hda_verb.c | 26 +++ + .../variants/780_usff/overridetree.cb | 10 ++ + 7 files changed, 219 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb + +diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig +index 2d06c75c9a..fc649e35d5 100644 +--- a/src/mainboard/dell/optiplex_780/Kconfig ++++ b/src/mainboard/dell/optiplex_780/Kconfig +@@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON + config BOARD_DELL_OPTIPLEX_780_MT + select BOARD_DELL_OPTIPLEX_780_COMMON + ++config BOARD_DELL_OPTIPLEX_780_USFF ++ select BOARD_DELL_OPTIPLEX_780_COMMON ++ + if BOARD_DELL_OPTIPLEX_780_COMMON + + config VGA_BIOS_ID +@@ -30,11 +33,13 @@ config MAINBOARD_DIR + + config MAINBOARD_PART_NUMBER + default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT ++ default "OptiPlex 780 USFF" if BOARD_DELL_OPTIPLEX_780_USFF + + config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + + config VARIANT_DIR + default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT ++ default "780_usff" if BOARD_DELL_OPTIPLEX_780_USFF + + endif # BOARD_DELL_OPTIPLEX_780_COMMON +diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name +index db7f2e8fe3..bc84c82a79 100644 +--- a/src/mainboard/dell/optiplex_780/Kconfig.name ++++ b/src/mainboard/dell/optiplex_780/Kconfig.name +@@ -2,3 +2,6 @@ + + config BOARD_DELL_OPTIPLEX_780_MT + bool "OptiPlex 780 MT" ++ ++config BOARD_DELL_OPTIPLEX_780_USFF ++ bool "OptiPlex 780 USFF" +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..dbd764f285ed18f7ee9c54bc777560138bd9b5f7 +GIT binary patch +literal 1917 +zcmd6nO>7%Q6vzLwGv3{}j$^l`v7@w1q*9sEq+2(b3K>`@c5#TSx@iP+W+B10OwbsGtX=N(gc4jSGjKDkP+yIUo^nsel8$^ny^9H?td8Ra=EiCEn=G +z@6DV4?!2AdojnUv^Rirgvs$heXUkGs9S+{Jc2WPhP0buTak^BTFP@&N9-E$(UtuSX +zS{r`=b+EX|Ig`2a*^5oDdG>8jE-1BBxs`*jgrf_sj_fP;%L|PwURRcCFBMCroNRQv +zmp$2TUhc}qJMB(u#jDG@x6(N85thC4%Z=8hiN}lj&zb2~``u3C;?lCrPQOTnInFqB +zhvdwqWv?lxTb=fVEH;~RPHDPw&g*&|s$pU7!7x2mLBtAF!g>K`zPnkx!DpPHuk6{_zc*0qi7)Aet$T +z1ks@8hWS#+6cI5)j1oD86{5PX8Zu2(^OC6M`xo)V)Ow=U6P12c +z=U0uNC9T9v{)-|#h(mSX*hSA8)ZeocL7l4J&!{RSO{6~oTtyn535j!RQh#GA*wTF8 +zvasRbO~d!?*FbM3K`W?lHx=v*(jiARIhWyh4^io|;n?@1H>uqJy>0sjV-Dt)_=%bE +zgNO3D@uE5m+7aqi?Y8b+inye%Z=HUmgBtaZ3Lc%OLt+bo+)5BjVwT<{mxT`nde$vb +zV99s{>`r76L#Hr6XW6r|>HT47I`**Q#Vu0QW!^VP-9S{xXzpq_zS#9k-;aXz?b+S!Ne$Kkk6dq&Hj-x+kx1W-4#E&beDT*S)=&NoSE?<-w!G@~aW()0ZN4O&=Q+nZa)p%Vd$k-_$a= +T#w3FFBiyj ++ ++void mb_get_spd_map(u8 spd_map[4]) ++{ ++ spd_map[0] = 0x50; ++ spd_map[2] = 0x52; ++} +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c +new file mode 100644 +index 0000000000..389f4077d7 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c +@@ -0,0 +1,166 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_NATIVE, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_GPIO, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_NATIVE, ++ .gpio8 = GPIO_MODE_NATIVE, ++ .gpio9 = GPIO_MODE_GPIO, ++ .gpio10 = GPIO_MODE_GPIO, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_NATIVE, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_NATIVE, ++ .gpio18 = GPIO_MODE_GPIO, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_GPIO, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio5 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio9 = GPIO_DIR_OUTPUT, ++ .gpio10 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio18 = GPIO_DIR_OUTPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio20 = GPIO_DIR_OUTPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_INPUT, ++ .gpio31 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio9 = GPIO_LEVEL_HIGH, ++ .gpio18 = GPIO_LEVEL_HIGH, ++ .gpio20 = GPIO_LEVEL_HIGH, ++ .gpio28 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio13 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_GPIO, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_NATIVE, ++ .gpio52 = GPIO_MODE_NATIVE, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio32 = GPIO_DIR_INPUT, ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio35 = GPIO_DIR_OUTPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio56 = GPIO_DIR_OUTPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio35 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_HIGH, ++ .gpio56 = GPIO_LEVEL_HIGH, ++ .gpio60 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio72 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio72 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ }, ++}; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c +new file mode 100644 +index 0000000000..c94e06b156 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header */ ++ 0x11d4194a, /* Analog Devices AD1984A */ ++ 0x10280420, /* Subsystem ID */ ++ 10, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ AZALIA_PIN_CFG(0, 0x11, 0x02214040), ++ AZALIA_PIN_CFG(0, 0x12, 0x01014010), ++ AZALIA_PIN_CFG(0, 0x13, 0x991301f0), ++ AZALIA_PIN_CFG(0, 0x14, 0x02a19020), ++ AZALIA_PIN_CFG(0, 0x15, 0x01813030), ++ AZALIA_PIN_CFG(0, 0x16, 0x413301f0), ++ AZALIA_PIN_CFG(0, 0x17, 0x41a601f0), ++ AZALIA_PIN_CFG(0, 0x1a, 0x41f301f0), ++ AZALIA_PIN_CFG(0, 0x1b, 0x414501f0), ++ AZALIA_PIN_CFG(0, 0x1c, 0x413301f0), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb +new file mode 100644 +index 0000000000..555b1c1f5c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb +@@ -0,0 +1,10 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device domain 0 on ++ chip southbridge/intel/i82801jx ++ device pci 1c.0 on end # PCIe 1 ++ device pci 1c.1 on end # PCIe 2 ++ end ++ end ++end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch deleted file mode 100644 index 4c693f65..00000000 --- a/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 82f47133c20abc720f5d5fa8a54be465ebd95f28 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 6 Jan 2025 01:53:53 +0000 -Subject: [PATCH 26/48] src/intel/x4x: Disable stack overflow debug - -Signed-off-by: Leah Rowe ---- - src/northbridge/intel/x4x/Kconfig | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 069fa0244d..8c70344846 100644 ---- a/src/northbridge/intel/x4x/Kconfig -+++ b/src/northbridge/intel/x4x/Kconfig -@@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER - int - default 256 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - # This number must be equal or lower than what's reported in ACPI PCI _CRS - config DOMAIN_RESOURCE_32BIT_LIMIT - default 0xfec00000 --- -2.47.3 - diff --git a/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch deleted file mode 100644 index da5ae94d..00000000 --- a/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 5c4439fb513c315ef3effff19146b331c492fa9b Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 22 Apr 2025 10:21:59 +0100 -Subject: [PATCH 27/48] hp/8300cmt: remove xhci_overcurrent_mapping - -No longer needed, as per the following commit: - -commit a3d1e6c4806e6c0e2e744be3a03fce12f21778d1 -Author: Keith Hui -Date: Tue Dec 31 18:19:31 2024 -0500 - - sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping - -Removing this from the devicetree also allows the -board to compile, otherwise an error is thrown: - -build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:10: error: 'const struct southbridge_intel_bd82x6x_config' has no member named 'xhci_overcurrent_mapping' - 147 | .xhci_overcurrent_mapping = 0x00000c03, - | ^~~~~~~~~~~~~~~~~~~~~~~~ -build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:37: error: excess elements in struct initializer [-Werror] - 147 | .xhci_overcurrent_mapping = 0x00000c03, - -Signed-off-by: Leah Rowe ---- - src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -index 3d21739b72..3a0b6d5c59 100644 ---- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -@@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - register "superspeed_capable_ports" = "0x0000000f" -- register "xhci_overcurrent_mapping" = "0x00000c03" - register "xhci_switchable_ports" = "0x0000000f" - register "usb_port_config" = "{ - { 1, 0, 0 }, --- -2.47.3 - diff --git a/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch new file mode 100644 index 00000000..1cbae3bf --- /dev/null +++ b/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch @@ -0,0 +1,33 @@ +From 5573eeadf45023d49f09606c6219004e20ba4b3c Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 6 Jan 2025 01:53:53 +0000 +Subject: [PATCH 27/51] src/intel/x4x: Disable stack overflow debug + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/x4x/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig +index 069fa0244d..8c70344846 100644 +--- a/src/northbridge/intel/x4x/Kconfig ++++ b/src/northbridge/intel/x4x/Kconfig +@@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER + int + default 256 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + # This number must be equal or lower than what's reported in ACPI PCI _CRS + config DOMAIN_RESOURCE_32BIT_LIMIT + default 0xfec00000 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch b/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch deleted file mode 100644 index 52b49b36..00000000 --- a/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 71ec1f7a6480e72b77a567f8cc0c2673a5e7905f Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Wed, 11 Dec 2024 01:06:01 +0000 -Subject: [PATCH 28/48] dell/3050micro: disable nvme hotplug - -in my testing, when running my 3050micro for a few days, -the nvme would sometimes randomly rename. - -e.g. nvme0n1 renamed to nvme0n2 - -this might cause crashes in linux, if booting only from the -nvme. in my case, i was booting from mdraid (sata+nvme) and -every few days, the nvme would rename at least once, causing -my RAID to become unsynced. since i'm using RAID1, this was -OK and I could simply re-sync the array, but this is quite -precarious indeed. if you're using raid0, that will potentially -corrupt your RAID array indefinitely. - -this same issue manifested on the T480/T480 thinkpads, and -S3 resume would break because of that, when booting from nvme, -because the nvme would be "unplugged" and appear to linux as a -new device (the one that you booted from). - -the fix there was to disable hotplugging on that pci-e slot -for the nvme, so apply the same fix here for 3050 micro - -Signed-off-by: Leah Rowe ---- - .../dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb -index c5f1749b2c..ff48a8121a 100644 ---- a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb -+++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb -@@ -46,7 +46,7 @@ chip soc/intel/skylake - register "PcieRpAdvancedErrorReporting[20]" = "1" - register "PcieRpLtrEnable[20]" = "true" - register "PcieRpClkSrcNumber[20]" = "3" -- register "PcieRpHotPlug[20]" = "1" -+ register "PcieRpHotPlug[20]" = "0" - end - - end --- -2.47.3 - diff --git a/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch new file mode 100644 index 00000000..d42b03fc --- /dev/null +++ b/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch @@ -0,0 +1,42 @@ +From 2973ad1738fb6c1ebd2a92d008e1cbd39c74abb2 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 22 Apr 2025 10:21:59 +0100 +Subject: [PATCH 28/51] hp/8300cmt: remove xhci_overcurrent_mapping + +No longer needed, as per the following commit: + +commit a3d1e6c4806e6c0e2e744be3a03fce12f21778d1 +Author: Keith Hui +Date: Tue Dec 31 18:19:31 2024 -0500 + + sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping + +Removing this from the devicetree also allows the +board to compile, otherwise an error is thrown: + +build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:10: error: 'const struct southbridge_intel_bd82x6x_config' has no member named 'xhci_overcurrent_mapping' + 147 | .xhci_overcurrent_mapping = 0x00000c03, + | ^~~~~~~~~~~~~~~~~~~~~~~~ +build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:37: error: excess elements in struct initializer [-Werror] + 147 | .xhci_overcurrent_mapping = 0x00000c03, + +Signed-off-by: Leah Rowe +--- + src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb +index 3d21739b72..3a0b6d5c59 100644 +--- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb +@@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" +- register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 0, 0 }, +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch b/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch new file mode 100644 index 00000000..fcfdf827 --- /dev/null +++ b/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch @@ -0,0 +1,47 @@ +From ff57e763d1f966584ac9b68fa1a1f204626a577b Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Wed, 11 Dec 2024 01:06:01 +0000 +Subject: [PATCH 29/51] dell/3050micro: disable nvme hotplug + +in my testing, when running my 3050micro for a few days, +the nvme would sometimes randomly rename. + +e.g. nvme0n1 renamed to nvme0n2 + +this might cause crashes in linux, if booting only from the +nvme. in my case, i was booting from mdraid (sata+nvme) and +every few days, the nvme would rename at least once, causing +my RAID to become unsynced. since i'm using RAID1, this was +OK and I could simply re-sync the array, but this is quite +precarious indeed. if you're using raid0, that will potentially +corrupt your RAID array indefinitely. + +this same issue manifested on the T480/T480 thinkpads, and +S3 resume would break because of that, when booting from nvme, +because the nvme would be "unplugged" and appear to linux as a +new device (the one that you booted from). + +the fix there was to disable hotplugging on that pci-e slot +for the nvme, so apply the same fix here for 3050 micro + +Signed-off-by: Leah Rowe +--- + .../dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb +index c5f1749b2c..ff48a8121a 100644 +--- a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb ++++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb +@@ -46,7 +46,7 @@ chip soc/intel/skylake + register "PcieRpAdvancedErrorReporting[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" + register "PcieRpClkSrcNumber[20]" = "3" +- register "PcieRpHotPlug[20]" = "1" ++ register "PcieRpHotPlug[20]" = "0" + end + + end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch deleted file mode 100644 index 78ccf785..00000000 --- a/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 95a0af0eea56e1bddcb243ed135835448b90fa56 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 6 Jan 2025 01:36:23 +0000 -Subject: [PATCH 29/48] src/intel/skylake: Disable stack overflow debug options - -The option was appearing in T480/3050micro configs of lbmk, -after updating on the coreboot/next uprev for 20241206 rev8: - -CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y - -I did some digging. See coreboot commit: - -commit 51cc2bacb6b07279b97e9934d079060475481fb6 -Author: Subrata Banik -Date: Fri Dec 13 13:07:28 2024 +0530 - - soc/intel/pantherlake: Disable stack overflow debug options - -Well now: - -I'm disabling this behaviour on Skylake, for the same -behaviour, because I want as few behaviour changes in general, -as possible, for the rev8 release. - -According to Subrata's patch, which was for Pantherlake, -without this change, stack corruption can occur on verstage -and romstage early on. Please look at that coreboot patch, -referenced above, for clarity. - -I see no harm in disabling this option for Skylake, since -the behaviour that it otherwise enables was not present -before. - -Signed-off-by: Leah Rowe ---- - src/soc/intel/skylake/Kconfig | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 7c530f2c75..70c2a7643c 100644 ---- a/src/soc/intel/skylake/Kconfig -+++ b/src/soc/intel/skylake/Kconfig -@@ -131,6 +131,15 @@ config DCACHE_RAM_SIZE - The size of the cache-as-ram region required during bootblock - and/or romstage. - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - config DCACHE_BSP_STACK_SIZE - hex - default 0x20400 if FSP_USES_CB_STACK --- -2.47.3 - diff --git a/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch deleted file mode 100644 index e5f4987b..00000000 --- a/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 7d94457ba0e2be10d781c5fd0659d895c9b558b1 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Thu, 26 Dec 2024 19:45:20 +0000 -Subject: [PATCH 30/48] soc/intel/skylake: Don't compress FSP-S - -Build systems like lbmk need to reproducibly insert -certain vendor files on release images. - -Compression isn't always reproducible, and making it -so costs a lot more time than simply disabling compression. - -With this change, the FSP-S module will now be inserted -without compression, which means that there will now be -about 40KB of extra space used in the flash. - -Signed-off-by: Leah Rowe ---- - src/soc/intel/skylake/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 70c2a7643c..a2854923e7 100644 ---- a/src/soc/intel/skylake/Kconfig -+++ b/src/soc/intel/skylake/Kconfig -@@ -14,7 +14,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE - select DRAM_SUPPORT_DDR4 - select DRIVERS_USB_ACPI - select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 -- select FSP_COMPRESS_FSP_S_LZ4 -+# select FSP_COMPRESS_FSP_S_LZ4 - select FSP_M_XIP - select GENERIC_GPIO_LIB - select HAVE_FSP_GOP --- -2.47.3 - diff --git a/config/coreboot/default/patches/0030-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0030-src-intel-skylake-Disable-stack-overflow-debug-optio.patch new file mode 100644 index 00000000..695a03a7 --- /dev/null +++ b/config/coreboot/default/patches/0030-src-intel-skylake-Disable-stack-overflow-debug-optio.patch @@ -0,0 +1,61 @@ +From 7c4df892425e076b1d2768f9b99362f58e7872dc Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 6 Jan 2025 01:36:23 +0000 +Subject: [PATCH 30/51] src/intel/skylake: Disable stack overflow debug options + +The option was appearing in T480/3050micro configs of lbmk, +after updating on the coreboot/next uprev for 20241206 rev8: + +CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y + +I did some digging. See coreboot commit: + +commit 51cc2bacb6b07279b97e9934d079060475481fb6 +Author: Subrata Banik +Date: Fri Dec 13 13:07:28 2024 +0530 + + soc/intel/pantherlake: Disable stack overflow debug options + +Well now: + +I'm disabling this behaviour on Skylake, for the same +behaviour, because I want as few behaviour changes in general, +as possible, for the rev8 release. + +According to Subrata's patch, which was for Pantherlake, +without this change, stack corruption can occur on verstage +and romstage early on. Please look at that coreboot patch, +referenced above, for clarity. + +I see no harm in disabling this option for Skylake, since +the behaviour that it otherwise enables was not present +before. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/skylake/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig +index c76239936a..f8ff8cfa7a 100644 +--- a/src/soc/intel/skylake/Kconfig ++++ b/src/soc/intel/skylake/Kconfig +@@ -136,6 +136,15 @@ config DCACHE_RAM_SIZE + The size of the cache-as-ram region required during bootblock + and/or romstage. + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + config DCACHE_BSP_STACK_SIZE + hex + default 0x20400 if FSP_USES_CB_STACK +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch deleted file mode 100644 index d1d47338..00000000 --- a/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 8768e53f3b2ceb00ec0c8abf0fc0af03993820b1 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Wed, 18 Dec 2024 02:06:18 +0000 -Subject: [PATCH 31/48] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN - -This is used by lbmk to know where a tb.bin file goes, -when extracting and padding TBT.bin from Lenovo ThunderBolt -firmware updates on T480/T480s and other machines, grabbing -Lenovo update files. - -Not used in any builds, so it's not relevant for ./mk inject - -However, the ThunderBolt firmware is now auto-downloaded on -T480/T480s. This is not inserted, because it doesn't go in -the main flash, but the resulting ROM image can be flashed -on the TB controller's separate flash chip. - -Locations are as follows: - -vendorfiles/t480s/tb.bin -vendorfiles/t480/tb.bin - -This can be used for other affected ThinkPads when they're -added to Libreboot, but note that Lenovo provides different -TB firmware files for each machine. - -Since I assume it's the same TB controller on all of those -machines, I have to wonder: what difference is there between -the various TBT.bin files provided by Lenovo, and how do they -differ in terms of actual flashed configuration? - -We simply flash the padded TBT.bin when updating the firmware, -flashing externally. That's what this patch is for, so that -lbmk can auto-download them. - -Signed-off-by: Leah Rowe ---- - src/mainboard/lenovo/Kconfig | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig -index 2ffbaab85f..512b326381 100644 ---- a/src/mainboard/lenovo/Kconfig -+++ b/src/mainboard/lenovo/Kconfig -@@ -18,4 +18,30 @@ config MAINBOARD_FAMILY - string - default MAINBOARD_PART_NUMBER - -+config LENOVO_TBFW_BIN -+ string "Lenovo ThunderBolt firmware bin file" -+ default "" -+ help -+ ThunderBolt firmware for certain ThinkPad models e.g. T480. -+ Not used in the actual build. Libreboot's build system uses this -+ along with config/vendor/*/pkg.cfg entries defining a URL to the -+ Lenovo download link and hash. The resulting file when processed by -+ lbmk can be flashed to the ThunderBolt firmware's 25XX NOR device. -+ Earlier versions of this firmware had debug commands enabled that -+ sent logs to said flash IC, and it would quickly fill up, bricking -+ the ThunderBolt controller. With these updates, flashed externally, -+ you can fix the issue if present or otherwise prevent it. The benefit -+ here is that you then don't need to use Windows or a boot disk. You -+ can flash the TB firmware while flashing Libreboot firmware. Easy! -+ Look for these variables in lbmk: -+ TBFW_url TBFW_url_bkup TBFW_hash and look at how it handles that and -+ CONFIG_LENOVO_TBFW_BIN, in lbmk's include/vendor.sh file. -+ The path set by CONFIG_LENOVO_TBFW_BIN is used by lbmk when extracting -+ the firmware, putting it at that desired location. In this way, lbmk -+ can auto-download such firmware. E.g. ./mk -d coreboot t480_fsp_16mb -+ and it appears at vendorfiles/t480/tb.bin fully padded and everything! -+ -+ Just leave this blank if you don't care about this option. It's not -+ useful for every ThinkPad, only certain models. -+ - endif # VENDOR_LENOVO --- -2.47.3 - diff --git a/config/coreboot/default/patches/0031-soc-intel-skylake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0031-soc-intel-skylake-Don-t-compress-FSP-S.patch new file mode 100644 index 00000000..42578730 --- /dev/null +++ b/config/coreboot/default/patches/0031-soc-intel-skylake-Don-t-compress-FSP-S.patch @@ -0,0 +1,36 @@ +From 564634f7f83f4118e44972c91e391125a7aa6e27 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Thu, 26 Dec 2024 19:45:20 +0000 +Subject: [PATCH 31/51] soc/intel/skylake: Don't compress FSP-S + +Build systems like lbmk need to reproducibly insert +certain vendor files on release images. + +Compression isn't always reproducible, and making it +so costs a lot more time than simply disabling compression. + +With this change, the FSP-S module will now be inserted +without compression, which means that there will now be +about 40KB of extra space used in the flash. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/skylake/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig +index f8ff8cfa7a..97354cdaa5 100644 +--- a/src/soc/intel/skylake/Kconfig ++++ b/src/soc/intel/skylake/Kconfig +@@ -15,7 +15,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE + select DRAM_SUPPORT_DDR4 + select DRIVERS_USB_ACPI + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 +- select FSP_COMPRESS_FSP_S_LZ4 ++# select FSP_COMPRESS_FSP_S_LZ4 + select FSP_M_XIP + select GENERIC_GPIO_LIB + select HAVE_FSP_GOP +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch b/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch deleted file mode 100644 index 6ed150e7..00000000 --- a/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 579c60fd77517497eb18dfeca8d73cdca94c15da Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 21 Apr 2025 05:14:45 +0100 -Subject: [PATCH 32/48] Conditional TBFW setting for kabylake thinkpads - -Otherwise, other boards will define it, which -might trigger the vendor download script, and -lead to a non-zero exit. - -Signed-off-by: Leah Rowe ---- - src/mainboard/lenovo/Kconfig | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig -index 512b326381..b2c7763198 100644 ---- a/src/mainboard/lenovo/Kconfig -+++ b/src/mainboard/lenovo/Kconfig -@@ -18,6 +18,8 @@ config MAINBOARD_FAMILY - string - default MAINBOARD_PART_NUMBER - -+if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580 -+ - config LENOVO_TBFW_BIN - string "Lenovo ThunderBolt firmware bin file" - default "" -@@ -44,4 +46,6 @@ config LENOVO_TBFW_BIN - Just leave this blank if you don't care about this option. It's not - useful for every ThinkPad, only certain models. - -+endif # BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580 -+ - endif # VENDOR_LENOVO --- -2.47.3 - diff --git a/config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch new file mode 100644 index 00000000..b5f1435e --- /dev/null +++ b/config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch @@ -0,0 +1,78 @@ +From 9e50b19e8d892819bebbebafe25c175f5a8faece Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Wed, 18 Dec 2024 02:06:18 +0000 +Subject: [PATCH 32/51] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN + +This is used by lbmk to know where a tb.bin file goes, +when extracting and padding TBT.bin from Lenovo ThunderBolt +firmware updates on T480/T480s and other machines, grabbing +Lenovo update files. + +Not used in any builds, so it's not relevant for ./mk inject + +However, the ThunderBolt firmware is now auto-downloaded on +T480/T480s. This is not inserted, because it doesn't go in +the main flash, but the resulting ROM image can be flashed +on the TB controller's separate flash chip. + +Locations are as follows: + +vendorfiles/t480s/tb.bin +vendorfiles/t480/tb.bin + +This can be used for other affected ThinkPads when they're +added to Libreboot, but note that Lenovo provides different +TB firmware files for each machine. + +Since I assume it's the same TB controller on all of those +machines, I have to wonder: what difference is there between +the various TBT.bin files provided by Lenovo, and how do they +differ in terms of actual flashed configuration? + +We simply flash the padded TBT.bin when updating the firmware, +flashing externally. That's what this patch is for, so that +lbmk can auto-download them. + +Signed-off-by: Leah Rowe +--- + src/mainboard/lenovo/Kconfig | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig +index 2ffbaab85f..512b326381 100644 +--- a/src/mainboard/lenovo/Kconfig ++++ b/src/mainboard/lenovo/Kconfig +@@ -18,4 +18,30 @@ config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + ++config LENOVO_TBFW_BIN ++ string "Lenovo ThunderBolt firmware bin file" ++ default "" ++ help ++ ThunderBolt firmware for certain ThinkPad models e.g. T480. ++ Not used in the actual build. Libreboot's build system uses this ++ along with config/vendor/*/pkg.cfg entries defining a URL to the ++ Lenovo download link and hash. The resulting file when processed by ++ lbmk can be flashed to the ThunderBolt firmware's 25XX NOR device. ++ Earlier versions of this firmware had debug commands enabled that ++ sent logs to said flash IC, and it would quickly fill up, bricking ++ the ThunderBolt controller. With these updates, flashed externally, ++ you can fix the issue if present or otherwise prevent it. The benefit ++ here is that you then don't need to use Windows or a boot disk. You ++ can flash the TB firmware while flashing Libreboot firmware. Easy! ++ Look for these variables in lbmk: ++ TBFW_url TBFW_url_bkup TBFW_hash and look at how it handles that and ++ CONFIG_LENOVO_TBFW_BIN, in lbmk's include/vendor.sh file. ++ The path set by CONFIG_LENOVO_TBFW_BIN is used by lbmk when extracting ++ the firmware, putting it at that desired location. In this way, lbmk ++ can auto-download such firmware. E.g. ./mk -d coreboot t480_fsp_16mb ++ and it appears at vendorfiles/t480/tb.bin fully padded and everything! ++ ++ Just leave this blank if you don't care about this option. It's not ++ useful for every ThinkPad, only certain models. ++ + endif # VENDOR_LENOVO +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0033-Conditional-TBFW-setting-for-kabylake-thinkpads.patch b/config/coreboot/default/patches/0033-Conditional-TBFW-setting-for-kabylake-thinkpads.patch new file mode 100644 index 00000000..a5a69887 --- /dev/null +++ b/config/coreboot/default/patches/0033-Conditional-TBFW-setting-for-kabylake-thinkpads.patch @@ -0,0 +1,37 @@ +From eb332dd2c30c54a78cd0ce573c3358df458ad8c5 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 21 Apr 2025 05:14:45 +0100 +Subject: [PATCH 33/51] Conditional TBFW setting for kabylake thinkpads + +Otherwise, other boards will define it, which +might trigger the vendor download script, and +lead to a non-zero exit. + +Signed-off-by: Leah Rowe +--- + src/mainboard/lenovo/Kconfig | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig +index 512b326381..b2c7763198 100644 +--- a/src/mainboard/lenovo/Kconfig ++++ b/src/mainboard/lenovo/Kconfig +@@ -18,6 +18,8 @@ config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + ++if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580 ++ + config LENOVO_TBFW_BIN + string "Lenovo ThunderBolt firmware bin file" + default "" +@@ -44,4 +46,6 @@ config LENOVO_TBFW_BIN + Just leave this blank if you don't care about this option. It's not + useful for every ThinkPad, only certain models. + ++endif # BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580 ++ + endif # VENDOR_LENOVO +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch b/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch deleted file mode 100644 index 64f257e4..00000000 --- a/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 23d8a97ff213f744b4e6333d92fc90e9ea97e879 Mon Sep 17 00:00:00 2001 -From: Riku Viitanen -Date: Sat, 27 Sep 2025 23:30:46 +0300 -Subject: [PATCH 33/48] soc/intel/alderlake: Disable - MRC_CACHE_USING_MRC_VERSION - -There's some issue with building against the FSP headers in src/vendorcode. -Headers in 3rdparty/fsp work, but since FspProducerDataHeaer.h is missing -from there, we need to disable MRC_CACHE_USING_MRC_VERSION by force. - -Signed-off-by: Riku Viitanen ---- - src/soc/intel/alderlake/Kconfig | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 34c9baf544..e0ab6b10fd 100644 ---- a/src/soc/intel/alderlake/Kconfig -+++ b/src/soc/intel/alderlake/Kconfig -@@ -36,7 +36,6 @@ config SOC_INTEL_ALDERLAKE - select INTEL_GMA_VERSION_2 - select INTEL_TXT_LIB - select MP_SERVICES_PPI_V2 -- select MRC_CACHE_USING_MRC_VERSION if (SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_RAPTORLAKE) && !FSP_USE_REPO - select MRC_SETTINGS_PROTECT - select PARALLEL_MP_AP_WORK - select PLATFORM_USES_FSP2_2 --- -2.47.3 - diff --git a/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch b/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch deleted file mode 100644 index bb6e39c0..00000000 --- a/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch +++ /dev/null @@ -1,76 +0,0 @@ -From e2e070ab1f080c0ae59c43131faa57f3499fd813 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sun, 28 Sep 2025 03:17:50 +0100 -Subject: [PATCH 34/48] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) - -if you pass -k (keep fptr modules), don't use -r, don't -use -t, you can essentially just use me_cleaner to -extract a ME image without changing it. this is useful -when for example, you just want to set the HAP bit. - -however, me_cleaner still performs a FPTR check. - -on some newer ME versions, it's always invalid according -to me_cleaner, because for example it doesn't handle -ME16 very well yet. - -this patch adds an option to override the FPTR check - -either pass -p or --pass-fptr - -NOTE: we probably won't use this on coreboot's me_cleaner, -which is the corna version. we only need it on the newer -me_cleaner versions for e.g. ME16, on certain setups. -still, it's best to have the patch here too, just in case. - -Signed-off-by: Leah Rowe ---- - util/me_cleaner/me_cleaner.py | 14 ++++++++++---- - 1 file changed, 10 insertions(+), 4 deletions(-) - -diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py -index fae5e56732..228bac899f 100755 ---- a/util/me_cleaner/me_cleaner.py -+++ b/util/me_cleaner/me_cleaner.py -@@ -246,8 +246,10 @@ def check_partition_signature(f, offset): - return "{:#x}".format(decrypted_sig).endswith(sha256.hexdigest()) # FIXME - - --def print_check_partition_signature(f, offset): -- if check_partition_signature(f, offset): -+def print_check_partition_signature(f, offset, pass_fptr): -+ if pass_fptr: -+ print("Skipping FPTR checks because the user told us to") -+ elif check_partition_signature(f, offset): - print("VALID") - else: - print("INVALID!!") -@@ -486,6 +488,8 @@ if __name__ == "__main__": - "--extract-me)", action="store_true") - parser.add_argument("-k", "--keep-modules", help="don't remove the FTPR " - "modules, even when possible", action="store_true") -+ parser.add_argument("-p", "--pass-fptr", help="skip FTPR signature checks" -+ "regardless of other operations", action="store_true") - bw_list.add_argument("-w", "--whitelist", metavar="whitelist", - help="Comma separated list of additional partitions " - "to keep in the final image. This can be used to " -@@ -871,12 +875,14 @@ if __name__ == "__main__": - print("Checking the FTPR RSA signature of the extracted ME " - "image... ", end="") - print_check_partition_signature(mef_copy, -- ftpr_offset + ftpr_mn2_offset) -+ ftpr_offset + ftpr_mn2_offset, -+ args.pass_fptr) - mef_copy.close() - - if not me6_ignition: - print("Checking the FTPR RSA signature... ", end="") -- print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset) -+ print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset, -+ args.pass_fptr) - - f.close() - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0034-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch b/config/coreboot/default/patches/0034-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch new file mode 100644 index 00000000..fabd23d4 --- /dev/null +++ b/config/coreboot/default/patches/0034-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch @@ -0,0 +1,30 @@ +From 97c167555bec5e8a69b90379c3350766fc5b1107 Mon Sep 17 00:00:00 2001 +From: Riku Viitanen +Date: Sat, 27 Sep 2025 23:30:46 +0300 +Subject: [PATCH 34/51] soc/intel/alderlake: Disable + MRC_CACHE_USING_MRC_VERSION + +There's some issue with building against the FSP headers in src/vendorcode. +Headers in 3rdparty/fsp work, but since FspProducerDataHeaer.h is missing +from there, we need to disable MRC_CACHE_USING_MRC_VERSION by force. + +Signed-off-by: Riku Viitanen +--- + src/soc/intel/alderlake/Kconfig | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index 334ea26e5b..0f1404ea49 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -36,7 +36,6 @@ config SOC_INTEL_ALDERLAKE + select INTEL_GMA_VERSION_2 + select INTEL_TXT_LIB + select MP_SERVICES_PPI_V2 +- select MRC_CACHE_USING_MRC_VERSION if (SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_RAPTORLAKE) && !FSP_USE_REPO + select MRC_SETTINGS_PROTECT + select PARALLEL_MP_AP_WORK + select PLATFORM_USES_FSP2_2 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0035-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch b/config/coreboot/default/patches/0035-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch new file mode 100644 index 00000000..8d5fa92f --- /dev/null +++ b/config/coreboot/default/patches/0035-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch @@ -0,0 +1,76 @@ +From fd552921d0a34b8ac2f9c21f8c1abf47f2f0c160 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sun, 28 Sep 2025 03:17:50 +0100 +Subject: [PATCH 35/51] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) + +if you pass -k (keep fptr modules), don't use -r, don't +use -t, you can essentially just use me_cleaner to +extract a ME image without changing it. this is useful +when for example, you just want to set the HAP bit. + +however, me_cleaner still performs a FPTR check. + +on some newer ME versions, it's always invalid according +to me_cleaner, because for example it doesn't handle +ME16 very well yet. + +this patch adds an option to override the FPTR check + +either pass -p or --pass-fptr + +NOTE: we probably won't use this on coreboot's me_cleaner, +which is the corna version. we only need it on the newer +me_cleaner versions for e.g. ME16, on certain setups. +still, it's best to have the patch here too, just in case. + +Signed-off-by: Leah Rowe +--- + util/me_cleaner/me_cleaner.py | 14 ++++++++++---- + 1 file changed, 10 insertions(+), 4 deletions(-) + +diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py +index fae5e56732..228bac899f 100755 +--- a/util/me_cleaner/me_cleaner.py ++++ b/util/me_cleaner/me_cleaner.py +@@ -246,8 +246,10 @@ def check_partition_signature(f, offset): + return "{:#x}".format(decrypted_sig).endswith(sha256.hexdigest()) # FIXME + + +-def print_check_partition_signature(f, offset): +- if check_partition_signature(f, offset): ++def print_check_partition_signature(f, offset, pass_fptr): ++ if pass_fptr: ++ print("Skipping FPTR checks because the user told us to") ++ elif check_partition_signature(f, offset): + print("VALID") + else: + print("INVALID!!") +@@ -486,6 +488,8 @@ if __name__ == "__main__": + "--extract-me)", action="store_true") + parser.add_argument("-k", "--keep-modules", help="don't remove the FTPR " + "modules, even when possible", action="store_true") ++ parser.add_argument("-p", "--pass-fptr", help="skip FTPR signature checks" ++ "regardless of other operations", action="store_true") + bw_list.add_argument("-w", "--whitelist", metavar="whitelist", + help="Comma separated list of additional partitions " + "to keep in the final image. This can be used to " +@@ -871,12 +875,14 @@ if __name__ == "__main__": + print("Checking the FTPR RSA signature of the extracted ME " + "image... ", end="") + print_check_partition_signature(mef_copy, +- ftpr_offset + ftpr_mn2_offset) ++ ftpr_offset + ftpr_mn2_offset, ++ args.pass_fptr) + mef_copy.close() + + if not me6_ignition: + print("Checking the FTPR RSA signature... ", end="") +- print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset) ++ print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset, ++ args.pass_fptr) + + f.close() + +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch deleted file mode 100644 index 2292605e..00000000 --- a/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch +++ /dev/null @@ -1,35 +0,0 @@ -From fee89a6c872ec26c2ea128ecdce62d6c3abe53f1 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 4 Oct 2025 21:57:43 +0100 -Subject: [PATCH 35/48] soc/intel/alderlake: Don't compress FSP-S - -Build systems like lbmk need to reproducibly insert -certain vendor files on release images. - -Compression isn't always reproducible, and making it -so costs a lot more time than simply disabling compression. - -With this change, FSP-S uses slightly more space inside -the flash, but it's not that much. - -Signed-off-by: Leah Rowe ---- - src/soc/intel/alderlake/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index e0ab6b10fd..a2e7cff6f6 100644 ---- a/src/soc/intel/alderlake/Kconfig -+++ b/src/soc/intel/alderlake/Kconfig -@@ -16,7 +16,7 @@ config SOC_INTEL_ALDERLAKE - select DRAM_SUPPORT_DDR5 - select DRIVERS_USB_ACPI - select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 -- select FSP_COMPRESS_FSP_S_LZ4 -+# select FSP_COMPRESS_FSP_S_LZ4 - select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW - select FSP_M_XIP - select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN --- -2.47.3 - diff --git a/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch b/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch deleted file mode 100644 index a4f9068d..00000000 --- a/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch +++ /dev/null @@ -1,33 +0,0 @@ -From abd26006eff71c9570bc90fdbce3a76f8f559cea Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 4 Oct 2025 22:20:11 +0100 -Subject: [PATCH 36/48] alderlake: don't require full fsp repo for fd path - -Signed-off-by: Leah Rowe ---- - src/soc/intel/alderlake/Kconfig | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - -diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index a2e7cff6f6..3402c1e3d5 100644 ---- a/src/soc/intel/alderlake/Kconfig -+++ b/src/soc/intel/alderlake/Kconfig -@@ -430,7 +430,14 @@ config FSP_HEADER_PATH - - config FSP_FD_PATH - string -- depends on FSP_USE_REPO -+# dependency removed for lbmk purposes, so that the path is present -+# in the config regardless of whether it's used. this is for ./mk -d -+# on alderlake boards, which is used by lbmk to manually split fsp, -+# even though the result is identical to what coreboot produces, because -+# this enables lbmk to strip the fsp in release archives, and re-insert -+# for compliance reasons (due to technicalities in intel's licensing), -+# and to enable lbmk's advanced checksum verification of vendor files -+# depends on FSP_USE_REPO - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P --- -2.47.3 - diff --git a/config/coreboot/default/patches/0036-soc-intel-alderlake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0036-soc-intel-alderlake-Don-t-compress-FSP-S.patch new file mode 100644 index 00000000..a5fa5bb5 --- /dev/null +++ b/config/coreboot/default/patches/0036-soc-intel-alderlake-Don-t-compress-FSP-S.patch @@ -0,0 +1,35 @@ +From f91e6c35aa0ff7111e65a89a4828b773d038a69c Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 4 Oct 2025 21:57:43 +0100 +Subject: [PATCH 36/51] soc/intel/alderlake: Don't compress FSP-S + +Build systems like lbmk need to reproducibly insert +certain vendor files on release images. + +Compression isn't always reproducible, and making it +so costs a lot more time than simply disabling compression. + +With this change, FSP-S uses slightly more space inside +the flash, but it's not that much. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/alderlake/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index 0f1404ea49..f78729a9c4 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -16,7 +16,7 @@ config SOC_INTEL_ALDERLAKE + select DRAM_SUPPORT_DDR5 + select DRIVERS_USB_ACPI + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 +- select FSP_COMPRESS_FSP_S_LZ4 ++# select FSP_COMPRESS_FSP_S_LZ4 + select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW + select FSP_M_XIP + select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0037-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch b/config/coreboot/default/patches/0037-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch new file mode 100644 index 00000000..5c9f8fbd --- /dev/null +++ b/config/coreboot/default/patches/0037-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch @@ -0,0 +1,33 @@ +From ab4937af6e193b057a8b0212f0667e57eb7ba7d7 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 4 Oct 2025 22:20:11 +0100 +Subject: [PATCH 37/51] alderlake: don't require full fsp repo for fd path + +Signed-off-by: Leah Rowe +--- + src/soc/intel/alderlake/Kconfig | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index f78729a9c4..c05d06289e 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -442,7 +442,14 @@ config FSP_HEADER_PATH + + config FSP_FD_PATH + string +- depends on FSP_USE_REPO ++# dependency removed for lbmk purposes, so that the path is present ++# in the config regardless of whether it's used. this is for ./mk -d ++# on alderlake boards, which is used by lbmk to manually split fsp, ++# even though the result is identical to what coreboot produces, because ++# this enables lbmk to strip the fsp in release archives, and re-insert ++# for compliance reasons (due to technicalities in intel's licensing), ++# and to enable lbmk's advanced checksum verification of vendor files ++# depends on FSP_USE_REPO + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch b/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch deleted file mode 100644 index d740f7a7..00000000 --- a/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 6a4a79d82df982c2fca859101040e407623f519c Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 6 Oct 2025 04:47:06 +0100 -Subject: [PATCH 37/48] soc/alderlake: disable stack overflow debug option - -same as on other boards. based on this commit: - -commit 51cc2bacb6b07279b97e9934d079060475481fb6 -Author: Subrata Banik -Author: Subrata Banik -Date: Fri Dec 13 13:07:28 2024 +0530 - - soc/intel/pantherlake: Disable stack overflow debug options - -yeah, i've been replicating this change per platform. - -we do alderlake now in libreboot, so let's set that here too. - -Signed-off-by: Leah Rowe ---- - src/soc/intel/alderlake/Kconfig | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 3402c1e3d5..06b9199e84 100644 ---- a/src/soc/intel/alderlake/Kconfig -+++ b/src/soc/intel/alderlake/Kconfig -@@ -331,6 +331,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ - int - default 19200000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ - int - default 133 --- -2.47.3 - diff --git a/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch b/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch deleted file mode 100644 index dd5412a2..00000000 --- a/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch +++ /dev/null @@ -1,92 +0,0 @@ -From bb286d13cb7702e9396deab04023cc58dcc01a15 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Sun, 11 May 2025 15:41:22 -0600 -Subject: [PATCH 38/48] ec/dell/mec5035: Add command to disable EC-initiated - thermal shutdown - -If command 0xBF isn't sent, the EC shuts down the system without warning -as soon as the CPU temperature reaches about 87 degrees, without letting -the CPU thermal throttle to try and reduce the temperature. With vendor -firmware, the CPU is able to reach around 100 degrees before thermal -throttling. - -This command was found by collecting EC commands by logging the LPC bus -while running with vendor firmware and then replaying observed commands -from coreboot. By systematically replaying subsets of commands in a -binary search pattern and then stress testing the system, the command to -disable the shutdown was isolated. - -The exact meaning of the parameters for this command are unknown at this -time, but do seem to differ between different generations of these -laptops. Due to this, the commmand should be called by mainboard -specific code which passes the specific parameter value used. - -The Google Wilco EC code, which runs on Latitude Chromebooks and shares -many commands with the standard Latitude ECs, suggests that command 0xBF -tells the EC about the processors CPUID. However, the values observed in -LPC bus logs do not seem to correspond with any CPUID values on the -non-Chromebook systems I tested. - -Observed command parameter values (sent on mailbox registers 2-4): -- E6430 (Ivy Bridge): 0x07, 0x00, 0x00 -- M6800 (Haswell): 0x14, 0x00, 0x00 - -Change-Id: I42f09a3ef681007f64d9c5b1a29248b594737a86 -Signed-off-by: Nicholas Chin ---- - src/ec/dell/mec5035/mec5035.c | 19 +++++++++++++++++++ - src/ec/dell/mec5035/mec5035.h | 2 ++ - 2 files changed, 21 insertions(+) - -diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index c5067c16f6..b316fa4989 100644 ---- a/src/ec/dell/mec5035/mec5035.c -+++ b/src/ec/dell/mec5035/mec5035.c -@@ -114,6 +114,25 @@ void mec5035_sleep_enable(void) - ec_command(CMD_SLEEP_ENABLE); - } - -+void mec5035_cmd_bf(u8 i) -+{ -+ /* -+ * If this command isn't sent, the EC shuts down the system as soon as -+ * the CPU temperature reaches about 87 degrees. It is unknown exactly -+ * what the parameters represent. The Google Wilco EC code, which runs -+ * on Latitude Chromebooks and shares some commands with the standard -+ * Latitude EC code, suggests command 0xBF tells the EC the CPUID, but -+ * the values observed in LPC bus logs don't seem to match any CPUID -+ * values of the normal Latitudes this was tested with. -+ * Observed i values: -+ * - E6430 (Ivy Bridge): 0x7 -+ * - M6800 (Haswell): 0x14 -+ */ -+ u8 buf[3] = {i, 0, 0}; -+ write_mailbox_regs(buf, 2, 3); -+ ec_command(CMD_BF); -+} -+ - void mec5035_early_init(void) - { - /* If this isn't sent the EC shuts down the system after about 15 -diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h -index 5cd907bf71..71d1a71075 100644 ---- a/src/ec/dell/mec5035/mec5035.h -+++ b/src/ec/dell/mec5035/mec5035.h -@@ -14,6 +14,7 @@ enum mec5035_cmd { - CMD_POWER_BUTTON_TO_HOST = 0x3e, - CMD_ACPI_WAKEUP_CHANGE = 0x4a, - CMD_SLEEP_ENABLE = 0x64, -+ CMD_BF = 0xbf, - CMD_CPU_OK = 0xc2, - }; - -@@ -65,5 +66,6 @@ void mec5035_change_wake(u8 source, enum ec_wake_change change); - void mec5035_sleep_enable(void); - - void mec5035_smi_sleep(int slp_type); -+void mec5035_cmd_bf(u8 i); - - #endif /* _EC_DELL_MEC5035_H_ */ --- -2.47.3 - diff --git a/config/coreboot/default/patches/0038-soc-alderlake-disable-stack-overflow-debug-option.patch b/config/coreboot/default/patches/0038-soc-alderlake-disable-stack-overflow-debug-option.patch new file mode 100644 index 00000000..4a3130ac --- /dev/null +++ b/config/coreboot/default/patches/0038-soc-alderlake-disable-stack-overflow-debug-option.patch @@ -0,0 +1,46 @@ +From dec241cc53669870365e103a22d21a9a3111abcc Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 6 Oct 2025 04:47:06 +0100 +Subject: [PATCH 38/51] soc/alderlake: disable stack overflow debug option + +same as on other boards. based on this commit: + +commit 51cc2bacb6b07279b97e9934d079060475481fb6 +Author: Subrata Banik +Author: Subrata Banik +Date: Fri Dec 13 13:07:28 2024 +0530 + + soc/intel/pantherlake: Disable stack overflow debug options + +yeah, i've been replicating this change per platform. + +we do alderlake now in libreboot, so let's set that here too. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/alderlake/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index c05d06289e..acb87275d4 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -343,6 +343,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ + int + default 19200000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0039-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch b/config/coreboot/default/patches/0039-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch new file mode 100644 index 00000000..6518493e --- /dev/null +++ b/config/coreboot/default/patches/0039-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch @@ -0,0 +1,92 @@ +From fa7d21faf931756d8adb84071bc503a0fe8e64c3 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Sun, 11 May 2025 15:41:22 -0600 +Subject: [PATCH 39/51] ec/dell/mec5035: Add command to disable EC-initiated + thermal shutdown + +If command 0xBF isn't sent, the EC shuts down the system without warning +as soon as the CPU temperature reaches about 87 degrees, without letting +the CPU thermal throttle to try and reduce the temperature. With vendor +firmware, the CPU is able to reach around 100 degrees before thermal +throttling. + +This command was found by collecting EC commands by logging the LPC bus +while running with vendor firmware and then replaying observed commands +from coreboot. By systematically replaying subsets of commands in a +binary search pattern and then stress testing the system, the command to +disable the shutdown was isolated. + +The exact meaning of the parameters for this command are unknown at this +time, but do seem to differ between different generations of these +laptops. Due to this, the commmand should be called by mainboard +specific code which passes the specific parameter value used. + +The Google Wilco EC code, which runs on Latitude Chromebooks and shares +many commands with the standard Latitude ECs, suggests that command 0xBF +tells the EC about the processors CPUID. However, the values observed in +LPC bus logs do not seem to correspond with any CPUID values on the +non-Chromebook systems I tested. + +Observed command parameter values (sent on mailbox registers 2-4): +- E6430 (Ivy Bridge): 0x07, 0x00, 0x00 +- M6800 (Haswell): 0x14, 0x00, 0x00 + +Change-Id: I42f09a3ef681007f64d9c5b1a29248b594737a86 +Signed-off-by: Nicholas Chin +--- + src/ec/dell/mec5035/mec5035.c | 19 +++++++++++++++++++ + src/ec/dell/mec5035/mec5035.h | 2 ++ + 2 files changed, 21 insertions(+) + +diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c +index c5067c16f6..b316fa4989 100644 +--- a/src/ec/dell/mec5035/mec5035.c ++++ b/src/ec/dell/mec5035/mec5035.c +@@ -114,6 +114,25 @@ void mec5035_sleep_enable(void) + ec_command(CMD_SLEEP_ENABLE); + } + ++void mec5035_cmd_bf(u8 i) ++{ ++ /* ++ * If this command isn't sent, the EC shuts down the system as soon as ++ * the CPU temperature reaches about 87 degrees. It is unknown exactly ++ * what the parameters represent. The Google Wilco EC code, which runs ++ * on Latitude Chromebooks and shares some commands with the standard ++ * Latitude EC code, suggests command 0xBF tells the EC the CPUID, but ++ * the values observed in LPC bus logs don't seem to match any CPUID ++ * values of the normal Latitudes this was tested with. ++ * Observed i values: ++ * - E6430 (Ivy Bridge): 0x7 ++ * - M6800 (Haswell): 0x14 ++ */ ++ u8 buf[3] = {i, 0, 0}; ++ write_mailbox_regs(buf, 2, 3); ++ ec_command(CMD_BF); ++} ++ + void mec5035_early_init(void) + { + /* If this isn't sent the EC shuts down the system after about 15 +diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h +index 5cd907bf71..71d1a71075 100644 +--- a/src/ec/dell/mec5035/mec5035.h ++++ b/src/ec/dell/mec5035/mec5035.h +@@ -14,6 +14,7 @@ enum mec5035_cmd { + CMD_POWER_BUTTON_TO_HOST = 0x3e, + CMD_ACPI_WAKEUP_CHANGE = 0x4a, + CMD_SLEEP_ENABLE = 0x64, ++ CMD_BF = 0xbf, + CMD_CPU_OK = 0xc2, + }; + +@@ -65,5 +66,6 @@ void mec5035_change_wake(u8 source, enum ec_wake_change change); + void mec5035_sleep_enable(void); + + void mec5035_smi_sleep(int slp_type); ++void mec5035_cmd_bf(u8 i); + + #endif /* _EC_DELL_MEC5035_H_ */ +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch b/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch deleted file mode 100644 index 1814806f..00000000 --- a/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch +++ /dev/null @@ -1,36 +0,0 @@ -From a93c01173c2f88b4a09286740c030314040c39fc Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Sun, 11 May 2025 16:28:23 -0600 -Subject: [PATCH 39/48] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown - at 87 degrees - -If command 0xBF isn't sent, the EC will shut down the system without -warning once the CPU reaches approximately 87 degrees, without the -system thermal throttling first. Call the newly added function from the -MEC5035 code to send this command and disable this behavior. - -Tested on the Latitude E6430. - -Change-Id: I2b2dc1e3ab115e05d05eaac06892343394d37fdf -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/snb_ivb_latitude/early_init.c | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/src/mainboard/dell/snb_ivb_latitude/early_init.c b/src/mainboard/dell/snb_ivb_latitude/early_init.c -index ff83db095b..ef385a0a70 100644 ---- a/src/mainboard/dell/snb_ivb_latitude/early_init.c -+++ b/src/mainboard/dell/snb_ivb_latitude/early_init.c -@@ -11,4 +11,9 @@ void bootblock_mainboard_early_init(void) - | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN - | COMB_LPC_EN | COMA_LPC_EN); - mec5035_early_init(); -+ -+ /* Observed from LPC logs with vendor firmware. Seems to disable -+ * EC-initiated shutdown when the CPU reaches approximately 87 degrees. -+ * The exact meaning of the parameter is currently unknown. */ -+ mec5035_cmd_bf(0x07); - } --- -2.47.3 - diff --git a/config/coreboot/default/patches/0040-fix-ifdtool-build.patch b/config/coreboot/default/patches/0040-fix-ifdtool-build.patch deleted file mode 100644 index b39fbc0b..00000000 --- a/config/coreboot/default/patches/0040-fix-ifdtool-build.patch +++ /dev/null @@ -1,28 +0,0 @@ -From dc4036353483c5fc0c140fc269d9bddb0bb7a967 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 20 Dec 2025 20:12:48 +0100 -Subject: [PATCH 40/48] fix ifdtool build - -not my mistake. someone messed up. - -Signed-off-by: Leah Rowe ---- - util/ifdtool/ifdtool.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index cab934c3a5..d181888e0f 100644 ---- a/util/ifdtool/ifdtool.c -+++ b/util/ifdtool/ifdtool.c -@@ -2598,7 +2598,7 @@ int main(int argc, char *argv[]) - } - mode_nuke = 1; - break; -- Case 'v': -+ case 'v': - print_version(); - exit(EXIT_SUCCESS); - break; --- -2.47.3 - diff --git a/config/coreboot/default/patches/0040-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch b/config/coreboot/default/patches/0040-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch new file mode 100644 index 00000000..0ebfe02a --- /dev/null +++ b/config/coreboot/default/patches/0040-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch @@ -0,0 +1,36 @@ +From 0397a0966953d47210a5ae1f7f0cd71a9a10dc68 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Sun, 11 May 2025 16:28:23 -0600 +Subject: [PATCH 40/51] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown + at 87 degrees + +If command 0xBF isn't sent, the EC will shut down the system without +warning once the CPU reaches approximately 87 degrees, without the +system thermal throttling first. Call the newly added function from the +MEC5035 code to send this command and disable this behavior. + +Tested on the Latitude E6430. + +Change-Id: I2b2dc1e3ab115e05d05eaac06892343394d37fdf +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/snb_ivb_latitude/early_init.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/src/mainboard/dell/snb_ivb_latitude/early_init.c b/src/mainboard/dell/snb_ivb_latitude/early_init.c +index ff83db095b..ef385a0a70 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/early_init.c ++++ b/src/mainboard/dell/snb_ivb_latitude/early_init.c +@@ -11,4 +11,9 @@ void bootblock_mainboard_early_init(void) + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); ++ ++ /* Observed from LPC logs with vendor firmware. Seems to disable ++ * EC-initiated shutdown when the CPU reaches approximately 87 degrees. ++ * The exact meaning of the parameter is currently unknown. */ ++ mec5035_cmd_bf(0x07); + } +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0041-fix-ifdtool-build.patch b/config/coreboot/default/patches/0041-fix-ifdtool-build.patch new file mode 100644 index 00000000..3124f7c3 --- /dev/null +++ b/config/coreboot/default/patches/0041-fix-ifdtool-build.patch @@ -0,0 +1,28 @@ +From 42fb6f08310a35587643bdfd75bcdca5318f1022 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 20 Dec 2025 20:12:48 +0100 +Subject: [PATCH 41/51] fix ifdtool build + +not my mistake. someone messed up. + +Signed-off-by: Leah Rowe +--- + util/ifdtool/ifdtool.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c +index 7f0c10bd0b..2a5365efe7 100644 +--- a/util/ifdtool/ifdtool.c ++++ b/util/ifdtool/ifdtool.c +@@ -2610,7 +2610,7 @@ int main(int argc, char *argv[]) + } + mode_nuke = 1; + break; +- Case 'v': ++ case 'v': + print_version(); + exit(EXIT_SUCCESS); + break; +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch b/config/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch deleted file mode 100644 index 8f61bcd0..00000000 --- a/config/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 5b7bbc6fcc6f737f259906f1919c1e28b6628a7e Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 20 Dec 2025 22:36:18 +0100 -Subject: [PATCH 41/48] tests/Makefile.mk: use 3rdparty/cmocka by default - -(tests) - -Signed-off-by: Leah Rowe ---- - tests/Makefile.mk | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/tests/Makefile.mk b/tests/Makefile.mk -index 9e3f86a138..a5a518cd35 100644 ---- a/tests/Makefile.mk -+++ b/tests/Makefile.mk -@@ -25,7 +25,9 @@ TEST_LDFLAGS += --coverage - endif - - # Use system cmoka in default, or build from 3rdparty source code if requested --USE_SYSTEM_CMOCKA ?= 1 -+# PATCH NOTE: lbmk sets it to 0 by default. You can still override it to 1 -+# if you wish; upstream sets this to 1 by default, but we do 0 -+USE_SYSTEM_CMOCKA ?= 0 - ifeq ($(USE_SYSTEM_CMOCKA),1) - ifeq ($(shell $(HOSTPKG_CONFIG) --exists cmocka || echo 1),1) - $(warning No system cmocka, build from 3rdparty instead...) --- -2.47.3 - diff --git a/config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch b/config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch deleted file mode 100644 index 4ce1241c..00000000 --- a/config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch +++ /dev/null @@ -1,51 +0,0 @@ -From ecbf5a133d839b6c8579e384e9db0a036eca939d Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 23 Dec 2025 18:41:27 +0100 -Subject: [PATCH 42/48] mb/dell/optiplex_780: use legacy HDA verb table - -See: - -commit 31fc5b06a6be62b30739d33eeabe6c2727679bb1 -Author: Nicholas Sudsgaard -Date: Thu Aug 7 08:31:24 2025 +0900 - - device: Introduce reworked azalia verb table - -and: - -commit 50a59d4464917503847eeeb2df4320c35cf2f6cc -Author: Nicholas Sudsgaard -Date: Mon Sep 15 16:25:21 2025 +0900 - - device: Add Kconfig to prepare for reworked verb table implementation - -Without this change, lbmk gets the following error -when building for Dell OptiPlex 780: - -i386-elf-ld.bfd: build/ramstage/device/azalia_device.o: in function `azalia_codecs_init': -/path/to/corebootclone/src/device/azalia_device.c:318:(.text.azalia_codecs_init+0xa): undefined reference to `mainboard_azalia_codecs' - -This is a temporary fix. Upstream will require that the code -be fully adapted at a future date. Therefore, one could consider -the current functionality to be "deprecated". - -Signed-off-by: Leah Rowe ---- - src/mainboard/dell/optiplex_780/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig -index fc649e35d5..172bb2fa87 100644 ---- a/src/mainboard/dell/optiplex_780/Kconfig -+++ b/src/mainboard/dell/optiplex_780/Kconfig -@@ -2,6 +2,7 @@ - - config BOARD_DELL_OPTIPLEX_780_COMMON - def_bool n -+ select AZALIA_USE_LEGACY_VERB_TABLE - select BOARD_ROMSIZE_KB_8192 - select CPU_INTEL_SOCKET_LGA775 - select DRIVERS_I2C_CK505 --- -2.47.3 - diff --git a/config/coreboot/default/patches/0042-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch b/config/coreboot/default/patches/0042-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch new file mode 100644 index 00000000..a8206276 --- /dev/null +++ b/config/coreboot/default/patches/0042-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch @@ -0,0 +1,30 @@ +From 5bcd048c8ded00a7c12e863a1a9a76c9bba1606a Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 20 Dec 2025 22:36:18 +0100 +Subject: [PATCH 42/51] tests/Makefile.mk: use 3rdparty/cmocka by default + +(tests) + +Signed-off-by: Leah Rowe +--- + tests/Makefile.mk | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/tests/Makefile.mk b/tests/Makefile.mk +index 9e3f86a138..a5a518cd35 100644 +--- a/tests/Makefile.mk ++++ b/tests/Makefile.mk +@@ -25,7 +25,9 @@ TEST_LDFLAGS += --coverage + endif + + # Use system cmoka in default, or build from 3rdparty source code if requested +-USE_SYSTEM_CMOCKA ?= 1 ++# PATCH NOTE: lbmk sets it to 0 by default. You can still override it to 1 ++# if you wish; upstream sets this to 1 by default, but we do 0 ++USE_SYSTEM_CMOCKA ?= 0 + ifeq ($(USE_SYSTEM_CMOCKA),1) + ifeq ($(shell $(HOSTPKG_CONFIG) --exists cmocka || echo 1),1) + $(warning No system cmocka, build from 3rdparty instead...) +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch b/config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch deleted file mode 100644 index e5ea4f3c..00000000 --- a/config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 962bfe1366598145a93cf6a7ed0f78393e5e9ff7 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 23 Dec 2025 18:46:45 +0100 -Subject: [PATCH 43/48] hp8300cmt: use legacy verb table - -same as for the 780 optiplex patch - -coreboot is making some changes to the way verbs are -handled. for now, this change is being made to adapt. - -Signed-off-by: Leah Rowe ---- - src/mainboard/hp/compaq_elite_8300_cmt/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig -index d2bfd35dc4..30be7fb3fe 100644 ---- a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig -@@ -2,6 +2,7 @@ if BOARD_HP_COMPAQ_ELITE_8300_CMT - - config BOARD_SPECIFIC_OPTIONS - def_bool y -+ select AZALIA_USE_LEGACY_VERB_TABLE - select BOARD_ROMSIZE_KB_16384 - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES --- -2.47.3 - diff --git a/config/coreboot/default/patches/0043-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch b/config/coreboot/default/patches/0043-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch new file mode 100644 index 00000000..1c614c17 --- /dev/null +++ b/config/coreboot/default/patches/0043-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch @@ -0,0 +1,51 @@ +From ac1c23e215f791c46094377f2f4c7a398e63cc80 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 23 Dec 2025 18:41:27 +0100 +Subject: [PATCH 43/51] mb/dell/optiplex_780: use legacy HDA verb table + +See: + +commit 31fc5b06a6be62b30739d33eeabe6c2727679bb1 +Author: Nicholas Sudsgaard +Date: Thu Aug 7 08:31:24 2025 +0900 + + device: Introduce reworked azalia verb table + +and: + +commit 50a59d4464917503847eeeb2df4320c35cf2f6cc +Author: Nicholas Sudsgaard +Date: Mon Sep 15 16:25:21 2025 +0900 + + device: Add Kconfig to prepare for reworked verb table implementation + +Without this change, lbmk gets the following error +when building for Dell OptiPlex 780: + +i386-elf-ld.bfd: build/ramstage/device/azalia_device.o: in function `azalia_codecs_init': +/path/to/corebootclone/src/device/azalia_device.c:318:(.text.azalia_codecs_init+0xa): undefined reference to `mainboard_azalia_codecs' + +This is a temporary fix. Upstream will require that the code +be fully adapted at a future date. Therefore, one could consider +the current functionality to be "deprecated". + +Signed-off-by: Leah Rowe +--- + src/mainboard/dell/optiplex_780/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig +index fc649e35d5..172bb2fa87 100644 +--- a/src/mainboard/dell/optiplex_780/Kconfig ++++ b/src/mainboard/dell/optiplex_780/Kconfig +@@ -2,6 +2,7 @@ + + config BOARD_DELL_OPTIPLEX_780_COMMON + def_bool n ++ select AZALIA_USE_LEGACY_VERB_TABLE + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_SOCKET_LGA775 + select DRIVERS_I2C_CK505 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0044-hp8300cmt-use-legacy-verb-table.patch b/config/coreboot/default/patches/0044-hp8300cmt-use-legacy-verb-table.patch new file mode 100644 index 00000000..b210ce34 --- /dev/null +++ b/config/coreboot/default/patches/0044-hp8300cmt-use-legacy-verb-table.patch @@ -0,0 +1,30 @@ +From 8802ad95c158e09e89c4bc0c14755d17b5f532bd Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 23 Dec 2025 18:46:45 +0100 +Subject: [PATCH 44/51] hp8300cmt: use legacy verb table + +same as for the 780 optiplex patch + +coreboot is making some changes to the way verbs are +handled. for now, this change is being made to adapt. + +Signed-off-by: Leah Rowe +--- + src/mainboard/hp/compaq_elite_8300_cmt/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig +index d2bfd35dc4..30be7fb3fe 100644 +--- a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig +@@ -2,6 +2,7 @@ if BOARD_HP_COMPAQ_ELITE_8300_CMT + + config BOARD_SPECIFIC_OPTIONS + def_bool y ++ select AZALIA_USE_LEGACY_VERB_TABLE + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch b/config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch deleted file mode 100644 index ae70996f..00000000 --- a/config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 88d29f792de89bb0a138e671432227cb5679b5ae Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 6 Jan 2026 21:42:21 +0000 -Subject: [PATCH 44/48] topton x2e n150: use old fsp - -i added the old fsp back, so that we didn't have to -mess around with vendor files in lbmk, because coreboot -upstream updated the fsp repo, which modified this -fsp file. - -we know the old fsp worked. there's no point testing -the new one yet, unless someone can tell me about -real bugs that got fixed. - -Signed-off-by: Leah Rowe ---- - src/soc/intel/alderlake/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 06b9199e84..f260d10285 100644 ---- a/src/soc/intel/alderlake/Kconfig -+++ b/src/soc/intel/alderlake/Kconfig -@@ -451,6 +451,7 @@ config FSP_FD_PATH - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S -+ default "3rdparty/fspcc36ae2b5775fa7400cb3282680afc0f6cb37a3c/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if BOARD_TOPTON_X2E_N150 - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_N - default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P - default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S --- -2.47.3 - diff --git a/config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch b/config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch deleted file mode 100644 index e4622ce4..00000000 --- a/config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 5b52abaa8529f7493f9d4ecf402e9ee130f4f8d2 Mon Sep 17 00:00:00 2001 -From: Ron Nazarov -Date: Sat, 14 Feb 2026 20:13:01 +0000 -Subject: [PATCH 45/48] mb/supermicro/x11-lga1151-series: Disable ME HECI in - devicetree - -Since we always use me_cleaner, this speeds up boot time by preventing -coreboot from wasting a few seconds waiting for HECI. - -Change-Id: Ifbb16ba9f09129795dabe7861260ea4d995c0350 -Signed-off-by: Ron Nazarov ---- - src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb -index fbf896c6ae..aa09a41f2f 100644 ---- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb -+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb -@@ -15,7 +15,7 @@ chip soc/intel/skylake - device ref sa_thermal on end - device ref south_xhci on end - device ref thermal on end -- device ref heci1 on end -+ device ref heci1 off end - device ref sata on - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ --- -2.47.3 - diff --git a/config/coreboot/default/patches/0045-topton-x2e-n150-use-old-fsp.patch b/config/coreboot/default/patches/0045-topton-x2e-n150-use-old-fsp.patch new file mode 100644 index 00000000..ef6f94a2 --- /dev/null +++ b/config/coreboot/default/patches/0045-topton-x2e-n150-use-old-fsp.patch @@ -0,0 +1,34 @@ +From ea848531d1a4ddd9952b8b8d3570770e5ac128cd Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 6 Jan 2026 21:42:21 +0000 +Subject: [PATCH 45/51] topton x2e n150: use old fsp + +i added the old fsp back, so that we didn't have to +mess around with vendor files in lbmk, because coreboot +upstream updated the fsp repo, which modified this +fsp file. + +we know the old fsp worked. there's no point testing +the new one yet, unless someone can tell me about +real bugs that got fixed. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/alderlake/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index acb87275d4..6f1e8b9107 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -463,6 +463,7 @@ config FSP_FD_PATH + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S ++ default "3rdparty/fspcc36ae2b5775fa7400cb3282680afc0f6cb37a3c/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if BOARD_TOPTON_X2E_N150 + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_N + default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0046-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch b/config/coreboot/default/patches/0046-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch new file mode 100644 index 00000000..49318070 --- /dev/null +++ b/config/coreboot/default/patches/0046-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch @@ -0,0 +1,31 @@ +From 276e29864adfaaa1234d1263a8bf751f7dfd357d Mon Sep 17 00:00:00 2001 +From: Ron Nazarov +Date: Sat, 14 Feb 2026 20:13:01 +0000 +Subject: [PATCH 46/51] mb/supermicro/x11-lga1151-series: Disable ME HECI in + devicetree + +Since we always use me_cleaner, this speeds up boot time by preventing +coreboot from wasting a few seconds waiting for HECI. + +Change-Id: Ifbb16ba9f09129795dabe7861260ea4d995c0350 +Signed-off-by: Ron Nazarov +--- + src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +index d25288420f..edbb485969 100644 +--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb ++++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +@@ -15,7 +15,7 @@ chip soc/intel/skylake + device ref sa_thermal on end + device ref south_xhci on end + device ref thermal on end +- device ref heci1 on end ++ device ref heci1 off end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch b/config/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch deleted file mode 100644 index 45539084..00000000 --- a/config/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch +++ /dev/null @@ -1,60 +0,0 @@ -From b9cc1be6f9d591dbc4f73b1448f8fce5ea20a0b4 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Fri, 20 Feb 2026 01:23:32 +0000 -Subject: [PATCH 46/48] util/ifdtool: option to allow region override - -Signed-off-by: Leah Rowe ---- - util/ifdtool/ifdtool.c | 12 ++++++++++-- - 1 file changed, 10 insertions(+), 2 deletions(-) - -diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index d181888e0f..dfefe316a9 100644 ---- a/util/ifdtool/ifdtool.c -+++ b/util/ifdtool/ifdtool.c -@@ -78,6 +78,8 @@ static unsigned int max_regions = 0; - static int selected_chip = 0; - static int platform = -1; - -+static int ignore_region_override = 0; -+ - static const struct region_name region_names[MAX_REGIONS] = { - { "Flash Descriptor", "fd", "flashregion_0_flashdescriptor.bin", "SI_DESC" }, - { "BIOS", "bios", "flashregion_1_bios.bin", "SI_BIOS" }, -@@ -2093,7 +2095,9 @@ static void new_layout(const char *filename, char *image, int size, - } - - for (j = i + 1; j < max_regions; j++) { -- if (regions_collide(&new_regions[i], &new_regions[j])) { -+ if (ignore_region_override) { -+ printf("Ignoring region overlap by user's will.\n"); -+ } else if (regions_collide(&new_regions[i], &new_regions[j])) { - fprintf(stderr, "Regions would overlap.\n"); - exit(EXIT_FAILURE); - } -@@ -2351,10 +2355,11 @@ int main(int argc, char *argv[]) - {"newvalue", 1, NULL, 'V'}, - {"topswapsize", 1, NULL, 'T'}, - {"nuke", 1, NULL, 'N'}, -+ {"ignore-region-overlap", 0, NULL, 'I'}, - {0, 0, 0, 0} - }; - -- while ((opt = getopt_long(argc, argv, "S:V:df:F:D:C:M:xi:n:O:s:p:T:elrugEcvth?", -+ while ((opt = getopt_long(argc, argv, "I:S:V:df:F:D:C:M:xi:n:O:s:p:T:elrugEcvth?", - long_options, &option_index)) != EOF) { - switch (opt) { - case 'd': -@@ -2598,6 +2603,9 @@ int main(int argc, char *argv[]) - } - mode_nuke = 1; - break; -+ case 'I': -+ ignore_region_override = 1; -+ break; - case 'v': - print_version(); - exit(EXIT_SUCCESS); --- -2.47.3 - diff --git a/config/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch b/config/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch deleted file mode 100644 index cfd5c6c9..00000000 --- a/config/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 1bc6028bf88ca6306ad89fc17fa6f31b9788b248 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Fri, 20 Feb 2026 19:31:19 +0000 -Subject: [PATCH 47/48] me_cleaner: don't modify if -k is used - -don't remove *anything*. in libreboot, we only -ever use -k when we werely want to extract the -ME, but otherwise not modify it. this is because -we rely on bruteforce, detecting when me.bin is -found based on mecleaner validation. - -this way, we can much more reliable get the ME -images. - -Signed-off-by: Leah Rowe ---- - util/me_cleaner/me_cleaner.py | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py -index 228bac899f..269aa4ad04 100755 ---- a/util/me_cleaner/me_cleaner.py -+++ b/util/me_cleaner/me_cleaner.py -@@ -677,7 +677,7 @@ if __name__ == "__main__": - # ME 6 Ignition: wipe everything - me6_ignition = False - if not args.check and not args.soft_disable_only and \ -- variant == "ME" and version[0] == 6: -+ variant == "ME" and version[0] == 6 and not args.keep_modules: - mef.seek(ftpr_offset + 0x20) - num_modules = unpack(" +Date: Fri, 20 Feb 2026 01:23:32 +0000 +Subject: [PATCH 47/51] util/ifdtool: option to allow region override + +Signed-off-by: Leah Rowe +--- + util/ifdtool/ifdtool.c | 13 +++++++++++-- + 1 file changed, 11 insertions(+), 2 deletions(-) + +diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c +index 2a5365efe7..c5c3570e6a 100644 +--- a/util/ifdtool/ifdtool.c ++++ b/util/ifdtool/ifdtool.c +@@ -78,6 +78,8 @@ static unsigned int max_regions = 0; + static int selected_chip = 0; + static int platform = -1; + ++static int ignore_region_override = 0; ++ + static const struct region_name region_names[MAX_REGIONS] = { + { "Flash Descriptor", "fd", "flashregion_0_flashdescriptor.bin", "SI_DESC" }, + { "BIOS", "bios", "flashregion_1_bios.bin", "SI_BIOS" }, +@@ -2094,7 +2096,9 @@ static void new_layout(const char *filename, char *image, int size, + } + + for (j = i + 1; j < max_regions; j++) { +- if (regions_collide(&new_regions[i], &new_regions[j])) { ++ if (ignore_region_override) { ++ printf("Ignoring region overlap by user's will.\n"); ++ } else if (regions_collide(&new_regions[i], &new_regions[j])) { + fprintf(stderr, "Regions would overlap:\n"); + + /* See which string is longer and make sure we pad the shorter one */ +@@ -2107,6 +2111,7 @@ static void new_layout(const char *filename, char *image, int size, + new_regions[i].base, new_regions[i].limit); + fprintf(stderr, " %*s : %x-%x\n", padding, region_name(j), + new_regions[j].base, new_regions[j].limit); ++ + exit(EXIT_FAILURE); + } + } +@@ -2363,10 +2368,11 @@ int main(int argc, char *argv[]) + {"newvalue", 1, NULL, 'V'}, + {"topswapsize", 1, NULL, 'T'}, + {"nuke", 1, NULL, 'N'}, ++ {"ignore-region-overlap", 0, NULL, 'I'}, + {0, 0, 0, 0} + }; + +- while ((opt = getopt_long(argc, argv, "S:V:df:F:D:C:M:xi:n:O:s:p:T:elrugEcvth?", ++ while ((opt = getopt_long(argc, argv, "I:S:V:df:F:D:C:M:xi:n:O:s:p:T:elrugEcvth?", + long_options, &option_index)) != EOF) { + switch (opt) { + case 'd': +@@ -2610,6 +2616,9 @@ int main(int argc, char *argv[]) + } + mode_nuke = 1; + break; ++ case 'I': ++ ignore_region_override = 1; ++ break; + case 'v': + print_version(); + exit(EXIT_SUCCESS); +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch b/config/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch deleted file mode 100644 index 76fc54e2..00000000 --- a/config/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch +++ /dev/null @@ -1,600 +0,0 @@ -From f5f73c2539e05cf85bf5eec795e4f91da50838ba Mon Sep 17 00:00:00 2001 -From: Kat Inskip -Date: Tue, 17 Feb 2026 16:18:15 -0800 -Subject: [PATCH 48/48] mb/lenovo/sklkbl: Add Lenovo Thinkpad X270 as a variant - -This machine is somewhat dissimilar from the X280 in the PCIe allocations in the overridetree. It also lacks soldered RAM, having a single SODIMM slot. - -This port was based upon the work done by Johann C Rode for the X280 and the VBT and hda verbs were obtained from that work, not obtained separately. GPIO ports and PCI-e allocations have been checked against schematics after editing. - -Functionality has been validated on a ThinkPad X270 with machine type model 20HMS2WU03 with 16GB onboard RAM and i5-7300U CPU. The laptop has been tested running libreboot, booting Guix via GRUB payload. A check of the hardware shows no issues (video, wifi, wired ethernet, reboot, sleep, NVMe). - -An untested variety allowing for a Skylake CPU (for 20K5 and 20K6) has been included. ---- - src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 14 ++ - .../lenovo/sklkbl_thinkpad/Kconfig.name | 3 + - .../sklkbl_thinkpad/variants/x270/data.vbt | Bin 0 -> 6144 bytes - .../variants/x270/gma-mainboard.ads | 19 ++ - .../sklkbl_thinkpad/variants/x270/gpio.c | 200 ++++++++++++++++++ - .../sklkbl_thinkpad/variants/x270/hda_verb.c | 124 +++++++++++ - .../variants/x270/memory_init_params.c | 19 ++ - .../variants/x270/overridetree.cb | 89 ++++++++ - 8 files changed, 468 insertions(+) - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -index b7cc705699..5945fe7b99 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -@@ -58,6 +58,16 @@ config BOARD_LENOVO_X280 - select SOC_INTEL_KABYLAKE - select HAVE_SPD_IN_CBFS - -+config BOARD_LENOVO_X270_20K6 -+ bool -+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON -+ select SOC_INTEL_SKYLAKE -+ -+config BOARD_LENOVO_X270_20HM -+ bool -+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON -+ select SOC_INTEL_KABYLAKE -+ - if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON - - config MAINBOARD_DIR -@@ -69,6 +79,8 @@ config VARIANT_DIR - default "t480s" if BOARD_LENOVO_T480S - default "t580" if BOARD_LENOVO_T580 - default "x280" if BOARD_LENOVO_X280 -+ default "x270" if BOARD_LENOVO_X270_20HM -+ default "x270" if BOARD_LENOVO_X270_20K6 - - config OVERRIDE_DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -@@ -79,6 +91,8 @@ config MAINBOARD_PART_NUMBER - default "T480s" if BOARD_LENOVO_T480S - default "T580" if BOARD_LENOVO_T580 - default "X280" if BOARD_LENOVO_X280 -+ default "X270" if BOARD_LENOVO_X270_20HM -+ default "X270" if BOARD_LENOVO_X270_20K6 - - config CBFS_SIZE - default 0x900000 -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name -index 1d2888840f..43f9296bc5 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name -@@ -14,3 +14,6 @@ config BOARD_LENOVO_T580 - - config BOARD_LENOVO_X280 - bool "ThinkPad X280" -+ -+config BOARD_LENOVO_X270_20HM -+ bool "ThinkPad X270" -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..bfb312850e0ab4ea834c535df35edb45834ed248 -GIT binary patch -literal 6144 -zcmeHKUu;ul6hF83w!Qs&FT30g8FkDf5a4S-84?3TW@j;APe}bIBew+?D_HG5sZf-7&vkyok@=# -z8c(ONZ(wf#4P2Q8j}K;2xbOJT;q+(=8en9Nz8wwCI}kNrqtD;ir1>5vxw&Phzs2{M -z%))J*^Nkaf-o`vHErAoDN*Y&A{MBB|1XA+35B93JbHvvt;HaeY7Ec#IkF@Xxj@ -zP6k(;H@P#F3nedGs=JfjzpYa!OobkwSsK#P$I2^BlEsV4e37vB4$G)q{*Nk!R-c0tBVQz1gd -z3e(o>A@DI1+dL($vl6C>0P5ZV{-g^pxYUnb>@yes;8K5cv0EIue9 -zGkl+^pEC9(!=IS?2V-_OZgs0qxY=Ge4!PAyH+#j6AGy^p-0ZR&e|4+8#AFGZCACdr -zF$s@L>dO*)UBXW!^=pZJE8*{w>Xz9W8F$NSx6GcD@g-S3E3@;mT(8=*w(DGW^(yn4 -zAdX73_atnRS>NOos_hk9XyacxDE>*#THX@!3ERpD`3eMIq6WR$s^UQVC#{1Gq^xt7 -zU?8;e8r(gGm_M5z*|kA$YW)zZ-l2VHoqv+IZZ{Mr6cJz<1g##<^?;^pBXkQfsMbG8 -zj)o*n*gYj7Okj_PE?l=Ea5?ktR3gF$jT6^lfz{96(n%>cxN^_?5@v=|=~qd!SZp&lSg_nlhO)&rS-Zlsuej$mNrsT3tiG@m({M -zLe6DKG@7OK!rMxtIkS-v>J2YzEOK;RC4{_vs)Sy=U6;SoGqpjBpI>WunFu_%4N1}+ -zr66ea`laMlN~`X%R;)1}c-lG)1mlXaawb#jKo7uXt@_M-9(a%~1Ur_1aKi)nIIh(s -zEo69Ey~xpeG&5 -I4@?IB2821pg#Z8m - -literal 0 -HcmV?d00001 - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads -new file mode 100644 -index 0000000000..fcfbd75a92 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads -@@ -0,0 +1,19 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ (eDP, -+ DP1, -+ DP2, -+ HDMI1, -+ HDMI2, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c -new file mode 100644 -index 0000000000..ec5db9c53c ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c -@@ -0,0 +1,200 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include "../../variant.h" -+ -+static const struct pad_config gpio_table[] = { -+ /* ------- GPIO Community 0 ------- */ -+ -+ /* ------- GPIO Group GPP_A ------- */ -+ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */ -+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */ -+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */ -+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */ -+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */ -+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */ -+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */ -+ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */ -+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */ -+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */ -+ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */ -+ PAD_NC(GPP_A11, NONE), -+ PAD_NC(GPP_A12, NONE), /* BM_BUSY#/ISH_GP6 */ -+ PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */ -+ PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */ -+ PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSACK*/ -+ PAD_NC(GPP_A16, NONE), -+ PAD_NC(GPP_A17, NONE), -+ PAD_NC(GPP_A18, NONE), /* ISH_GP0 */ -+ PAD_NC(GPP_A19, NONE), /* ISH_GP1 */ -+ PAD_NC(GPP_A20, NONE), /* ISH_GP2 */ -+ PAD_NC(GPP_A21, NONE), /* ISH_GP3 */ -+ PAD_NC(GPP_A22, NONE), /* ISH_GP4 */ -+ PAD_NC(GPP_A23, NONE), /* ISH_GP5 */ -+ -+ /* ------- GPIO Group GPP_B ------- */ -+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ -+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ -+ PAD_NC(GPP_B2, NONE), -+ PAD_NC(GPP_B3, NONE), -+ PAD_NC(GPP_B4, NONE), -+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (Card Reader / SD) */ -+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE1 (WLAN) */ -+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE2 (GBE) */ -+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (NVMe) */ -+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WWAN) */ -+ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* -EXT_PWR_GATE */ -+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */ -+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */ -+ PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */ -+ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */ -+ PAD_NC(GPP_B16, NONE), /* GSPIO0_CLK */ -+ PAD_NC(GPP_B17, NONE), -+ PAD_NC(GPP_B18, NONE), -+ PAD_NC(GPP_B19, NONE), -+ PAD_NC(GPP_B20, NONE), -+ PAD_NC(GPP_B21, NONE), -+ PAD_NC(GPP_B22, NONE), -+ PAD_NC(GPP_B23, NONE), -+ -+ /* ------- GPIO Community 1 ------- */ -+ -+ /* ------- GPIO Group GPP_C ------- */ -+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ -+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ -+ PAD_NC(GPP_C2, NONE), /* -SMBALERT */ -+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */ -+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ -+ PAD_NC(GPP_C5, NONE), -+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */ -+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */ -+ PAD_NC(GPP_C8, NONE), -+ PAD_NC(GPP_C9, NONE), -+ PAD_NC(GPP_C10, NONE), -+ PAD_NC(GPP_C11, NONE), -+ PAD_NC(GPP_C12, NONE), -+ PAD_NC(GPP_C13, NONE), -+ PAD_NC(GPP_C14, NONE), -+ PAD_NC(GPP_C15, NONE), -+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */ -+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */ -+ PAD_NC(GPP_C18, NONE), -+ PAD_NC(GPP_C19, NONE), -+ PAD_NC(GPP_C20, NONE), -+ PAD_NC(GPP_C21, NONE), /* X280: TBT_FORCE_PWR X270: INT#_TYPEC_CPU */ -+ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ -+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ -+ -+ /* ------- GPIO Group GPP_D ------- */ -+ PAD_NC(GPP_D0, NONE), -+ PAD_NC(GPP_D1, NONE), -+ PAD_NC(GPP_D2, NONE), -+ PAD_NC(GPP_D3, NONE), -+ PAD_NC(GPP_D4, NONE), -+ PAD_NC(GPP_D5, NONE), -+ PAD_NC(GPP_D6, NONE), -+ PAD_NC(GPP_D7, NONE), -+ PAD_NC(GPP_D8, NONE), -+ PAD_NC(GPP_D9, UP_20K), -+ PAD_NC(GPP_D10, NONE), -+ PAD_NC(GPP_D11, UP_20K), -+ PAD_NC(GPP_D12, UP_20K), -+ PAD_NC(GPP_D13, NONE), -+ PAD_NC(GPP_D14, NONE), -+ PAD_NC(GPP_D15, NONE), -+ PAD_NC(GPP_D16, NONE), -+ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */ -+ PAD_NC(GPP_D18, NONE), -+ PAD_NC(GPP_D19, NONE), -+ PAD_NC(GPP_D20, NONE), -+ PAD_NC(GPP_D21, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */ -+ PAD_NC(GPP_D23, NONE), -+ -+ /* ------- GPIO Group GPP_E ------- */ -+ PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */ -+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -SATA1_DTCT */ -+ PAD_NC(GPP_E2, NONE), -+ PAD_NC(GPP_E3, NONE), /* X280: -TBT_PLUG_EVENT X270: ? */ -+ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */ -+ PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1), /* SATA1_DEVSLP */ -+ PAD_NC(GPP_E6, NONE), -+ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* -WWAN_DISABLE */ -+ PAD_NC(GPP_E8, NONE), -+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */ -+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */ -+ PAD_NC(GPP_E11, NONE), -+ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */ -+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */ -+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */ -+ PAD_NC(GPP_E15, NONE), -+ PAD_NC(GPP_E16, NONE), -+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ -+ PAD_NC(GPP_E18, NONE), -+ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */ -+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */ -+ PAD_NC(GPP_E22, NONE), -+ PAD_NC(GPP_E23, NONE), -+ -+ /* ------- GPIO Community 2 ------- */ -+ -+ /* -------- GPIO Group GPD -------- */ -+ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */ -+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */ -+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */ -+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */ -+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */ -+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */ -+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */ -+ PAD_NC(GPD7, NONE), -+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */ -+ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */ -+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */ -+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ -+ -+ /* ------- GPIO Community 3 ------- */ -+ -+ /* ------- GPIO Group GPP_F ------- */ -+ PAD_NC(GPP_F0, NONE), /* NFC_ACTIVE */ -+ PAD_NC(GPP_F1, NONE), -+ PAD_NC(GPP_F2, NONE), -+ PAD_NC(GPP_F3, NONE), -+ PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */ -+ PAD_NC(GPP_F5, UP_20K), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, RSMRST, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, RSMRST, OFF, ACPI), /* -INT_MIC_DTCT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, RSMRST, OFF, ACPI), /* PLANARID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, RSMRST, OFF, ACPI), /* PLANARID1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, RSMRST, OFF, ACPI), /* PLANARID2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, RSMRST, OFF, ACPI), /* PLANARID3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID4 */ -+ PAD_NC(GPP_F21, UP_20K), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, RSMRST, OFF, ACPI), /* -TAMPER_SW_DTCT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, RSMRST, OFF, ACPI), /* -SC_DTCT */ -+ -+ /* ------- GPIO Group GPP_G ------- */ -+ PAD_NC(GPP_G0, NONE), /* SD_CMD */ -+ PAD_NC(GPP_G1, NONE), /* SD_DATA0 */ -+ PAD_NC(GPP_G2, NONE), /* SD_DATA1 */ -+ PAD_NC(GPP_G3, NONE), /* SD_DATA2 */ -+ PAD_NC(GPP_G4, NONE), /* X280: TBT_RTD3_PWR_EN X270: SD_DATA3 */ -+ PAD_NC(GPP_G5, NONE), /* X280: TBT_FORCE_USB_PWR X270: SD_CD# */ -+ PAD_NC(GPP_G6, NONE), /* X280: -TBT_PERST X270: SD_CLK */ -+ PAD_NC(GPP_G7, NONE), /* X280: -TBT_PCIE_WAKE X270: SD_WP */ -+ -+}; -+ -+void variant_config_gpios(void) -+{ -+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c -new file mode 100644 -index 0000000000..089e605eaf ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c -@@ -0,0 +1,124 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ 0x10ec0257, // Vendor/Device ID: Realtek ALC257 -+ 0x17aa2256, // Subsystem ID -+ 18, -+ AZALIA_SUBVENDOR(0, 0x17aa2256), -+ -+ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( -+ AZALIA_INTEGRATED, -+ AZALIA_INTERNAL, -+ AZALIA_MIC_IN, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_NO_JACK_PRESENCE_DETECT, -+ 2, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( -+ AZALIA_INTEGRATED, -+ AZALIA_INTERNAL, -+ AZALIA_SPEAKER, -+ AZALIA_OTHER_ANALOG, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_NO_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_MIC_IN, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 3, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_HP_OUT, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 15 -+ )), -+ -+ //==========Widget node 0x20 - 0 :Hidden register SW reset -+ 0x0205001A, -+ 0x0204C003, -+ 0x0205001A, -+ 0x0204C003, -+ 0x05850000, -+ 0x0584F880, -+ 0x05850000, -+ 0x0584F880, -+ //==========Widget node 0x20 - 1 : ClassD 2W -+ 0x02050038, -+ 0x02048981, -+ 0x0205001B, -+ 0x02040A4B, -+ //==========Widget node 0x20 - 2 -+ 0x0205003C, -+ 0x02043154, -+ 0x0205003C, -+ 0x02043114, -+ //==========Widget node 0x20 - 3 : -+ 0x02050046, -+ 0x02040004, -+ 0x05750003, -+ 0x057409A3, -+ //==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD -+ 0x02050009, -+ 0x02046003, -+ 0x0205000A, -+ 0x02047770, -+ //==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB) -+ 0x02050037, -+ 0x0204FE15, -+ 0x02050030, -+ 0x02049004, -+ -+ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI -+ 0x80860101, // Subsystem ID -+ 4, -+ AZALIA_SUBVENDOR(2, 0x80860101), -+ -+ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+}; -+ -+const u32 pc_beep_verbs[] = {}; -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c -new file mode 100644 -index 0000000000..a2317c026d ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c -@@ -0,0 +1,19 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+ -+void mainboard_memory_init_params(FSPM_UPD *mupd) -+{ -+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; -+ mem_cfg->DqPinsInterleaved = false; /* DDR_DQ probably not in interleave mode */ -+ mem_cfg->CaVrefConfig = 1; /* VREF_CA to CH_A */ -+ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; -+ -+ /* Get SPD for memory slots */ -+ struct spd_block blk = { .addr_map = { 0x50 } }; -+ get_spd_smbus(&blk); -+ dump_spd_info(&blk); -+ -+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb -new file mode 100644 -index 0000000000..3191cdfac5 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb -@@ -0,0 +1,89 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+chip soc/intel/skylake -+ device domain 0 on -+ device ref south_xhci on -+ register "usb2_ports" = "{ -+ [0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on) -+ [1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A) -+ [2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot) -+ [3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB docking station) -+ [4] = USB2_PORT_MID(OC_SKIP), // JIRCAM (IR camera) -+ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB) -+ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB) -+ [7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam) -+ [8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader) -+ [9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel) -+ }" -+ register "usb3_ports" = "{ -+ [0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on) -+ [1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A) -+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader) -+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSB3 (USB docking station) -+ }" -+ end -+ -+ # PCIe -+ # PCIe Controller 1 - 1x2 + 2x1 -+ # PCIE 1 - RP1 - Media / SD - CLKOUT0 - CLKREQ0 -+ # PCIE 2 - USB3 Port -+ # PCIE 3 - RP3 - WiGig - CLKOUT1 - CLKREQ1 -+ # PCIE 3 - RP3 - WLAN - CLKOUT2 - CLKREQ2 -+ # PCIE 4 - GbE - GbE - CLKOUT3 - CLKREQ3 -+ # PCIe Controller 2 - 1x4 -+ # PCIE 5 - RP5 - NVMe - CLKOUT4 - CLKREQ4 -+ # PCIe Controller 3 - 4x1 -+ # PCIE 7 - RP8 - WWAN - CLKOUT5 - CLKREQ5 -+ # PCIE 8 - Optane -+ -+ # Media / SD - x2 -+ device ref pcie_rp1 on -+ register "PcieRpClkReqSupport[0]" = "true" -+ register "PcieRpClkReqNumber[0]" = "0" -+ register "PcieRpClkSrcNumber[0]" = "0" -+ register "PcieRpAdvancedErrorReporting[0]" = "true" -+ register "PcieRpHotPlug[0]" = "true" -+ end -+ -+ # M.2 WLAN x1 -+ device ref pcie_rp3 on -+ register "PcieRpClkReqSupport[2]" = "true" -+ register "PcieRpClkReqNumber[2]" = "2" -+ register "PcieRpClkSrcNumber[2]" = "2" -+ register "PcieRpAdvancedErrorReporting[2]" = "true" -+ register "PcieRpLtrEnable[2]" = "true" -+ smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X" -+ end -+ -+ # Ethernet (clobbers RP4) -+ device ref gbe on -+ register "LanClkReqSupported" = "true" -+ register "LanClkReqNumber" = "3" -+ register "PcieRpClkReqNumber[3]" = "3" -+ register "PcieRpClkSrcNumber[3]" = "3" -+ register "EnableLanLtr" = "true" -+ register "EnableLanK1Off" = "true" -+ end -+ -+ # M.2 2280 SSD - x4 (RP9) -+ device ref pcie_rp5 on -+ register "PcieRpClkReqSupport[4]" = "true" -+ register "PcieRpClkReqNumber[4]" = "4" -+ register "PcieRpClkSrcNumber[4]" = "4" -+ register "PcieRpAdvancedErrorReporting[4]" = "true" -+ register "PcieRpLtrEnable[4]" = "true" -+ register "PcieRpHotPlug[4]" = "false" -+ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" -+ end -+ -+ # M.2 WWAN x1 -+ device ref pcie_rp8 on -+ register "PcieRpClkReqSupport[7]" = "true" -+ register "PcieRpClkReqNumber[7]" = "5" -+ register "PcieRpClkSrcNumber[7]" = "5" -+ register "PcieRpAdvancedErrorReporting[7]" = "true" -+ register "PcieRpLtrEnable[7]" = "true" -+ smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X" -+ end -+ end -+end --- -2.47.3 - diff --git a/config/coreboot/default/patches/0048-me_cleaner-don-t-modify-if-k-is-used.patch b/config/coreboot/default/patches/0048-me_cleaner-don-t-modify-if-k-is-used.patch new file mode 100644 index 00000000..db705b60 --- /dev/null +++ b/config/coreboot/default/patches/0048-me_cleaner-don-t-modify-if-k-is-used.patch @@ -0,0 +1,44 @@ +From fb4bc4ed6e1fca747e54a34127ca927cb70318ad Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Fri, 20 Feb 2026 19:31:19 +0000 +Subject: [PATCH 48/51] me_cleaner: don't modify if -k is used + +don't remove *anything*. in libreboot, we only +ever use -k when we werely want to extract the +ME, but otherwise not modify it. this is because +we rely on bruteforce, detecting when me.bin is +found based on mecleaner validation. + +this way, we can much more reliable get the ME +images. + +Signed-off-by: Leah Rowe +--- + util/me_cleaner/me_cleaner.py | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py +index 228bac899f..269aa4ad04 100755 +--- a/util/me_cleaner/me_cleaner.py ++++ b/util/me_cleaner/me_cleaner.py +@@ -677,7 +677,7 @@ if __name__ == "__main__": + # ME 6 Ignition: wipe everything + me6_ignition = False + if not args.check and not args.soft_disable_only and \ +- variant == "ME" and version[0] == 6: ++ variant == "ME" and version[0] == 6 and not args.keep_modules: + mef.seek(ftpr_offset + 0x20) + num_modules = unpack(" +Date: Tue, 17 Feb 2026 16:18:15 -0800 +Subject: [PATCH 49/51] mb/lenovo/sklkbl: Add Lenovo Thinkpad X270 as a variant + +This machine is somewhat dissimilar from the X280 in the PCIe allocations in the overridetree. It also lacks soldered RAM, having a single SODIMM slot. + +This port was based upon the work done by Johann C Rode for the X280 and the VBT and hda verbs were obtained from that work, not obtained separately. GPIO ports and PCI-e allocations have been checked against schematics after editing. + +Functionality has been validated on a ThinkPad X270 with machine type model 20HMS2WU03 with 16GB onboard RAM and i5-7300U CPU. The laptop has been tested running libreboot, booting Guix via GRUB payload. A check of the hardware shows no issues (video, wifi, wired ethernet, reboot, sleep, NVMe). + +An untested variety allowing for a Skylake CPU (for 20K5 and 20K6) has been included. +--- + src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 14 ++ + .../lenovo/sklkbl_thinkpad/Kconfig.name | 3 + + .../sklkbl_thinkpad/variants/x270/data.vbt | Bin 0 -> 6144 bytes + .../variants/x270/gma-mainboard.ads | 19 ++ + .../sklkbl_thinkpad/variants/x270/gpio.c | 200 ++++++++++++++++++ + .../sklkbl_thinkpad/variants/x270/hda_verb.c | 124 +++++++++++ + .../variants/x270/memory_init_params.c | 19 ++ + .../variants/x270/overridetree.cb | 89 ++++++++ + 8 files changed, 468 insertions(+) + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +index 9d4b5f4965..1aaef40a0c 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +@@ -59,6 +59,16 @@ config BOARD_LENOVO_X280 + select SOC_INTEL_KABYLAKE + select HAVE_SPD_IN_CBFS + ++config BOARD_LENOVO_X270_20K6 ++ bool ++ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON ++ select SOC_INTEL_SKYLAKE ++ ++config BOARD_LENOVO_X270_20HM ++ bool ++ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON ++ select SOC_INTEL_KABYLAKE ++ + if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON + + config MAINBOARD_DIR +@@ -70,6 +80,8 @@ config VARIANT_DIR + default "t480s" if BOARD_LENOVO_T480S + default "t580" if BOARD_LENOVO_T580 + default "x280" if BOARD_LENOVO_X280 ++ default "x270" if BOARD_LENOVO_X270_20HM ++ default "x270" if BOARD_LENOVO_X270_20K6 + + config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" +@@ -80,6 +92,8 @@ config MAINBOARD_PART_NUMBER + default "T480s" if BOARD_LENOVO_T480S + default "T580" if BOARD_LENOVO_T580 + default "X280" if BOARD_LENOVO_X280 ++ default "X270" if BOARD_LENOVO_X270_20HM ++ default "X270" if BOARD_LENOVO_X270_20K6 + + config CBFS_SIZE + default 0x900000 +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name +index 1d2888840f..43f9296bc5 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name +@@ -14,3 +14,6 @@ config BOARD_LENOVO_T580 + + config BOARD_LENOVO_X280 + bool "ThinkPad X280" ++ ++config BOARD_LENOVO_X270_20HM ++ bool "ThinkPad X270" +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..bfb312850e0ab4ea834c535df35edb45834ed248 +GIT binary patch +literal 6144 +zcmeHKUu;ul6hF83w!Qs&FT30g8FkDf5a4S-84?3TW@j;APe}bIBew+?D_HG5sZf-7&vkyok@=# +z8c(ONZ(wf#4P2Q8j}K;2xbOJT;q+(=8en9Nz8wwCI}kNrqtD;ir1>5vxw&Phzs2{M +z%))J*^Nkaf-o`vHErAoDN*Y&A{MBB|1XA+35B93JbHvvt;HaeY7Ec#IkF@Xxj@ +zP6k(;H@P#F3nedGs=JfjzpYa!OobkwSsK#P$I2^BlEsV4e37vB4$G)q{*Nk!R-c0tBVQz1gd +z3e(o>A@DI1+dL($vl6C>0P5ZV{-g^pxYUnb>@yes;8K5cv0EIue9 +zGkl+^pEC9(!=IS?2V-_OZgs0qxY=Ge4!PAyH+#j6AGy^p-0ZR&e|4+8#AFGZCACdr +zF$s@L>dO*)UBXW!^=pZJE8*{w>Xz9W8F$NSx6GcD@g-S3E3@;mT(8=*w(DGW^(yn4 +zAdX73_atnRS>NOos_hk9XyacxDE>*#THX@!3ERpD`3eMIq6WR$s^UQVC#{1Gq^xt7 +zU?8;e8r(gGm_M5z*|kA$YW)zZ-l2VHoqv+IZZ{Mr6cJz<1g##<^?;^pBXkQfsMbG8 +zj)o*n*gYj7Okj_PE?l=Ea5?ktR3gF$jT6^lfz{96(n%>cxN^_?5@v=|=~qd!SZp&lSg_nlhO)&rS-Zlsuej$mNrsT3tiG@m({M +zLe6DKG@7OK!rMxtIkS-v>J2YzEOK;RC4{_vs)Sy=U6;SoGqpjBpI>WunFu_%4N1}+ +zr66ea`laMlN~`X%R;)1}c-lG)1mlXaawb#jKo7uXt@_M-9(a%~1Ur_1aKi)nIIh(s +zEo69Ey~xpeG&5 +I4@?IB2821pg#Z8m + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads +new file mode 100644 +index 0000000000..fcfbd75a92 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads +@@ -0,0 +1,19 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (eDP, ++ DP1, ++ DP2, ++ HDMI1, ++ HDMI2, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c +new file mode 100644 +index 0000000000..ec5db9c53c +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c +@@ -0,0 +1,200 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include "../../variant.h" ++ ++static const struct pad_config gpio_table[] = { ++ /* ------- GPIO Community 0 ------- */ ++ ++ /* ------- GPIO Group GPP_A ------- */ ++ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */ ++ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */ ++ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */ ++ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */ ++ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */ ++ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */ ++ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */ ++ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */ ++ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */ ++ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */ ++ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */ ++ PAD_NC(GPP_A11, NONE), ++ PAD_NC(GPP_A12, NONE), /* BM_BUSY#/ISH_GP6 */ ++ PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */ ++ PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */ ++ PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSACK*/ ++ PAD_NC(GPP_A16, NONE), ++ PAD_NC(GPP_A17, NONE), ++ PAD_NC(GPP_A18, NONE), /* ISH_GP0 */ ++ PAD_NC(GPP_A19, NONE), /* ISH_GP1 */ ++ PAD_NC(GPP_A20, NONE), /* ISH_GP2 */ ++ PAD_NC(GPP_A21, NONE), /* ISH_GP3 */ ++ PAD_NC(GPP_A22, NONE), /* ISH_GP4 */ ++ PAD_NC(GPP_A23, NONE), /* ISH_GP5 */ ++ ++ /* ------- GPIO Group GPP_B ------- */ ++ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ ++ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ ++ PAD_NC(GPP_B2, NONE), ++ PAD_NC(GPP_B3, NONE), ++ PAD_NC(GPP_B4, NONE), ++ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (Card Reader / SD) */ ++ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE1 (WLAN) */ ++ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE2 (GBE) */ ++ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (NVMe) */ ++ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), ++ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WWAN) */ ++ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* -EXT_PWR_GATE */ ++ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */ ++ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */ ++ PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */ ++ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */ ++ PAD_NC(GPP_B16, NONE), /* GSPIO0_CLK */ ++ PAD_NC(GPP_B17, NONE), ++ PAD_NC(GPP_B18, NONE), ++ PAD_NC(GPP_B19, NONE), ++ PAD_NC(GPP_B20, NONE), ++ PAD_NC(GPP_B21, NONE), ++ PAD_NC(GPP_B22, NONE), ++ PAD_NC(GPP_B23, NONE), ++ ++ /* ------- GPIO Community 1 ------- */ ++ ++ /* ------- GPIO Group GPP_C ------- */ ++ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ ++ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ ++ PAD_NC(GPP_C2, NONE), /* -SMBALERT */ ++ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */ ++ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ ++ PAD_NC(GPP_C5, NONE), ++ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */ ++ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */ ++ PAD_NC(GPP_C8, NONE), ++ PAD_NC(GPP_C9, NONE), ++ PAD_NC(GPP_C10, NONE), ++ PAD_NC(GPP_C11, NONE), ++ PAD_NC(GPP_C12, NONE), ++ PAD_NC(GPP_C13, NONE), ++ PAD_NC(GPP_C14, NONE), ++ PAD_NC(GPP_C15, NONE), ++ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */ ++ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */ ++ PAD_NC(GPP_C18, NONE), ++ PAD_NC(GPP_C19, NONE), ++ PAD_NC(GPP_C20, NONE), ++ PAD_NC(GPP_C21, NONE), /* X280: TBT_FORCE_PWR X270: INT#_TYPEC_CPU */ ++ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ ++ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ ++ ++ /* ------- GPIO Group GPP_D ------- */ ++ PAD_NC(GPP_D0, NONE), ++ PAD_NC(GPP_D1, NONE), ++ PAD_NC(GPP_D2, NONE), ++ PAD_NC(GPP_D3, NONE), ++ PAD_NC(GPP_D4, NONE), ++ PAD_NC(GPP_D5, NONE), ++ PAD_NC(GPP_D6, NONE), ++ PAD_NC(GPP_D7, NONE), ++ PAD_NC(GPP_D8, NONE), ++ PAD_NC(GPP_D9, UP_20K), ++ PAD_NC(GPP_D10, NONE), ++ PAD_NC(GPP_D11, UP_20K), ++ PAD_NC(GPP_D12, UP_20K), ++ PAD_NC(GPP_D13, NONE), ++ PAD_NC(GPP_D14, NONE), ++ PAD_NC(GPP_D15, NONE), ++ PAD_NC(GPP_D16, NONE), ++ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */ ++ PAD_NC(GPP_D18, NONE), ++ PAD_NC(GPP_D19, NONE), ++ PAD_NC(GPP_D20, NONE), ++ PAD_NC(GPP_D21, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */ ++ PAD_NC(GPP_D23, NONE), ++ ++ /* ------- GPIO Group GPP_E ------- */ ++ PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */ ++ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -SATA1_DTCT */ ++ PAD_NC(GPP_E2, NONE), ++ PAD_NC(GPP_E3, NONE), /* X280: -TBT_PLUG_EVENT X270: ? */ ++ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */ ++ PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1), /* SATA1_DEVSLP */ ++ PAD_NC(GPP_E6, NONE), ++ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* -WWAN_DISABLE */ ++ PAD_NC(GPP_E8, NONE), ++ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */ ++ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */ ++ PAD_NC(GPP_E11, NONE), ++ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */ ++ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */ ++ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */ ++ PAD_NC(GPP_E15, NONE), ++ PAD_NC(GPP_E16, NONE), ++ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ ++ PAD_NC(GPP_E18, NONE), ++ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), ++ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */ ++ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */ ++ PAD_NC(GPP_E22, NONE), ++ PAD_NC(GPP_E23, NONE), ++ ++ /* ------- GPIO Community 2 ------- */ ++ ++ /* -------- GPIO Group GPD -------- */ ++ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */ ++ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */ ++ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */ ++ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */ ++ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */ ++ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */ ++ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */ ++ PAD_NC(GPD7, NONE), ++ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */ ++ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */ ++ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */ ++ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ ++ ++ /* ------- GPIO Community 3 ------- */ ++ ++ /* ------- GPIO Group GPP_F ------- */ ++ PAD_NC(GPP_F0, NONE), /* NFC_ACTIVE */ ++ PAD_NC(GPP_F1, NONE), ++ PAD_NC(GPP_F2, NONE), ++ PAD_NC(GPP_F3, NONE), ++ PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */ ++ PAD_NC(GPP_F5, UP_20K), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, RSMRST, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, RSMRST, OFF, ACPI), /* -INT_MIC_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, RSMRST, OFF, ACPI), /* PLANARID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, RSMRST, OFF, ACPI), /* PLANARID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, RSMRST, OFF, ACPI), /* PLANARID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, RSMRST, OFF, ACPI), /* PLANARID3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID4 */ ++ PAD_NC(GPP_F21, UP_20K), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, RSMRST, OFF, ACPI), /* -TAMPER_SW_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, RSMRST, OFF, ACPI), /* -SC_DTCT */ ++ ++ /* ------- GPIO Group GPP_G ------- */ ++ PAD_NC(GPP_G0, NONE), /* SD_CMD */ ++ PAD_NC(GPP_G1, NONE), /* SD_DATA0 */ ++ PAD_NC(GPP_G2, NONE), /* SD_DATA1 */ ++ PAD_NC(GPP_G3, NONE), /* SD_DATA2 */ ++ PAD_NC(GPP_G4, NONE), /* X280: TBT_RTD3_PWR_EN X270: SD_DATA3 */ ++ PAD_NC(GPP_G5, NONE), /* X280: TBT_FORCE_USB_PWR X270: SD_CD# */ ++ PAD_NC(GPP_G6, NONE), /* X280: -TBT_PERST X270: SD_CLK */ ++ PAD_NC(GPP_G7, NONE), /* X280: -TBT_PCIE_WAKE X270: SD_WP */ ++ ++}; ++ ++void variant_config_gpios(void) ++{ ++ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c +new file mode 100644 +index 0000000000..089e605eaf +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c +@@ -0,0 +1,124 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ 0x10ec0257, // Vendor/Device ID: Realtek ALC257 ++ 0x17aa2256, // Subsystem ID ++ 18, ++ AZALIA_SUBVENDOR(0, 0x17aa2256), ++ ++ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_MIC_IN, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_MIC_IN, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 3, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_HP_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 15 ++ )), ++ ++ //==========Widget node 0x20 - 0 :Hidden register SW reset ++ 0x0205001A, ++ 0x0204C003, ++ 0x0205001A, ++ 0x0204C003, ++ 0x05850000, ++ 0x0584F880, ++ 0x05850000, ++ 0x0584F880, ++ //==========Widget node 0x20 - 1 : ClassD 2W ++ 0x02050038, ++ 0x02048981, ++ 0x0205001B, ++ 0x02040A4B, ++ //==========Widget node 0x20 - 2 ++ 0x0205003C, ++ 0x02043154, ++ 0x0205003C, ++ 0x02043114, ++ //==========Widget node 0x20 - 3 : ++ 0x02050046, ++ 0x02040004, ++ 0x05750003, ++ 0x057409A3, ++ //==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD ++ 0x02050009, ++ 0x02046003, ++ 0x0205000A, ++ 0x02047770, ++ //==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB) ++ 0x02050037, ++ 0x0204FE15, ++ 0x02050030, ++ 0x02049004, ++ ++ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI ++ 0x80860101, // Subsystem ID ++ 4, ++ AZALIA_SUBVENDOR(2, 0x80860101), ++ ++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++}; ++ ++const u32 pc_beep_verbs[] = {}; ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c +new file mode 100644 +index 0000000000..a2317c026d +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c +@@ -0,0 +1,19 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_memory_init_params(FSPM_UPD *mupd) ++{ ++ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; ++ mem_cfg->DqPinsInterleaved = false; /* DDR_DQ probably not in interleave mode */ ++ mem_cfg->CaVrefConfig = 1; /* VREF_CA to CH_A */ ++ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; ++ ++ /* Get SPD for memory slots */ ++ struct spd_block blk = { .addr_map = { 0x50 } }; ++ get_spd_smbus(&blk); ++ dump_spd_info(&blk); ++ ++ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb +new file mode 100644 +index 0000000000..3191cdfac5 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb +@@ -0,0 +1,89 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++chip soc/intel/skylake ++ device domain 0 on ++ device ref south_xhci on ++ register "usb2_ports" = "{ ++ [0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on) ++ [1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A) ++ [2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot) ++ [3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB docking station) ++ [4] = USB2_PORT_MID(OC_SKIP), // JIRCAM (IR camera) ++ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB) ++ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB) ++ [7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam) ++ [8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader) ++ [9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel) ++ }" ++ register "usb3_ports" = "{ ++ [0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on) ++ [1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A) ++ [2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader) ++ [3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSB3 (USB docking station) ++ }" ++ end ++ ++ # PCIe ++ # PCIe Controller 1 - 1x2 + 2x1 ++ # PCIE 1 - RP1 - Media / SD - CLKOUT0 - CLKREQ0 ++ # PCIE 2 - USB3 Port ++ # PCIE 3 - RP3 - WiGig - CLKOUT1 - CLKREQ1 ++ # PCIE 3 - RP3 - WLAN - CLKOUT2 - CLKREQ2 ++ # PCIE 4 - GbE - GbE - CLKOUT3 - CLKREQ3 ++ # PCIe Controller 2 - 1x4 ++ # PCIE 5 - RP5 - NVMe - CLKOUT4 - CLKREQ4 ++ # PCIe Controller 3 - 4x1 ++ # PCIE 7 - RP8 - WWAN - CLKOUT5 - CLKREQ5 ++ # PCIE 8 - Optane ++ ++ # Media / SD - x2 ++ device ref pcie_rp1 on ++ register "PcieRpClkReqSupport[0]" = "true" ++ register "PcieRpClkReqNumber[0]" = "0" ++ register "PcieRpClkSrcNumber[0]" = "0" ++ register "PcieRpAdvancedErrorReporting[0]" = "true" ++ register "PcieRpHotPlug[0]" = "true" ++ end ++ ++ # M.2 WLAN x1 ++ device ref pcie_rp3 on ++ register "PcieRpClkReqSupport[2]" = "true" ++ register "PcieRpClkReqNumber[2]" = "2" ++ register "PcieRpClkSrcNumber[2]" = "2" ++ register "PcieRpAdvancedErrorReporting[2]" = "true" ++ register "PcieRpLtrEnable[2]" = "true" ++ smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X" ++ end ++ ++ # Ethernet (clobbers RP4) ++ device ref gbe on ++ register "LanClkReqSupported" = "true" ++ register "LanClkReqNumber" = "3" ++ register "PcieRpClkReqNumber[3]" = "3" ++ register "PcieRpClkSrcNumber[3]" = "3" ++ register "EnableLanLtr" = "true" ++ register "EnableLanK1Off" = "true" ++ end ++ ++ # M.2 2280 SSD - x4 (RP9) ++ device ref pcie_rp5 on ++ register "PcieRpClkReqSupport[4]" = "true" ++ register "PcieRpClkReqNumber[4]" = "4" ++ register "PcieRpClkSrcNumber[4]" = "4" ++ register "PcieRpAdvancedErrorReporting[4]" = "true" ++ register "PcieRpLtrEnable[4]" = "true" ++ register "PcieRpHotPlug[4]" = "false" ++ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" ++ end ++ ++ # M.2 WWAN x1 ++ device ref pcie_rp8 on ++ register "PcieRpClkReqSupport[7]" = "true" ++ register "PcieRpClkReqNumber[7]" = "5" ++ register "PcieRpClkSrcNumber[7]" = "5" ++ register "PcieRpAdvancedErrorReporting[7]" = "true" ++ register "PcieRpLtrEnable[7]" = "true" ++ smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X" ++ end ++ end ++end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch b/config/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch deleted file mode 100644 index df86ee01..00000000 --- a/config/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch +++ /dev/null @@ -1,132 +0,0 @@ -From 9d39437b9447ab6e6164440bddf459111bd4903f Mon Sep 17 00:00:00 2001 -From: Kat Inskip -Date: Sat, 21 Feb 2026 19:48:17 +0000 -Subject: [PATCH] mb/lenovo/x270: Provide correct vbt and hda_verb - ---- - .../sklkbl_thinkpad/variants/x270/data.vbt | Bin 6144 -> 4449 bytes - .../sklkbl_thinkpad/variants/x270/hda_verb.c | 29 +++++++++--------- - 2 files changed, 15 insertions(+), 14 deletions(-) - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt -index bfb312850e0ab4ea834c535df35edb45834ed248..c6561a9c57e4e600bc0adb5f6679f2f5d6b6c640 100644 -GIT binary patch -delta 1043 -zcmZoLc&Ic%f;Calfx%$%L?+>h1_E+-8N?V21pmEaU`SzPl;klqFfjDYD@o1K2+~vt -z_MVtzqhMg55a6s}XrgCqqM%@?Z)B)%WMF8jpkQcVWoTw)YB_PgJ|n}#S5l0olUW%J -zmH8bQ7#aQ=F)(m2Ft9K%I51!UfyozHMC%0@m~0uDSQr@8IT+X^kQH$;FffDp4h#xl -z8bl~CurORpU|?Wi|HJ{}Gcd3-Ft9R!tPx;TV1x)UFbFU>fRs5fu(NPN#30UK;9yW- -zRA7P#ft0y`jTR8#5QD0NNii@mDnP7fU|>*S5CDk_2ry`1Q#Lt(Nn)}ATY5b+BLl;q -zDh37ys6!YT7(sx6fsfIEA&*mz!Jk=!p@x}>p^e#sL5t-Cg8-)jgE6N7gBzy+LnNmF -z!(~=3hP$j>49{7)7(TLcG5lubVqj(CV&G@vVvuCxVo+w|V$fydVlZdpVsK>RV(@0; -zVhCm9Vu)wsV#s9k=3-zgW%%=-sR0x!3=9knjO-wHGc*W7Xa)fmhCWS(hB;92IZ$!V -z4=iAHTu_?(1IuJZHeH|p|Jm6Y{{25E!SMe-hb_othYu_u&oR0{ReC^aA27|#8~~;n -z7(yWG7$Ttj|Nl2@GH+mFWY~O*Rg<|MY#YO>RjXDpFlbI;V0PwG$m9~L=HhDQQdrF; -zw3mzPIG4g(E}{QiT%6nr`rJZ}++5z=3WeN4&D>nQ+zOkyg^qG_o#$5g$}Pms!zIY0 -zV9q1t$-@=Qqfp5s)Xl>+l}BMWkI-2juIoGse|d!XdATHc73_J10(rTjc@?x9d4(qP -za?RycILs?_m6z*2uL3KdkT@TgBA3mJn+L(*wrIjyy_}&vV92KFDLv -zD6u(}E1HG>1Or3FDlZ6mhk<$WLq5C7@A-r#%kwKri!pS#F)%QAGH@}3G6XQBFz7H& -kV|c;Lpl851c_M$+Bmr(DBv}6+5)=${r;WiWnGIq+0Ot0jSpWb4 - -delta 808 -zcmaE;)L<|{f|X04kilTGBa`q%0|BLr3}Oto`2W3PU`SzPl;klqFf;bdD@o1K2+~vt -z_V&^DcA6MxqiANV5a6s}XrgCqqM%@4sBdVdZ)9L-si0tBY-MU@WoSNem;S_eVvL59 -zSs4xM*_{{|8U7kE@Nlqra5!jiC`fP!xUe{=uqcSI2n09?BseG-Cs$;B%pfk41A_vHW&l$x4A&AE92giP -zgh70R>+B2+tPBhcP7LeOpPyu8rNLWCCp${g?0TZ2U$Rsz}l1X5)C6gG8t_NAi%*ep-r;34r0pbFX0T9f` -zXuz<9Lk_}$k_pTw7~D7%7&18o7-~2K82UK`7&uwE7=&557-U(w7}Qz07z|mt7_3>j -z7+hJo82nke7$RA@7?N4J7;;&;7|L0>7#dl*7`j=x7^bqaaWTwifrvL*3 -zg8+j7gW=>2Y~q^_vvD!kgT2kLYSpS$3=Eo67?>+L73OmaZRF(I&8hH^Q|L1%*I!Nr -zWiBC8E-rg6g;Xw~axSh$E`{Y>LOZ#*4s$8I{9}tk){DbW~<0kg^a6CDHNgDv8%8_CK - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c -index 089e605eaf..60289355f8 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c -@@ -3,10 +3,10 @@ - #include - - const u32 cim_verb_data[] = { -- 0x10ec0257, // Vendor/Device ID: Realtek ALC257 -- 0x17aa2256, // Subsystem ID -- 18, -- AZALIA_SUBVENDOR(0, 0x17aa2256), -+ 0x10ec0298, // Vendor/Device ID: Realtek ALC298 -+ 0x17aa5062, // Subsystem ID -+ 19, -+ AZALIA_SUBVENDOR(0, 0x17aa5062), - - AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( - AZALIA_INTEGRATED, -@@ -15,7 +15,7 @@ const u32 cim_verb_data[] = { - AZALIA_OTHER_DIGITAL, - AZALIA_COLOR_UNKNOWN, - AZALIA_NO_JACK_PRESENCE_DETECT, -- 2, 0 -+ 4, 0 - )), - AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device - AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( -@@ -27,28 +27,29 @@ const u32 cim_verb_data[] = { - AZALIA_NO_JACK_PRESENCE_DETECT, - 1, 0 - )), -- AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), -- AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( -+ AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( - AZALIA_JACK, -- AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT, - AZALIA_MIC_IN, - AZALIA_STEREO_MONO_1_8, - AZALIA_BLACK, - AZALIA_JACK_PRESENCE_DETECT, - 3, 0 - )), -+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), -- AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), -- AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x1d, 0x40648605), // does not describe a jack or internal device - AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( - AZALIA_JACK, -- AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT, - AZALIA_HP_OUT, - AZALIA_STEREO_MONO_1_8, - AZALIA_BLACK, - AZALIA_JACK_PRESENCE_DETECT, -- 1, 15 -+ 2, 0 - )), - - //==========Widget node 0x20 - 0 :Hidden register SW reset -@@ -107,7 +108,7 @@ const u32 cim_verb_data[] = { - AZALIA_OTHER_DIGITAL, - AZALIA_COLOR_UNKNOWN, - AZALIA_JACK_PRESENCE_DETECT, -- 1, 0 -+ 2, 0 - )), - AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( - AZALIA_JACK, -@@ -116,7 +117,7 @@ const u32 cim_verb_data[] = { - AZALIA_OTHER_DIGITAL, - AZALIA_COLOR_UNKNOWN, - AZALIA_JACK_PRESENCE_DETECT, -- 1, 0 -+ 3, 0 - )), - }; - --- -2.52.0 - diff --git a/config/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port.patch b/config/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port.patch deleted file mode 100644 index a2e5d5a2..00000000 --- a/config/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port.patch +++ /dev/null @@ -1,1528 +0,0 @@ -From 24856e5e383b1b9aa078b879064b8c2b99f4494c Mon Sep 17 00:00:00 2001 -From: Todd Baker -Date: Thu, 12 Mar 2026 13:12:04 -0400 -Subject: [PATCH] mb/dell: Add OptiPlex 3040 Micro port (upstream-compatible) - -Based on the OptiPlex 3050 Micro (same Skylake H110 PCH-H platform). -Key differences from 3050: -- DDR3L SODIMMs (256-byte SPD at 0x50/0x52) -- Intel Pentium G4400T-class CPUs (Skylake only, no Kabylake/Coffeelake) -- Realtek ALC3234 HDA (subsystem ID 0x102806bb) -- VBT: DDI E entry removed (phantom port, causes i915 WARN_ON) -- PCIe root ports rp5/rp8/rp21 enabled (PcieRpEnable removed; use device on/off) -- HECI1 set off to prevent stall when HAP bit is set (ME neutralized) - -Signed-off-by: Todd Baker ---- - src/mainboard/dell/optiplex_3040/Kconfig | 37 ++ - src/mainboard/dell/optiplex_3040/Kconfig.name | 4 + - src/mainboard/dell/optiplex_3040/Makefile.mk | 12 + - src/mainboard/dell/optiplex_3040/acpi/ec.asl | 3 + - .../dell/optiplex_3040/acpi/superio.asl | 3 + - .../dell/optiplex_3040/board_info.txt | 7 + - src/mainboard/dell/optiplex_3040/bootblock.c | 107 ++++ - src/mainboard/dell/optiplex_3040/cmos.default | 5 + - src/mainboard/dell/optiplex_3040/cmos.layout | 54 ++ - src/mainboard/dell/optiplex_3040/data.vbt | Bin 0 -> 4300 bytes - .../dell/optiplex_3040/devicetree.cb | 100 ++++ - src/mainboard/dell/optiplex_3040/dsdt.asl | 27 + - .../dell/optiplex_3040/gma-mainboard.ads | 19 + - src/mainboard/dell/optiplex_3040/hda_verb.c | 90 +++ - .../dell/optiplex_3040/include/early_gpio.h | 11 + - .../dell/optiplex_3040/include/gpio.h | 241 +++++++++ - src/mainboard/dell/optiplex_3040/ramstage.c | 512 ++++++++++++++++++ - src/mainboard/dell/optiplex_3040/romstage.c | 22 + - src/mainboard/dell/optiplex_3040/sch5555_ec.c | 54 ++ - src/mainboard/dell/optiplex_3040/sch5555_ec.h | 10 + - 20 files changed, 1318 insertions(+) - create mode 100644 src/mainboard/dell/optiplex_3040/Kconfig - create mode 100644 src/mainboard/dell/optiplex_3040/Kconfig.name - create mode 100644 src/mainboard/dell/optiplex_3040/Makefile.mk - create mode 100644 src/mainboard/dell/optiplex_3040/acpi/ec.asl - create mode 100644 src/mainboard/dell/optiplex_3040/acpi/superio.asl - create mode 100644 src/mainboard/dell/optiplex_3040/board_info.txt - create mode 100644 src/mainboard/dell/optiplex_3040/bootblock.c - create mode 100644 src/mainboard/dell/optiplex_3040/cmos.default - create mode 100644 src/mainboard/dell/optiplex_3040/cmos.layout - create mode 100644 src/mainboard/dell/optiplex_3040/data.vbt - create mode 100644 src/mainboard/dell/optiplex_3040/devicetree.cb - create mode 100644 src/mainboard/dell/optiplex_3040/dsdt.asl - create mode 100644 src/mainboard/dell/optiplex_3040/gma-mainboard.ads - create mode 100644 src/mainboard/dell/optiplex_3040/hda_verb.c - create mode 100644 src/mainboard/dell/optiplex_3040/include/early_gpio.h - create mode 100644 src/mainboard/dell/optiplex_3040/include/gpio.h - create mode 100644 src/mainboard/dell/optiplex_3040/ramstage.c - create mode 100644 src/mainboard/dell/optiplex_3040/romstage.c - create mode 100644 src/mainboard/dell/optiplex_3040/sch5555_ec.c - create mode 100644 src/mainboard/dell/optiplex_3040/sch5555_ec.h - -diff --git a/src/mainboard/dell/optiplex_3040/Kconfig b/src/mainboard/dell/optiplex_3040/Kconfig -new file mode 100644 -index 0000000000..eab8e7d814 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/Kconfig -@@ -0,0 +1,37 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+if BOARD_DELL_OPTIPLEX_3040 -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ select BOARD_ROMSIZE_KB_16384 -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ select INTEL_GMA_ADD_VBT -+ select INTEL_GMA_HAVE_VBT -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_SUPPORTS_SKYLAKE_CPU -+ select SKYLAKE_SOC_PCH_H -+ select AZALIA_USE_LEGACY_VERB_TABLE -+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB -+ select SOC_INTEL_KABYLAKE -+ select SUPERIO_SMSC_SCH555x -+ -+config CBFS_SIZE -+ default 0x900000 -+ -+config MAINBOARD_DIR -+ default "dell/optiplex_3040" -+ -+config MAINBOARD_PART_NUMBER -+ default "OptiPlex 3040 Micro" -+ -+config INTEL_GMA_VBT_FILE -+ default "src/mainboard/$(MAINBOARDDIR)/data.vbt" -+ -+config DIMM_SPD_SIZE -+ default 256 # DDR3L -+ -+endif -diff --git a/src/mainboard/dell/optiplex_3040/Kconfig.name b/src/mainboard/dell/optiplex_3040/Kconfig.name -new file mode 100644 -index 0000000000..e06da5010a ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/Kconfig.name -@@ -0,0 +1,4 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_DELL_OPTIPLEX_3040 -+ bool "Dell OptiPlex 3040 Micro" -diff --git a/src/mainboard/dell/optiplex_3040/Makefile.mk b/src/mainboard/dell/optiplex_3040/Makefile.mk -new file mode 100644 -index 0000000000..0bd72fe691 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/Makefile.mk -@@ -0,0 +1,12 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+bootblock-y += bootblock.c -+bootblock-y += sch5555_ec.c -+ -+romstage-y += romstage.c -+ -+ramstage-y += ramstage.c -+ramstage-y += sch5555_ec.c -+ramstage-y += hda_verb.c -+ -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -diff --git a/src/mainboard/dell/optiplex_3040/acpi/ec.asl b/src/mainboard/dell/optiplex_3040/acpi/ec.asl -new file mode 100644 -index 0000000000..16990d45f4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/acpi/ec.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: CC-PDDC */ -+ -+/* Please update the license if adding licensable material. */ -diff --git a/src/mainboard/dell/optiplex_3040/acpi/superio.asl b/src/mainboard/dell/optiplex_3040/acpi/superio.asl -new file mode 100644 -index 0000000000..16990d45f4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/acpi/superio.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: CC-PDDC */ -+ -+/* Please update the license if adding licensable material. */ -diff --git a/src/mainboard/dell/optiplex_3040/board_info.txt b/src/mainboard/dell/optiplex_3040/board_info.txt -new file mode 100644 -index 0000000000..e43a925ec3 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/board_info.txt -@@ -0,0 +1,7 @@ -+Category: desktop -+Board URL: https://www.dell.com/support/home/en-us/product-support/product/optiplex-3040-micro/overview -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2016 -diff --git a/src/mainboard/dell/optiplex_3040/bootblock.c b/src/mainboard/dell/optiplex_3040/bootblock.c -new file mode 100644 -index 0000000000..10689c42a1 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/bootblock.c -@@ -0,0 +1,107 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include -+#include "include/early_gpio.h" -+#include "sch5555_ec.h" -+ -+struct ec_init_entry { -+ uint16_t addr; -+ uint8_t val; -+}; -+ -+static void bootblock_ec_init(void) -+{ -+ /* -+ * Early EC init -+ */ -+ -+ static const struct ec_init_entry init_table1[] = { -+ {0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10}, -+ {0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10}, -+ {0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12}, -+ {0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12}, -+ {0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10}, -+ {0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11}, -+ }; -+ -+ for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i) -+ sch5555_mbox_write(2, init_table1[i].addr, init_table1[i].val); -+ -+ static const struct ec_init_entry init_table2[] = { -+ {0x0040, 0x00}, {0x00f8, 0x10}, {0x00f9, 0x00}, {0x00f0, 0x30}, -+ {0x00fa, 0x00}, {0x00fb, 0x00}, {0x00ea, 0x00}, {0x00eb, 0x00}, -+ {0x00ef, 0x7c}, {0x0005, 0x0f}, {0x0014, 0x01}, {0x0018, 0x2f}, -+ {0x0019, 0x2f}, {0x001a, 0x2f}, {0x001b, 0x2f}, {0x01d8, 0x01}, -+ {0x0040, 0x11}, -+ }; -+ -+ for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i) -+ sch5555_mbox_write(1, init_table2[i].addr, init_table2[i].val); -+ -+ sch5555_mbox_write(1, 0x000b, 0x01); -+ sch5555_mbox_write(4, 0x001a, 0x04); -+ sch5555_mbox_write(4, 0x0028, 0x18); -+ sch5555_mbox_write(4, 0x001a, 0x00); -+ sch5555_mbox_write(1, 0x000b, 0x03); -+ -+ /* -+ * Early HWM init -+ */ -+ -+ sch5555_mbox_read(1, 0xcb); -+ sch5555_mbox_read(1, 0xb8); -+ -+ static const struct ec_init_entry hwm_init_table[] = { -+ {0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f}, -+ {0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33}, -+ {0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff}, -+ {0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00}, -+ {0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00}, -+ {0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80}, -+ {0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02}, -+ {0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04}, -+ {0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50}, -+ {0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50}, -+ {0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c}, -+ {0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd}, -+ {0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e}, -+ {0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00}, -+ {0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff}, -+ {0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00}, -+ {0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c}, -+ {0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02}, -+ {0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03}, {0x0015, 0x33}, -+ {0x018b, 0x00}, {0x018c, 0x00}, {0x02f8, 0x5e}, {0x02f9, 0x01}, -+ }; -+ -+ for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i) -+ sch5555_mbox_write(1, hwm_init_table[i].addr, hwm_init_table[i].val); -+} -+ -+ -+#define SCH555x_IOBASE 0x2e -+#define GLOBAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL) -+#define SERIAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1) -+ -+void bootblock_mainboard_early_init(void) -+{ -+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -+ -+ // Super I/O early init will map Runtime and EMI registers -+ sch555x_early_init(GLOBAL_DEV); -+ -+ // Changes LED color among a few other things -+ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS); -+ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN); -+ outb(0xf, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); -+ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); -+ -+ // Perform bootblock EC initialization -+ bootblock_ec_init(); -+ -+ // Bootblock EC initialization is required for UART1 to work -+ sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -+} -diff --git a/src/mainboard/dell/optiplex_3040/cmos.default b/src/mainboard/dell/optiplex_3040/cmos.default -new file mode 100644 -index 0000000000..79961f43d8 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/cmos.default -@@ -0,0 +1,5 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -diff --git a/src/mainboard/dell/optiplex_3040/cmos.layout b/src/mainboard/dell/optiplex_3040/cmos.layout -new file mode 100644 -index 0000000000..54a5147b7d ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/cmos.layout -@@ -0,0 +1,54 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+#start-bit length config config-ID name -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+# coreboot config options: southbridge -+409 2 e 7 power_on_after_fail -+ -+# coreboot config options: bootloader -+#Used by ChromeOS: -+416 128 r 0 vbnv -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 415 984 -diff --git a/src/mainboard/dell/optiplex_3040/data.vbt b/src/mainboard/dell/optiplex_3040/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..b503dfc20277775982256a4bdc9108c2ad96f856 -GIT binary patch -literal 4300 -zcmeHJU2GIp6#nLSXYbBzr$d#pV7($jx3pz;m0GlwX?H0tEiwzWuF-@o*+oezEo~tM -zf4YX6kSJy!)Szid6JN~w(!}_rMiOHr!Jldr9_@>X5=}_J_yVk%JJapDM0Z0%l!R}R -zIrp4<=DX+Id*|M>Zm4^Z?&*JOpsRly^^k^%uk_0>aU;6>cJ0|4?;7md+dZ%=)=$5~ -z-I&#{Uj)(|w@Qteno(A5h19#EjB-JKfpSLz9t6Gqt-rd*eI% -zXydjXI}&cDcC0gQN0=IQ)OcsyjxzPZa5LT3V@D}H&^5CAB!m#Vv -zb~=3~N1dVBi0zTwnGQIN<6r&rpgWXJWs< -z0o#Q}ObR?+7TU2^JPXB7vC*&NF~5$4U&lF#;75tzCyC%!iQuwCa7`lc$pp1B!D^Y{ -z0hwTvOt3{Jh{*&yWr8PVf?=6JK8&jcJ_{ckJj;2q)|Jpjyb(rr*0axgcK;=3B>>{d -zfG4X(q2Tl3df}UT6beeG6M=O}1P5?&kEz#_1565n?dgNAACjJ4DELzVqKMv-x4@Xm -zIcFogC=_n@mbwBvAVN?&W<+Ft?P3S`&rfOsra)?yrR-p+&Vm$CcN%iY)qEXAYZ?B_ -zo{)1Ctp1H(@DVKdu5c$-{6AaHl<5_oCDeLY((m97O0lLF=l$6nUA#wEQfu9whMTk8 -z`;2pqD-fZ=LL9xN;}oHQ@5Pdn3ucO=v?x%(i|o!{2BoNR@9KXR8eUBI)5%L+KKNI6mLbw3k5HPj`NGw1P1dJB~DHi;2$H9RT9YAV`9&^U8)Su!GOl95m*iC@uW)bhNXq)EU`bTw+^U4hARj|6S-mE{-<}%c` -zO$)3(g9-_v!_Xn%U$QWpa4G@QGRN341}6rIRb^18q)=51Q#29MExm++%Slc=RWiK4 -zX=*VMT5ly!Eyuv+Sk0$e@_ZFB^lr7xee+SvIDe=H^nN2Fs-0S~Rpxi#b1=hpexfEE+qqb7S-OTPAHP?guHy>J)WO -znyF$xyc?cdNX)D??RQod83eG>SheJ87|bT?Y-%QL)+gM0(8)r8%Cfl0J;@j}mqDUc -zWN|TsIh(FDRWr7nMJ~t~oa(0Xf5AVJtv}S>VkKLa*Fr#z8-oJ5@_!Mwkji33O4q%s -znq{FghJhY?uRVM)GxGTG^O@UI$;9oJ$OV - -literal 0 -HcmV?d00001 - -diff --git a/src/mainboard/dell/optiplex_3040/devicetree.cb b/src/mainboard/dell/optiplex_3040/devicetree.cb -new file mode 100644 -index 0000000000..f1c919fbc7 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/devicetree.cb -@@ -0,0 +1,100 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+chip soc/intel/skylake -+ register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN" -+ -+ # Enable Enhanced Intel SpeedStep -+ register "eist_enable" = "1" -+ -+ device domain 0 on -+ device ref igpu on -+ register "PrimaryDisplay" = "Display_iGFX" -+ end -+ -+ device ref south_xhci on -+ register "usb2_ports" = "{ -+ [0] = USB2_PORT_MID(OC0), // Front panel (blue) -+ [1] = USB2_PORT_MID(OC0), // Front panel (blue) -+ [2] = USB2_PORT_MID(OC3), // Back panel (black) -+ [3] = USB2_PORT_MID(OC2), // Back panel (blue) -+ [4] = USB2_PORT_MID(OC1), // Back panel (blue) -+ [6] = USB2_PORT_MID(OC1), // Back panel (black) -+ [8] = USB2_PORT_MID(OC_SKIP), // WiFi slot -+ }" -+ register "usb3_ports" = "{ -+ [0] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) -+ [1] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) -+ [2] = USB3_PORT_DEFAULT(OC2), // Back panel (blue) -+ [3] = USB3_PORT_DEFAULT(OC1), // Back panel (blue) -+ }" -+ end -+ -+ # ME interface is 'off' to avoid HECI reset delay due to HAP -+ device ref heci1 off end -+ -+ device ref sata on -+ register "SataSalpSupport" = "1" -+ register "SataPortsEnable[0]" = "1" -+ end -+ -+ # M.2 SSD -+ device ref pcie_rp21 on -+ register "PcieRpClkReqSupport[20]" = "1" -+ register "PcieRpClkReqNumber[20]" = "3" -+ register "PcieRpAdvancedErrorReporting[20]" = "1" -+ register "PcieRpLtrEnable[20]" = "true" -+ register "PcieRpClkSrcNumber[20]" = "3" -+ register "PcieRpHotPlug[20]" = "0" -+ end -+ -+ # Realtek LAN -+ device ref pcie_rp5 on -+ register "PcieRpClkReqSupport[4]" = "0" -+ register "PcieRpHotPlug[4]" = "0" -+ end -+ -+ # M.2 WiFi -+ device ref pcie_rp8 on -+ register "PcieRpClkReqSupport[7]" = "0" -+ register "PcieRpHotPlug[7]" = "1" -+ end -+ -+ # UART0 is exposed on test points on the bottom of the board -+ device ref uart0 on -+ register "SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci" -+ end -+ -+ device ref lpc_espi on -+ register "serirq_mode" = "SERIRQ_CONTINUOUS" -+ -+ # I/O decode for EMI/Runtime registers -+ register "gen1_dec" = "0x007c0a01" -+ -+ # SCH5553 -+ chip superio/smsc/sch555x -+ device pnp 2e.0 on # EMI -+ io 0x60 = 0xa00 -+ end -+ device pnp 2e.1 off end # 8042 -+ device pnp 2e.7 on # UART1 -+ io 0x60 = 0x3f8 -+ irq 0x0f = 2 -+ irq 0x70 = 4 -+ end -+ device pnp 2e.8 off end # UART2 -+ device pnp 2e.c on # LPC interface -+ io 0x60 = 0x2e -+ end -+ device pnp 2e.a on # Runtime registers -+ io 0x60 = 0xa40 -+ end -+ device pnp 2e.b off end # Floppy Controller -+ device pnp 2e.11 off end # Parallel Port -+ end -+ end -+ -+ device ref hda on end -+ -+ device ref smbus on end -+ end -+end -diff --git a/src/mainboard/dell/optiplex_3040/dsdt.asl b/src/mainboard/dell/optiplex_3040/dsdt.asl -new file mode 100644 -index 0000000000..9762f6ff74 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/dsdt.asl -@@ -0,0 +1,27 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20110725 -+) -+{ -+ #include -+ #include -+ #include -+ -+ Scope (\_SB) -+ { -+ Device (PCI0) -+ { -+ #include -+ #include -+ } -+ } -+ -+ #include -+} -diff --git a/src/mainboard/dell/optiplex_3040/gma-mainboard.ads b/src/mainboard/dell/optiplex_3040/gma-mainboard.ads -new file mode 100644 -index 0000000000..cb4c22f285 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/gma-mainboard.ads -@@ -0,0 +1,19 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ (HDMI1, -- External HDMI -+ DP2, -- External DP (native) -+ HDMI2, -- External DP (DP++) -+ DP3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) -+ HDMI3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/optiplex_3040/hda_verb.c b/src/mainboard/dell/optiplex_3040/hda_verb.c -new file mode 100644 -index 0000000000..5a1db019c7 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/hda_verb.c -@@ -0,0 +1,90 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ /* coreboot specific header, codec 0 */ -+ 0x10ec0255, /* Realtek ALC3234 */ -+ 0x102806bb, /* Subsystem ID */ -+ 11, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ -+ AZALIA_SUBVENDOR(0, 0x102806bb), -+ -+ AZALIA_PIN_CFG(0, 0x12, 0x40000000), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( -+ AZALIA_INTEGRATED, -+ AZALIA_INTERNAL, -+ AZALIA_SPEAKER, -+ AZALIA_OTHER_ANALOG, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_NO_JACK_PRESENCE_DETECT, -+ 5, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, -+ AZALIA_LINE_OUT, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 2, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x1d, 0x4054c029), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, -+ AZALIA_HP_OUT, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 5, 15 -+ )), -+ -+ /* coreboot specific header, codec 2 */ -+ 0x80862809, /* Intel Skylake HDMI */ -+ 0x80860101, /* Subsystem ID */ -+ 4, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ -+ AZALIA_SUBVENDOR(2, 0x80860101), -+ -+ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+}; -+ -+const u32 pc_beep_verbs[] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/optiplex_3040/include/early_gpio.h b/src/mainboard/dell/optiplex_3040/include/early_gpio.h -new file mode 100644 -index 0000000000..fdf1a64c7c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/include/early_gpio.h -@@ -0,0 +1,11 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __OPTIPLEX_3040_EARLY_GPIO_H__ -+#define __OPTIPLEX_3040_EARLY_GPIO_H__ -+ -+static const struct pad_config early_gpio_table[] = { -+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ -+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ -+}; -+ -+#endif -diff --git a/src/mainboard/dell/optiplex_3040/include/gpio.h b/src/mainboard/dell/optiplex_3040/include/gpio.h -new file mode 100644 -index 0000000000..29da4b11d4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/include/gpio.h -@@ -0,0 +1,241 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __OPTIPLEX_3040_GPIO_H__ -+#define __OPTIPLEX_3040_GPIO_H__ -+ -+static const struct pad_config gpio_table[] = { -+ -+ /* ------- GPIO Community 0 ------- */ -+ -+ /* ------- GPIO Group GPP_A ------- */ -+ PAD_CFG_NF(GPP_A0, UP_20K, PLTRST, NF1), /* RCIN# */ -+ PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* LAD0 */ -+ PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* LAD1 */ -+ PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* LAD2 */ -+ PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* LAD3 */ -+ PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */ -+ PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKRUN# */ -+ PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), /* CLKOUT_LPC0 */ -+ PAD_CFG_NF(GPP_A10, NONE, PLTRST, NF1), /* CLKOUT_LPC1 */ -+ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), /* PME# */ -+ PAD_CFG_GPO(GPP_A12, 0, PLTRST), /* GPIO */ -+ PAD_CFG_NF(GPP_A13, NONE, PLTRST, NF1), /* SUSWARN#/SUSPWRDNACK */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_A15, UP_20K, PLTRST, NF1), /* SUS_ACK# */ -+ PAD_CFG_GPO(GPP_A16, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_B ------- */ -+ PAD_CFG_GPO(GPP_B0, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B1, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B2, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_B3, 1, RSMRST), /* GPIO (ME_CNTL, B3 -> LOW => HDA_SDO -> HIGH) */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_B5, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B6, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B7, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_B9, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1), /* SLP_S0# */ -+ PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), /* PLTRST# */ -+ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* SPKR */ -+ PAD_CFG_GPO(GPP_B15, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B16, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* GSPIO_MOSI */ -+ PAD_CFG_GPO(GPP_B19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B20, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* GPIO */ -+ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), /* GSPI1_MOSI */ -+ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), /* PCHHOT# */ -+ -+ /* ------- GPIO Community 1 ------- */ -+ -+ /* ------- GPIO Group GPP_C ------- */ -+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ -+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_C2, DN_20K, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_C3, NONE, PLTRST, NF1), /* SML0CLK */ -+ PAD_CFG_NF(GPP_C4, NONE, PLTRST, NF1), /* SML0DATA */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK */ -+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1DATA */ -+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ -+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ -+ PAD_CFG_GPO(GPP_C10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C11, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C12, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C13, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C14, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C15, 0, PLTRST), /* GPIO */ -+ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), /* I2C0_SDA */ -+ PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), /* I2C0_SCL */ -+ PAD_CFG_GPO(GPP_C18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C21, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_D ------- */ -+ PAD_CFG_GPO(GPP_D0, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D1, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D2, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D3, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_D6, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_D7, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D8, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D9, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D11, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D13, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D14, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D15, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D16, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D21, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_E ------- */ -+ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATAXPCIE0 */ -+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SATAXPCIE1 */ -+ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* SATAXPCIE2 */ -+ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* SATA_LED# */ -+ PAD_CFG_NF(GPP_E9, UP_20K, PLTRST, NF1), /* USB_OC0# */ -+ PAD_CFG_NF(GPP_E10, UP_20K, PLTRST, NF1), /* USB_OC1# */ -+ PAD_CFG_NF(GPP_E11, UP_20K, PLTRST, NF1), /* USB_OC2# */ -+ PAD_CFG_NF(GPP_E12, UP_20K, PLTRST, NF1), /* USB_OC3# */ -+ -+ /* ------- GPIO Group GPP_F ------- */ -+ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* SATAXPCIE3 */ -+ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* SATAXPCIE4 */ -+ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* SATAXPCIE5 */ -+ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* SATAXPCIE6 */ -+ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* SATAXPCIE7 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_F6, NONE, RSMRST, NF1), /* SATA_DEVSLP4 */ -+ PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_F9, 0, RSMRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_F13, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), /* USB_OC4# */ -+ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), /* USB_OC5# */ -+ PAD_CFG_NF(GPP_F17, UP_20K, PLTRST, NF1), /* USB_OC6# */ -+ PAD_CFG_TERM_GPO(GPP_F18, 0, UP_20K, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_F19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_F20, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_F21, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_F22, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_F23, 1, RSMRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_G ------- */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_G9, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_G12, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_G14, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G15, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G16, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G17, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_G19, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G20, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_G21, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G22, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_H ------- */ -+ PAD_CFG_GPO(GPP_H0, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H2, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H3, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H4, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H5, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H6, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_H7, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H8, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H9, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H11, 0, PLTRST), /* GPIO */ -+ PAD_CFG_TERM_GPO(GPP_H12, 1, DN_20K, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H15, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H16, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H21, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Community 2 ------- */ -+ -+ /* -------- GPIO Group GPD -------- */ -+ PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* BATLOW# */ -+ PAD_CFG_GPO(GPD1, 0, PWROK), /* GPIO */ -+ PAD_CFG_NF(GPD2, NONE, RSMRST, NF1), /* LAN_WAKE# */ -+ PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), /* PWRBTN# */ -+ PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */ -+ PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */ -+ PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* SLP_A# */ -+ PAD_CFG_GPO(GPD7, 1, RSMRST), /* GPIO */ -+ PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* SUSCLK */ -+ PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */ -+ PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */ -+ PAD_CFG_GPO(GPD11, 1, RSMRST), /* GPIO */ -+ -+ /* ------- GPIO Community 3 ------- */ -+ -+ /* ------- GPIO Group GPP_I ------- */ -+ PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */ -+ PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPC_HPD1 */ -+ PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DDPD_HPD2 */ -+ PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* DDPE_HPD3 */ -+ PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), /* EDP_HPD */ -+ PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* DDPB_CTRLCLK */ -+ PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), /* DDPB_CTRLDATA */ -+ PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* DDPC_CTRLCLK */ -+ PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), /* DDPC_CTRLDATA */ -+ PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */ -+ PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), /* DDPD_CTRLDATA */ -+}; -+ -+#endif -diff --git a/src/mainboard/dell/optiplex_3040/ramstage.c b/src/mainboard/dell/optiplex_3040/ramstage.c -new file mode 100644 -index 0000000000..c391e4ac6d ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/ramstage.c -@@ -0,0 +1,512 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "include/gpio.h" -+#include "sch5555_ec.h" -+ -+void mainboard_silicon_init_params(FSP_SIL_UPD *params) -+{ -+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -+} -+ -+#define FORM_FACTOR_MICRO 0 -+#define FORM_FACTOR_SFF 1 -+// Probably DT and MT -+#define FORM_FACTOR_UNK2 2 -+#define FORM_FACTOR_UNK3 3 -+ -+#define HWM_TAB_ADD_TEMP_TARGET 1 -+#define HWM_TAB_PKG_POWER_ANY 0xffff -+ -+struct hwm_tab_entry { -+ uint16_t addr; -+ uint8_t val; -+ uint8_t flags; -+ uint16_t pkg_power; -+}; -+ -+static const struct hwm_tab_entry HWM_TAB_MICRO_BASE[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x01b, 0x0f, 0, 0xffff }, -+ { 0x057, 0xff, 0, 0xffff }, -+ { 0x059, 0xff, 0, 0xffff }, -+ { 0x05b, 0xff, 0, 0xffff }, -+ { 0x05d, 0xff, 0, 0xffff }, -+ { 0x05f, 0xff, 0, 0xffff }, -+ { 0x061, 0xff, 0, 0xffff }, -+ { 0x06e, 0x00, 0, 0xffff }, -+ { 0x06f, 0x03, 0, 0xffff }, -+ { 0x070, 0x03, 0, 0xffff }, -+ { 0x071, 0x02, 0, 0xffff }, -+ { 0x072, 0x02, 0, 0xffff }, -+ { 0x073, 0x01, 0, 0xffff }, -+ { 0x074, 0x06, 0, 0xffff }, -+ { 0x075, 0x07, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x80, 0, 0xffff }, -+ { 0x082, 0x80, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0xf1, 0, 0xffff }, -+ { 0x086, 0x88, 0, 0xffff }, -+ { 0x087, 0x61, 0, 0xffff }, -+ { 0x088, 0x08, 0, 0xffff }, -+ { 0x089, 0x00, 0, 0xffff }, -+ { 0x08a, 0x73, 0, 0xffff }, -+ { 0x08b, 0x73, 0, 0xffff }, -+ { 0x08c, 0x73, 0, 0xffff }, -+ { 0x090, 0x6d, 0, 0xffff }, -+ { 0x091, 0x7e, 0, 0xffff }, -+ { 0x092, 0x66, 0, 0xffff }, -+ { 0x093, 0xa4, 0, 0xffff }, -+ { 0x094, 0x7c, 0, 0xffff }, -+ { 0x095, 0xa4, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x099, 0xa4, 0, 0xffff }, -+ { 0x09a, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x2e, 0, 0xffff }, -+ { 0x0a1, 0x00, 0, 0xffff }, -+ { 0x0a2, 0x00, 0, 0xffff }, -+ { 0x0ae, 0xa4, 0, 0xffff }, -+ { 0x0af, 0xa4, 0, 0xffff }, -+ { 0x0b0, 0xa4, 0, 0xffff }, -+ { 0x0b1, 0xa4, 0, 0xffff }, -+ { 0x0b2, 0xa4, 0, 0xffff }, -+ { 0x0b3, 0xa4, 0, 0xffff }, -+ { 0x0b6, 0x00, 0, 0xffff }, -+ { 0x0b7, 0x00, 0, 0xffff }, -+ { 0x0d1, 0xff, 0, 0xffff }, -+ { 0x0d6, 0xff, 0, 0xffff }, -+ { 0x0db, 0xff, 0, 0xffff }, -+ { 0x0ea, 0x5c, 0, 0xffff }, -+ { 0x0eb, 0x5c, 0, 0xffff }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x184, 0xff, 0, 0xffff }, -+ { 0x186, 0xff, 0, 0xffff }, -+ { 0x1a1, 0xce, 0, 0xffff }, -+ { 0x1a2, 0x0c, 0, 0xffff }, -+ { 0x1a3, 0x0c, 0, 0xffff }, -+ { 0x1a6, 0x00, 0, 0xffff }, -+ { 0x1a7, 0x00, 0, 0xffff }, -+ { 0x1a8, 0xa4, 0, 0xffff }, -+ { 0x1a9, 0xa4, 0, 0xffff }, -+ { 0x1ab, 0x2d, 0, 0xffff }, -+ { 0x1ac, 0x2d, 0, 0xffff }, -+ { 0x1b1, 0x00, 0, 0xffff }, -+ { 0x1bb, 0x00, 0, 0xffff }, -+ { 0x1bc, 0x00, 0, 0xffff }, -+ { 0x1bd, 0x00, 0, 0xffff }, -+ { 0x1be, 0x01, 0, 0xffff }, -+ { 0x1bf, 0x01, 0, 0xffff }, -+ { 0x1c0, 0x01, 0, 0xffff }, -+ { 0x1c1, 0x01, 0, 0xffff }, -+ { 0x1c2, 0x01, 0, 0xffff }, -+ { 0x280, 0x00, 0, 0xffff }, -+ { 0x281, 0x00, 0, 0xffff }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x040, 0x01, 0, 0xffff }, -+}; -+ -+static const struct hwm_tab_entry HWM_TAB_MICRO_TEMP80[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x01b, 0x0f, 0, 0xffff }, -+ { 0x057, 0xff, 0, 0xffff }, -+ { 0x059, 0xff, 0, 0xffff }, -+ { 0x05b, 0xff, 0, 0xffff }, -+ { 0x05d, 0xff, 0, 0xffff }, -+ { 0x05f, 0xff, 0, 0xffff }, -+ { 0x061, 0xff, 0, 0xffff }, -+ { 0x06e, 0x00, 0, 0xffff }, -+ { 0x06f, 0x03, 0, 0xffff }, -+ { 0x070, 0x03, 0, 0xffff }, -+ { 0x071, 0x02, 0, 0xffff }, -+ { 0x072, 0x02, 0, 0xffff }, -+ { 0x073, 0x01, 0, 0xffff }, -+ { 0x074, 0x06, 0, 0xffff }, -+ { 0x075, 0x07, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x80, 0, 0xffff }, -+ { 0x082, 0x80, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0xf6, 0, 0xffff }, -+ { 0x086, 0x88, 0, 0xffff }, -+ { 0x087, 0x61, 0, 0xffff }, -+ { 0x088, 0x08, 0, 0xffff }, -+ { 0x089, 0x00, 0, 0xffff }, -+ { 0x08a, 0x73, 0, 0xffff }, -+ { 0x08b, 0x73, 0, 0xffff }, -+ { 0x08c, 0x73, 0, 0xffff }, -+ { 0x090, 0x6d, 0, 0xffff }, -+ { 0x091, 0x86, 0, 0xffff }, -+ { 0x092, 0x66, 0, 0xffff }, -+ { 0x093, 0xa4, 0, 0xffff }, -+ { 0x094, 0x7c, 0, 0xffff }, -+ { 0x095, 0xa4, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x099, 0xa4, 0, 0xffff }, -+ { 0x09a, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x2e, 0, 0xffff }, -+ { 0x0a1, 0x00, 0, 0xffff }, -+ { 0x0a2, 0x00, 0, 0xffff }, -+ { 0x0ae, 0xa4, 0, 0xffff }, -+ { 0x0af, 0xa4, 0, 0xffff }, -+ { 0x0b0, 0xa4, 0, 0xffff }, -+ { 0x0b1, 0xa4, 0, 0xffff }, -+ { 0x0b2, 0xa4, 0, 0xffff }, -+ { 0x0b3, 0xa4, 0, 0xffff }, -+ { 0x0b6, 0x00, 0, 0xffff }, -+ { 0x0b7, 0x00, 0, 0xffff }, -+ { 0x0d1, 0xff, 0, 0xffff }, -+ { 0x0d6, 0xff, 0, 0xffff }, -+ { 0x0db, 0xff, 0, 0xffff }, -+ { 0x0ea, 0x50, 0, 0xffff }, -+ { 0x0eb, 0x50, 0, 0xffff }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x184, 0xff, 0, 0xffff }, -+ { 0x186, 0xff, 0, 0xffff }, -+ { 0x1a1, 0xce, 0, 0xffff }, -+ { 0x1a2, 0x0c, 0, 0xffff }, -+ { 0x1a3, 0x0c, 0, 0xffff }, -+ { 0x1a6, 0x00, 0, 0xffff }, -+ { 0x1a7, 0x00, 0, 0xffff }, -+ { 0x1a8, 0xa4, 0, 0xffff }, -+ { 0x1a9, 0xa4, 0, 0xffff }, -+ { 0x1ab, 0x2d, 0, 0xffff }, -+ { 0x1ac, 0x2d, 0, 0xffff }, -+ { 0x1b1, 0x00, 0, 0xffff }, -+ { 0x1bb, 0x00, 0, 0xffff }, -+ { 0x1bc, 0x00, 0, 0xffff }, -+ { 0x1bd, 0x00, 0, 0xffff }, -+ { 0x1be, 0x01, 0, 0xffff }, -+ { 0x1bf, 0x01, 0, 0xffff }, -+ { 0x1c0, 0x01, 0, 0xffff }, -+ { 0x1c1, 0x01, 0, 0xffff }, -+ { 0x1c2, 0x01, 0, 0xffff }, -+ { 0x280, 0x00, 0, 0xffff }, -+ { 0x281, 0x00, 0, 0xffff }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x040, 0x01, 0, 0xffff }, -+}; -+ -+static const struct hwm_tab_entry HWM_TAB_MICRO_EARLY_STEPPING[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x01b, 0x0f, 0, 0xffff }, -+ { 0x057, 0xff, 0, 0xffff }, -+ { 0x059, 0xff, 0, 0xffff }, -+ { 0x05b, 0xff, 0, 0xffff }, -+ { 0x05d, 0xff, 0, 0xffff }, -+ { 0x05f, 0xff, 0, 0xffff }, -+ { 0x061, 0xff, 0, 0xffff }, -+ { 0x06e, 0x01, 0, 0xffff }, -+ { 0x06f, 0x03, 0, 0xffff }, -+ { 0x070, 0x03, 0, 0xffff }, -+ { 0x071, 0x02, 0, 0xffff }, -+ { 0x072, 0x02, 0, 0xffff }, -+ { 0x073, 0x01, 0, 0xffff }, -+ { 0x074, 0x06, 0, 0xffff }, -+ { 0x075, 0x07, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x80, 0, 0xffff }, -+ { 0x082, 0x80, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0xfd, 0, 0xffff }, -+ { 0x086, 0x60, 0, 0xffff }, -+ { 0x087, 0x50, 0, 0xffff }, -+ { 0x088, 0x08, 0, 0xffff }, -+ { 0x089, 0x00, 0, 0xffff }, -+ { 0x08a, 0x73, 0, 0xffff }, -+ { 0x08b, 0x73, 0, 0xffff }, -+ { 0x08c, 0x73, 0, 0xffff }, -+ { 0x090, 0x6d, 0, 0xffff }, -+ { 0x091, 0x7a, 0, 0xffff }, -+ { 0x092, 0x6b, 0, 0xffff }, -+ { 0x093, 0xa4, 0, 0xffff }, -+ { 0x094, 0x78, 0, 0xffff }, -+ { 0x095, 0xa4, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x099, 0xa4, 0, 0xffff }, -+ { 0x09a, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x2e, 0, 0xffff }, -+ { 0x0a1, 0x00, 0, 0xffff }, -+ { 0x0a2, 0x00, 0, 0xffff }, -+ { 0x0ae, 0xa4, 0, 0xffff }, -+ { 0x0af, 0xa4, 0, 0xffff }, -+ { 0x0b0, 0xa4, 0, 0xffff }, -+ { 0x0b1, 0xa4, 0, 0xffff }, -+ { 0x0b2, 0xa4, 0, 0xffff }, -+ { 0x0b3, 0xa4, 0, 0xffff }, -+ { 0x0b6, 0x00, 0, 0xffff }, -+ { 0x0b7, 0x00, 0, 0xffff }, -+ { 0x0d1, 0xff, 0, 0xffff }, -+ { 0x0d6, 0xff, 0, 0xffff }, -+ { 0x0db, 0xff, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0xffff }, -+ { 0x0eb, 0x64, 0, 0xffff }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x184, 0xff, 0, 0xffff }, -+ { 0x186, 0xff, 0, 0xffff }, -+ { 0x1a1, 0xce, 0, 0xffff }, -+ { 0x1a2, 0x0c, 0, 0xffff }, -+ { 0x1a3, 0x0c, 0, 0xffff }, -+ { 0x1a6, 0x00, 0, 0xffff }, -+ { 0x1a7, 0x00, 0, 0xffff }, -+ { 0x1a8, 0xa4, 0, 0xffff }, -+ { 0x1a9, 0xa4, 0, 0xffff }, -+ { 0x1ab, 0x2d, 0, 0xffff }, -+ { 0x1ac, 0x2d, 0, 0xffff }, -+ { 0x1b1, 0x00, 0, 0xffff }, -+ { 0x1bb, 0x00, 0, 0xffff }, -+ { 0x1bc, 0x00, 0, 0xffff }, -+ { 0x1bd, 0x00, 0, 0xffff }, -+ { 0x1be, 0x01, 0, 0xffff }, -+ { 0x1bf, 0x01, 0, 0xffff }, -+ { 0x1c0, 0x01, 0, 0xffff }, -+ { 0x1c1, 0x01, 0, 0xffff }, -+ { 0x1c2, 0x01, 0, 0xffff }, -+ { 0x280, 0x00, 0, 0xffff }, -+ { 0x281, 0x00, 0, 0xffff }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x040, 0x01, 0, 0xffff }, -+}; -+ -+static const struct hwm_tab_entry HWM_TAB_SFF[] = { -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x040, 0x01, 0, 0xffff }, -+ { 0x072, 0x03, 0, 0xffff }, -+ { 0x075, 0x06, 0, 0xffff }, -+ { 0x07c, 0x00, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x00, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0x59, 0, 0xffff }, -+ { 0x086, 0x6a, 0, 0xffff }, -+ { 0x087, 0xc0, 0, 0xffff }, -+ { 0x08a, 0x33, 0, 0xffff }, -+ { 0x090, 0x77, 0, 0xffff }, -+ { 0x091, 0x66, 0, 0xffff }, -+ { 0x092, 0x94, 0, 0xffff }, -+ { 0x093, 0x90, 0, 0xffff }, -+ { 0x094, 0x68, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x099, 0xa4, 0, 0xffff }, -+ { 0x09a, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x3e, 0, 0xffff }, -+ { 0x0ae, 0x86, 0, 0xffff }, -+ { 0x0af, 0x86, 0, 0xffff }, -+ { 0x0b0, 0xa4, 0, 0xffff }, -+ { 0x0b1, 0xa4, 0, 0xffff }, -+ { 0x0b2, 0x90, 0, 0xffff }, -+ { 0x0b6, 0x48, 0, 0xffff }, -+ { 0x0b7, 0x48, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x1b1, 0x48, 0, 0xffff }, -+ { 0x1b8, 0x00, 0, 0xffff }, -+ { 0x1be, 0x95, 0, 0xffff }, -+ { 0x1c1, 0x90, 0, 0xffff }, -+ { 0x1c6, 0x00, 0, 0xffff }, -+ { 0x1c9, 0x00, 0, 0xffff }, -+ { 0x280, 0x68, 0, 0xffff }, -+ { 0x281, 0x10, 0, 0xffff }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff} -+}; -+ -+static const struct hwm_tab_entry HWM_TAB_MT[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x00, 0, 0xffff }, -+ { 0x082, 0x80, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0xb9, 0, 0x0010 }, -+ { 0x086, 0xac, 0, 0x0010 }, -+ { 0x087, 0x87, 0, 0x0010 }, -+ { 0x08a, 0x51, 0, 0x0010 }, -+ { 0x08b, 0x39, 0, 0x0010 }, -+ { 0x090, 0x78, 0, 0xffff }, -+ { 0x091, 0x6a, 0, 0xffff }, -+ { 0x092, 0x8f, 0, 0xffff }, -+ { 0x094, 0x68, 0, 0xffff }, -+ { 0x095, 0x5b, 0, 0xffff }, -+ { 0x096, 0x92, 0, 0xffff }, -+ { 0x097, 0x86, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x09a, 0x8b, 0, 0xffff }, -+ { 0x0a0, 0x0a, 0, 0xffff }, -+ { 0x0a1, 0x26, 0, 0xffff }, -+ { 0x0a2, 0xd1, 0, 0xffff }, -+ { 0x0ae, 0x7c, 0, 0xffff }, -+ { 0x0af, 0x7c, 0, 0xffff }, -+ { 0x0b0, 0x9a, 0, 0xffff }, -+ { 0x0b3, 0x7c, 0, 0xffff }, -+ { 0x0b6, 0x08, 0, 0xffff }, -+ { 0x0b7, 0x00, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0xffff }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x0fd, 0x01, 0, 0xffff }, -+ { 0x1a1, 0x99, 0, 0xffff }, -+ { 0x1a2, 0x00, 0, 0xffff }, -+ { 0x1a4, 0x00, 0, 0xffff }, -+ { 0x1b1, 0x00, 0, 0xffff }, -+ { 0x1be, 0x90, 0, 0xffff }, -+ { 0x280, 0xc4, 0, 0xffff }, -+ { 0x281, 0x09, 0, 0xffff }, -+ { 0x282, 0x0a, 0, 0xffff }, -+ { 0x283, 0x14, 0, 0xffff }, -+ { 0x284, 0x01, 0, 0xffff }, -+ { 0x285, 0x01, 0, 0xffff }, -+ { 0x288, 0x94, 0, 0xffff }, -+ { 0x289, 0x11, 0, 0xffff }, -+ { 0x28a, 0x0a, 0, 0xffff }, -+ { 0x28b, 0x14, 0, 0xffff }, -+ { 0x28c, 0x01, 0, 0xffff }, -+ { 0x28d, 0x01, 0, 0xffff }, -+ { 0x294, 0x24, 0, 0xffff }, -+}; -+ -+static uint8_t get_temp_target(void) -+{ -+ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; -+ if (!val) -+ val = 20; -+ return 0x95 - val; -+} -+ -+static uint16_t get_pkg_power(void) -+{ -+ const unsigned int pkg_power = rdmsr(0x614).lo & 0x7fff; -+ const unsigned int power_unit = 1 << (rdmsr(0x606).lo & 0xf); -+ if (pkg_power / power_unit > 65) -+ return 32; -+ else -+ return 16; -+} -+ -+static uint8_t get_core_cnt(void) -+{ -+ // Intel describes this CPUID field as: -+ // > Maximum number of addressable IDs for processor cores in the physical package -+ if (cpuid(0).eax >= 4) -+ return cpuid_ext(4, 0).eax >> 26; -+ return 0; -+} -+ -+static void apply_hwm_tab(const struct hwm_tab_entry *arr, size_t size) -+{ -+ uint8_t temp_target = get_temp_target(); -+ uint16_t pkg_power = get_pkg_power(); -+ -+ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target); -+ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power); -+ -+ for (size_t i = 0; i < size; ++i) { -+ // Skip entry if it doesn't apply for this package power -+ if (arr[i].pkg_power != pkg_power && -+ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY) -+ continue; -+ -+ uint8_t val = arr[i].val; -+ -+ // Add temp target to value if requested (current tables never do) -+ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET) -+ val += temp_target; -+ -+ // Perform write -+ sch5555_mbox_write(1, arr[i].addr, val); -+ } -+} -+ -+static void sch5555_ec_hwm_init(void *arg) -+{ -+ uint8_t form_fac_id, saved_2fc, core_cnt; -+ -+ printk(BIOS_DEBUG, "OptiPlex 3040 late HWM init\n"); -+ -+ form_fac_id = gpio_get(GPP_G2) | gpio_get(GPP_G3) << 1; -+ printk(BIOS_DEBUG, "Form Factor ID = %#x\n", form_fac_id); -+ -+ saved_2fc = sch5555_mbox_read(1, 0x2fc); -+ sch5555_mbox_write(1, 0x2fc, 0xa0); -+ sch5555_mbox_write(1, 0x2fd, 0x32); -+ -+ switch (form_fac_id) { -+ case FORM_FACTOR_MICRO: -+ // CPU stepping <= 3 -+ if ((cpuid(1).eax & 0xf) <= 3) -+ apply_hwm_tab(HWM_TAB_MICRO_EARLY_STEPPING, ARRAY_SIZE(HWM_TAB_MICRO_EARLY_STEPPING)); -+ // Tjunction == 80 -+ else if ((rdmsr(0x1a2).lo >> 16 & 0xff) == 80) -+ apply_hwm_tab(HWM_TAB_MICRO_TEMP80, ARRAY_SIZE(HWM_TAB_MICRO_TEMP80)); -+ else -+ apply_hwm_tab(HWM_TAB_MICRO_BASE, ARRAY_SIZE(HWM_TAB_MICRO_BASE)); -+ break; -+ case FORM_FACTOR_SFF: -+ apply_hwm_tab(HWM_TAB_SFF, ARRAY_SIZE(HWM_TAB_SFF)); -+ break; -+ default: -+ apply_hwm_tab(HWM_TAB_MT, ARRAY_SIZE(HWM_TAB_MT)); -+ break; -+ } -+ -+ core_cnt = get_core_cnt(); -+ printk(BIOS_DEBUG, "CPU Core Count = %#x\n", core_cnt); -+ if (core_cnt > 2) { -+ sch5555_mbox_write(1, 0x9e, 0x30); -+ sch5555_mbox_write(1, 0xeb, sch5555_mbox_read(1, 0xea)); -+ } -+ -+ sch5555_mbox_write(1, 0x2fc, saved_2fc); -+ sch5555_mbox_read(1, 0xb8); -+} -+ -+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); -diff --git a/src/mainboard/dell/optiplex_3040/romstage.c b/src/mainboard/dell/optiplex_3040/romstage.c -new file mode 100644 -index 0000000000..c2ce2369a4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/romstage.c -@@ -0,0 +1,22 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+ -+void mainboard_memory_init_params(FSPM_UPD *mupd) -+{ -+ /* -+ * OptiPlex 3040 Micro uses DDR3L SO-DIMMs. -+ * SODIMM slots are at I2C addresses 0x50 (slot 0) and 0x52 (slot 1). -+ * SPD size for DDR3L is 256 bytes. -+ */ -+ struct spd_block blk = { .addr_map = { 0x50, 0x52, } }; -+ get_spd_smbus(&blk); -+ dump_spd_info(&blk); -+ -+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; -+ mem_cfg->DqPinsInterleaved = true; -+ mem_cfg->MemorySpdDataLen = blk.len; -+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; -+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; -+} -diff --git a/src/mainboard/dell/optiplex_3040/sch5555_ec.c b/src/mainboard/dell/optiplex_3040/sch5555_ec.c -new file mode 100644 -index 0000000000..1df5026531 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/sch5555_ec.c -@@ -0,0 +1,54 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include "sch5555_ec.h" -+ -+uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2) -+{ -+ // clear ec-to-host mailbox -+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); -+ outb(tmp, SCH555x_EMI_IOBASE + 1); -+ -+ // send address -+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); -+ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); -+ -+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); -+ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); -+ -+ // send message to ec -+ outb(1, SCH555x_EMI_IOBASE); -+ -+ // wait for ack -+ for (size_t retry = 0; retry < 0xfff; ++retry) -+ if (inb(SCH555x_EMI_IOBASE + 1) & 1) -+ break; -+ -+ // read result -+ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); -+ return inb(SCH555x_EMI_IOBASE + 4); -+} -+ -+void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val) -+{ -+ // clear ec-to-host mailbox -+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); -+ outb(tmp, SCH555x_EMI_IOBASE + 1); -+ -+ // send address and value -+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); -+ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); -+ -+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); -+ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); -+ -+ // send message to ec -+ outb(1, SCH555x_EMI_IOBASE); -+ -+ // wait for ack -+ for (size_t retry = 0; retry < 0xfff; ++retry) -+ if (inb(SCH555x_EMI_IOBASE + 1) & 1) -+ break; -+} -diff --git a/src/mainboard/dell/optiplex_3040/sch5555_ec.h b/src/mainboard/dell/optiplex_3040/sch5555_ec.h -new file mode 100644 -index 0000000000..9d262d5787 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/sch5555_ec.h -@@ -0,0 +1,10 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __SCH5555_EC_H__ -+#define __SCH5555_EC_H__ -+ -+uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2); -+ -+void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val); -+ -+#endif --- -2.53.0 - diff --git a/config/coreboot/default/patches/0050-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch b/config/coreboot/default/patches/0050-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch new file mode 100644 index 00000000..b55797ca --- /dev/null +++ b/config/coreboot/default/patches/0050-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch @@ -0,0 +1,129 @@ +From 15cfc08cea1e4a091a2dd729bf88fa2a10ef0a3d Mon Sep 17 00:00:00 2001 +From: Kat Inskip +Date: Sat, 21 Feb 2026 19:48:17 +0000 +Subject: [PATCH 50/51] mb/lenovo/x270: Provide correct vbt and hda_verb + +--- + .../sklkbl_thinkpad/variants/x270/data.vbt | Bin 6144 -> 4449 bytes + .../sklkbl_thinkpad/variants/x270/hda_verb.c | 29 +++++++++--------- + 2 files changed, 15 insertions(+), 14 deletions(-) + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt +index bfb312850e0ab4ea834c535df35edb45834ed248..c6561a9c57e4e600bc0adb5f6679f2f5d6b6c640 100644 +GIT binary patch +delta 1043 +zcmcgq-Afcv6hC)nXFtw-?CgzfEwH0LgQ9&f-Qz1ka^prZC-JMFP=YHJZ{oQls$2s?7a?V`MjktC+ +zmIBAkE35L3T{R08;KY{a0fvRBG?I>!>>E2haF{QO$c=4v8Y8%=?LrDlLIKmZ^Gf5CQN1XgElP&$RejtyZ5 +z##fpUKrO{7px=4oVy};I82ZMAiwFT|EMc$(iBg6qn;Wt%1))HsoGWjGZ6rwfW9y;f +z+P1?LzVFv3072#UoFOjAux+UOm(9&6an}i+$f~@7#c_7}8xbIi0I-AuW05M@qt?NB +zRe{Uu7N`$QfgK@eiP+G~9Av)K5N4SlnO~Vdm|74a%B*D8G8>rf%r0h{d4PGCIT}nO +z1kb>tr{s#a!pI3%9?|1Fclp|1QdQ0P@qX6gB^>l)&nqO<`-*_VTP>kxOWk0S0g$)_YB$m-%5#X9 +zknW*;i1-ZYGfEFJqEnMDyL3$JbV`>Ob-boiL6=W;oYCpKE<*;!3~D!IpMe7goi*fD +z18*Djz>w1hzAjgD~h(eazMzGB3(Uim8EziUhBPY#yb{{-gtq*(v} + +delta 808 +zcmX|e2Y=7&(6 +z1vl8CW+z-x@(%LgW907_fIdYjust^(YddwW|77|83Odly8SQ9J9BnF&$EbTJc{NqB +z8Y0(=dhuwr>(#T5HPpr%yse4n(Ztt0#S21;HymyT1(vJ9HuOD)Uv5yoA$IBhCY^G0 +z(d~;~pIj21x?ibNp&{7!_@YPn0@PYX)d4me@cII*iNKvl04c{p;T8;tmbA>dO!%ck**r) +zYT&6wLA@%NymTDqLC|>RKbP37?tsmjG8Gpd7)9xHCH87_(8_ZjHv|kZZECQLbP;tP`&Ou1y@vPq>VYZ132^`jg_97TGF@)_bR(jv;=h#`x%SaO?%yDb{9 +zsC+JqU`~#!PkzxP< + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c +index 089e605eaf..60289355f8 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c +@@ -3,10 +3,10 @@ + #include + + const u32 cim_verb_data[] = { +- 0x10ec0257, // Vendor/Device ID: Realtek ALC257 +- 0x17aa2256, // Subsystem ID +- 18, +- AZALIA_SUBVENDOR(0, 0x17aa2256), ++ 0x10ec0298, // Vendor/Device ID: Realtek ALC298 ++ 0x17aa5062, // Subsystem ID ++ 19, ++ AZALIA_SUBVENDOR(0, 0x17aa5062), + + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, +@@ -15,7 +15,7 @@ const u32 cim_verb_data[] = { + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, +- 2, 0 ++ 4, 0 + )), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( +@@ -27,28 +27,29 @@ const u32 cim_verb_data[] = { + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, 0 + )), +- AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), +- AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( ++ AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( + AZALIA_JACK, +- AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 3, 0 + )), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), +- AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), +- AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1d, 0x40648605), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( + AZALIA_JACK, +- AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, +- 1, 15 ++ 2, 0 + )), + + //==========Widget node 0x20 - 0 :Hidden register SW reset +@@ -107,7 +108,7 @@ const u32 cim_verb_data[] = { + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, +- 1, 0 ++ 2, 0 + )), + AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( + AZALIA_JACK, +@@ -116,7 +117,7 @@ const u32 cim_verb_data[] = { + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, +- 1, 0 ++ 3, 0 + )), + }; + +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0051-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch b/config/coreboot/default/patches/0051-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch new file mode 100644 index 00000000..b6473d8e --- /dev/null +++ b/config/coreboot/default/patches/0051-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch @@ -0,0 +1,1530 @@ +From 24cb7949962e910c22ccb3e388699709591f2834 Mon Sep 17 00:00:00 2001 +From: Todd Baker +Date: Thu, 12 Mar 2026 13:12:04 -0400 +Subject: [PATCH 51/51] mb/dell: Add OptiPlex 3040 Micro port + (upstream-compatible) + +Based on the OptiPlex 3050 Micro (same Skylake H110 PCH-H platform). +Key differences from 3050: +- DDR3L SODIMMs (256-byte SPD at 0x50/0x52) +- Intel Pentium G4400T-class CPUs (Skylake only, no Kabylake/Coffeelake) +- Realtek ALC3234 HDA (subsystem ID 0x102806bb) +- VBT: DDI E entry removed (phantom port, causes i915 WARN_ON) +- PCIe root ports rp5/rp8/rp21 enabled (PcieRpEnable removed; use device on/off) +- HECI1 set off to prevent stall when HAP bit is set (ME neutralized) + +Signed-off-by: Todd Baker +--- + src/mainboard/dell/optiplex_3040/Kconfig | 37 ++ + src/mainboard/dell/optiplex_3040/Kconfig.name | 4 + + src/mainboard/dell/optiplex_3040/Makefile.mk | 12 + + src/mainboard/dell/optiplex_3040/acpi/ec.asl | 3 + + .../dell/optiplex_3040/acpi/superio.asl | 3 + + .../dell/optiplex_3040/board_info.txt | 7 + + src/mainboard/dell/optiplex_3040/bootblock.c | 107 ++++ + src/mainboard/dell/optiplex_3040/cmos.default | 5 + + src/mainboard/dell/optiplex_3040/cmos.layout | 54 ++ + src/mainboard/dell/optiplex_3040/data.vbt | Bin 0 -> 4300 bytes + .../dell/optiplex_3040/devicetree.cb | 100 ++++ + src/mainboard/dell/optiplex_3040/dsdt.asl | 27 + + .../dell/optiplex_3040/gma-mainboard.ads | 19 + + src/mainboard/dell/optiplex_3040/hda_verb.c | 90 +++ + .../dell/optiplex_3040/include/early_gpio.h | 11 + + .../dell/optiplex_3040/include/gpio.h | 241 +++++++++ + src/mainboard/dell/optiplex_3040/ramstage.c | 512 ++++++++++++++++++ + src/mainboard/dell/optiplex_3040/romstage.c | 22 + + src/mainboard/dell/optiplex_3040/sch5555_ec.c | 54 ++ + src/mainboard/dell/optiplex_3040/sch5555_ec.h | 10 + + 20 files changed, 1318 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_3040/Kconfig + create mode 100644 src/mainboard/dell/optiplex_3040/Kconfig.name + create mode 100644 src/mainboard/dell/optiplex_3040/Makefile.mk + create mode 100644 src/mainboard/dell/optiplex_3040/acpi/ec.asl + create mode 100644 src/mainboard/dell/optiplex_3040/acpi/superio.asl + create mode 100644 src/mainboard/dell/optiplex_3040/board_info.txt + create mode 100644 src/mainboard/dell/optiplex_3040/bootblock.c + create mode 100644 src/mainboard/dell/optiplex_3040/cmos.default + create mode 100644 src/mainboard/dell/optiplex_3040/cmos.layout + create mode 100644 src/mainboard/dell/optiplex_3040/data.vbt + create mode 100644 src/mainboard/dell/optiplex_3040/devicetree.cb + create mode 100644 src/mainboard/dell/optiplex_3040/dsdt.asl + create mode 100644 src/mainboard/dell/optiplex_3040/gma-mainboard.ads + create mode 100644 src/mainboard/dell/optiplex_3040/hda_verb.c + create mode 100644 src/mainboard/dell/optiplex_3040/include/early_gpio.h + create mode 100644 src/mainboard/dell/optiplex_3040/include/gpio.h + create mode 100644 src/mainboard/dell/optiplex_3040/ramstage.c + create mode 100644 src/mainboard/dell/optiplex_3040/romstage.c + create mode 100644 src/mainboard/dell/optiplex_3040/sch5555_ec.c + create mode 100644 src/mainboard/dell/optiplex_3040/sch5555_ec.h + +diff --git a/src/mainboard/dell/optiplex_3040/Kconfig b/src/mainboard/dell/optiplex_3040/Kconfig +new file mode 100644 +index 0000000000..eab8e7d814 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/Kconfig +@@ -0,0 +1,37 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++if BOARD_DELL_OPTIPLEX_3040 ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ select BOARD_ROMSIZE_KB_16384 ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ select INTEL_GMA_ADD_VBT ++ select INTEL_GMA_HAVE_VBT ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_SUPPORTS_SKYLAKE_CPU ++ select SKYLAKE_SOC_PCH_H ++ select AZALIA_USE_LEGACY_VERB_TABLE ++ select SOC_INTEL_COMMON_BLOCK_HDA_VERB ++ select SOC_INTEL_KABYLAKE ++ select SUPERIO_SMSC_SCH555x ++ ++config CBFS_SIZE ++ default 0x900000 ++ ++config MAINBOARD_DIR ++ default "dell/optiplex_3040" ++ ++config MAINBOARD_PART_NUMBER ++ default "OptiPlex 3040 Micro" ++ ++config INTEL_GMA_VBT_FILE ++ default "src/mainboard/$(MAINBOARDDIR)/data.vbt" ++ ++config DIMM_SPD_SIZE ++ default 256 # DDR3L ++ ++endif +diff --git a/src/mainboard/dell/optiplex_3040/Kconfig.name b/src/mainboard/dell/optiplex_3040/Kconfig.name +new file mode 100644 +index 0000000000..e06da5010a +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/Kconfig.name +@@ -0,0 +1,4 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_DELL_OPTIPLEX_3040 ++ bool "Dell OptiPlex 3040 Micro" +diff --git a/src/mainboard/dell/optiplex_3040/Makefile.mk b/src/mainboard/dell/optiplex_3040/Makefile.mk +new file mode 100644 +index 0000000000..0bd72fe691 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/Makefile.mk +@@ -0,0 +1,12 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++bootblock-y += bootblock.c ++bootblock-y += sch5555_ec.c ++ ++romstage-y += romstage.c ++ ++ramstage-y += ramstage.c ++ramstage-y += sch5555_ec.c ++ramstage-y += hda_verb.c ++ ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +diff --git a/src/mainboard/dell/optiplex_3040/acpi/ec.asl b/src/mainboard/dell/optiplex_3040/acpi/ec.asl +new file mode 100644 +index 0000000000..16990d45f4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/acpi/ec.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: CC-PDDC */ ++ ++/* Please update the license if adding licensable material. */ +diff --git a/src/mainboard/dell/optiplex_3040/acpi/superio.asl b/src/mainboard/dell/optiplex_3040/acpi/superio.asl +new file mode 100644 +index 0000000000..16990d45f4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/acpi/superio.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: CC-PDDC */ ++ ++/* Please update the license if adding licensable material. */ +diff --git a/src/mainboard/dell/optiplex_3040/board_info.txt b/src/mainboard/dell/optiplex_3040/board_info.txt +new file mode 100644 +index 0000000000..e43a925ec3 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/board_info.txt +@@ -0,0 +1,7 @@ ++Category: desktop ++Board URL: https://www.dell.com/support/home/en-us/product-support/product/optiplex-3040-micro/overview ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y ++Release year: 2016 +diff --git a/src/mainboard/dell/optiplex_3040/bootblock.c b/src/mainboard/dell/optiplex_3040/bootblock.c +new file mode 100644 +index 0000000000..10689c42a1 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/bootblock.c +@@ -0,0 +1,107 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include "include/early_gpio.h" ++#include "sch5555_ec.h" ++ ++struct ec_init_entry { ++ uint16_t addr; ++ uint8_t val; ++}; ++ ++static void bootblock_ec_init(void) ++{ ++ /* ++ * Early EC init ++ */ ++ ++ static const struct ec_init_entry init_table1[] = { ++ {0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10}, ++ {0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10}, ++ {0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12}, ++ {0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12}, ++ {0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10}, ++ {0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11}, ++ }; ++ ++ for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i) ++ sch5555_mbox_write(2, init_table1[i].addr, init_table1[i].val); ++ ++ static const struct ec_init_entry init_table2[] = { ++ {0x0040, 0x00}, {0x00f8, 0x10}, {0x00f9, 0x00}, {0x00f0, 0x30}, ++ {0x00fa, 0x00}, {0x00fb, 0x00}, {0x00ea, 0x00}, {0x00eb, 0x00}, ++ {0x00ef, 0x7c}, {0x0005, 0x0f}, {0x0014, 0x01}, {0x0018, 0x2f}, ++ {0x0019, 0x2f}, {0x001a, 0x2f}, {0x001b, 0x2f}, {0x01d8, 0x01}, ++ {0x0040, 0x11}, ++ }; ++ ++ for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i) ++ sch5555_mbox_write(1, init_table2[i].addr, init_table2[i].val); ++ ++ sch5555_mbox_write(1, 0x000b, 0x01); ++ sch5555_mbox_write(4, 0x001a, 0x04); ++ sch5555_mbox_write(4, 0x0028, 0x18); ++ sch5555_mbox_write(4, 0x001a, 0x00); ++ sch5555_mbox_write(1, 0x000b, 0x03); ++ ++ /* ++ * Early HWM init ++ */ ++ ++ sch5555_mbox_read(1, 0xcb); ++ sch5555_mbox_read(1, 0xb8); ++ ++ static const struct ec_init_entry hwm_init_table[] = { ++ {0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f}, ++ {0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33}, ++ {0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff}, ++ {0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00}, ++ {0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00}, ++ {0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80}, ++ {0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02}, ++ {0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04}, ++ {0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50}, ++ {0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50}, ++ {0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c}, ++ {0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd}, ++ {0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e}, ++ {0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00}, ++ {0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff}, ++ {0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00}, ++ {0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c}, ++ {0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02}, ++ {0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03}, {0x0015, 0x33}, ++ {0x018b, 0x00}, {0x018c, 0x00}, {0x02f8, 0x5e}, {0x02f9, 0x01}, ++ }; ++ ++ for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i) ++ sch5555_mbox_write(1, hwm_init_table[i].addr, hwm_init_table[i].val); ++} ++ ++ ++#define SCH555x_IOBASE 0x2e ++#define GLOBAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL) ++#define SERIAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1) ++ ++void bootblock_mainboard_early_init(void) ++{ ++ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); ++ ++ // Super I/O early init will map Runtime and EMI registers ++ sch555x_early_init(GLOBAL_DEV); ++ ++ // Changes LED color among a few other things ++ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS); ++ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN); ++ outb(0xf, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); ++ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); ++ ++ // Perform bootblock EC initialization ++ bootblock_ec_init(); ++ ++ // Bootblock EC initialization is required for UART1 to work ++ sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ++} +diff --git a/src/mainboard/dell/optiplex_3040/cmos.default b/src/mainboard/dell/optiplex_3040/cmos.default +new file mode 100644 +index 0000000000..79961f43d8 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/cmos.default +@@ -0,0 +1,5 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Disable +diff --git a/src/mainboard/dell/optiplex_3040/cmos.layout b/src/mainboard/dell/optiplex_3040/cmos.layout +new file mode 100644 +index 0000000000..54a5147b7d +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/cmos.layout +@@ -0,0 +1,54 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++#start-bit length config config-ID name ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++ ++# coreboot config options: southbridge ++409 2 e 7 power_on_after_fail ++ ++# coreboot config options: bootloader ++#Used by ChromeOS: ++416 128 r 0 vbnv ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 415 984 +diff --git a/src/mainboard/dell/optiplex_3040/data.vbt b/src/mainboard/dell/optiplex_3040/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..b503dfc20277775982256a4bdc9108c2ad96f856 +GIT binary patch +literal 4300 +zcmeHJU2GIp6h1SvzjtP~vs09^U_BzjZlPs%m0GmOYuF-@o*+oezEo~tM +ze;7keND#9RYS0kU#1~Uvni!wdNMej6_=85_(Y}}{(ZmFdFTi^4%(PpVU{|7163*n@ +z^D}3@x%b>Ncg~9bjy~Mc^F(j5XA`UD;e#W4o_=Nw +zqp27s48v$n81XpTQ^wTL$Z!iL2M2LGj~T`7#nIx(fnuRWWhw(W4FQh;g5ZTZ3k0~D +zfV>GA6VfIa2rE3W$OFSB6inzd;Q@p(vwA)ni0cH=1F&-b9VCO`B@zKJfty4KAb8-L +zJZM_r&?0VUz7+txAMU3C1SFjZiA^|fN4;W4&0Gio&?_L|M*&4r>?lVetW$OrKoG#k +z@A(Y@`Kui)nFqF%F +zKU^z+*#PBoU<03lNeGk+A?+e{xw6-ml9X}nK9amda;{x22lHem==wKC$wp>pc_BMg +zF5l{!QV(0`OOgWZ6CSYqZJu@zKRK>SFb*tCADK(KVkdgmTyzS25y$Yi&pNB+e|aau +zkAkH?i|70d&iOA3N9+He8qb-wz%`rKuuHS{ZFxHb^E0rl3(g0v63*PE1@gHz +zx%(-qNijeNg97yLhpzeWnbQLxcG2J5339x)D^1T-h+H1~pI>nyLLL7=|AL|ssDsh! +z0Bec}Aodza4>KHK`Y2;BFnpWo?=$u>!ylObJ7a>3t7Lt>%u+J$k@e?f_Oguc%KAq# +z`%K1PWW6l2pn_`^J*luB1@|fX5rrLB@I6KURAFB!_?x2pRTft9K~?Wo*$x#Cs`@dN +zy{_U1s{Vz_E~t1_)$2lRNeDNF^lXSd8B&{cuO-e1RybrgI)M>|&Yqm8*z&TVk@VKB +zqQBhro6>rinl8Rt1*M$0Fv4UVLOiz&qZairoElpXi(uze;m7&H2!$nJCSj$~aJ1Dy +zXlOkw+5H*qxfeVfp`CiB8?VA>f)iOVOk=p-L7+L%gIrg}y^)#_#xWbwOl=;5Q1bo_ +zgm>1C&txMj&D@E~9E6hH^C_lpx`sJ)Z8VKt(+Sf&T|w|U9gx!RttFGY@9Ce)LZi`H +za`%E~vSj}|X)3kk;rW)*WIobp8tCo?Wztik=9MyO`DRqtm0w>CNsF$P>fV%6(#x}?M$}W^}vh###JpoWHsz-Yc_MumA#PYEaC`sjQJM+ +zE@CF+EvV0HT9`j&?}bF?DUs6Knc0~c*jpTYbl}OV + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/optiplex_3040/devicetree.cb b/src/mainboard/dell/optiplex_3040/devicetree.cb +new file mode 100644 +index 0000000000..f1c919fbc7 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/devicetree.cb +@@ -0,0 +1,100 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++chip soc/intel/skylake ++ register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN" ++ ++ # Enable Enhanced Intel SpeedStep ++ register "eist_enable" = "1" ++ ++ device domain 0 on ++ device ref igpu on ++ register "PrimaryDisplay" = "Display_iGFX" ++ end ++ ++ device ref south_xhci on ++ register "usb2_ports" = "{ ++ [0] = USB2_PORT_MID(OC0), // Front panel (blue) ++ [1] = USB2_PORT_MID(OC0), // Front panel (blue) ++ [2] = USB2_PORT_MID(OC3), // Back panel (black) ++ [3] = USB2_PORT_MID(OC2), // Back panel (blue) ++ [4] = USB2_PORT_MID(OC1), // Back panel (blue) ++ [6] = USB2_PORT_MID(OC1), // Back panel (black) ++ [8] = USB2_PORT_MID(OC_SKIP), // WiFi slot ++ }" ++ register "usb3_ports" = "{ ++ [0] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) ++ [1] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) ++ [2] = USB3_PORT_DEFAULT(OC2), // Back panel (blue) ++ [3] = USB3_PORT_DEFAULT(OC1), // Back panel (blue) ++ }" ++ end ++ ++ # ME interface is 'off' to avoid HECI reset delay due to HAP ++ device ref heci1 off end ++ ++ device ref sata on ++ register "SataSalpSupport" = "1" ++ register "SataPortsEnable[0]" = "1" ++ end ++ ++ # M.2 SSD ++ device ref pcie_rp21 on ++ register "PcieRpClkReqSupport[20]" = "1" ++ register "PcieRpClkReqNumber[20]" = "3" ++ register "PcieRpAdvancedErrorReporting[20]" = "1" ++ register "PcieRpLtrEnable[20]" = "true" ++ register "PcieRpClkSrcNumber[20]" = "3" ++ register "PcieRpHotPlug[20]" = "0" ++ end ++ ++ # Realtek LAN ++ device ref pcie_rp5 on ++ register "PcieRpClkReqSupport[4]" = "0" ++ register "PcieRpHotPlug[4]" = "0" ++ end ++ ++ # M.2 WiFi ++ device ref pcie_rp8 on ++ register "PcieRpClkReqSupport[7]" = "0" ++ register "PcieRpHotPlug[7]" = "1" ++ end ++ ++ # UART0 is exposed on test points on the bottom of the board ++ device ref uart0 on ++ register "SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci" ++ end ++ ++ device ref lpc_espi on ++ register "serirq_mode" = "SERIRQ_CONTINUOUS" ++ ++ # I/O decode for EMI/Runtime registers ++ register "gen1_dec" = "0x007c0a01" ++ ++ # SCH5553 ++ chip superio/smsc/sch555x ++ device pnp 2e.0 on # EMI ++ io 0x60 = 0xa00 ++ end ++ device pnp 2e.1 off end # 8042 ++ device pnp 2e.7 on # UART1 ++ io 0x60 = 0x3f8 ++ irq 0x0f = 2 ++ irq 0x70 = 4 ++ end ++ device pnp 2e.8 off end # UART2 ++ device pnp 2e.c on # LPC interface ++ io 0x60 = 0x2e ++ end ++ device pnp 2e.a on # Runtime registers ++ io 0x60 = 0xa40 ++ end ++ device pnp 2e.b off end # Floppy Controller ++ device pnp 2e.11 off end # Parallel Port ++ end ++ end ++ ++ device ref hda on end ++ ++ device ref smbus on end ++ end ++end +diff --git a/src/mainboard/dell/optiplex_3040/dsdt.asl b/src/mainboard/dell/optiplex_3040/dsdt.asl +new file mode 100644 +index 0000000000..9762f6ff74 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/dsdt.asl +@@ -0,0 +1,27 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20110725 ++) ++{ ++ #include ++ #include ++ #include ++ ++ Scope (\_SB) ++ { ++ Device (PCI0) ++ { ++ #include ++ #include ++ } ++ } ++ ++ #include ++} +diff --git a/src/mainboard/dell/optiplex_3040/gma-mainboard.ads b/src/mainboard/dell/optiplex_3040/gma-mainboard.ads +new file mode 100644 +index 0000000000..cb4c22f285 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/gma-mainboard.ads +@@ -0,0 +1,19 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (HDMI1, -- External HDMI ++ DP2, -- External DP (native) ++ HDMI2, -- External DP (DP++) ++ DP3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) ++ HDMI3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/optiplex_3040/hda_verb.c b/src/mainboard/dell/optiplex_3040/hda_verb.c +new file mode 100644 +index 0000000000..5a1db019c7 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/hda_verb.c +@@ -0,0 +1,90 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header, codec 0 */ ++ 0x10ec0255, /* Realtek ALC3234 */ ++ 0x102806bb, /* Subsystem ID */ ++ 11, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ ++ AZALIA_SUBVENDOR(0, 0x102806bb), ++ ++ AZALIA_PIN_CFG(0, 0x12, 0x40000000), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 5, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, ++ AZALIA_LINE_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x1d, 0x4054c029), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, ++ AZALIA_HP_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 5, 15 ++ )), ++ ++ /* coreboot specific header, codec 2 */ ++ 0x80862809, /* Intel Skylake HDMI */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ ++ AZALIA_SUBVENDOR(2, 0x80860101), ++ ++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++}; ++ ++const u32 pc_beep_verbs[] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/optiplex_3040/include/early_gpio.h b/src/mainboard/dell/optiplex_3040/include/early_gpio.h +new file mode 100644 +index 0000000000..fdf1a64c7c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/include/early_gpio.h +@@ -0,0 +1,11 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __OPTIPLEX_3040_EARLY_GPIO_H__ ++#define __OPTIPLEX_3040_EARLY_GPIO_H__ ++ ++static const struct pad_config early_gpio_table[] = { ++ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ ++ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ ++}; ++ ++#endif +diff --git a/src/mainboard/dell/optiplex_3040/include/gpio.h b/src/mainboard/dell/optiplex_3040/include/gpio.h +new file mode 100644 +index 0000000000..29da4b11d4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/include/gpio.h +@@ -0,0 +1,241 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __OPTIPLEX_3040_GPIO_H__ ++#define __OPTIPLEX_3040_GPIO_H__ ++ ++static const struct pad_config gpio_table[] = { ++ ++ /* ------- GPIO Community 0 ------- */ ++ ++ /* ------- GPIO Group GPP_A ------- */ ++ PAD_CFG_NF(GPP_A0, UP_20K, PLTRST, NF1), /* RCIN# */ ++ PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* LAD0 */ ++ PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* LAD1 */ ++ PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* LAD2 */ ++ PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* LAD3 */ ++ PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */ ++ PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKRUN# */ ++ PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), /* CLKOUT_LPC0 */ ++ PAD_CFG_NF(GPP_A10, NONE, PLTRST, NF1), /* CLKOUT_LPC1 */ ++ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), /* PME# */ ++ PAD_CFG_GPO(GPP_A12, 0, PLTRST), /* GPIO */ ++ PAD_CFG_NF(GPP_A13, NONE, PLTRST, NF1), /* SUSWARN#/SUSPWRDNACK */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_A15, UP_20K, PLTRST, NF1), /* SUS_ACK# */ ++ PAD_CFG_GPO(GPP_A16, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_B ------- */ ++ PAD_CFG_GPO(GPP_B0, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B1, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B2, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_B3, 1, RSMRST), /* GPIO (ME_CNTL, B3 -> LOW => HDA_SDO -> HIGH) */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_B5, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B6, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B7, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_B9, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1), /* SLP_S0# */ ++ PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), /* PLTRST# */ ++ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* SPKR */ ++ PAD_CFG_GPO(GPP_B15, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B16, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* GSPIO_MOSI */ ++ PAD_CFG_GPO(GPP_B19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B20, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* GPIO */ ++ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), /* GSPI1_MOSI */ ++ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), /* PCHHOT# */ ++ ++ /* ------- GPIO Community 1 ------- */ ++ ++ /* ------- GPIO Group GPP_C ------- */ ++ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ ++ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_C2, DN_20K, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_C3, NONE, PLTRST, NF1), /* SML0CLK */ ++ PAD_CFG_NF(GPP_C4, NONE, PLTRST, NF1), /* SML0DATA */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK */ ++ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1DATA */ ++ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ ++ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ ++ PAD_CFG_GPO(GPP_C10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C11, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C12, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C13, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C14, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C15, 0, PLTRST), /* GPIO */ ++ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), /* I2C0_SDA */ ++ PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), /* I2C0_SCL */ ++ PAD_CFG_GPO(GPP_C18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C21, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_D ------- */ ++ PAD_CFG_GPO(GPP_D0, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D1, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D2, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D3, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_D6, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_D7, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D8, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D9, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D11, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D13, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D14, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D15, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D16, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D21, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_E ------- */ ++ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATAXPCIE0 */ ++ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SATAXPCIE1 */ ++ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* SATAXPCIE2 */ ++ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* SATA_LED# */ ++ PAD_CFG_NF(GPP_E9, UP_20K, PLTRST, NF1), /* USB_OC0# */ ++ PAD_CFG_NF(GPP_E10, UP_20K, PLTRST, NF1), /* USB_OC1# */ ++ PAD_CFG_NF(GPP_E11, UP_20K, PLTRST, NF1), /* USB_OC2# */ ++ PAD_CFG_NF(GPP_E12, UP_20K, PLTRST, NF1), /* USB_OC3# */ ++ ++ /* ------- GPIO Group GPP_F ------- */ ++ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* SATAXPCIE3 */ ++ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* SATAXPCIE4 */ ++ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* SATAXPCIE5 */ ++ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* SATAXPCIE6 */ ++ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* SATAXPCIE7 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_F6, NONE, RSMRST, NF1), /* SATA_DEVSLP4 */ ++ PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_F9, 0, RSMRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_F13, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), /* USB_OC4# */ ++ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), /* USB_OC5# */ ++ PAD_CFG_NF(GPP_F17, UP_20K, PLTRST, NF1), /* USB_OC6# */ ++ PAD_CFG_TERM_GPO(GPP_F18, 0, UP_20K, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_F19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_F20, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_F21, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_F22, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_F23, 1, RSMRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_G ------- */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_G9, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_G12, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_G14, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G15, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G16, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G17, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_G19, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G20, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_G21, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G22, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_H ------- */ ++ PAD_CFG_GPO(GPP_H0, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H2, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H3, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H4, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H5, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H6, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_H7, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H8, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H9, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H11, 0, PLTRST), /* GPIO */ ++ PAD_CFG_TERM_GPO(GPP_H12, 1, DN_20K, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H15, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H16, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H21, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Community 2 ------- */ ++ ++ /* -------- GPIO Group GPD -------- */ ++ PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* BATLOW# */ ++ PAD_CFG_GPO(GPD1, 0, PWROK), /* GPIO */ ++ PAD_CFG_NF(GPD2, NONE, RSMRST, NF1), /* LAN_WAKE# */ ++ PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), /* PWRBTN# */ ++ PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */ ++ PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */ ++ PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* SLP_A# */ ++ PAD_CFG_GPO(GPD7, 1, RSMRST), /* GPIO */ ++ PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* SUSCLK */ ++ PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */ ++ PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */ ++ PAD_CFG_GPO(GPD11, 1, RSMRST), /* GPIO */ ++ ++ /* ------- GPIO Community 3 ------- */ ++ ++ /* ------- GPIO Group GPP_I ------- */ ++ PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */ ++ PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPC_HPD1 */ ++ PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DDPD_HPD2 */ ++ PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* DDPE_HPD3 */ ++ PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), /* EDP_HPD */ ++ PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* DDPB_CTRLCLK */ ++ PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), /* DDPB_CTRLDATA */ ++ PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* DDPC_CTRLCLK */ ++ PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), /* DDPC_CTRLDATA */ ++ PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */ ++ PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), /* DDPD_CTRLDATA */ ++}; ++ ++#endif +diff --git a/src/mainboard/dell/optiplex_3040/ramstage.c b/src/mainboard/dell/optiplex_3040/ramstage.c +new file mode 100644 +index 0000000000..c391e4ac6d +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/ramstage.c +@@ -0,0 +1,512 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "include/gpio.h" ++#include "sch5555_ec.h" ++ ++void mainboard_silicon_init_params(FSP_SIL_UPD *params) ++{ ++ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); ++} ++ ++#define FORM_FACTOR_MICRO 0 ++#define FORM_FACTOR_SFF 1 ++// Probably DT and MT ++#define FORM_FACTOR_UNK2 2 ++#define FORM_FACTOR_UNK3 3 ++ ++#define HWM_TAB_ADD_TEMP_TARGET 1 ++#define HWM_TAB_PKG_POWER_ANY 0xffff ++ ++struct hwm_tab_entry { ++ uint16_t addr; ++ uint8_t val; ++ uint8_t flags; ++ uint16_t pkg_power; ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MICRO_BASE[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x01b, 0x0f, 0, 0xffff }, ++ { 0x057, 0xff, 0, 0xffff }, ++ { 0x059, 0xff, 0, 0xffff }, ++ { 0x05b, 0xff, 0, 0xffff }, ++ { 0x05d, 0xff, 0, 0xffff }, ++ { 0x05f, 0xff, 0, 0xffff }, ++ { 0x061, 0xff, 0, 0xffff }, ++ { 0x06e, 0x00, 0, 0xffff }, ++ { 0x06f, 0x03, 0, 0xffff }, ++ { 0x070, 0x03, 0, 0xffff }, ++ { 0x071, 0x02, 0, 0xffff }, ++ { 0x072, 0x02, 0, 0xffff }, ++ { 0x073, 0x01, 0, 0xffff }, ++ { 0x074, 0x06, 0, 0xffff }, ++ { 0x075, 0x07, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x80, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xf1, 0, 0xffff }, ++ { 0x086, 0x88, 0, 0xffff }, ++ { 0x087, 0x61, 0, 0xffff }, ++ { 0x088, 0x08, 0, 0xffff }, ++ { 0x089, 0x00, 0, 0xffff }, ++ { 0x08a, 0x73, 0, 0xffff }, ++ { 0x08b, 0x73, 0, 0xffff }, ++ { 0x08c, 0x73, 0, 0xffff }, ++ { 0x090, 0x6d, 0, 0xffff }, ++ { 0x091, 0x7e, 0, 0xffff }, ++ { 0x092, 0x66, 0, 0xffff }, ++ { 0x093, 0xa4, 0, 0xffff }, ++ { 0x094, 0x7c, 0, 0xffff }, ++ { 0x095, 0xa4, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x2e, 0, 0xffff }, ++ { 0x0a1, 0x00, 0, 0xffff }, ++ { 0x0a2, 0x00, 0, 0xffff }, ++ { 0x0ae, 0xa4, 0, 0xffff }, ++ { 0x0af, 0xa4, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0xa4, 0, 0xffff }, ++ { 0x0b3, 0xa4, 0, 0xffff }, ++ { 0x0b6, 0x00, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0d1, 0xff, 0, 0xffff }, ++ { 0x0d6, 0xff, 0, 0xffff }, ++ { 0x0db, 0xff, 0, 0xffff }, ++ { 0x0ea, 0x5c, 0, 0xffff }, ++ { 0x0eb, 0x5c, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x184, 0xff, 0, 0xffff }, ++ { 0x186, 0xff, 0, 0xffff }, ++ { 0x1a1, 0xce, 0, 0xffff }, ++ { 0x1a2, 0x0c, 0, 0xffff }, ++ { 0x1a3, 0x0c, 0, 0xffff }, ++ { 0x1a6, 0x00, 0, 0xffff }, ++ { 0x1a7, 0x00, 0, 0xffff }, ++ { 0x1a8, 0xa4, 0, 0xffff }, ++ { 0x1a9, 0xa4, 0, 0xffff }, ++ { 0x1ab, 0x2d, 0, 0xffff }, ++ { 0x1ac, 0x2d, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1bb, 0x00, 0, 0xffff }, ++ { 0x1bc, 0x00, 0, 0xffff }, ++ { 0x1bd, 0x00, 0, 0xffff }, ++ { 0x1be, 0x01, 0, 0xffff }, ++ { 0x1bf, 0x01, 0, 0xffff }, ++ { 0x1c0, 0x01, 0, 0xffff }, ++ { 0x1c1, 0x01, 0, 0xffff }, ++ { 0x1c2, 0x01, 0, 0xffff }, ++ { 0x280, 0x00, 0, 0xffff }, ++ { 0x281, 0x00, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MICRO_TEMP80[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x01b, 0x0f, 0, 0xffff }, ++ { 0x057, 0xff, 0, 0xffff }, ++ { 0x059, 0xff, 0, 0xffff }, ++ { 0x05b, 0xff, 0, 0xffff }, ++ { 0x05d, 0xff, 0, 0xffff }, ++ { 0x05f, 0xff, 0, 0xffff }, ++ { 0x061, 0xff, 0, 0xffff }, ++ { 0x06e, 0x00, 0, 0xffff }, ++ { 0x06f, 0x03, 0, 0xffff }, ++ { 0x070, 0x03, 0, 0xffff }, ++ { 0x071, 0x02, 0, 0xffff }, ++ { 0x072, 0x02, 0, 0xffff }, ++ { 0x073, 0x01, 0, 0xffff }, ++ { 0x074, 0x06, 0, 0xffff }, ++ { 0x075, 0x07, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x80, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xf6, 0, 0xffff }, ++ { 0x086, 0x88, 0, 0xffff }, ++ { 0x087, 0x61, 0, 0xffff }, ++ { 0x088, 0x08, 0, 0xffff }, ++ { 0x089, 0x00, 0, 0xffff }, ++ { 0x08a, 0x73, 0, 0xffff }, ++ { 0x08b, 0x73, 0, 0xffff }, ++ { 0x08c, 0x73, 0, 0xffff }, ++ { 0x090, 0x6d, 0, 0xffff }, ++ { 0x091, 0x86, 0, 0xffff }, ++ { 0x092, 0x66, 0, 0xffff }, ++ { 0x093, 0xa4, 0, 0xffff }, ++ { 0x094, 0x7c, 0, 0xffff }, ++ { 0x095, 0xa4, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x2e, 0, 0xffff }, ++ { 0x0a1, 0x00, 0, 0xffff }, ++ { 0x0a2, 0x00, 0, 0xffff }, ++ { 0x0ae, 0xa4, 0, 0xffff }, ++ { 0x0af, 0xa4, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0xa4, 0, 0xffff }, ++ { 0x0b3, 0xa4, 0, 0xffff }, ++ { 0x0b6, 0x00, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0d1, 0xff, 0, 0xffff }, ++ { 0x0d6, 0xff, 0, 0xffff }, ++ { 0x0db, 0xff, 0, 0xffff }, ++ { 0x0ea, 0x50, 0, 0xffff }, ++ { 0x0eb, 0x50, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x184, 0xff, 0, 0xffff }, ++ { 0x186, 0xff, 0, 0xffff }, ++ { 0x1a1, 0xce, 0, 0xffff }, ++ { 0x1a2, 0x0c, 0, 0xffff }, ++ { 0x1a3, 0x0c, 0, 0xffff }, ++ { 0x1a6, 0x00, 0, 0xffff }, ++ { 0x1a7, 0x00, 0, 0xffff }, ++ { 0x1a8, 0xa4, 0, 0xffff }, ++ { 0x1a9, 0xa4, 0, 0xffff }, ++ { 0x1ab, 0x2d, 0, 0xffff }, ++ { 0x1ac, 0x2d, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1bb, 0x00, 0, 0xffff }, ++ { 0x1bc, 0x00, 0, 0xffff }, ++ { 0x1bd, 0x00, 0, 0xffff }, ++ { 0x1be, 0x01, 0, 0xffff }, ++ { 0x1bf, 0x01, 0, 0xffff }, ++ { 0x1c0, 0x01, 0, 0xffff }, ++ { 0x1c1, 0x01, 0, 0xffff }, ++ { 0x1c2, 0x01, 0, 0xffff }, ++ { 0x280, 0x00, 0, 0xffff }, ++ { 0x281, 0x00, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MICRO_EARLY_STEPPING[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x01b, 0x0f, 0, 0xffff }, ++ { 0x057, 0xff, 0, 0xffff }, ++ { 0x059, 0xff, 0, 0xffff }, ++ { 0x05b, 0xff, 0, 0xffff }, ++ { 0x05d, 0xff, 0, 0xffff }, ++ { 0x05f, 0xff, 0, 0xffff }, ++ { 0x061, 0xff, 0, 0xffff }, ++ { 0x06e, 0x01, 0, 0xffff }, ++ { 0x06f, 0x03, 0, 0xffff }, ++ { 0x070, 0x03, 0, 0xffff }, ++ { 0x071, 0x02, 0, 0xffff }, ++ { 0x072, 0x02, 0, 0xffff }, ++ { 0x073, 0x01, 0, 0xffff }, ++ { 0x074, 0x06, 0, 0xffff }, ++ { 0x075, 0x07, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x80, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xfd, 0, 0xffff }, ++ { 0x086, 0x60, 0, 0xffff }, ++ { 0x087, 0x50, 0, 0xffff }, ++ { 0x088, 0x08, 0, 0xffff }, ++ { 0x089, 0x00, 0, 0xffff }, ++ { 0x08a, 0x73, 0, 0xffff }, ++ { 0x08b, 0x73, 0, 0xffff }, ++ { 0x08c, 0x73, 0, 0xffff }, ++ { 0x090, 0x6d, 0, 0xffff }, ++ { 0x091, 0x7a, 0, 0xffff }, ++ { 0x092, 0x6b, 0, 0xffff }, ++ { 0x093, 0xa4, 0, 0xffff }, ++ { 0x094, 0x78, 0, 0xffff }, ++ { 0x095, 0xa4, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x2e, 0, 0xffff }, ++ { 0x0a1, 0x00, 0, 0xffff }, ++ { 0x0a2, 0x00, 0, 0xffff }, ++ { 0x0ae, 0xa4, 0, 0xffff }, ++ { 0x0af, 0xa4, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0xa4, 0, 0xffff }, ++ { 0x0b3, 0xa4, 0, 0xffff }, ++ { 0x0b6, 0x00, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0d1, 0xff, 0, 0xffff }, ++ { 0x0d6, 0xff, 0, 0xffff }, ++ { 0x0db, 0xff, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0xffff }, ++ { 0x0eb, 0x64, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x184, 0xff, 0, 0xffff }, ++ { 0x186, 0xff, 0, 0xffff }, ++ { 0x1a1, 0xce, 0, 0xffff }, ++ { 0x1a2, 0x0c, 0, 0xffff }, ++ { 0x1a3, 0x0c, 0, 0xffff }, ++ { 0x1a6, 0x00, 0, 0xffff }, ++ { 0x1a7, 0x00, 0, 0xffff }, ++ { 0x1a8, 0xa4, 0, 0xffff }, ++ { 0x1a9, 0xa4, 0, 0xffff }, ++ { 0x1ab, 0x2d, 0, 0xffff }, ++ { 0x1ac, 0x2d, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1bb, 0x00, 0, 0xffff }, ++ { 0x1bc, 0x00, 0, 0xffff }, ++ { 0x1bd, 0x00, 0, 0xffff }, ++ { 0x1be, 0x01, 0, 0xffff }, ++ { 0x1bf, 0x01, 0, 0xffff }, ++ { 0x1c0, 0x01, 0, 0xffff }, ++ { 0x1c1, 0x01, 0, 0xffff }, ++ { 0x1c2, 0x01, 0, 0xffff }, ++ { 0x280, 0x00, 0, 0xffff }, ++ { 0x281, 0x00, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_SFF[] = { ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++ { 0x072, 0x03, 0, 0xffff }, ++ { 0x075, 0x06, 0, 0xffff }, ++ { 0x07c, 0x00, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x59, 0, 0xffff }, ++ { 0x086, 0x6a, 0, 0xffff }, ++ { 0x087, 0xc0, 0, 0xffff }, ++ { 0x08a, 0x33, 0, 0xffff }, ++ { 0x090, 0x77, 0, 0xffff }, ++ { 0x091, 0x66, 0, 0xffff }, ++ { 0x092, 0x94, 0, 0xffff }, ++ { 0x093, 0x90, 0, 0xffff }, ++ { 0x094, 0x68, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x3e, 0, 0xffff }, ++ { 0x0ae, 0x86, 0, 0xffff }, ++ { 0x0af, 0x86, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0x90, 0, 0xffff }, ++ { 0x0b6, 0x48, 0, 0xffff }, ++ { 0x0b7, 0x48, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x1b1, 0x48, 0, 0xffff }, ++ { 0x1b8, 0x00, 0, 0xffff }, ++ { 0x1be, 0x95, 0, 0xffff }, ++ { 0x1c1, 0x90, 0, 0xffff }, ++ { 0x1c6, 0x00, 0, 0xffff }, ++ { 0x1c9, 0x00, 0, 0xffff }, ++ { 0x280, 0x68, 0, 0xffff }, ++ { 0x281, 0x10, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff} ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MT[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xb9, 0, 0x0010 }, ++ { 0x086, 0xac, 0, 0x0010 }, ++ { 0x087, 0x87, 0, 0x0010 }, ++ { 0x08a, 0x51, 0, 0x0010 }, ++ { 0x08b, 0x39, 0, 0x0010 }, ++ { 0x090, 0x78, 0, 0xffff }, ++ { 0x091, 0x6a, 0, 0xffff }, ++ { 0x092, 0x8f, 0, 0xffff }, ++ { 0x094, 0x68, 0, 0xffff }, ++ { 0x095, 0x5b, 0, 0xffff }, ++ { 0x096, 0x92, 0, 0xffff }, ++ { 0x097, 0x86, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x09a, 0x8b, 0, 0xffff }, ++ { 0x0a0, 0x0a, 0, 0xffff }, ++ { 0x0a1, 0x26, 0, 0xffff }, ++ { 0x0a2, 0xd1, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x7c, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x99, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1a4, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1be, 0x90, 0, 0xffff }, ++ { 0x280, 0xc4, 0, 0xffff }, ++ { 0x281, 0x09, 0, 0xffff }, ++ { 0x282, 0x0a, 0, 0xffff }, ++ { 0x283, 0x14, 0, 0xffff }, ++ { 0x284, 0x01, 0, 0xffff }, ++ { 0x285, 0x01, 0, 0xffff }, ++ { 0x288, 0x94, 0, 0xffff }, ++ { 0x289, 0x11, 0, 0xffff }, ++ { 0x28a, 0x0a, 0, 0xffff }, ++ { 0x28b, 0x14, 0, 0xffff }, ++ { 0x28c, 0x01, 0, 0xffff }, ++ { 0x28d, 0x01, 0, 0xffff }, ++ { 0x294, 0x24, 0, 0xffff }, ++}; ++ ++static uint8_t get_temp_target(void) ++{ ++ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; ++ if (!val) ++ val = 20; ++ return 0x95 - val; ++} ++ ++static uint16_t get_pkg_power(void) ++{ ++ const unsigned int pkg_power = rdmsr(0x614).lo & 0x7fff; ++ const unsigned int power_unit = 1 << (rdmsr(0x606).lo & 0xf); ++ if (pkg_power / power_unit > 65) ++ return 32; ++ else ++ return 16; ++} ++ ++static uint8_t get_core_cnt(void) ++{ ++ // Intel describes this CPUID field as: ++ // > Maximum number of addressable IDs for processor cores in the physical package ++ if (cpuid(0).eax >= 4) ++ return cpuid_ext(4, 0).eax >> 26; ++ return 0; ++} ++ ++static void apply_hwm_tab(const struct hwm_tab_entry *arr, size_t size) ++{ ++ uint8_t temp_target = get_temp_target(); ++ uint16_t pkg_power = get_pkg_power(); ++ ++ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target); ++ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power); ++ ++ for (size_t i = 0; i < size; ++i) { ++ // Skip entry if it doesn't apply for this package power ++ if (arr[i].pkg_power != pkg_power && ++ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY) ++ continue; ++ ++ uint8_t val = arr[i].val; ++ ++ // Add temp target to value if requested (current tables never do) ++ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET) ++ val += temp_target; ++ ++ // Perform write ++ sch5555_mbox_write(1, arr[i].addr, val); ++ } ++} ++ ++static void sch5555_ec_hwm_init(void *arg) ++{ ++ uint8_t form_fac_id, saved_2fc, core_cnt; ++ ++ printk(BIOS_DEBUG, "OptiPlex 3040 late HWM init\n"); ++ ++ form_fac_id = gpio_get(GPP_G2) | gpio_get(GPP_G3) << 1; ++ printk(BIOS_DEBUG, "Form Factor ID = %#x\n", form_fac_id); ++ ++ saved_2fc = sch5555_mbox_read(1, 0x2fc); ++ sch5555_mbox_write(1, 0x2fc, 0xa0); ++ sch5555_mbox_write(1, 0x2fd, 0x32); ++ ++ switch (form_fac_id) { ++ case FORM_FACTOR_MICRO: ++ // CPU stepping <= 3 ++ if ((cpuid(1).eax & 0xf) <= 3) ++ apply_hwm_tab(HWM_TAB_MICRO_EARLY_STEPPING, ARRAY_SIZE(HWM_TAB_MICRO_EARLY_STEPPING)); ++ // Tjunction == 80 ++ else if ((rdmsr(0x1a2).lo >> 16 & 0xff) == 80) ++ apply_hwm_tab(HWM_TAB_MICRO_TEMP80, ARRAY_SIZE(HWM_TAB_MICRO_TEMP80)); ++ else ++ apply_hwm_tab(HWM_TAB_MICRO_BASE, ARRAY_SIZE(HWM_TAB_MICRO_BASE)); ++ break; ++ case FORM_FACTOR_SFF: ++ apply_hwm_tab(HWM_TAB_SFF, ARRAY_SIZE(HWM_TAB_SFF)); ++ break; ++ default: ++ apply_hwm_tab(HWM_TAB_MT, ARRAY_SIZE(HWM_TAB_MT)); ++ break; ++ } ++ ++ core_cnt = get_core_cnt(); ++ printk(BIOS_DEBUG, "CPU Core Count = %#x\n", core_cnt); ++ if (core_cnt > 2) { ++ sch5555_mbox_write(1, 0x9e, 0x30); ++ sch5555_mbox_write(1, 0xeb, sch5555_mbox_read(1, 0xea)); ++ } ++ ++ sch5555_mbox_write(1, 0x2fc, saved_2fc); ++ sch5555_mbox_read(1, 0xb8); ++} ++ ++BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); +diff --git a/src/mainboard/dell/optiplex_3040/romstage.c b/src/mainboard/dell/optiplex_3040/romstage.c +new file mode 100644 +index 0000000000..c2ce2369a4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/romstage.c +@@ -0,0 +1,22 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_memory_init_params(FSPM_UPD *mupd) ++{ ++ /* ++ * OptiPlex 3040 Micro uses DDR3L SO-DIMMs. ++ * SODIMM slots are at I2C addresses 0x50 (slot 0) and 0x52 (slot 1). ++ * SPD size for DDR3L is 256 bytes. ++ */ ++ struct spd_block blk = { .addr_map = { 0x50, 0x52, } }; ++ get_spd_smbus(&blk); ++ dump_spd_info(&blk); ++ ++ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; ++ mem_cfg->DqPinsInterleaved = true; ++ mem_cfg->MemorySpdDataLen = blk.len; ++ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; ++ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; ++} +diff --git a/src/mainboard/dell/optiplex_3040/sch5555_ec.c b/src/mainboard/dell/optiplex_3040/sch5555_ec.c +new file mode 100644 +index 0000000000..1df5026531 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/sch5555_ec.c +@@ -0,0 +1,54 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include "sch5555_ec.h" ++ ++uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t retry = 0; retry < 0xfff; ++retry) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++ ++ // read result ++ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); ++ return inb(SCH555x_EMI_IOBASE + 4); ++} ++ ++void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address and value ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t retry = 0; retry < 0xfff; ++retry) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++} +diff --git a/src/mainboard/dell/optiplex_3040/sch5555_ec.h b/src/mainboard/dell/optiplex_3040/sch5555_ec.h +new file mode 100644 +index 0000000000..9d262d5787 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/sch5555_ec.h +@@ -0,0 +1,10 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __SCH5555_EC_H__ ++#define __SCH5555_EC_H__ ++ ++uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2); ++ ++void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val); ++ ++#endif +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0051-mb-supermicro-x11-lga1151-series-Enable-SATA-hotplug.patch b/config/coreboot/default/patches/0051-mb-supermicro-x11-lga1151-series-Enable-SATA-hotplug.patch deleted file mode 100644 index 58c1a1d9..00000000 --- a/config/coreboot/default/patches/0051-mb-supermicro-x11-lga1151-series-Enable-SATA-hotplug.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 88519aed6c7f305f7f2319e335c1421137df7ce3 Mon Sep 17 00:00:00 2001 -From: Ron Nazarov -Date: Mon, 23 Mar 2026 17:04:03 +0000 -Subject: [PATCH] mb/supermicro/x11-lga1151-series: Enable SATA hotplug - -Before this patch, hotplugging only worked to replace drives (if you -tried to plug a drive into a SATA port that no drive was plugged in to -at boot, it wouldn't be detected) and you'd have to manually rescan -the bus (echo "- - -" > /sys/class/scsi_host/host*/scan) to make -plugs/unplugs get detected by the operating system. - -Now, hotplugging works for all ports (tested and working on Supermicro -X11SSH-LN4F) and there's no need to manually rescan (it sometimes -takes a few seconds for unplugs to be detected, but plugs are detected -instantly). - -Change-Id: Id978a047697795ea657048fb6dc6665736c293f9 -Signed-off-by: Ron Nazarov ---- - .../supermicro/x11-lga1151-series/devicetree.cb | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb -index fbf896c6ae..d25288420f 100644 ---- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb -+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb -@@ -28,6 +28,16 @@ chip soc/intel/skylake - [6] = 1, - [7] = 1, - }" -+ register "SataPortsHotPlug" = "{ -+ [0] = 1, -+ [1] = 1, -+ [2] = 1, -+ [3] = 1, -+ [4] = 1, -+ [5] = 1, -+ [6] = 1, -+ [7] = 1, -+ }" - end - device ref lpc_espi on - register "serirq_mode" = "SERIRQ_CONTINUOUS" --- -2.52.0 - -- cgit v1.2.1