From 63b527e8ff7eb173fc479d572a286e5938883afd Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 19 Dec 2025 07:30:59 +0000 Subject: cb/default: bump to rev def7aa7094, December 2025 latest coreboot revision of of today / right now at the time of this commit this brings the following upstream changes: * def7aa7094 arch/riscv/smp: Fix race condition * fc37085ddb Documentation/vboot: Update vboot supported boards list * 5bb7a83a7a acpi/acpi_apic.c: Generate MADT LAPIC entries based on current mode * 077191641b vendorcode/amd/opensil/Makefile.mk: Add 0x prefix for BIOS address * 4b353affd4 soc/amd/common/acpi/lpc.asl: Add HPET device * 0a867b3971 acpi/ivrs: Fill second EFR image value * 92f03c0c28 mb/google/ocelot/var/kodkod: Config touchpad I2C frequency * a923470688 drv/intel/mipi_camera: Remove duplicate comments for DSM methods * 896984e800 mb/google/bluey/quartz: Enable parallel charging support * de87ea0efa mb/google/bluey: Add parallel charging infrastructure * cfb0d8a144 mb/google/bluey: Enable PD negotiation when battery is missing * ddc1b51b43 mb/google/bluey: Enable PD negotiation in charging modes * c4ee22e267 Reapply "mb/google/bluey: Implement EC-based off-mode detection" * a225eefd4c drivers/spi: Add Macronix MX77U51250F chip id * 793c15a866 mb/google/ocelot: Fix Gen4 SSD power sequencing * b689671e79 include/acpi/acpi_apei.h: Add MCE APEI structs * 7a41dc416b include/acpi/acpi_apei.h: Add NMI APEI struct * 5251284e39 include/acpi/acpi_apei.h: Add PCIe APEI structs * 53350d5c8d include/acpi/acpi_apei.h: Add internal acpi_head_t struct * 5001b07f9c drivers/intel/mipi_camera: Add validation and remove unused defaults * 0f1ae4ae5f drivers/gfx/generic: Add support for non-VGA devices * ae0d232402 drivers/intel/mipi_camera: Add ACPI device type selection * 1532eb60ee drv/intel/mipi_camera: Add CVF Support DSM function * a64b93562d drv/intel/mipi_camera: Add I2C V2 DSM function * c8f89e00e4 drv/intel/mipi_camera: Refactor DSM generator functions * ea099e8b8c drivers/intel/mipi_camera: Split DSM generation into per-UUID functions * 6459a2007a mb/{google,intel}: Add ROM type and address for MIPI camera sensors * 11ea868b02 mb/google/volteer/var/drobit: Update pl2 minimum value * 8ed87f71ec mb/google/volteer: Make touchpad wake user-selectable via CFR * 7e1962a3cc mb/google/hatch: Make touchpad wake user-selectable via CFR * 152914272c device/azalia: Drop spurious read-back of STATESTS * 6e074550a5 device/azalia: Repurpose azalia_set_bits() for link-reset only * ecf202b8e4 device/azalia: Add missing 521us delay after RESET# de-assertion * d5d27badd4 Documentation: Add coreboot release 26.03 template * 8e23c46beb Docs/releases: Update release notes for 25.12 release * 01bc527afa soc/qualcomm/common: Add CMD-DB driver support * 2277edff88 soc/qualcomm/x1p42100: Split dram_aop region to map dram_aop_cmd_db as non-cacheable * a4cc178486 soc/qualcomm/common: Map AOP CMD-DB region as uncached region in MMU * 1b5f105595 mb/google/ocelot/var/ocelot: disable ISH UART0 RX pin * b67725d3f5 Revert "mb/google/bluey: Implement EC-based off-mode detection" * 1dc3e45f7c mipi: Support passing user data to mipi_cmd_func_t * 42c1947d99 mb/google/bluey: Implement EC-based off-mode detection * e54b82b85b mb/google/ocelot/var/kodkod: Enable pcie_rp5 to allow proper enumeration of pcie_rp6 * 4cc830349c mb/google/rex/var/karis: Add fw_config probe to enable all wifi * 173a32aa55 MAINTAINERS: Add Jayvik Desai to Google Bluey & Qualcomm SoCs * f28997dcdd soc/qualcomm/common: Add PD negotiation attribute macro * b70309350f arch/x86/acpi_bert_storage.c: Fix Error Section GUID compare * 847d91b82e include/acpi/acpi_apei.h: Update APEI structs for better readability * 679ea61d4d include/acpi/acpi_apei.h: Add APEI definitions * eb79807bec soc/qualcomm/x1p42100: Add mainboard hook for QcLib override * 8ece648c30 soc/qualcomm/common: Use bitwise OR for global_attributes * 22e54a701d soc/qualcomm/x1p42100: Add AOP, QDSS, and QSEE regions to SSRAM layout * 4d53aa7704 soc/qualcomm/x1p42100: Relocate PRERAM stack to BSRAM memory * a26b718d5a soc/qc/x1p42100: Define pre- & post-RAM stack regions in linker script * 1b599a8844 arch/arm64: Add an alternative entry point for ramstage code * 641f7ac677 arch/arm64: Introduce distinct PRERAM and POSTRAM stack regions * 2183326306 soc/qualcomm/x1p42100: Rename qcsdi region to aop_sdi in memlayout * fad9878a3e vc/intel/fsp/fsp2_0/wildcatlake: Update WCL FSP headers to FSP WCL.3393.02 * 71b79018da util/release/genrelnotes: Restore to saved HEAD instead of origin/main * 9f6e297399 vc/intel/fsp/mtl: Fix license header in MemInfoHob.h * 2171af0f5f mb/lenovo/sklkbl_x280: Fix build failure * a5d3c4c119 mb/lenovo/sklkbl: Fix headphone jack * 0b4d41004d mb/lenovo/sklkbl: Add Lenovo Thinkpad X280 as a variant * 9a3818f9b6 soc/mediatek/common: Print DRAM calibration status as string * 1e8cea55a0 soc/mediatek/common/emi: Cache SDRAM size * 9203cc827f soc/mediatek/mt8196: Add MTE tag memory to bootmem * 3d5135fdd0 lib/bootmem: Add memory type for Armv9 MTE tag storage * 2d45723d87 lib/bootmem: Add bootmem_add_range_from function * 4f78a40f53 mb/google/ocelot/var/ocicat: Update Touchscreen settings * 510f1950b4 mb/google/ocelot/var/ocicat: Update devicetree * 35cb6aea50 mb/google/hatch: Fix CFR pointer * 8f34fdfab3 Remove and swabXX() functions * d556bc65c2 mb/google/fatcat/var/ruby: Change GPIO pins to fix audio function * 6b5a872ce8 soc/mediatek: Pass dsi_regs/mipi_tx_regs to DSI API * 74c13eead4 soc/mediatek/mt8196: Define dsi_regs/mipi_tx_regs structs * a3317182ff soc/mediatek/common: Move dsi0 definition to dsi_register_v*.h * 3607024944 soc/mediatek: Move mtk_dsi_init declaration to display_dsi.h * 7ef424c75e soc/mediatek/common: Rename mipi_tx to mipi_tx0 * cf0b91d774 soc/mediatek: Move dsi_regs/mipi_tx_regs definitions to soc/dsi_reg.h * 403a42f1f0 soc/mediatek/mt8173: Fix mipi_tx1 address * 72010408b5 mb/google/eve: Add CFR option menu support * c36b149392 mb/google/eve/Makefile: Organize and group entries by stage * f61ecfa154 mb/google/link: Add CFR option menu support * 75460f531c mb/google/poppy: Add CFR option to enable/disable IPU cameras * ae8f2d8cee mb/google/poppy: Add CFR option menu support * 99d67bae63 mb/google/glados: Add CFR option menu support * 0d81d38a31 mb/google/skyrim: Add CFR option menu support * c397821cb6 mb/google/guybrush: Add CFR option menu support * c1f0be39da mb/google/zork: Add CFR option menu support * d105934073 mb/google/kahlee: Add CFR option menu support * 46a32a2b56 mb/google/sarien: Add CFR option menu support * e3bee6397d mb/google/rex: Add CFR option menu support * d0345005ad mb/google/brox: Add CFR option menu support * ee599486ac mb/google/dedede/galtic: Add CFR option for touchpad type * 7a78543eca mb/google/dedede/drawcia: Add CFR option for touchscreen selection * 1890c6d165 mb/google/dedede: Add CFR option menu support * bd89858f09 mb/google/brya: Add CFR option menu support * a58e0704c7 mb/google/volteer: Add CFR option menu support * 8b34490137 mb/google/drallion: Add CFR option menu support * 0762c7d6ee mb/google/drallion/Makefile: Organize and group entries by stage * 89902e8c80 mb/google/hatch: Add CFR option menu support * 0f93d154b2 mb/google/octopus: Add CFR option menu support * f0346845cd mb/google/reef: Add CFR option menu support * 2b959f4560 mb/google/puff: Add CFR option for automatic fan control * a8a77f9da2 mb/google/fizz: Add CFR option for automatic fan control * cde4280796 soc/intel/apollolake: Add CFR objects for existing options * 2e10f75751 mb/google/sarien: Increase size of SMMSTORE to 512KB * 91c6a0b5e6 mb/google/reef: Increase size of SMMSTORE to 512KB * 36a345f99e mb/google/octopus: Increase size of SMMSTORE to 512KB * d7cb2d2bc5 mb/google/drallion: Increase size of SMMSTORE to 512KB * d32a372846 drivers/smmstore: Increase default size of store to 512KB * c109fc92ff libpayload: Add API to get physical memory size * 519332de10 mb/google/fatcat/var/ruby: Modify VCCCORE VR Fast Vmode ICC limit * 7f93e2fe29 soc/intel/*: Add CFR option to enable/disable the Intel iGPU * d5ea359347 soc/intel/**/cfr.h: Fix typo of "ACPI" in UI help text * 02a2fe7907 Merge coreboot and libpayload into commonlib * 5eb7b8bd34 payloads/external/edk2/Makefile: Set SMBIOS to 3.0.0 * c3afc13a0a soc/qualcomm/x1p42100: Update memlayout for BL31 region and realign TA region * 04f83ff7dc cpu/x86/mtrr: Simplify MTRR solution calculation on AMD systems * 6957f84aa7 soc/qualcomm/x1p42100: Define MDSS domain registers for display clock enablement * 9a95aef482 soc/qualcomm/common: Add API to enable Lucidole PLL for X1P42100 * 5eaf85d19b soc/intel/skylake: Use CSE reset status for reset * 84a4cdc6a5 soc/intel/*: Only skip PMC fallback on successful CSE reset * 4f52ca6ba6 soc/intel/common/cse: Return usable error codes * 8795680828 cpu/x86/lapic/lapic.c: Set spurious interrupt vector to 0xF * 41348477e3 sb/intel/common/firmware/Makefile.mk: fix INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE * c11faad2bf mb/google/skywalker: Correct MIPI panel power sequence * 459cdd09f4 mb/google/rauru: Add variant-specific firmware config * fee2befc82 3rdparty/blobs: Update to upstream main * 626789b40a mb/siemens/mc_ehl{1..5}: Unify devicetrees SerialIoI2cPadsTermination * 0513c45a38 mb/google/nissa/var/pujjoga: Generate RAM ID for MT62F1G32D2DS-031RF WT:C * 4a5d0dee4a soc/mediatek/mt8189: Correct AUX LDO mask bit definition * db01aa6cb2 commonlib/device_tree.c: Fix skipping NOP tokens * 29bec62a22 cpu/x86/Kconfig: Remove SOC_SETS_MSRS option * f4aeac4276 soc/amd/glinda: Set FSP UPDs from devicetree for USB4 * f68450e39b vendorcode/amd/fsp/glinda: Update FSP UPDs * 244e8edf18 soc/amd/glinda/Kconfig: Add Faegan SoC as Glinda variant * 9e5c7eb3f8 soc/amd/glinda: Add XGBE devices * 87475d693a soc/amd/glinda: Remove set_resets_to_cold * dcd4f07188 soc/amd/common/fsp: Fill in DIMM voltages * 8929659d93 soc/amd/common/acpi/lpc.asl: Report ESPI1 fixed resource * 3053cd2dad soc/amd/common/acpi/lpc.asl: Report fixed base addresses * 7e1aa974bf soc/mediatek/common: Refactor mtk_ddp_mode_set to support dual DSI and DSC for MIPI * 3aaeca8378 soc/mediatek/common: Refactor mtk_dsi_dphy_timing * aeee9450a2 mb/google/ocelot/var/matsu: Add fw_config definitions with UFSC * 67a7e06c38 drivers/tpm: Remove duplicated op * ac5c57d24a drivers/tpm/ppi: Fix generated ACPI * d922ad79c6 mb/google/fatcat/var/ruby: Add firmware configuration fields with UFSC * 980c269643 mb/google/ocelot/var/ojal: Enable Audio Codec and update FW config * 8e7975edfd mb/google/ocelot/var/ojal: enable CS42L43 driver options * 9a6d1d4d69 mb/ocelot/var/ocicat: Modify ocicat Kconfig for bring up * 94fe4c6926 mb/google/ocelot/var/kodkod: Add wake configuration to cnvi_bluetooth * e3588d82bc mb/google/ocelot/var/kodkod: Enable CNVi Wi-Fi and BT cores * 36edc2e371 soc/qualcomm/x1p42100: Add Dload mode detection and ramdump packing * 26a18c674d acpi: Clear whole FACS table before filling it * 5a6addca4b mb/google/fatcat/var/ruby: Change GPIO pins to fix audio function * e6a8143d8b drivers/intel/touch: Add support for new Intel touch I2C _DSD entries * 25c4501223 device/dram/ddr3: Fill in voltage fields for SMBIOS type 17 * 273a41c4d9 commonlib/memory_info: Introduce new fields to memory_info structure * abe1ac0744 mb/google/brya/var/uldrenite: Add memory MT62F1G32D2DS-031RF WT:C * 0599f3e1bd mb/google/bluey: Condition slow charging enablement on charger presence * 8b3ceacd93 ec/google: Check AC charger presence by reading host event register * 5b544c67eb mb/google/rauru: Add MIPI panel support with BOE NS130069-M00 * ed9239cd85 mb/google/nissa/var/gothrax: Add Samsung parts to RAM ID table * 445961c604 soc/qualcomm/common: Add support for loading ramdump image * 3c563669b5 soc/qualcomm/x1p42100: Add support for APDP image packing in CBFS * 1d70286d4e soc/qualcomm/common: Add support for loading APDP image * fc9f828ac0 mainboard/google/bluey: Select VBOOT_ALWAYS_ENABLE_DISPLAY * c77d256886 {mb, security}: Use EC_REBOOT_FLAG_IMMEDIATE for cold reboots * 1a0d123ec1 ec/google/chromeec: Update EC headers * 3bd554feb2 soc/mediatek/mt8196: Align the struct for storing DRAM calibration data * 33fc33c132 soc/amd/common/block/cpu/noncar: Add support for bootblock CRTM init * 8b97968e53 soc/amd/common/block/pci/amd_pci_mmconf.c: Support 64bit ECAM MMCONF * 7a98a62f7b drivers/intel/gma: Unify coding style * 23b00a06da drivers/intel/gma: Fix brightness handling with valid-cache logic * 4068ba39f8 soc/intel/common/block/rtc/rtc.c: Top Swap: add Slot B selection mechanism * a65b874472 mb/dell: Convert OptiPlex 3050 into variant * 2ce1068542 mb/google/ocelot/var/ojal: Decrease display count from 5 to 4 * b31e62ae5c mb/intel/ptlrvp: Add LPCAMM T3 RVP board support * 58cdf9e668 soc/intel/pantherlake: Add LPCAMM memory support * 67777b7671 soc/intel/common: Add LPCAMM memory topology support * bb18e0b91d mb/google/skyrim: Increase size of SMMSTORE to 512KB * dd1e54efc0 mb/google/zork: Increase size of SMMSTORE to 512KB * 60e375fae4 mb/google/guybrush: Increase size of SMMSTORE to 512KB * eb52862132 mb/google/brox/var/caboc: Update SSD port and FPMCU setting * 85101704ae mb/ocelot/var/ocicat: Create ocicat variant * 2975d7220a mb/google/ocelot/var/matsu: Update devicetree * 0e9d85425e mb/google/ocelot/var/matsu: Fix GPP_V3 internal pull-up configuration * 4f257a28f8 mb/google/ocelot: Add EC_GOOGLE_CHROMEEC_SKUID config * db2ac42405 soc/mediatek/common: Refactor DDP mode setting * d51f780515 mb/siemens/mc_rpl: Correct SMBIOS socket type to BGA1744 * 2f95552802 mb/siemens/mc_ehl: Move Kconfig switch to variants * 3c49c13995 util/ifdtool: fix typo PSL->MSL * a87e699f04 mb/lenovo/m900_tiny: Enable Vboot * afc191357f 3rdparty/intel-microcode: Update to upstream main * cbfa28b06e mb/google/fatcat/var/ruby: Modify power limit configuration * f13e800a71 mb/amd/crater/Kconfig: Use A/B recovery scheme for renoir * 416f67f670 vendorcode/amd/fsp/.../fsp_h_c99.h: Use fsp2_0 structs * b94a84a792 drivers/efi: Exclude verstage from EFI variable store files * bae5262c69 include/option: Add verstage stub for UEFI variable store backend * 2d78478345 drivers/intel/gma: Reapply cached brightness once BCLM is valid * 2ad08f9d72 drivers/intel/gma: Expose full brightness ladder * 2e96a71e6f drivers/intel/gma: Cache brightness level * 36632a08a8 soc/qualcomm/x1p42100: Reserve 33 MB DRAM memory for Display requirement * 5807b59fc5 mb/google/rauru: Report panel ID for sapphire * 49da58dccf drivers/mipi: Add support for BOE NS130069-M00 panel * e9ebcb2918 mb/{google,intel}: Fix MIPI camera VCM type and address configuration * 30b4383944 mb/{google,intel}: Set SSDB platform field for MIPI camera sensors * 4c025191c7 drivers/intel/mipi_camera: Remove disable_ssdb_defaults option * c75236d436 drivers/intel/mipi_camera: Set additional SSDB defaults * 866b79c9fe drivers/intel/mipi_camera: Always generate PLD for camera sensors * c6ed8c91fb drivers/intel/mipi_camera: Document more SSDB fields * 423fbcd06b drivers/intel/mipi_camera: Adopt SSDB sensor SKU bitfield * aa18a6fe8d drivers/intel/mipi_camera: Codify SSDB field enums * f8d12a0bdb drivers/intel/mipi_camera: Add SSDB platform subtype enum * 99cb6415ba drivers/intel/mipi_camera: Rename flash enum to match SSDB field * c91ea7c582 drivers/intel/mipi_camera: Flesh out SSDB platform enum * 0361e1a865 drivers/intel/mipi_camera: Verify SSDB struct size at build time * b5d68e41a2 drivers/intel/mipi_camera: Tidy SSDB comment wrapping * ab4c2fd0e8 drivers/intel/mipi_camera: Extract SSDB definitions into separate header * d09ea1c351 cpu/intel: Add SMBIOS Socket BGA1744 type * d97cb61b50 ec/google/chromeec: Add CFR option for RGB keyboard boot color * e695731399 ec/google/chromeec: Add RGB keyboard helper functions and enum * 4eb524ee9d spd/ddr4: Add three more parts * e4a809d441 spd/ddr4: Double packageBusWidth of dual die package parts to 16 * 8753155f71 mb/google/slippy/var/peppy: Add CFR menu option for touchpad type * 6f6a10df88 mb/google/slippy: Add CFR option menu support * e366e0ba7d mb/google/slippy/Makefile: Organize and group entries by stage * 6be83443e5 mb/google/auron/var/lulu: Add CFR option to enable/disable touchscreen * 88d3f563b3 mb/google/auron: Add CFR option menu support * 7ed515d1c3 mb/google/auron/Makefile: Organize and group entries by stage * e15895b5c4 mb/google/poppy/var/nautilus/acpi: Fix CI02 comment * 4dc03c54fc mb/google/poppy/var/nocturne: Hide FPR device in ACPI * e85a0b7ff1 mb/google/puff: Remove unsupported EC features * 3459502e0c mb/starlabs/starfighter: Enable pmc_shared_sram device * 9b0af48604 mb/starlabs/starbook/mtl: Update GPIO config * d3d4571411 soc/intel/common/block/graphics: Use Xeon W-11865MRE IGD PCI ID * 1cfe413f95 soc/intel/common/block/lpc: Support RM590E eSPI * c195859748 soc/amd: add ACPI code for I3C controller * 02342b31df soc/amd/*/memmap.c: Report FCH MMIO regions as reserved * 5078d32ccc mb/google/brya: Enable ACPI S3 sleep state support * eb504eb49a mb/samsung/lumpy: Fix HDA pin configuration issues * afd5e5d444 mb/samsung/lumpy: Convert HDA verbs to use AZALIA_PIN_DESC macros * 109672a9a9 drivers/intel/gma: Guard legacy brightness fallback * 908c2b54c6 mb/starlabs/starbook/mtl: Fix Card Reader USB Port * 796d3b37aa mb/google/fatcat/var/moonstone: Update fw_config definitions with UFSC * 2ce4e09469 drivers/intel/fsp2_0: Add typedef FSP_UPD_HEADER * 7afe1e9f9d mb/google/fatcat/var/lapis: Adjust touchpanel power on timing * 36f4341533 mb/starlabs/starfighter: Add Arrow Lake (285H) variant * 80cf2008a9 spd/lp5: Add SPD for MT62F1G32D2DS-031RF WT:C * f1d1c825dc mb/siemens/mc_rpl1: Enable IBECC * 866a0591f7 mb/siemens/mc_rpl1: Set coreboot ready LED * 801795d4dd mb/siemens/mc_ehl6: Alphabetize Kconfig options * 1a11dca12d mb/siemens/mc_ehl6: Send POST codes to NC FPGA via PCI * fceb033372 mb/siemens/mc_ehl6: Limit PCIe RP7 speed to Gen2 * 760c3f6abc mb/siemens/mc_ehl6: Activate SATA interface port 1 * 54f2652bde mb/siemens/mc_ehl6: Enable auto impedance calibration on GbE 0 * b6e7f3e005 mb/siemens/mc_ehl6: Change GbE LED settings * aad2b715ea mb/siemens/mc_ehl6: Remove PSE GbE 1 * e19f2b313e mb/siemens/mc_ehl6: Enable PCHHOT_N via GPIO * 43d5f70576 mb/siemens/mc_ehl6: Enable PTM for all enabled PCIe RPs * 864e3ca661 mb/siemens/mc_ehl6: Adjust I2C setup * 31f44f5521 mipi: Add DSC configuration and rate control parameters to panel header * 743e31939c drivers/intel/fsp2_0/.../fsp/upd.h: Fix excess endif * 2aadfc2b5e soc/amd/common/block/acpi: Add ACPI HEST table * cc542c15f4 include/acpi: Move Error definitions/declarations into acpi_apei.h * 2462e3a027 soc/mediatek/mt8188: Adjust memlayout for bootblock * 804aab3abb mb/google/fatcat/var/ruby: Modify usb3 port setting * fecf05c4f2 mb/google/trulo/var/kaladin: Mute speaker amp to prevent pop noise on reboot * f35cb39de5 soc/amd/cezanne: Increase APOB DRAM size for Renoir * 384e6e1c37 soc/amd/cezanne: Remove set_resets_to_cold * 97291b5838 soc/amd/cezanne: Optionally propagate UART0 through ACPI * 149d11d1d8 soc/amd/cezanne/Kconfig: Select Kconfig to program the PSP_ADDR MSR * 520bc70b57 mb/amd/crater: Configure UART1 GPIOs * 0ed1529ce3 src/vc/amd/fsp: fix type 17 DMI info * e8599956dc mb/amd/crater: Make NVMe reset GPIO configurable * 67bf203e52 mb/google/nissa/var/guren: Add missing settings for WWAN * 3dabe4f857 mb/google/brox/var/caboc: Increase I2C0 touchpad tHD to 0.53 us * 12e763eece device/pci_ids: Add DIDs for TGL-H (GT1 and RM590E) * 01540f036e mb/google/fatcat/var/ruby: Use spd-11 for MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV * 14e96b4ef1 mb/google/brox/caboc: Mute speaker amp to prevent pop noise on reboot * 567186a000 mb/google/bluey: Add support for off-mode charging * 27fcb8617d commonlib: Add CBMEM ID to store boot mode * d6132c4c03 mb/google/bluey: Use SOC PMIC API to detect off-mode charging event * 201ebd48ee soc/qc/x1p42100: Add APIs to read PON reason from PMIC * 293f3a7f5c soc/qc/spmi: Add API to read byte array * 9f675eb96b soc/qc/common: Update SPMI_ADDR macro for better type safety * cb1045a8b8 soc/intel/pantherlake: Update GT domain TDC value for PTL_TDC_1 SKU * b0ee0c4620 soc/intel/pantherlake: Fix IA domain TDC value for PTL_TDC_2 SKU * 6dbcf903a5 soc/intel/pantherlake: Add ICC Max and TDC settings for SKU_7 * 2148143ae9 soc/intel/pantherlake: Separate TDC configuration for different TDPs * c7273c8ddc mb/google/fatcat/var/ruby: Add proto touch panel address * 8575232317 mb/google/ruby: Migrate to UFSC * 47101fc224 soc/amd/cezanne/Kconfig: Make AMDFW_CONFIG_FILE configurable * c9f124a8fb mb/amd/crater/ec: Make macro ENABLE_M2_SSD1 a Kconfig option * 430e34cd0f mb/amd/crater: Move gpio configuration to early_gpio * 14b5c004f5 mb/amd/crater/ec: Create function to get board revision * bd858faee8 mb/amd/crater: Add XGBE support * f61553c9fa vc/amd/fsp/cezanne: Add Renoir FSP * 87f8d15c87 ec/google/chromeec/cfr: Fix CFR callback signatures * 7fb0f14ebe libpayload: arm64: Fix asynchronous exception routing in payload * b584967d04 mb/google/ocelot: Add wake configuration to cnvi_bluetooth * fc88b62174 mb/siemens/mc_ehl6: Enable PCIe root ports and clocks * 5a4c749520 mb/siemens/mc_ehl6: Add new board variant based on mc_ehl2 * f5f304a5f3 mb/google/skywalker: Disable CHROMEOS_USE_EC_WATCHDOG_FLAG * e4b0410946 soc/mediatek/mt8189: Enable MEDIATEK_WDT_RESET_BY_SW * 1ae0cebff3 soc/mediatek: Add Kconfig option MEDIATEK_WDT_RESET_BY_SW * 7d3bf767cc soc/mediatek/mt8189: Move WATCHDOG_TOMBSTONE from SRAM to SRAM_L2C * a64dd410d8 mb/google/fatcat/var/ruby: Update EN_SPK_PA GPIO pin configuration * 2f9b4ad6a5 soc/qualcomm/x1p42100: Add DFSR table configuration support * 51e99de558 soc/intel/common/block/rtc/rtc.c: control Top Swap via CMOS option * 56be23114e mb/google/rauru: Use chromeos-legacy.fmd for Hylia and Navi * 10802bac16 spd/lp5: Modify SPD for MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV * e5d10e5d23 mb/lenovo/t480: Fix headphone jack * 40b2a2b03c soc/mediatek/mt8196/booker: Refactor CMO property clearing with loop * 1b0f9c5458 mb/google/nissa/var/telith: Add parade touchscreen support * ddb3f0b17f drivers/hwid_dmi: Populate SMBIOS product name from CBFS hwid file * 7a1e63308a acpigen_ps2_keybd: map insert * 607740999d acpigen_ps2_keybd: map capslock * a7efa40e39 acpigen_ps2_keybd: map KEY_HOMEPAGE to 0xaa scancode and TK_HOME * fd603e5102 libpayload: Add CBMEM_ID_MEMINFO to sysinfo * bae3e02662 include: commonlib: Move memory_info and dimm_info to commonlib * d03799ec3c soc/mediatek/mt8196: Configure registers and parameters required for MTE * 7521f3ea83 soc/qualcomm/x1p42100: Define pre and post-RAM DMA coherent regions * d277b35307 soc/qualcomm/x1p42100: Relocate ddr_information and watchdog tombstone * 958099b114 soc/qualcomm: Map the post-RAM DMA coherent buffer * 931fa9c01d memlayout: Introduce PRERAM and POSTRAM DMA coherent regions * af9d809823 soc/qualcomm/x1p42100: Move coreboot stack to SSRAM * fec1032ee8 arch/arm64: Add timestamps for Secure OS (BL32) loading * d0177bd102 soc/qualcomm: Add QCLib execution timestamps * 0145ebe847 commonlib: Add timestamps for Qualcomm QCLib and ARM TFA * cf2978f4b6 drivers/vpd: Search VPD info at 0x0 first * a56a97d167 mb/starlabs/common/cfr: Adjust help text for S0IX * 541fd14fd9 mb/google/nissa/var/uldren: Increase Touch IC enable delay time * 0c18e7680a mb/google/fatcat/var/ruby: Remove GPP_D16 and GPP_D17 in fw_config.c * 237944186e mb/google/nissa/pujjolo: update verb table * cae53bea52 ec/google/chromeec: Add CFR options for keyboard backlight and fan control * 1ca1dc6c31 ec/google/chromeec: Add ability to enable auto fan control via setup option * 450389be05 ec/google/chromeec: Add fan presence helper function * 9d355a39aa mb/amd/crater/ec.c: Enable power/reset for PCIe lanes * 141fd11d79 mb/amd/crater: Rename ETH_AIC_SLOT_ONLY -> PCIE_DT_SLOT * 1e28ff6955 src/mb/amd/crater/port_descriptors_renoir.c: Prettify code * a48fd9ed7f soc/amd/cezanne: Add SOC_AMD_RENOIR as a Cezanne variant * 760e19e18f mb/lenovo/sklkbl: Use spd_tools infrastructure for SPD binaries * 8a83b86254 spd/ddr4: add parts * 0ef4bd807c mb/google/ocelot/var/ocelot: Update DDR5 memory configs * 7b11254d58 mb/google/ocelot/var/kodkod: Add overridetree * aa1d44b644 mb/google/ocelot/var/kodkod: Update gpio settings * a363007c3b ec/dell/mec5035: Route power button event to host * 18dbeca5f4 util/autoport/azalia.go: Select CONFIG_AZALIA_USE_LEGACY_VERB_TABLE * e9c47bf99e drivers/intel/fsp2_0: Add 1-bpp monochrome option for VGA mode 12 * f643141728 mb/google/fatcat: Option to enable monochrome VGA mode 12 * e05492cfb4 soc/intel/pantherlake/romstage: Configure VGA mode 12 monochrome buffer * d3760cdfdf mb/google/bluey: Configure QUP0 SE5 as I2C * abc87d533d mb/google/bluey: Introduce config to specify absence of USB-A port * 872e06d60c mb/samsung/stumpy: inline fan thresholds and drop GNVS programming * 8401bbd2ff mb/google/fatcat/var/ruby: Change touch panel address * a4242e5c38 ec/starlabs/merlin: Fix get_ec_value_from_option() value validation * 567470cbb3 payloads/edk2: Add iPXE EFI support for EDK2 payload * f40de4e162 payloads/ipxe: Default enable serial output only if CONSOLE_SERIAL * 962edb7e6d payloads/ipxe: Guard PXE_ROM_ID for non-EFI builds * a907c6fb8d payloads/ipxe: Default to building from master branch * 4081793ff2 payloads/external/edk2: Replace dependencies on EDK2_REPO_MRCHROMEBOX * 10d606bfca soc/intel/common/acpi: Add P2SB write functions * 7436c59875 util/amdtool: Add support for Phoenix AM5 CPUs * 8f3626c4b5 util/amdtool: Add utility to dump useful information on AMD CPUs * 3cf976e51a soc/mediatek/mt8196: Add dual display pipe path * 14595d64de lib/edid_fill_fb: Add dual pipe flag to lb_framebuffer_flags * 486b1b51af mb/google/bluey: Cache low battery mode check * 33418b7e68 soc/qc/x1p42100: Disable compression for peripheral firmware binaries * 5bfc2d23bb soc/qc/x1p42100:: Select Secure OS options in SoC Kconfig * f5f943c1c3 bluey/kconfig: Consolidate SPI flash driver selection * ee59936e83 commonlib/device_tree: Add an API to check if a DT is an overlay * 0416ac9829 mb/google/var/fatcat/lapis: Modify type-A USB3 port0/1 tx_de_emp * dfe553aebb util/intelvbttool/Makefile: Add install target * 493e3d182e payloads/external/iPXE: Allow building EFI target * 62fc93de90 soc/qualcomm/x1p42100: Add NVMe Power Loss Notification GPIO configuration * 2b7b89ae31 soc/qualcomm/x1p42100: Update PCIE PHY init sequence * 91594f4894 drivers/option/cfr.c: Replace memcpy() to avoid uninitialized object * 04ea4724e2 Makefile.mk: separate bootblocks into BOOTBLOCK and TOPSWAP * f164feba3e ifittool: allow adding files from a separate region * 91073f37d7 mb/google/brya: Increase RW_SECTION_* by 256KB for 16MiB boards * a43498e193 util/inteltool: Enable dumping GPIOs from Tiger Lake IoT PCH * 04778ddd38 drivers/option/cfr: Remove old sm_object from constructor * b535db8f1e soc/intel/cmn/usb: Add helper macro for USB 3.0 port TX configuration * c197643d44 drivers/intel/gma/acpi: Add power management methods for GFX0 * 773997c92d drivers/intel/touch: Avoid returning undefined pointer * 9dc35142ac soc/amd/stoneyridge: Generate SATA ACPI registers at runtime * d62653749c payloads/libpayload: Support legacy LZ4 compression format * 29faf77d4a mb/siemens/mc_rpl1: Limit CPU RP1 to PCIe Gen2 speed * fad0908c5b soc/intel/alderlake: Make CPU RP PCIe speed configurable * 04d5201426 treewide: Fix include guards * 971f10d1d7 mb/google/var/fatcat/lapis: set custom SVID/SSID to load fw for CS35L56 * ace2e540d0 soc/intel/pantherlake: Update CONSOLE_UART_BASE_ADDRESS Kconfig value * a65d9fe589 mb/google/fatcat: Remove FSP_UGOP_EARLY_SIGN_OF_LIFE from Lapis * 729918628d 3rdparty/blobs: Update to upstream main * d4bee96484 mb/lenovo/sklkbl: refactor memory_init_params to use gpio_base2_value() * 2a9deabc35 commonlib/coreboot_tables.h: Fix lb_smmstorev2 alignment * 0ba4505024 payloads/external/edk2/Makefile: Configure AP wakeup in UEFI payload * 87c3373925 mb/google/fatcat: Add FW_CONFIG Support for TAS2563 * e08a35f806 drivers/sof: Add support for tas2563 speaker topology * a3ea128ecf drivers/i2c/tas2563: Add driver for generating device in SSDT * 240e17025c src/soc/intel/ptl: Add LPSS UART DMA control * afa6c31ef5 soc/intel/alderlake/romstage/fsp_params.c: Refactor `pcie_rp_init()` * ec5b5386d4 soc/intel/mtl/romstage/fsp_params.c: Refactor `pcie_rp_init()` * 4c5c62bc8d mb/google/fatcat/var/ruby: Modify gpio pin for enabling audio function * 2804a0d771 mb/google/fatcat/var/lapis: Update fw_config definitions with UFSC * 0e1742a7e2 mb/google/bluey: Control slow battery charging via boot mode * 113cef70fd soc/intel: Move USB port macros (2.0/3.0/TCSS) to IA common header * 3c69295ce4 mb/google/fatcat/var/ruby: Add new supported memory part * d18cc50e6a soc/intel/xeon_sp: Use common smm_relocate * d0c936eea1 mb/google/nissa/var/guren: Tune SX9324 register for 5G LTE module * 8851b5b0e7 soc/intel/pantherlake: Program HDA SVID/SSID * c917ecf21e soc/intel/{adl,mtl}: Fix CLKSRC handling for compliance mode * 312d455a93 soc/intel/{adl,mtl}/romstage/fsp_params.c: Fix printf specifier * 786ac14d48 drivers/option/cfr: Add optional override table for default values * ea84a29a27 mb/google/trulo/var/pujjoquince: Enable Bayhub LV2 driver * 84e000b88e libpayload: arm64: Fix alignment for exception_state * 9210f2fd1c mb/google/fatcat/var/lapis: add ILITEK touchscreen support * b933a554ba mb/google/var/fatcat/lapis: Modify fw_config for audio and touch * b3b7b7a027 mb/emulation/qemu-q35/Makefile.mk: Use all-y for memmap.c * bb3e59051a mb/google/brya: Check power state before process _ON method for BT * 0f7c54d7d1 mb/google/fatcat/var/felino: Disable card reader in coreboot * 7946d2d65d mb/google/fatcat/var/felino: Add reset_gpio for SSD RTD3 configuration * 8e2567c7a9 mb/google/fatcat/var/lapis: Adjust touchpad I2C frequency * f8da2bf9b2 mb/google/fatcat/var/ruby: Modify camera enable gpio pin. * 45163509cf util/cbfstool/cbfs-payload-linux.c: Remove TODO * bdcd65bd7f ec/starlabs/merlin: Add battery capacity offsets * 224ddb85e3 ec/starlabs/merlin: Choose a better default for GPE SCI * 696344ac01 ec/starlabs/merlin: Optimise Kconfig defaults * 649a6a591b ec/starlabs/merlin: Correct Kconfig dependancies * 0d35c3fcc3 mb/starlabs/starbook: Fix inclusion of CPU RP ASPM option * 87475ef37f mb/starlabs/common: Move power profile enum to common code * 98e0ff1e4b mb/starlabs/*: Move DMIC disabling code to common dir * 082ad480d9 mb/starlabs/*: Separate WiFi and Bluetooth controls * abf630c96b mb/starlabs/byte_adl: Add wireless CFR object * a58d99575e mb/starlabs/*: Move CFR object defs to common directory * 74dcb4c679 mb/starlabs/common: Adjust the includes inline with coreboot * 6b30e1f46b mb/google/dedede/var/pirika: Add support memory for CXMT CXDB5CBAM-MA-B * d4e8af407c spd/lp4x: Add CXMT CXDB5CBAM-MA-B memory * 8d7183a904 ec/google/chromeec: Add option to set keyboard backlight level at boot * 973d0faf65 util/amdfwtool: Move needs_ish and combo_new_rab to data_parse.c * 8449a15aed soc/qualcomm/x1p42100: Reduce USB OTG state enable timeout to 20ms * f4af55a008 spd/lp5: Add SPD for MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV * 9bea3130b5 mb/google/skywalker: Add AW88081 support for beep sound * d8bcf242c6 Revert "commonlib/endian: Silence GCC -Warray-bounds false positives" * 66039a61f1 Revert "commonlib/endian: Restore -Warray-bounds at the end of file" * c27c9db51b mb/samsung/stumpy: Fix thermal configuration issues * 288889cd98 mb/google/jecht: Fix thermal configuration issues * 9fa2d55987 mb/google/beltino: Fix thermal configuration issues * 76a48b5158 mb/google/beltino: Remove unused GNVS fan configuration * 8cc8f219bf Documentation/drivers: Add ACPI five-level fan control documentation * 47c4da36c4 util/amdfwtool/data_parse.c: Remove duplicate MP2_CFG_FILE * fa23504c59 mb/siemens/mc_rpl: Alphabetize Kconfig options * 8411fef90f mb/siemens/mc_rpl1: Switch from LPSS UART to legacy 8250 I/O UART * 534fceb36a mb/siemens/mc_rpl1: Set PCI bridge function for NC_FPGA * 8ce9255f82 mb/samsung/stumpy: Fix ACPI fan control FNP4 power resource * f12f292d91 mb/google/intel/*: Fix ACPI fan control FNP4 power resource * b9b95c917a mb/google/guado: Fix ACPI fan control FNP4 power resource * 8a518b2134 mb/google/beltino: Fix ACPI fan control FNP4 power resource * 6d751ef987 payloads/edk2: Drop EDK2_PCO_MMIO_EMMC Kconfig option * 4423a0b390 payloads/edk2: Drop EDK2_UFS_ENABLE Kconfig option * a86a5ebf7c payloads/edk2: Update default MrChromebox branch from 2502 to 2508 * 40a8466655 mb/google/fatcat: Add option to enable VGA mode 12 * 824992ddef soc/intel/pantherlake/romstage: Configure VGA mode 12 planar buffer * 74113f5d5e drivers/intel/fsp2_0: Add options to config VGA mode 12 * 75318743c3 commonlib: Add pKVM DRNG related timestamps * 2646eeffb2 mb/google/skywalker: Create variant Dooku * 1b2675e4f2 soc/mediatek/mt8189: Require libbl31.a to exist * 9c0a914192 libpayload: Fix printf edge cases for precision * ebc2030ff7 soc/intel/pantherlake: Enable HW managed microphone privacy * 4d9dacae16 mb/google/fatcat/var/ruby: Modify touchpad device setting to enable function * 2821e8e2ae soc/intel/ptl: Remove redundant HAVE_BMP_LOGO_COMPRESS_LZMA Kconfig * eadf2ee4a3 ec/starlabs/merlin/cfr: Replace integer literals with named constants * 2bbc0f1ad3 mb/starlabs/starbook/{kbl,cml,tgl}: Control USB Bluetooth with wireless * 2c9596555b mb/google/skyrim: Use edge (vs level) triggering for PS2K * 0c3f304d5a mb/starlabs/byte_adl: Enable Wake On Lan * ca5b51ef9c mb/google/bluey: Select QTEE firmware dependent Kconfig * fe7b75d792 mb/google/fatcat/var/moonstone: Add fw_config touchscreen setting * cfdaff3f70 commonlib/endian: Restore -Warray-bounds at the end of file * 32ec29a51e mb/google/fatcat/var/kinmen: Disable RT721 clock stop support * 4b50bc9e5f payloads/external/U-Boot/Makefile: Add custom repo and tag * 3d41ac370d payloads/external/U-Boot/Makefile: Remove conditional * c3b5c8723e ec/google/chromeec: Add function to determine keyboard backlight presence * 7afd731849 ec/google/chromeec/acpi: Fix long battery string reporting for Windows * bc475414c7 MAINTAINERS: Add Chen-Tsung Hsieh for MediaTek platforms * 65dc0bdd7e mainboard/fatcat/lapis: Override PMC GPE configuration * 4ea33e5ffa mb/google/fatcat/var/lapis: Enable THC HID over I2C mode * 111da2557a mb/google/fatcat: Preserve VGPIO GPE for THC wake on touch * e167e56883 mb/google/nissa/var/yavilla: Add stop pin for G2 touchscreen * 1fa24898e2 soc/intel/common/block/pcie: Move speed helper to pcie_helpers.c * 66f40a86de ec/starlabs/merlin: Move version offsets to ECDEFs * 82367b8205 mb/google/ocelot/var/matsu: Add overridetree * 05c0e16593 mb/google/ocelot/var/matsu: Update GPIO table * 98c7be30ad mb/google/fatcat/var/moonstone: Support new schematic changes * 5eafe672e3 vc/intel/fsp: Update WCL FSP headers to 3344_03 * 641eeca835 lib/vga_gfx: Fix left-up and right-up orientations * a4f067c058 Makefile.mk: Align FMAP COREBOOT region to 4k boundary * 410506b47c Makefile.mk: Print all FMAP region sizes in hexadecimal format * c189604f43 mb/goog/ocelot/var/ocelot: Enable rp5 if PCIE WiFi detected * 4a806a6865 ec/starlabs/merlin: Only show EC FW options for ITE EC * 04d9a0d0f0 ec/starlabs/merlin/Kconfig: Fix typo in description/help text * 1eda98a16e mb/siemens/mc_rpl1: Document CLKSRC 2 usage for PCIe RP5 * 1815a204b4 src/mainboard/lenovo: Add smbios_slot_desc, fix register types * da204a92c1 vc/intel/fsp/wildcatlake: Expose PchHdaMicPrivacyMode * 105598545e soc/intel/pantherlake: Update thermal design current parameters * a5b51ab285 mb/google/rex/var/kanix: Add H58G66CK8BX147 to RAM ID table * d7f427a7d2 util/xcompile: Fix compiler detection on newer Linux distros * 82d90b1f21 Revert "mb/starlabs/*/rpl: Re-enable GpioOverride" * 784d8f25f9 mb/google/fatcat/var/ruby: Enable panel touch function * 56a8c40efa mb/starlabs/starlite_adl: Add missing ACPI entry for USB card reader * 4047a44b68 sio/nuvoton/common/nuvoton.h: Add common Nuvoton SIO LDNs * 3a1d6d5ded mb/google/brox/var/caboc: Adjust WWAN power off sequence * b42f74122c Documentation/mb/lenovo: Adjust docs for Thinkpad T470s/T580 * 70e79f43b1 Haswell NRI: Print and fill in memory-related info * 1730d05ec3 nb/intel/haswell: Factor out `report_memory_config()` * 3bbfbd37e1 nb/intel/haswell: Factor out `setup_sdram_meminfo()` * 3ffb01e9cb mb/siemens/mc_rpl1: Disable I2C1 and enable I2C6 * 4563db2807 mb/google/nissa/var/riven: Add H58G66CK8BX147 to RAM ID table * a748e8b82b mb/google/fatcat/var/ruby: Enable touchpad function using I2C interface * a92a2ee5d6 mb/starlabs/byte_adl: Expose fan control option in CFR * bbb895436f mb/nissa/var/pujjoga: Add single ram configuration * e2cf7f7dc7 soc/mediatek/common: Fix MMU assertion for framebuffer region * a5ddfa963f mb/starlabs/starlite_adl: Increase ME region size to match IFD * 7484a887b8 mb/google/ocelot: Fix EC sync IRQ configuration for board variants * b1ed60b910 mb/google/fatcat/var/ruby: Disable FSP_UGOP_EARLY_SIGN_OF_LIFE temporarily * fea1b2abbe mb/google/nissa/var/pujjocento: Adjust touch panel timing for stability * 8f1c54685a drivers/mipi: Fix pixel clock and enable C-PHY for TM_TL121BVMS07_00C * 979fdee1d9 soc/mediatek/mt8189: Support MIPI C-PHY interface * 44635f328c soc/mediatek/common: Add C-PHY support for MIPI DSI * c63e901b99 mipi: Add panel flags to support C-PHY interface * 385ae6669b mb/gigabyte/ga-h77m-d3h/devicetree.cb: Re-enable IGD and PCIe VGA * 2c6cf2c2a8 include/cper.h: Update CPER structures with __packed attribute * d97644dd3f mb/asrock: Add Z77 Extreme4 * a73db6d451 mb/intel/ptlrvp: Add fw_config support for SPD selection * 3ef1cf9f84 soc/amd/turin_poc: Add Turin SoC structure as a copy of genoa_poc * 668d643e5c mb/lenovo/sklkbl_thinkpad: Add Lenovo Thinkpad T470s as a variant * 8a6f9bf731 ec/google/chromeec: Update EC headers * 745f1312aa include/cper.h: Update comments to UEFI spec version 2.10 * aab8ad98b6 mb/google/ocelot: Create kodkod variant * 2279ba80e1 .gitignore: Add .clangd as a "Development friendly file" * cd4af952e7 mb/google/ocelot/var/ocelot: Update DDR5 memory configs * 1af54d9784 drivers/intel/touch: Change I2C speed type to i2c_speed enum * 84a348f4bf ec/starlabs/merlin: Remove the fast charge option * 1699d455e7 vc/intel/fsp: Update PTL FSP headers to FSP 3373_03 * b87a9795de tree: Use boolean for s3resume * ec1068883f mb/google/nissa/var/guren: Add initial WWAN related settings * 752d49a4ff mb/google/fatcat/var/moonstone: Disable RT721 clock stop support * 155041ad4c soc/qualcomm/x1p42100: Add EUSB2 HS repeater support for USB Type-C * 6e45016610 intel soc,southbridge: Add Kconfig to set TSBS in IFD during build * f4271cad0a ifdtool: Add set top swap size PCH strap subcommand * ab4b82fb3c util/lint: Add a license check exception for .gitkeep files * 03524780ff soc/qualcomm/x1p42100: Support loading QTEE FW config files * 50adb3f23c mb/google/bluey: Increase FW_MAIN_A/B slot size to 4.5MB * bbdf2eab6a soc/mediatek: Rename DSI common files for improved readability * 8a2c04e04d mb/starlabs/*/rpl: Re-enable GpioOverride * 9ff9f2904b mb/google/bluey/var/quartz: Enable all spi flash drivers * f6743fba29 mb/google/fatcat/var/moonstone: Enable Intel DPTF support * fc736de10e ec/starlabs/merlin: Remove the EC_STARLABS_NEED_ITE_BIN option * 3dee4cd0c0 soc/intel/pantherlake: Correct Touch Controller Speed Configuration * 7376761bdf mb/nissa/var/pujjoquince: Modify fingerprint configuration * 6ffbc9a929 soc/mediatek: Move mtk_dsi_reset() to mtk_dsi_common.c for reuse * 668ea97075 commonlib/endian: Silence GCC -Warray-bounds false positives * 4a3cc37cbd crossgcc: Upgrade binutils from version 2.44 to 2.45 * 35d4b3f2f4 arch/arm64: Support to load QTEE firmware in x1P42100 * e38056bef8 amdfwtool: Move ISH before PSP L2 * c1c83df3b5 mb/emulation/qemu-riscv: Enable ACPI by default * 5daf497df4 arch/riscv: Add ACPI support for riscv * 5c85793d26 mb/google/fatcat/var/lapis: Add cs42l43 and cs35l56 Soundwire links * 14fc6c3469 crossgcc: Drop nds32le-elf toolchain from default builds * fce489e9e5 drivers/intel/touch: Check SoC I2C speed function exists before calling * 249883d5bf mb/starlabs/starlite_adl: Squash SB and non-SB board variants * 80861a9f69 mb/starlabs/starlite_adl: Add CFR option for USB card reader * 5c1a9fa809 mb/google/fatcat: Create ruby variant * 43df7b14ae mb/var/uldrenite: Fix ISH UART port and VR configuration mismatch * 1a0b7195f9 mb/google/nissa/var/glassway: Removed the flag of DB_1A for pmc_mux * 9f0f373ff9 mainboard/amd/crater: Select the option to keep the AMD ACP active in S3 * f04c45acee mb/google/fatcat/var/lapis: enable CS35L56_FAMILY and CS42L43 driver options * 78e7dcb152 drivers/soundwire/cs42l43: Add optional properties for controlling jack and accessory detect * f1c973bbff drivers/soundwire/cs42l43: Support Cirrus Logic CS42L43 codec * 35970abcdf mb/google/nissa/var/dirks: Add H58G56CK8BX146 to RAM ID table * 402ac7cd81 crossgcc: Upgrade acpica from 20250404 to 20250807 * 3aa312e4c9 soc/mediatek/mt8189: Add DSI path support and update mutex * 6b93516e02 soc/intel/baytrail/acpi: Add missing MMIO window below 4GB * 321d8c5b21 soc/intel/braswell/acpi: Add missing MMIO window below 4GB * 74d7a21382 nb/intel/haswell/acpi: Add missing MMIO window below 4GB * 07f25bef86 mb/google/ocelot/var/ocelot: fix gpio settings * 10b0697dc3 soc/intel/pantherlake: Update power limits and voltage regulator parameters * 163e6a502c mb/starlabs/common: Deduplicate Pin Mix * 7622a57771 mb/starlabs/common: Move the SMBIOS code to common directory * e7dd184e5f Makefile.mk: Add support for mainboard vendor common code * dd3d7dcdfa mb/purism/librem_skl: Add CFR option menu support * 0d50fdf035 mb/purism/librem_l1um_v2: Add CFR option menu support * e9a01dea32 mb/purism/librem_jsl: Add CFR option menu support * 08efea5141 mb/purism/librem_cnl: Add CFR option menu support * 1d02f139d3 mb/google/fatcat: Add wake configuration to cnvi_bluetooth * cf97e1bc25 mb/intel/ptlrvp: Add power meter acpi changes * 7e3883633a mb/google/brox/var/jubilant: Apply fw_config to enable/disable I2C1 * 114d24cd7a lib: Generalize BMP_LOGO help text * e468e32dfb mb/google/*: Update Kconfig.name with actual device names * 85d7a1c85f drivers/ipmi: add Block Transfer (BT) interface * fe26234cf2 mb/google/trulo/var/uldrenite: Update DPTF parameters * 660f71e704 mb/google/trulo/var/uldrenite: Set GPP_E16 to NC for non-WWAN SKU * 3747b47df1 mb/lenovo/sklkbl_thinkpad: Add Lenovo Thinkpad T580 as a variant * d23eaa356f util/lint: maintainers-syntax: Add a check to ensure paths exist * 079c9c47aa soc/amd/cezanne: Add config option to keep ACP running in ACPI S3 state * f665e189da mb/starlabs/{starbook/mtl,byte_adl}: Select USB4_PCIE_RESOURCES * a7a49e5f74 mb/starlabs/starfighter: Correct reference for second TBT port * f22bcc1d42 mb/starlabs/starbook/rpl: Disconnect unused GPIOs * a8c70f7578 mb/starlabs/starbook/rpl: Reconfigure TBT GPIOs * 83aa4417cb mb/starlabs/starbook/rpl: Tidy up GPIO config straps * 7ad632cbc7 mb/starlabs/starbook/adl: Disconnect unused GPIOs * d7627a39e8 mb/starlabs/starbook/adl: Tidy up GPIO config straps * 711d49d4ec mb/starlabs/starbook/adl: Configure additional SSD GPIOs * 90d87c5941 mb/starlabs/starbook/*: Remove comments for unused GPIOs * f6b5e26fe7 soc/mediatek/mt8196: Add 24MB framebuffer region * 815f3f7df2 mb/google/rauru: Increase RW firmware sections size to 1756KB * 193420fe0b soc/mediatek/common: Add bootsplash support * bdd4561536 soc/mediatek/mt8196: Add mtk_ddp_ovlsys_start for rendering framebuffer * 0ff213d711 soc/mediatek/common: Conditionally set up framebuffer * 5271ac7ac5 soc/qualcomm/x1p42100: Reserve DDR carveout region * 19feafc018 drivers/intel/fsp2_0/ppi/mp_service_ppi: Support CPU_V2_EXTENDED_TOPOLOGY * 16feb1bb28 mb/google/brya/var/nissa: Add missing device type to gfx device * f4ecb69314 util/inteltool: Add Twin Lake UHD Graphics PCI IDs * ed736a47d8 mb/starlabs/byte_adl: Configure additional SSD GPIOs * 38525716d8 mb/starlabs/starbook/adl: Re-order the config strap GPIOs * 2c465c0e21 mb/starlabs/starbook/adl: Re-order GPIOs to match other boards * 115a6ce36a mb/starlabs/starbook/adl: Correct clock request number in comment * 1b5aaaefd9 soc/intel/meteorlake: Fix IGD IRQ * 06de11693f mb/starlabs/starfighter: Fix Thunderbolt disabling code * 5e36d9ba04 mb/starlabs/starbook/mtl: Update the VBT from 256 to 261 * fba8c14c27 mb/google/brya: add cnvi BT recovery mechanism * 1fb4a7409b soc/intel/pantherlake: Add VR power state current thresholds * 59ede353c5 soc/intel/pantherlake: Add Thermal Design Current (TDC) configuration * c54658d200 soc/intel/pantherlake: Add ICC Max configuration support * 0d1545ffac soc/intel/pantherlake: Add hysteresis window UPDs support * 8f24546fc4 vc/intel/fsp/fsp2_0/wildcatlake: Expose Thermal current thresholds and mode * 04affc3354 mb/google/ocelot: Update gpio's for ALC721 sndw * 3ac1a2b124 MAINTAINERS: Drop non-existant TPM files from VBOOT * af8b15ae04 Revert "libpayload: Define UCHAR_MAX/CHAR_MIN/CHAR_MAX" * 5e64ae2554 mb/starlabs/starbook/mtl: Enable PCH Energy * 375847acfe soc/intel/meteorlake: Configure PmcPchLpmS0ixSubStateEnableMask * db0faffdb8 mb/starlabs/*: Add comment about not configuring eSPI GPIOs * 990ad929a0 mb/starlabs/starbook/tgl: Don't configure eSPI GPIOs * 7ebcd6763f soc/qualcomm/x1p42100: Handle Type-C polarity for USB4/DP PHY init * f1708cf21a drivers/intel/touch: Enhance Intel touch driver for new devices * 55bf4ea07e cpu/x86/topology: Add tile and die ID CPU topology fields * 0c97aed8ac mb/google/fatcat/var/lapis: Modify touchpad and touchpanel configuration * 9e4a0a6026 mb/starlabs/starbook/mtl: Don't configure eSPI GPIOs * 3e0457e087 security/vboot/Makefile.mk: Fix building vboot lib with OpenSIL * 60ef877d93 mb/google/skywalker: Modify the RST pin naming * d5a8cec748 soc/intel/meteorlake: Rely on FSP_DIMM_INFO * e168a516e4 soc/intel/pantherlake: Rely on FSP_DIMM_INFO * 23419df34c drivers/intel/fsp2_0: Implement API to retrieve DIMM info * 1f328351e6 mb/starlabs/*: Select SPD_READ_BY_WORD * 88439b4cd3 mb/starlabs/starbook/mtl: Set the VPU default to disabled * 8ffa58723a soc/qualcomm/x1p42100: Add USB Type-C support * 45cedbb992 soc/qualcomm/x1p42100: Add HS/SS PHY support for USB Type-C ports * b18dfde22a soc/qualcomm/x1p42100: Add Clock support for USB Type-C ports * c7e4ef822d mb/starlabs/{starbook,starfighter}: Remove DRIVER_TPM_SPI_CHIP * 0c73e45493 ec/starlabs/merlin: Add disabled option for lid switch * ac7bb7694d mb/starlabs/starbook/mtl: Configure eSPI GPIO Mux * b37821ac25 mb/starlabs/*: Unify settings across device VBTs * ac8765c88a mb/starlabs/*: Correct USB Type-C Port Configuration * f7512c8647 mb/starlabs/starbook/{adl,rpl}: Remove USB OverCurrent Configuration * bf67771656 mb/google/fatcat/var/lapis: Update gpio GPP_E07 configuration * ff5daa0581 MAINTAINERS: Remove '/' from the beginning of paths * 6bfa257eef MAINTAINERS: Correct the path of cbmem_id.h * d7ae81132b MAINTAINERS: Correct asus/p8z77-series to asus/p8x7x-series * ef8eb79636 MAINTAINERS: Rename util/ipqheader to util/qualcomm * 0965bb9f68 MAINTAINERS: Remove non-existant mainboards * f5d1505c6b mb/google/fatcat/var/moonstone: Add Elan touchpad support * 24bfeb154e mb/google/fatcat/var/moonstone: Add focaltech touchscreen support * 1580346fa7 mb/google/fatcat/var/moonstone: correct the Kconfig settting * 150647a2fb ec/google/chromeec: Fix ACPI _CRS method generation for LPC memory range * ffa262db59 Documentation/FIT: reference archived copy of Intel TXT lab handout * f47e6c3905 MAINTAINERS: Fix typo "copperlake_sp" to "cooperlake_sp" * 1af0497c12 mb/google/dedede: Fix MAINBOARD_FAMILY conditional * b4b6c3aa55 mb/google/brya/var/{marasov,mithrax,omnigul}: Add SOF chip driver entries * 738fd2efc9 util/chromeos/extract_blobs: Add support for command line params * e59c5abd13 ec/google/chromeec: Add EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC * 341b108a71 mb/starlabs/starfighter: Add missing GPP_A5 definition * 414f1a61dd vc/intel/fsp/fsp2_0/pantherlake: Expose Thermal current thresholds and mode * 2e92833172 soc/qualcomm/common/usb/qmpv4_usb_phy: Fix delay value in comment to 10 ms * b48532c694 soc/mediatek: Refactor MMU configuration for DMA region * 28a8eaa57b soc/mediatek/mt8192: Clean up memlayout.ld * bca876849a soc/mediatek/common: Add enable parameter for configure_backlight * 46ce812c1b mb/google/skywalker: Create variant Grogu * 98a5445328 MAINTAINERS: Correct paths for Dell Latitude mainboards * 984ee53de8 mb/asus/p8x7x-series: Introduce CFR setup menu * 830ec89bca mb/google/bluey: Update mainboard part number for QuenbiH * c2fcf69e41 arch/x86: Use boolean for flag_is_changeable_p() * 2a791fcd66 mb/imb-1222/hda: Use AZALIA_PIN_CFG_NC() for disabled SPDIF_OUT2 pin * 217a7962d0 ec/google/chromeec: Update EC headers * 59cbb073c2 util/chromeos/crosfirmware.sh: Fix download of ninja (baytrail) recovery * fba92daed3 soc/qualcomm/x1p42100: Clean up DDR and IMEM memory layout * 5609174786 mb/google/rauru: Create variant Sapphire * 386feb720e soc/mediatek/mt8196: Add DVFS support for the second SoC SKU * 4b93b36170 mb/purism: add missing terminators to azalia codec tables * a927d124be mb/asus: Replace verb tables with reworked implementation * 9c0c925fe6 mb/siemens/mc_rpl1: Send POST codes to NC FPGA via PCI * 10361583b3 mb/siemens/mc_rpl: Add code to wait for legacy devices before PCI scan * d9979ba6a3 mb/siemens/mc_rpl: Sort includes alphabetically * d9b609b139 nb/intel/haswell: Use boolean for cbmem_was_initted * 1f2408f573 console: Fix flushing for slow consoles * 6a016a784b Documentation: Finalize 25.09 release notes * a0c5669c1b mb/asrock/imb-1222: Use macros for HDA verb table * c94ca87d40 mb/google/fatcat/var/kinmen: Enable Intel DPTF support * fe5f8494f6 docs/releases: Remove outdated "Upcoming release" in titles * aef86a7e89 mb/google/ocelot/var/ocelot: disable HDA GPIOs by default * 21f6ccf3a4 soc/intel/pantherlake: Use CPU ID mask for all stepping * 8bc41fc937 mb/google/trulo/var/pujjocento: Update DTT settings for thermal control * d5f1ecedf7 {device/azalia_codec,mainboard}: Use node ID enums for Realtek ALC887 * 02059c2250 mb/google/trulo/var/pujjoquince: Disable ISH gpio setting by fw_config * 58459b8210 mb/var/uldrenite,orisa: Include the variant GPIO header * 88ad238eca mb/google/skywalker: Fix incorrect GPIO_USB3_HUB_RST_L pull-down * b8a8800152 mb/google/fatcat/var/lapis: Configure gpio of fingerprint sensor * 4431848ee6 acpi: Move most of HEST ACPI table to common code * ce1ced7f6a mb/intel/ptlrvp: Fix WIFI driver device settings under root port 4 * 691a23a272 mb/google/fatcat: Fix WIFI driver device settings under root port 4 * 16bf80b9b1 tests/imd: Fix invalid NULL comparison on uintptr_t * 6d816b3b43 mb/asus/h610i-plus-d4: Add missing AZALIA_USE_LEGACY_VERB_TABLE * 6f042c6ae4 lib: coreboot_tables: Fix grammar of *These information* in comment * bcc7fce590 mb/topton/adl: Add TWL variant (X2E_N150) * f634121fa4 mb/purism: Replace verb tables with reworked implementation * 20d4042458 mb/asrock: Replace verb tables with reworked implementation * 2b7dbf80c9 mb/apple: Replace verb tables with reworked implementation * 970249694f mb/amd: Replace verb tables with reworked implementation * 94beaa7ab3 mb/acer: Replace verb tables with reworked implementation * f3db3a19d5 mb/51nb: Replace verb tables with reworked implementation * bc92d9a666 nb/intel/haswell/minihd.c: Add reworked verb table implementation * 69781b9806 soc/intel/broadwell/minihd.c: Add reworked verb table implementation * 31fc5b06a6 device: Introduce reworked azalia verb table * 50a59d4464 device: Add Kconfig to prepare for reworked verb table implementation * a3e2073591 lib/vga_gfx: Add API to render text on a bitmap buffer * ec2875e38f mb/google/ocelot/var/ojal: Enable FPS and update FW config * beb0951c1c mb/google/ocelot/var/ojal: Update touchpad config * bd933b641e mb/google/ocelot/var/ojal: Add overridetree * 82a9e601bd mb/google/ocelot/var/ojal: Add initial GPIOs config * 622c504a71 mb/emulation/qemu-riscv: Select DRIVERS_EMULATION_QEMU_FW_CFG * ba3f529681 drivers/emulation/qemu: Adjust fw_cfg driver for Arm and RISCV * c1e0384367 arch/riscv/include: Cast 'id' to int in OTHER_HLS() * 67a3fb6abe mb/asus: Add PRIME H610i-PLUS D4 (Alderlake/LGA1700) * 4f13f72dbc libpayload: Define UCHAR_MAX/CHAR_MIN/CHAR_MAX * 7f8c442a09 soc/intel/meteorlake: Correct function naming * 6d265ca31d device/pci_device: Fix typo in comments * d4b6b55977 payloads/Kconfig: default to Skiboot payload on PPC64 * cb899b0c4d mb/google/brox/var/caboc: Update HDA verb table * 15b903e1fd soc/intel/pantherlake: Add DDR5 memory type debug message * a5252bd5b9 drivers/soundwire/cs35l56: Support Cirrus Logic CS35L56 Smart Amplifier Family * 7d44128b2f mb/asus/p8z77-m_pro: Enable serial port A instead * 894c8069fc superio/nuvoton: Add NCT5535D * 69b0541375 sio/nuvoton/nct6779d: Add power loss resume support * f61ffb68c9 soc/intel/pantherlake: Remove unused TxDqDqs retraining parameter * 3a84c93b5b soc/intel/pantherlake: Correct function naming and code style * 3b34079b19 mb/google/trulo/var/kaladin: Enable External bypass config2 settings * 61488ffd57 mb/google/skywalker: Add CS35L51 support for beep sound for Padme * 4a7d779ed0 soc/mediatek/mt8196: Set RTC EOSC calibration to 8 seconds * 07df08836e Docs/releases: Update release notes for 25.09 release * 8f52c0774e docs/security/vboot: Update supported board list * 1f08b36f84 Documentation: Add coreboot release 25.12 template * 02980f0ea6 soc/amd/common/block/psp: Add comments * a17a41559a soc/amd/common/block/psp: Add BIOS SPI flash semaphore * 038262155e soc/amd/common/block/psp/psp_smi_flash: Fix flash busy check * 67e3579d61 sb/intel/lynxpoint: Enable PCIe Relaxed Order * 865649edc0 util/docker/jenkins-node: Use the correct branch for encapsulate * 6af7d299b2 mb/google/skywalker: Add MIPI panel support with TM_TL121BVMS07_00C * 4fc5f7a843 mb/google/fatcat/var/lapis: Modify the gpio order of mem_id * 2764a508ad mb/google/fatcat/var/lapis: Add 4 DDR modules to RAM id table * 886bd1d186 spd/lp5: Add Samsung K3KLALA0EM-MGCU memory part * 0a6f3e3868 mb/google/brox/var/caboc: Add PDC FW hash to hint romstage init * cbd1529126 mb/google/brox: Update Auxiliary Firmware Version check * 0d4c0ee7fc ec/google/chromeec: Add API for AP shutdown command * bbd72abae5 ec/google/chromeec: Update EC headers * 21ca3c5f3d mb/intel/ptlrvp: Update CKD/QCK mapping parameters * 3d7b898ff4 mb/google/ocelot/var/ocelot: Disable ALC721 clock stop support * c822148f2b mb/google/fatcat/var/lapis: Modify dq/dqs setting * 78fb910fe2 mb/google/fatcat/var/lapis: Update the configuration of fw_config * eb3497fae4 mb/google/fatcat/var/lapis: Update tpm i2c configuration * 3a33217349 mb/google/fatcat/var/lapis: Update thermal strategy * 36d2dc7cb9 mb/google/ocelot: Update wake event mapping for gspi0 * 59bd0e3206 mb/google/ocelot/var/ocelot: Update USB and TCSS port configuration * c4627e0dda mb/google/ocelot: Remove FP_PRESENT probe from ISH device configuration * 8e9ec16f45 mb/google/trulo/var/pujjolo: Add tablet mode fw config for ish fw * e3a2d1cecf soc/qualcomm/qclib: Improve logging on invalid MRC cache data * 289c01e6fb mb/google/ocelot: implement variant_memory_sku() * fbb68982c9 mainboard/google/ocelot: Update PCIe root port for SD card interface * c98155cbcd soc/intel/pantherlake: Generate TME keys only if TME is enabled * d8ed977358 mb/google/skywalker: Remove space before tabs in gpio.h * 1e7908fa9f mb/google/skywalker: Set up all output GPIOs * 14e6c62c10 mb/google/skywalker: Define all GPIO pins * 2859a5cba5 mb/{google,intel}/{fatcat,ptlrvp}: Prevent access to disconnected camera * ffae0f7d73 security/vboot: Extend CROS_EC_HASH_TIMEOUT_MS * d2345e0c60 mb/google/fatcat: Set `SkipExtGfxScan` FSP-M UPD * 8953c772cf lib: Fix bad whitespace in add_bmp_logo_file_to_cbfs_call * ef0c650edf soc/intel/cmn/blk/fast_spi: Cancel DMA transfer before locking * b3ad2aa3e7 mb/google/ocelot: GPIO config for headphone jack detection * 508c399bc1 mb/goog/ocelot/var/ocelot: add H58G66CK8BX147 memory option * d8a3f2aedd mb/goog/ocelot/var/ocelot: add H58GE6AK8BX104 memory option * f4110cebf6 spd/lp5: Add SPD for H58GE6AK8BX104 * 7acc99c3d2 acpi/acpi_pm: Fix compilation without SMBIOS * c77d3d67cf mb/google/skywalker: Report panel ID and SKU ID for padme * 6185983028 soc/intel/pantherlake: Standardize macros for core count and SKUs * 9a8402adf9 mb/google/trulo/var/kaladin: Update HDA verb table * 9af9e1d1f4 mb/google/trulo/var/kaladin: Add eMMC DLL settings * 3b4c446fbb mb/google/bluey: Configure QUP0 SE1 as I2C * ddf5987c1e drivers/mipi: Add support for TM_TL121BVMS07_00C panel * 0fec287327 mb/google/nissa/var/dirks: Drive GPIO GPP_D2 high to fix noise issue * 5a9ca2b040 mb/starlabs/starbook/mtl: Set SPD size to 512 * 79119456a2 soc/amd/common/block/iommu: Add missing newline to debug print * 81bb2663b7 soc/qualcomm/x1p42100: Select HAVE_CBFS_FILE_OPTION_BACKEND * bf83dd9927 soc/qualcomm/common/qclib: Introduce runtime debug log level control * cf3af46e50 mb/google/skywalker: Create variant Padme * 2b1809e026 mb/google/fatcat: Increase Fast VMode I_TRIP threshold to 63A * 2a7a0e86cd mb/google/fatcat: Configure Acoustic noise mitigation * 6c06602c75 mb/google/brya/var/uldrenite: Add fw_config probe for touchpad * a3b73464b5 soc/qualcomm/x1p42100/usb: Fix code comments and debug messages * e924021e69 mb/google/trulo/var/kaladin: Add GTH1563 and GTH7503 * d1967d927a spd/lp5: Add SPD for MT62F1G32D2DS-031 WT:C and MT62F2G32D4DS-031 WT:C * 2e10ddb1ee mb/starlabs/starbook/mtl: Make TCSS notify the IGD of changes * 47fb46e0e4 vc/intel/fsp/mtl: Update the headers to 5124_47 (13.0.228.64) * bb760bc9f3 Kconfig: Introduce HAVE_CBFS_FILE_OPTION_BACKEND * f1b83c8759 mb/google/rex/var/kanix: Add K3KL8L80EM-MGCU to RAM ID table * bcb3263078 mb/goog/ocelot/var/ocelot: add H58G66BK8BX067 memory option * 751afeb060 mb/google/brox/var/caboc: Update HDA verb table * 56700713de mb/google/trulo/var/kaladin: Disable eMMC GPIOs via firmware config * 93c147c5e6 commonlib/device_tree: Add dt_add_iommu_addr_prop function * d3d2f0f1c8 mb/google/fatcat/var/moonstone: Add to support ALC1320 Smart Amp * 1da045f6a5 mb/google/skywalker: Add API support for regulator VCN18 * fe70426dd7 soc/mediatek/common: Add support for regulator VCN18 * f4a123f055 tests: Allow specifying using system Cmocka or building from source * e7d598ba2c Reland "tests: Allow specifying vboot source directory" * a348ef46db mb/google/trulo/var/pujjolo: Change setting for lite ISH fw * 16db59ccef mb/google/rex/var/karis: Add K3KL8L80EM-MGCU to RAM ID table * 3639648f81 mb/google/fatcat/var/felino: Set GPP_A15 and GPP_B23 as not used * 8585591596 mb/google/fatcat/var/lapis: Set GPP_A15 as not used * b9af91dfe1 mb/starlabs/starlite_adl: Drop HDMI entries from verb table * 461c6a7d31 mb/starlabs/starfighter/rpl: Drop HDMI entries from verb table * fc3a647579 mb/starlabs/starbook/rpl: Drop HDMI entries from verb table * a88d9e1033 mb/starlabs/starbook/mtl: Drop HDMI entries from verb table * 90f94287fd mb/starlabs/starbook/adl_n: Drop HDMI entries from verb table * 684530ebdc mb/starlabs/starbook/adl: Drop HDMI entries from verb table * 258da6b1ef mb/goog/ocelot/var/ocelot: add H58G66BK7BX067 memory option * 883103c77f mb/google/ocelot: Disable memory training progress bar * f3a49c8b3d mb/google/ocelot/var/ocelot: Disable audio for invalid Audio FW_CONFIG * be3148575e mainboard/google/ocelot: Set OEM footer logo bottom margin * 092fca3210 mb/google/fatcat/var/kinmen: Add support ALC1320 Smart Amp * 4ba1b615db mb/starlabs/starlite_adl: Use macros for HDA verb table * ca8d6a7512 mb/starlabs/starfighter/rpl: Use macros for HDA verb table * c30163dace mb/starlabs/starbook/tgl: Use macros for HDA verb table * 15111ebb21 mb/starlabs/starbook/rpl: Use macros for HDA verb table * 6d6a280ab2 mb/starlabs/starbook/mtl: Use macros for HDA verb table * 543f6c2a52 mb/starlabs/starbook/kbl: Use macros for HDA verb table * 6d7c8f5477 mb/starlabs/starbook/cml: Use macros for HDA verb table * 515f566840 mb/starlabs/starbook/adl_n: Use macros for HDA verb table * 4b61d4de5f mb/starlabs/starbook/adl: Use macros for HDA verb table * 8bc0eddf15 soc/intel/pantherlake: Add support for a new Panther Lake B0 SKU * 2b84d26f55 payloads/edk2: configure capsule updates * f3211e9639 soc/intel/pantherlake: Add support for Acoustic Noise Mitigation UPDs * 2c03fd06a9 mb/google/trulo/var/kaladin: Disable ISH via firmware config * f8574f7145 soc/intel/ptl: Add Wildcat Lake SKU power map * b1fe32dd9e mb/{intel,google}/{fatcat,ptlrvp}: Update GPP_A15 GPIO configuration * 6074ca18d3 mb/google/ocelot: Create matsu variant * 76e0f64035 mb/google/brya: Update GPIO_PCH_WP for trulo variants * b69e66721d mb/google/brya: Update GPIO_PCH_WP configuration in trulo baseboard * 17c623277b mb/google/trulo/var/pujjolo: Change stylus settings * 7f74155aa4 mb/google/trulo/var/uldrenite: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS * f373faa9c8 mb/google/trulo/var/uldrenite: Add fw_config probe for storage * a262cdbc27 mb/intel/ptlrvp: Add wake configuration to cnvi_bluetooth * 1c0186f280 soc/intel/common/block/cnvi: Add CNVi chip configuration support * bdbe8b9b6f util/kconfig: Fix xconfig * 241b940ac7 mb/google/nissa/var/rull: add RAM ID H58G56CK8BX146 * 599d660c4b mb/google/fatcat: Enable support for Realtek EC * 89a3ae3d80 mb/google/trulo/var/pujjolo: Update GPP_D15 setting * b849c9daa1 3rdparty/qc_blobs: Update submodule to upstream main * 8159b2e06c device/azalia_codec: Add header with enums for Realtek node IDs * 18ae0c48e1 mb/google/fatcat/var/moonstone: Support new schematic changes * c1f76dd87e mb/google/brya/var/dochi: Add H58G56CK8BX146 to RAM ID table * 164b4a1d90 mb/google/nissa/var/craask: Add parade touchscreen support * 492826771e mb/google/bluey: Enable USB support * 96eb6a3ac1 soc/qualcomm/x1p42100: Add USB Type-A Host support * 2908a955e5 mb/google/rex/var/kanix: Add H58G56CK8BX146 to RAM ID table * 7fc414c886 mb/google/trulo/var/kaladin: Enable EC keyboard backlight * 859cc31e3a mb/google/brox/jubilant: Generate RAM IDs * a6c15129a7 mb/google/fatcat/var/moonstone: Generate SPD ID for memory module * 1028f3e846 soc/intel/pantherlake: Add Bluetooth to PME wake source mapping * 3f926bc110 commonlib/bsd: Add Bluetooth wake source in ELOG event data * 84ec1493a3 drivers/wifi/generic: Fix typo in header guard comment * 2e2490256f soc/qualcomm/x1p42100: Add USB clock support for X1P42100 * 159afbc5d5 lib/lzmadecode: Increase decoding speed by 30% * 0b8ad35ac1 mb/starlabs/byte_adl: Adjust the VBT * d3cea61907 mb/starlabs/starlite_adl: Adjust the VBT * 3507992d1d mb/starlabs/starbook/adl_n: Adjust the VBT * 05cd5a7ab9 mb/google/nissa/var/telith: Generate RAM IDs for telith * a0bdf3961c soc/qualcomm/common: Add clock reset function support * cf11722e68 soc/mediatek/mt8189: Enable tracker debug hardware * 382a7caff3 soc/mediatek/mt8196: Refactor tracker driver to support new platform * 97f9ebb5c2 mb/google/ocelot: Create ojal variant * ef1d48ee1d util/lint: Don't check for Kconfig.name in common directory * 5cb36eb16c util/lint: Don't check for board_info.txt in common directory * 46b03e682c util/amdfwtool: Handle address mode properly for Turin * 97cf4a1919 util/amdfwtool/amdfwread: fix offset decision for PSP/BIOS directory lookup * 73dd7bb046 util/amdfwtool/amdfwread: add initial parsing for EFW structure * d4da533473 smbios.h: Update smbios_memory_type * 183589dcbd smbios.h: Update smbios_memory_form_factor * 58726e58e4 mb/starlabs/starbook/mtl: Adjust the VBT to fix hot plug * 80df8c336f mb/intel/ptlrvp: Update Kconfig for ptlrvp_chromeec4s and ptlrvp4es support * ed59c1de34 soc/qualcomm/x1p42100: Update TF-A memory reservation * 56dbafcff4 soc/intel/pantherlake: Remove UFS support * 5b46caef93 mainboard/intel/ptlrvp: Remove UFS support * 621633af9b mainboard/google/fatcat: Remove UFS support * 5e2f5050ba mb/starlabs/starbook/kbl: Update HDA verb table * 4626c053dd mb/starlabs/starbook/adl_n: Update HDA verb table * 6f11c31354 mb/starlabs/starbook/mtl: Update HDA verb table * b748a5e10b mb/starlabs/{starbook,starfighter}/rpl: Disable GPIO override * 29ca9c8bfa mb/google/bluey: Disable charging during normal boot * e82338b0a2 mb/google/bluey: Add boot mode to coreboot tables * 893a2b008a libpayload: Add coreboot boot mode table * a45c8441af lib: Add boot mode information to coreboot tables * c73f30e74b mb/google/nissa/var/riven: Add H58G56CK8BX146 to RAM ID table * 8c717df03a soc/intel/ptl: Update Wildcat Lake PCIe root port numbering * afaef0b904 mainboard/google/ocelot: Update GPIO configuration for SLP_S0_GATE * 97dbfd3098 cpu/intel/car/non-evict: Improve CAR setup * cd48dc7d69 mb/google/rex/var/karis: Add H58G66CK8BX147 to RAM ID table * ffbf40f6c0 ec/google/chromeec: Update EC headers * 517185eca2 mb/google/bluey: Configure touchpad power GPIO * baf159a1c8 mb/google/bluey: Configure GSC and EC for Quartz * f8685bb2ee soc/mediatek/mt8189: Enable lastbus debug hardware * 6e61ea65a8 mb/google/bluey: Add disable slow charging support * 45d1f9cce4 mb/google/bluey: Move charging functions to dedicated file * 9fb306f53c soc/qualcomm/x1p42100: Add SPMI driver to ramstage * ac5bb861d8 mb/google/brya/var/uldrenite: Update HDA verb table * f2d3051631 ec/lenovo/h8: Turn on PWR LED * d8de1c4974 ec/lenovo/h8: Disable POST codes * d5a92542aa mb/google/fatcat/var/fatcat: Disable ALC721 & ALC722 clock stop support * 3b2962929b lib/timestamp: Init TSC frequency early on x86 * b0a63052b7 sb/intel/bd82x6x: Fix CPU replaced check * 9ecf04c2bc mb/google/nissa/var/quandiso: Generate RAM ID for MT62F512M32D1DS-023 WT:E * 16318a32ce spd/lp5x: Generate initial SPD for MT62F512M32D1DS-023 WT:E * 283c25beec mb/google/trulo/var/kaladin: Select Strauss keyboard to show G icon * 2709ae443b cpu/x86/entry16.S: Move reset vector to this file * 53810448fc cpu/x86/reset16.S: Remove handcoded reset vector * a1b7f5e1b8 mb/siemens/mc_rpl: Disable EIST to improve deterministic behavior * e6f8900c2d mb/siemens/mc_rpl: Disable S0ix power states * c71071397f soc/intel/common/fast_spi: Add static bus scanning * e73b4579c6 mb/siemens/mc_rpl: Disable DPTF * 77061d8427 mb/google/bluey: Add Quartz board (Qualcomm Hamoa) * ee1446a791 mainboard/emulation/qemu-q35: Do not compile memmap into SMM * a7b6590aca mb/google/dedede/var/dexi: Add and use VBT * 70ce81c86f mb/google/dedede/var/dita: Add and use VBT * 87f5d4c54a tree: use boolean for PcieRpLtrEnable[] * 725ab7b066 soc/mediatek/common: Increase WAIT_AUX_READY_TIME_MS * f02e755364 config/builder/mitac: Hook up public FSP repo and microcode * fc62ffab48 soc/amd/common/fsp/dmi: Skip parsing when memory type UNKNOWN * c3071b7150 soc/amd/cezanne/fsp_m_params: add UPD pointer parameter to mb callback * eb9a673a8e soc/amd/cezanne: Add a Kconfig option for SERIRQ_CONTINUOUS_MODE * c590e8e75c mb/brya/var/uldrenite: Increase Touch IC enable delay time * 9996fc58fd mb/siemens/mc_rpl: Disable C1E state via MSR_POWER_CTL * c58c988b8e mb/siemens/mc_rpl: Remove unused code and power limit functionality * 8e5e87a1cf mb/siemens/mc_rpl1: Configure CPU power limits to 28W TDP * 4853f16a59 mb/google/fatcat/var/kinmen: Support new schematic changes * 9d67120078 mb/google/moonstone: Create moonstone variant * 00d954977c util/smmstoretool: Support other block sizes * 4fd3cb35c2 util/cbmem: Change abort() to exit(1) in die() * 62b6d1e336 mb/siemens/mc_rpl: Enable master bit in PCI config space if allowed * a8bce33b82 mb/siemens/mc_rpl: Disable Intel Turbo Boost * 1a9008b261 device/azalia: Use clrsetbits32() and friends * cbf8527345 device/azalia: Amend the mistake of codec_is_operative() * 0a328282ec device/azalia: Add enums for HDA verb and parameter IDs * c15006eb0c soc/intel/alderlake: Add 28W TDP support for RPL-P ID 8 (0xa716) * d7a996cf44 mb/siemens/mc_rpl1: Enable 4 P-Cores, disable E-Cores * 2f9273f1f4 mb/siemens/mc_rpl: Select FSP_TYPE_IOT * 1b14664311 mb/siemens/mc_rpl: Remove unused DPTF settings * 66a3f2a1b1 mb/siemens/mc_rpl: Disable SaGv * 993a9c9e14 mb/siemens/mc_rpl1: Configure SATA Ports * e03f50bf5f mb/siemens/mc_rpl: Enable Siemens NC_FPGA driver * 699c28c01d sb/intel/bd82x6x: Fix replay issues * c2110e3161 tree: Use true, false for PcieRpClkReqSupport * ebab858d92 soc/intel/pantherlake: Enable memory bandwidth compression for IGD * ad10d4a977 soc/intel/cmn/blk/graphics: Reserve memory compression region * 8a52418e9a commonlib/device_tree: Fix memory leak in fdt_unflatten() * 7896f4950c mb/google/skywalker: Turn off UFS power for eMMC SKUs * 22fe08c04b soc/mediatek/mt8189: Implement UFS power-off API for non-UFS SKUs * 5f0225a7b5 drivers/intel/fsp2_0: Refactor for earlier graphics memory WC MTRR * 1c571446ec soc/intel/common/block/systemagent: Increase MTRR region size to 32 MiB * 67afbf5f96 soc/intel/pantherlake: Add TDP mappings for Panther Lake-U SKUs * ec69479bdb mb/google/ocelot: Drop redundant SNDW GPIO mapping * 5f168e9441 mb/google/ocelot/var/ocelot: Conditionally init ALC256 HDA using fw_config * 152b584167 mb/goog/ocelot/var/ocelot: Add AUDIO_MAX98360_ALC5682I_I2S * 8f2633cd60 soc/power9/rom_media.c: find CBFS in PNOR * 44ec090551 ppc64: Kconfig switch for bootblock in SEEPROM, zero HRMOR * 921027e09b src/lib/cbmem_common: Delete a space(' ') in the source code * acb86babdf mb/protectli/vault_kbl/mainboard.c: bring back the beep * 76d45a8219 soc/amd/genoa_poc/root_complex.c: Explain the order of IOHCs * 8dcfa915f2 soc/amd/common/block/psp: Probe SPI flash early * 00217275b2 soc/amd/common/block: Don't clobber SPI registers * c13eadeadb soc/amd/common/block/psp/psp_smi_flash: Fix busy check * fbcf031181 mb/qemu-riscv: set PCI_IOBASE * bf0ee592f5 soc/intel/alderlake: Make SATA speed limit configurable * 482a2d6548 nb/intel/sandybridge/northbridge.c: Disable non-active PEG devices * 7e73d4ef30 Documentation: mb/erying/tgl: Update documentation * 73cba1fdea mb/erying/tgl: Introduce CFR * 23cf7c64f9 mb/erying/tgl: Use booleans in devicetree * 261b6b4fd1 soc/intel/skylake: Allow generating USB ACPI code * 23e92a5ac0 mb/erying/tgl: Map remaining USB ports * 762a535551 mb/erying/tgl: Clean up the GPIO table * 179b8444c3 soc/intel/xeon-sp/gnr: Hook up public FSP bin and headers * 42ba7a9e48 soc/intel/xeon_sp/gnr: Add Kconfig symbols for SKUs GNR-AP and GNR-SP * c732f406c7 mb/google/ocelot: ec.h: Disable sync IRQ, sync IRQ wake capable for OCELOT4ES * 73961bf680 mb/google/ocelot: Use same mainboard part number for all ocelot variants * 691d5e84cd mainboard/google/oceot: Drop redundant logo_valignment selection * b67d88aecb mb/google/bluey: Enable PMIC based slow charging in romstage * dcb7c317c2 mb/siemens/mc_rpl1: Enable Intel I210 MACPHY driver * 2b26ea0eda mb/siemens/mc_rpl1: Configure SPI and implement TPM support * 2bcd7f1522 mb/siemens/mc_rpl1: Adjust UART settings and enable LPSS UART * 524fd18bd6 mb/siemens/mc_rpl1: Create variant specific Kconfig file * c7cd4e3305 mb/siemens/mc_rpl: Move SOC selection to baseboard * 6427e51c4f mb/siemens/mc_rpl1: Adjust USB port settings in devicetree * 71c4619045 mb/siemens/mc_rpl: Remove unused devices from devicetree and Kconfig * 296f5968d3 mb/siemens/mc_rpl1: Adjust I2C bus enablement in devicetree * a1dd6bfc22 mb/siemens/mc_rpl1: Adjust PCIe settings in devicetree * f94469c2a9 mb/google/nissa/var/pujjolo/pujjoquince: Add wifi sar table * 6781f458ee mb/google/trulo/var/pujjolo: Enable fivr settings * 17a88540fd soc/qualcomm/x1p42100: Use SPMI driver * c1128ae649 soc/qualcomm/cmn: Add SPMI driver * 0eebd5596b mb/google/fatcat: Create lapis variant * 4931b978d9 soc/mediatek: Increase CBFS cache to 8MB in memlayout.ld * 234eb53ed9 nb/intel/sandybridge/raminit: Speed up reading SPD EEPROMs * 7d57333529 ec/starlabs/merlin: Add a "off" mode for the power LED * 36624072a6 mb/google/trulo/var/pujjolo: Update wlan rtd3 settings * 42a5c189b2 mb/lenovo/X220: Add CFR support * 8509798006 sb/intel/common/smbus: Use proper delay instruction * 5f7b5fcb19 mb/starlabs/byte: Lower the PL4 value to 65W * 4a6a0de029 3rdparty/fsp: Update to upstream master * de98da43fa 3rdparty/intel-microcode: Update to upstream main * bdee19ba87 soc/qualcomm/x1p42100: Add ASCII memory map diagram to memlayout.ld * 51a8e238b0 lib: Correct logo bottom margin handling for all panel orientations * 9999a4aebb mb/google/nissa/var/pujjocento: Change touchscreen properties * 8d2df573a8 soc/qualcomm/x1p42100/qclib: Support to pack and load CPR binary in CBFS * a484a6529c soc/qualcomm/common/qclib: Support to declare cpr_settings region * dc04ee827b mb/google/fatcat/var/kinmen: Generate SPD ID for memory modules * e7cdf035fb mb/google/brox/var/caboc: Enable RTD3 for SSD to resolve S0ix issue * cec34128d0 soc/qualcomm/x1p42100: Support to load CPUCP firmware in x1p42100 * a2b6e20509 soc/mediatek/common: Increase per-channel SPMI max byte count to 2 * 6ba2df9be5 soc/mediatek/common: Use polling to reduce eDP HPD wait time * ee347d8812 soc/qualcomm/common/qclib: Support to load AOP config and meta in CBFS * 3f4c84513d soc/qualcomm/x1p42100/qclib: Support to pack AOP config and meta in CBFS * 5de5b519ca mb/prodrive/atlas/vpd.c: Replace union {0} initializers with {} for C23 compliance * 48207895af lint: Warn about using change IDs for merged changes * 6acf07022d Doc/contributing: Add clarification on how to reference other commits * 40d0ec0fa4 Revert "soc/mediatek/common: Remove 200 ms delay from eDP init path" * 244a34b3d0 cpu/x86/mp_init: Refactor ICR wait logic * eee5be070a cpu/intel: Use mtrr_use_temp_range() * e37a53a2fc arch/x86/memcpy: Fix undefined behaviour * 7c0f7e0b3f vc/intel/fsp: Update PTL FSP headers to FSP 3272_04 * d315f26217 payload/seabios: Update from 1.16.3 to 1.17.0 * c61a762a47 mb/google/bluey: Add QuenbiH board * 9edf49b008 mb/google/bluey: Add BlueyH board * 9868417d5e mb/google/bluey: Refactor Kconfig for Hamoa SoC * 74d91d0b76 mb/google/nissa/var/glassway: Support Memory MICRON MT62F512M32D2DR-031WT:B * 7eb832b1dc mb/google/skywalker: Configure GPIO GPIO_AP_EDP_BKLTEN as output * cdd42ccde8 soc/qualcomm/x1p42100: Use 4K for memory region alignment * 2146ecc8e1 mb/google/brox/caboc: Enable PEG60 with PEG62 * 6925fd69f8 soc/qualcomm: Move common region macros to `soc/memlayout.h` * d220b65b8f soc/qualcomm/qcs405: Add common include path * b25939786d soc/qualcomm/x1p42100: Refactor CBMEM top address to use linker symbols * d6ec4f108d soc/qualcomm/x1p42100: Mark additional reserved memory ranges * 1b760645b9 soc/qc/x1p42100: Dynamically configure DRAM resources in ramstage * 276432faf7 soc/qualcomm/common: Add MMU configuration for fragmented DRAM regions * b4347f11d9 include: Make DRAM an explicit region * 11c8d423d1 soc/qc/common: Remove ddr_base from qc_mmu_dram_config_post_dram_init * 73de3f95ac mb/google/bluey: Support hardware watchdog logging * 25e0a4642c mb/google/brox/var/caboc: Update LAN LED behavior * e5ff7cb186 mb/google/ocelot/var/ocelot: Update DDI port Configuration * 8df079c609 mb/lattepanda/mu: Enable CRB TPM (Intel fTPM) * 6e9c0a26e3 device/device_util: Fix format specifier for DEVICE_PATH_GICC_V3 * 4a82f37525 mb/google/nissa/var/quandiso: Generate new RAM ID * 17a7c351b8 mb/google/brya/var/kaladin/hda_verb.c: Correct number of entries to 21 * b65b98ace6 mb/goog/ocelot/var/ocelot: switch to H58G56BK8BX068 memory part * 8097809c8a libpayload: Fix strsep() edge cases * e38a216368 soc/intel/pantherlake: Rearm and clear only for valid crashlog in PMC * 510686add4 soc/intel/pantherlake: Rearm crashlog using watcher * 609eb4c5f1 mb/google/ocelot/var/ocelot: Remove unused I2C controllers * df7bf9404d soc/mediatek/common: Remove 200 ms delay from eDP init path * a70bf82036 soc/mediatek/common: Measure eDP initialization time * 6bb1ba95e1 soc/mediatek/common/dp: Move mtk_edp_init to dptx_common.c * e49e8c6355 soc/qc/x1p42100: Add memory layouts for CPUCP and TZ regions * c418a3b843 mb/google/brox/var/caboc: Update WWAN gpio * 77b52ed3cc mb/google/brox/var/caboc: HDA: Correct number of jacks to 35 * e31fbc493d soc/qualcomm/cmn/qclib: Support reuse of existing DDR training data * bdcf19f404 mb/google/trulo/var/pujjolo: Add fw config for PDC * 13897bde9a mb/google/trulo/var/pujjolo: Add wlan rtd3 setting * 90589d44d2 soc/qualcomm/x1p42100: Reserve DDR memory regions for AOP and BL31 * 2e61995b2f soc/qualcomm/x1p42100: Add support for Hamoa SoC * 281b01ce5e soc/qualcomm/x1p42100: Remove unused PMIC file from CBFS * ecbca16bf4 tree: Replace union {0} initializers with {} for C23 compliance * b74d2b77d2 mb/google/trulo/var/kaladin: Add WIFI SAR table * 4b46a0690e mb/hp: Add HP ProDesk 600 G1 SFF Business PC (Haswell / NPCD379 SIO) * 2339508b6c mb/google/trulo/var/pujjolo: Update P-sensor parameters * cd2a969c82 soc/intel/pantherlake: Remove storage-off related code * fe6fa36504 mb/asrock: Add SPR 1S server board ASRock Rack SPC741D8-2L2T/BCM * b486c84b23 mb/google/trulo/var/pujjolo: Update DTT settings for thermal control * ece0072d1c mb/google/trulo/var/pujjolo: Update verb table to fix pop noise * 795157a606 mb/google/bluey: Increase MRC cache size * 34d9305dcc soc/qc/x1p42100: Pack QcLib DTB into CBFS * 8f09629fb1 spi_flash: Fix initialization of `flags` field in lb_spi_flash * ab2ef8878c mb/google/trulo/var/pujjocento: Update touchscreen information * 0bedce05d8 mb/google/nissa/var/pujjocento: Change touchpanel sequence to meet spec * 543fb60ec4 mb/google/brox/var/lotso: Set slew rate to 1/8 * c114906239 mb/google/trulo/var/pujjocento: Update DTT settings for thermal control * b603f23088 mb/google/bluey: Avoid using function call table * dc64b9659d soc/qc/cmn: Refactor qclib_load_and_run function * e290bb6750 mb/baseboard/ptlrvp: Disable memory training progress bar * 05a38e2af3 mb/google/fatcat: Disable memory training progress bar * f789899dac sb/intel/common/gpio: Move register defines * d6ceaf72da mb/samsung/lumpy: Use gpio_base2_value * 21639c3771 mb/getac/p470: Use common gpio functions * 8d4bb94663 sb/intel/common/gpio: Add and use gpio_invert() * 85306062d8 mb/google/skywalker: Create variant Tarkin * 1da2f46db8 soc/intel/alderlake: Restore mem_init_override_channel_mask() * f0d5b25e02 mb/google/trulo/var/kaladin: Add firmware name and gpio for ISH * 0b3fc8ce2d mb/google/nissa/var/pujjoniru: Decrease cpu power limits * f01cc9258b mb/google/rex/var/screebo: Use ACPI for touchscreen power sequencing * ef11f95125 soc/qualcomm/x1p42100: Set 1ms TX delay * 2c8d157ea4 {drivers, soc/qualcomm/common}: Add configurable delay for UART bitbang * b0d2d522ea soc/qualcomm/x1p42100: Enable bootblock compression * 1e11bda5d0 soc/intel/cmn/smbus: Drop use of update_spd_len() * 910f111891 soc/intel/mtl: Fill in SPD data on both channels of DDR5 memory * 0da943ed99 soc/intel/meteorlake: Fix DDR5 channel mapping * 87c9bb3994 soc/intel/adl: Fill in SPD data on both channels of DDR5 memory * a23be7a6fe mb/google/fatcat/var/francka: Disable ALC721 & ALC722 clock stop support * 227d434e2d drivers/soundwire/alc711: Support clock stop flag from devicetree * 49219f1ce1 Docs: Use markdown autolinks instead of Sphinx doc directive * 6afc1ff9ac soc/mediatek/mt8189: Disable 8189G APU power to reduce power consumption * 965131e40f soc/mediatek/common: Fix build error by including stdint.h in cpu_id.h * e49743755d mb/google/ocelot: Select EC_GOOGLE_CHROMEEC_MEC for MCHP variants * 32b944b77a mb/google/brox/var/caboc: Update hda_verb table * ba228d160f mb/google/fatcat: Create new kinmen4es variant * 6a42eb9134 soc/intel/pantherlake: Disable memory training progress bar * e9cb352706 soc/common/smbus: Support reading SPD5 hubs for DDR5 * cba46a41b7 mainboard/{hardkernel,protectli}: Drop use of DRAM_SUPPORT_DDR5 * a79f341d29 mb/google/trulo/var/pujjolo: Disable mipi camera dmic LED * 9411c6e7c7 util/amdfwtool: Fix NULL pointer dereference in fill_dir_header * 280d3a25e8 util/lint/kconfig_lint: Fix operator precedence issue * fbc2d76ab3 soc/intel/*: Select 'DRAM_SUPPORT_DDRx' as appropriate * 008f0ec078 util/smmstoretool: Alias EfiImageSecurityDatabaseGuid to "secureboot" * 88aeb8b7cd util/smmstoretool: Allow setting authenticated variable * e977560e72 payloads/edk2: Increase non-full-screen menu size * ac7487d766 mb/google/fatcat: Use same MAINBOARD_PART_NUMBER for felino variants * 0f84878c89 mb/google/brox: Handle NULL return value in variant_get_auxfw_version_file * 749fd1a8d8 soc/intel/pantherlake: Use macro for VGA Init Control * 3c4fb7b729 mb/google/trulo/var/pujjolo: Update verb table * 2ae0f6cdb9 mb/google/trulo/var/kaladin: Add fw config for ELAN touchscreen * 53dd93ff14 libpayload/drivers/pci_qcom: Fix address during ATU config * 54016e273e util/cbmem/sysfs_drv: Fix incompatible pointer type for 'size' * a9997f2d7f soc/intel/cmn/block: Request bus master in final op for DSP and HDA * fea789ed63 mb/google/fatcat/var/francka: Use ACPI for touchscreen power sequencing * 211526ff38 Revert "mb/google/brya: Fix mux_conn index used by ec/google/chromeec" * 7b91339e55 Revert "mb/google/brya: Fix pmc_mux port mapping for mithrax and felwinter" * 8a45e505b9 soc/mediatek/common/dp: Change dptx_hal_phy_wait_aux_ldo_ready to static * 350c977fef soc/intel/pantherlake: Clear crashlog record using watcher * ae942a70b8 mb/google/trulo/var/kaladin: Update GPIOs table * 0a4bc79685 mb/google/trulo/var/kaladin: Update USB2 driving settings * f34bc61ca7 mb/google/trulo/var/pujjolo: Correct the Goodix touchpad description * d4b735f9f1 mb/google/ocelot: Turn off unused I2C ports * 190c27d08b mb/google/brya/var/marasov: Add SPD ID for K3KL6L60GM-MGCT and K3KL8L80EM-MGCU * d79febf356 soc/qc/x1p42100: Enable QcLib, SHRM and AOP firmware load * db10b681b4 soc/qc/x1p42100: Load and populate QcLib interface table entries * eee3ea0346 mb/google/bluey: Enable PCIE Feature for bluey * 6f115f7bf0 soc/qualcomm/x1p42100: Configure Gen4 PHY link for x1p42100 * 823fa6b8f6 soc/qualcomm/common: Integrate QMP PCIe 4.0 PHY 2x2/1x4 * 6bb199d258 mb/google/fatcat/var/fatcat: Move `ISH_GP_x` pads to fw_config.c * a5212f15ce mb/google/fatcat/var/fatcat: Remove unused GPP_B06 GPIO configuration * d7415f5d9a mb/google/trulo/var/kaladin: Remove external bypass settings * 479b39c3e9 mb/google/ocelot: Update wake on touch GPIO * 7095c99a87 util/cbmem: Add support for CBMEM in sysfs * eeb15e83cb mb/gigabyte: Add ga-h81m-d2w (ITE8620E superio) * 5537ce7c2f mb/google/fatcat: Fix GPIO config for headphone jack detection * 953957e961 mb/google/trulo/var/pujjolo: Change ICCmax at VCCIN_AUX from 25A to 27A * 87d5c7224b mb/google/trulo/var/pujjolo: Select Strauss keyboard to show G icon * eb005f5f5c mb/google/brya/var: Clarify comment for 'tcss_aux_ori' * 85b26f75d2 soc/intel/xeon_sp: Remove fast_spi_cache_bios_region * fc4911ec35 soc/qualcomm/x1p42100: Add CPU Clock boost support for X1P42100 * 1a9fb29a53 soc/qualcomm/common: Add API to enable Zondaole PLL for X1P42100 * e272b20c85 sb/intel/common: Remove unused function prototype * c54fde5040 sb/inte/common/gpio: Implement gpio_input() and gpio_output() * 55bed620a4 mb/dell: Use gpio_base2_value * 84899e6fb7 sb/intel: Convert set_gpio to gpio_set * 0c79443ca9 sb/intel/*/gpio: Convert get_gpios to gpio_base2_value * 69364fc9e0 sb/intel: Convert get_gpio() to gpio_get() * 2d7891abe2 sb/intel: Add soc/gpio.h * 6a20caea01 drivers/lenovo/hybrid_graphics: Add missing header * 04cc15feb4 sb/intel/common/pmutil: Drop unused header * b44c0ab25b ec/lenovo/pmh7: Include stdbool.h * b20f6d27e2 device/dram: Rename 'USE_DDRx' config options * 1ade8247ce mb/google/trulo/var/pujjocento: update hda_verb table for ALC257 * 28848dc4fb mb/google/trulo/var/kaladin: Add elan touchscreen support * 9a89e3b4c6 mb/google/trulo/var/kaladin: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS * f84934a203 mb/google/trulo/var/kaladin: Add DRAM part H58G56CK8BX146 * dd76bcc4c3 soc/qc/sc7280: Relocate SHRM firmware load to common Qualcomm path * 88b10e09b6 mb/google/ocelot: Set TPM_TIS_ACPI_INTERRUPT for all ocelot variants * c2dfe61016 mb/google/ocelot: Disable CNVi bluetooth core in the baseboard code * 69e6d96aad mb/google/fatcat: Configure host command ranges for FATCAT4ES variant * 8bdc170901 mb/google/brox/var/lotso: Update VR domain config * a6842184ab mb/google/fatcat/var/kinmen: Use ACPI for touchscreen power sequencing * 712aac780f mb/google/rex/kanix: Use ACPI for touchscreen power sequencing * 26e6d0be00 mb/google/rex/var/karis: Use ACPI for touchscreen power sequencing * 00d99a6e9b mb/google/brox/var/lotso: Configure Acoustic noise mitigation * 4b6ebbdd94 mb/google/skywalker: Initialize clkbuf and srclken in romstage * f131f0e336 soc/mediatek/mt8189: Add clk_buf and srclken_rc drivers * 2de0158eec soc/intel/pantherlake: Add asynchronous CBFS file loading support * eb1b5ee116 soc/intel/cmn/block/fast_spi: Introduce a DMA transfer queue * 182ba52792 soc/intel/pantherlake: Remove mailbox interface offset * 2ee78458be soc/intel/pantherlake: Use CONSUMED_BIOS bit * 9a8ba5b39a {lib, drivers/intel}: Move BMP rendering logic out of SoC code * a617317775 mb/google/fatcat/var/kinmen: Support SAR table selection via FW_CONFIG * 92dd8cea59 mb/google/nissa/var/riven: Add parade touchscreen support * b98f786375 mb/google/fatcat/var/francka: Increase reset delay to 100ms for ILTK0001 * 5f0177ac5d mb/google/trulo/var/pujjolo: Update Stylus IRQ wakeup group * 5b1a8b53b6 soc/amd/common/i23c_pad_ctrl: add I3C pad config options * 4b58ec5ac2 soc/amd/common/block/psp: Add fTPM specific bits * 15bf25de78 Documentation/soc/intel: Update the referenced linuxboot_defconfig * debfac6352 mb/google/ocelot/var/ocelot: Add wake support for touchpad * b6425a9a78 soc/amd/common: Add comments about bootblock * 69888bc7fc util/cbfstool/amdcompress: Bail out on invalid ELF * 3b008bde8c soc/mediatek/mt8196: Fix intermittent black screen issue * da33feeb51 soc/mediatek/mt8189: Correct thermal SRAM base address and length Signed-off-by: Leah Rowe --- ...01-add-c3-and-clockgen-to-apple-macbook21.patch | 4 +- .../0002-lenovo-t400-Enable-all-SATA-ports.patch | 4 +- ...230-set-me_state-Disabled-in-cmos.default.patch | 4 +- ..._state-Disabled-on-all-cmos.default-files.patch | 4 +- ...-ifdtool-add-nuke-flag-all-0xFF-on-region.patch | 48 +- ...00-Enable-01.0-device-in-devicetree-for-d.patch | 4 +- ...ing-for-coreboot-images-built-without-a-p.patch | 4 +- ...CK-Disable-coreboot-related-BL31-features.patch | 6 +- ...-dell-e6430-use-ME-Soft-Temporary-Disable.patch | 4 +- ...0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch | 4 +- ...intel-haswell-make-IOMMU-a-runtime-option.patch | 4 +- ...ll-optiplex_9020-Disable-IOMMU-by-default.patch | 4 +- ...well-Fully-disable-iGPU-when-dGPU-is-used.patch | 4 +- ...c-dell-mec5035-Add-S3-suspend-SMI-handler.patch | 30 +- ...ell-lock-policy-regs-when-disabling-IOMMU.patch | 4 +- ...0016-nb-intel-gm45-Make-DDR2-raminit-work.patch | 12 +- ...Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch | 8 +- ...00-Use-100-MHz-reference-clock-for-displa.patch | 10 +- ...019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch | 6 +- ...-mb-dell-gm45_latitudes-Add-E4300-variant.patch | 10 +- ...ell-Add-S3-SMI-handler-for-Dell-Latitudes.patch | 4 +- ...-Disable-compression-on-refcode-insertion.patch | 31 + ...-mec5035-Route-power-button-event-to-host.patch | 92 --- ...-Disable-compression-on-refcode-insertion.patch | 31 - ...ntel-Disable-stack-overflow-debug-options.patch | 187 ++++++ ...024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch | 708 +++++++++++++++++++++ ...ntel-Disable-stack-overflow-debug-options.patch | 187 ------ ...025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch | 708 --------------------- ...025-mb-dell-optiplex_780-Add-USFF-variant.patch | 326 ++++++++++ ...026-mb-dell-optiplex_780-Add-USFF-variant.patch | 326 ---------- ...rc-intel-x4x-Disable-stack-overflow-debug.patch | 33 + ...p-8300cmt-remove-xhci_overcurrent_mapping.patch | 42 ++ ...rc-intel-x4x-Disable-stack-overflow-debug.patch | 33 - .../0028-dell-3050micro-disable-nvme-hotplug.patch | 47 ++ ...p-8300cmt-remove-xhci_overcurrent_mapping.patch | 42 -- .../0029-dell-3050micro-disable-nvme-hotplug.patch | 49 -- ...kylake-Disable-stack-overflow-debug-optio.patch | 61 ++ ...30-soc-intel-skylake-Don-t-compress-FSP-S.patch | 36 ++ ...0030-soc-intel-skylake-configure-usb-acpi.patch | 94 --- ...Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch | 78 +++ ...kylake-Disable-stack-overflow-debug-optio.patch | 61 -- ...ional-TBFW-setting-for-kabylake-thinkpads.patch | 37 ++ ...32-soc-intel-skylake-Don-t-compress-FSP-S.patch | 36 -- ...Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch | 78 --- ...lderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch | 30 + ...4-Conditional-TBFW-setting-for-T480-T480S.patch | 37 -- ...PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch | 76 +++ ...35-mb-topton-adl-Add-TWL-variant-X2E_N150.patch | 106 --- ...-soc-intel-alderlake-Don-t-compress-FSP-S.patch | 35 + ...e-don-t-require-full-fsp-repo-for-fd-path.patch | 33 + ...lderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch | 30 - ...PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch | 76 --- ...rlake-disable-stack-overflow-debug-option.patch | 46 ++ ...5035-Add-command-to-disable-EC-initiated-.patch | 92 +++ ...-soc-intel-alderlake-Don-t-compress-FSP-S.patch | 35 - ...e-don-t-require-full-fsp-repo-for-fd-path.patch | 33 - ..._ivb_latitude-Disable-EC-initiated-shutdo.patch | 36 ++ ...0-Haswell-NRI-Implement-SMBIOS-type-16-17.patch | 184 ------ ...ntel-dtbt-Add-discrete-Thunderbolt-driver.patch | 358 +++++++++++ .../0041-mb-lenovo-t480-s-Enable-TBT-support.patch | 117 ++++ ...rlake-disable-stack-overflow-debug-option.patch | 46 -- ...5035-Add-command-to-disable-EC-initiated-.patch | 92 --- ..._ivb_latitude-Disable-EC-initiated-shutdo.patch | 36 -- .../0044-mb-lenovo-t480-Fix-headphone-jack.patch | 83 --- .../0045-mb-lenovo-t480s-Fix-headphone-jack.patch | 82 --- ...ntel-dtbt-Add-discrete-Thunderbolt-driver.patch | 358 ----------- .../0047-mb-lenovo-t480-s-Enable-TBT-support.patch | 123 ---- 67 files changed, 2501 insertions(+), 3148 deletions(-) create mode 100644 config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch delete mode 100644 config/coreboot/default/patches/0022-ec-dell-mec5035-Route-power-button-event-to-host.patch delete mode 100644 config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch create mode 100644 config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch create mode 100644 config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch delete mode 100644 config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch delete mode 100644 config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch create mode 100644 config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch delete mode 100644 config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch create mode 100644 config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch create mode 100644 config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch delete mode 100644 config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch create mode 100644 config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch delete mode 100644 config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch delete mode 100644 config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch create mode 100644 config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch create mode 100644 config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch delete mode 100644 config/coreboot/default/patches/0030-soc-intel-skylake-configure-usb-acpi.patch create mode 100644 config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch delete mode 100644 config/coreboot/default/patches/0031-src-intel-skylake-Disable-stack-overflow-debug-optio.patch create mode 100644 config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch delete mode 100644 config/coreboot/default/patches/0032-soc-intel-skylake-Don-t-compress-FSP-S.patch delete mode 100644 config/coreboot/default/patches/0033-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch create mode 100644 config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch delete mode 100644 config/coreboot/default/patches/0034-Conditional-TBFW-setting-for-T480-T480S.patch create mode 100644 config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch delete mode 100644 config/coreboot/default/patches/0035-mb-topton-adl-Add-TWL-variant-X2E_N150.patch create mode 100644 config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch create mode 100644 config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch delete mode 100644 config/coreboot/default/patches/0036-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch delete mode 100644 config/coreboot/default/patches/0037-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch create mode 100644 config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch create mode 100644 config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch delete mode 100644 config/coreboot/default/patches/0038-soc-intel-alderlake-Don-t-compress-FSP-S.patch delete mode 100644 config/coreboot/default/patches/0039-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch create mode 100644 config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch delete mode 100644 config/coreboot/default/patches/0040-Haswell-NRI-Implement-SMBIOS-type-16-17.patch create mode 100644 config/coreboot/default/patches/0040-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch create mode 100644 config/coreboot/default/patches/0041-mb-lenovo-t480-s-Enable-TBT-support.patch delete mode 100644 config/coreboot/default/patches/0041-soc-alderlake-disable-stack-overflow-debug-option.patch delete mode 100644 config/coreboot/default/patches/0042-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch delete mode 100644 config/coreboot/default/patches/0043-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch delete mode 100644 config/coreboot/default/patches/0044-mb-lenovo-t480-Fix-headphone-jack.patch delete mode 100644 config/coreboot/default/patches/0045-mb-lenovo-t480s-Fix-headphone-jack.patch delete mode 100644 config/coreboot/default/patches/0046-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch delete mode 100644 config/coreboot/default/patches/0047-mb-lenovo-t480-s-Enable-TBT-support.patch (limited to 'config/coreboot/default/patches') diff --git a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch index 04e896d9..3a050d3b 100644 --- a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch +++ b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch @@ -1,7 +1,7 @@ -From 7436b357fbe12233f3fbc5d360f296e6e15d3c2d Mon Sep 17 00:00:00 2001 +From 4e350ac1b7d5f27ae0887bb016d748b0987ad14d Mon Sep 17 00:00:00 2001 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> Date: Wed, 27 Oct 2021 13:36:01 +0200 -Subject: [PATCH 01/40] add c3 and clockgen to apple/macbook21 +Subject: [PATCH 01/41] add c3 and clockgen to apple/macbook21 --- src/mainboard/apple/macbook21/Kconfig | 1 + diff --git a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch index 2040cbc2..228eb57d 100644 --- a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch +++ b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch @@ -1,7 +1,7 @@ -From 7d2e54028f5558f0ccea5ecd8f5f812e28597a47 Mon Sep 17 00:00:00 2001 +From 0322228c25be7d95e7dbcc905dec81960905152b Mon Sep 17 00:00:00 2001 From: persmule Date: Sun, 31 Oct 2021 23:33:26 +0000 -Subject: [PATCH 02/40] lenovo/t400: Enable all SATA ports +Subject: [PATCH 02/41] lenovo/t400: Enable all SATA ports There are 2 SATA ports on the chassis of t400(s), but at least one dock for t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its diff --git a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch index 89294d6f..ec891ccf 100644 --- a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch +++ b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -1,7 +1,7 @@ -From 61051fbf9f1da48932930b512527626d1cf5bfbd Mon Sep 17 00:00:00 2001 +From 4714f4388bf90fc7ff3d25dd62feec07de5f4c7e Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 3 Jan 2022 19:06:22 +0000 -Subject: [PATCH 03/40] lenovo/x230: set me_state=Disabled in cmos.default +Subject: [PATCH 03/41] lenovo/x230: set me_state=Disabled in cmos.default I only recently found out about this. It's possible to use me_cleaner to do the same thing, but some people might just flash coreboot and not do diff --git a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch index 7b2ceabd..e55f8847 100644 --- a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch +++ b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -1,7 +1,7 @@ -From be0124d69fef77370eff57cfdfb2d6eae4b0cec3 Mon Sep 17 00:00:00 2001 +From 0d8c12b68060ebfe4df4cf0d7cb1abd4c2b2243b Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 2 Mar 2022 21:50:01 +0000 -Subject: [PATCH 04/40] set me_state=Disabled on all cmos.default files! +Subject: [PATCH 04/41] set me_state=Disabled on all cmos.default files! yeah. why the hell isn't this the default diff --git a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch index 314c6932..1a300e11 100644 --- a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -1,7 +1,7 @@ -From d97018fc490daf106582b0b7885a497cc2daba5a Mon Sep 17 00:00:00 2001 +From a3bc9753261ebd534df6c6752169b3edbb588a97 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 05/40] util/ifdtool: add --nuke flag (all 0xFF on region) +Subject: [PATCH 05/41] util/ifdtool: add --nuke flag (all 0xFF on region) When this option is used, the region's contents are overwritten with all ones (0xFF). @@ -16,22 +16,22 @@ Rebased since the last revision update in lbmk. Signed-off-by: Leah Rowe --- - util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++----------- - 1 file changed, 83 insertions(+), 31 deletions(-) + util/ifdtool/ifdtool.c | 116 +++++++++++++++++++++++++++++------------ + 1 file changed, 84 insertions(+), 32 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index b21a89c0e1..fc91d4c239 100644 +index 75238c73b2..ea8dfc788d 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c -@@ -2230,6 +2230,7 @@ static void print_usage(const char *name) +@@ -2240,6 +2240,7 @@ static void print_usage(const char *name) " tgl - Tiger Lake\n" " wbg - Wellsburg\n" " -S | --setpchstrap Write a PCH strap\n" + " -N | --nuke Overwrite the specified region with 0xFF (all ones)\n" " -V | --newvalue The new value to write into PCH strap specified by -S\n" - " -v | --version: print the version\n" - " -h | --help: print this help\n\n" -@@ -2238,6 +2239,60 @@ static void print_usage(const char *name) + " -T | --topswapsize Set the Top Swap Block Size PCH strap value\n" + " Possible values: 0x10000, 0x20000, 0x40000, 0x80000,\n" +@@ -2251,6 +2252,60 @@ static void print_usage(const char *name) "\n"); } @@ -92,23 +92,23 @@ index b21a89c0e1..fc91d4c239 100644 int main(int argc, char *argv[]) { int opt, option_index = 0; -@@ -2245,6 +2300,7 @@ int main(int argc, char *argv[]) +@@ -2258,6 +2313,7 @@ int main(int argc, char *argv[]) int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; + int mode_nuke = 0; int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0; + int mode_settopswapsize = 0; char *region_type_string = NULL, *region_fname = NULL, *layout_fname = NULL; - char *new_filename = NULL; -@@ -2279,6 +2335,7 @@ int main(int argc, char *argv[]) - {"validate", 0, NULL, 't'}, +@@ -2294,6 +2350,7 @@ int main(int argc, char *argv[]) {"setpchstrap", 1, NULL, 'S'}, {"newvalue", 1, NULL, 'V'}, + {"topswapsize", 1, NULL, 'T'}, + {"nuke", 1, NULL, 'N'}, {0, 0, 0, 0} }; -@@ -2328,35 +2385,8 @@ int main(int argc, char *argv[]) +@@ -2343,35 +2400,8 @@ int main(int argc, char *argv[]) region_fname++; // Descriptor, BIOS, ME, GbE, Platform // valid type? @@ -146,10 +146,11 @@ index b21a89c0e1..fc91d4c239 100644 fprintf(stderr, "No such region type: '%s'\n\n", region_type_string); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); -@@ -2533,6 +2563,22 @@ int main(int argc, char *argv[]) - case 't': - mode_validate = 1; +@@ -2552,7 +2582,23 @@ int main(int argc, char *argv[]) + mode_settopswapsize = 1; + top_swap_size_arg = optarg; break; +- case 'v': + case 'N': + region_type_string = strdup(optarg); + if (!region_type_string) { @@ -166,12 +167,13 @@ index b21a89c0e1..fc91d4c239 100644 + } + mode_nuke = 1; + break; - case 'v': ++ Case 'v': print_version(); exit(EXIT_SUCCESS); -@@ -2552,7 +2598,8 @@ int main(int argc, char *argv[]) + break; +@@ -2571,7 +2617,8 @@ int main(int argc, char *argv[]) if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + - mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 | + mode_setstrap + mode_settopswapsize + mode_newlayout + (mode_spifreq | mode_em100 | mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + - (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) { + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status + @@ -179,9 +181,9 @@ index b21a89c0e1..fc91d4c239 100644 fprintf(stderr, "You may not specify more than one mode.\n\n"); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); exit(EXIT_FAILURE); -@@ -2561,7 +2608,8 @@ int main(int argc, char *argv[]) +@@ -2580,7 +2627,8 @@ int main(int argc, char *argv[]) if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + - mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 + + mode_setstrap + mode_settopswapsize + mode_newlayout + mode_spifreq + mode_em100 + mode_locked + mode_unlocked + mode_density + mode_altmedisable + - mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) { + mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status + @@ -189,7 +191,7 @@ index b21a89c0e1..fc91d4c239 100644 fprintf(stderr, "You need to specify a mode.\n\n"); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); exit(EXIT_FAILURE); -@@ -2674,6 +2722,10 @@ int main(int argc, char *argv[]) +@@ -2746,6 +2794,10 @@ int main(int argc, char *argv[]) write_image(new_filename, image, size); } diff --git a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch index 104df923..bcf15cf0 100644 --- a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -1,7 +1,7 @@ -From 1acdf1d0ff0c7a7ab5f2a0d7e5b57e21bdfaa1ae Mon Sep 17 00:00:00 2001 +From c3f93c58ddeb1e44daf76db9d67e33bcd2c54a62 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 06/40] mb/dell/e6400: Enable 01.0 device in devicetree for +Subject: [PATCH 06/41] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU models Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed diff --git a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch index e8c0f449..b27e013f 100644 --- a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,7 +1,7 @@ -From aab9296997bd88a86bbb40079a9caf504db81cea Mon Sep 17 00:00:00 2001 +From 9c0234bac4d37670da6831e3ff9545a0c6119237 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 07/40] Remove warning for coreboot images built without a +Subject: [PATCH 07/41] Remove warning for coreboot images built without a payload I added this in upstream to prevent people from accidentally flashing diff --git a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch index 66043dc3..e392d1f7 100644 --- a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch +++ b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch @@ -1,7 +1,7 @@ -From 319a77d9eeaaf1e344a380b1b449e6a56b3dc92c Mon Sep 17 00:00:00 2001 +From 495eab54f7c2224a0ad3da3dc79905182eca6eee Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Thu, 22 Jun 2023 16:44:27 +0300 -Subject: [PATCH 08/40] HACK: Disable coreboot related BL31 features +Subject: [PATCH 08/41] HACK: Disable coreboot related BL31 features I don't know why, but removing this BL31 make argument lets gru-kevin power off properly when shut down from Linux. Needs investigation. @@ -10,7 +10,7 @@ power off properly when shut down from Linux. Needs investigation. 1 file changed, 3 deletions(-) diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk -index f54c6d22fc..b075abfd42 100644 +index 279d31fb47..3d436179fe 100644 --- a/src/arch/arm64/Makefile.mk +++ b/src/arch/arm64/Makefile.mk @@ -162,9 +162,6 @@ BL31_MAKEARGS += LOG_LEVEL=40 diff --git a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch index 5ffd4431..f71badef 100644 --- a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch +++ b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch @@ -1,7 +1,7 @@ -From d9066d7f51d5742ae8ed1c7ab096ee857358cc48 Mon Sep 17 00:00:00 2001 +From bf464f17367c0dfa7f2c667d699800f3c6e60040 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 5 Nov 2023 11:41:41 +0000 -Subject: [PATCH 09/40] dell/e6430: use ME Soft Temporary Disable +Subject: [PATCH 09/41] dell/e6430: use ME Soft Temporary Disable i overlooked this. it's set on other boards. diff --git a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch index f093db5c..a03102e0 100644 --- a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch +++ b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch @@ -1,7 +1,7 @@ -From 922357b7d5b0b5304b0d4296b2f03961a17288a6 Mon Sep 17 00:00:00 2001 +From 5c27543224963e7fa17ad18dea27d186685e9f13 Mon Sep 17 00:00:00 2001 From: Riku Viitanen Date: Sat, 23 Dec 2023 19:02:10 +0200 -Subject: [PATCH 10/40] mb/hp: Add Compaq Elite 8300 CMT port +Subject: [PATCH 10/41] mb/hp: Add Compaq Elite 8300 CMT port Based on autoport and Z220 SuperIO code. diff --git a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch index 4c773248..abd27757 100644 --- a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch +++ b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -1,7 +1,7 @@ -From 41256272a7637426c9e68fd633ceb1c108f183c9 Mon Sep 17 00:00:00 2001 +From 062b28da685d1c9f7cbe8333e98257a83ce4ca82 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 2 Mar 2024 22:51:09 +0000 -Subject: [PATCH 11/40] nb/intel/haswell: make IOMMU a runtime option +Subject: [PATCH 11/41] nb/intel/haswell: make IOMMU a runtime option When I tested graphics cards on a coreboot port for Dell OptiPlex 9020 SFF, I could not use a graphics card unless diff --git a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch index 24b769cd..efe5f358 100644 --- a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch +++ b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -1,7 +1,7 @@ -From b243452bf1ed7c9aee1e6685091e98f52d7229c7 Mon Sep 17 00:00:00 2001 +From 5bd5bc755af744b51e0577970dc6f5214bd0cfee Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 2 Mar 2024 23:00:09 +0000 -Subject: [PATCH 12/40] dell/optiplex_9020: Disable IOMMU by default +Subject: [PATCH 12/41] dell/optiplex_9020: Disable IOMMU by default Needed to make graphics cards work. Turning it on is recommended if only using iGPU, otherwise leave it off diff --git a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch index 447693aa..84d83c77 100644 --- a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch +++ b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -1,7 +1,7 @@ -From 215661dbe631c21a2533cc93bdd1e9f82aa9601e Mon Sep 17 00:00:00 2001 +From 78da1e003a69a4cc6bd5e71e4bc43a4844d05f16 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 6 Apr 2024 01:22:47 +0100 -Subject: [PATCH 13/40] nb/haswell: Fully disable iGPU when dGPU is used +Subject: [PATCH 13/41] nb/haswell: Fully disable iGPU when dGPU is used My earlier patch disabled decode *and* disabled the iGPU itself, but a subsequent revision disabled only VGA decode. Upon revisiting, I diff --git a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch index bfbddae1..1340effa 100644 --- a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch +++ b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch @@ -1,7 +1,7 @@ -From aadef041f002b9f0504fcc67df39654680d67bdd Mon Sep 17 00:00:00 2001 +From 0a982ec4b606b6c236f71478350b69f532f30719 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Fri, 3 May 2024 11:03:32 -0600 -Subject: [PATCH 14/40] ec/dell/mec5035: Add S3 suspend SMI handler +Subject: [PATCH 14/41] ec/dell/mec5035: Add S3 suspend SMI handler This is necessary for S3 resume to work on SNB and newer Dell Latitude laptops. If a command isn't sent, the EC cuts power to the DIMMs, @@ -28,10 +28,10 @@ Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070 Signed-off-by: Nicholas Chin --- src/ec/dell/mec5035/Makefile.mk | 1 + - src/ec/dell/mec5035/mec5035.c | 14 ++++++++++++++ + src/ec/dell/mec5035/mec5035.c | 13 +++++++++++++ src/ec/dell/mec5035/mec5035.h | 22 ++++++++++++++++++++++ src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++ - 4 files changed, 54 insertions(+) + 4 files changed, 53 insertions(+) create mode 100644 src/ec/dell/mec5035/smihandler.c diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk @@ -46,13 +46,13 @@ index 4ebdd811f9..be557e4599 100644 endif diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index dffbb7960c..85c2ab0140 100644 +index 17ac2c1dab..c5067c16f6 100644 --- a/src/ec/dell/mec5035/mec5035.c +++ b/src/ec/dell/mec5035/mec5035.c -@@ -94,6 +94,20 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state) - ec_command(CMD_RADIO_CTRL); +@@ -100,6 +100,19 @@ static void mec5035_power_button_route(enum ec_power_button_route target) + write_mailbox_regs(&buf, 2, 1); + ec_command(CMD_POWER_BUTTON_TO_HOST); } - +void mec5035_change_wake(u8 source, enum ec_wake_change change) +{ + u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40}; @@ -66,15 +66,14 @@ index dffbb7960c..85c2ab0140 100644 + write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS); + ec_command(CMD_SLEEP_ENABLE); +} -+ + void mec5035_early_init(void) { - /* If this isn't sent the EC shuts down the system after about 15 diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h -index 32f791cb01..8d4fded28b 100644 +index 5fdf56631b..5cd907bf71 100644 --- a/src/ec/dell/mec5035/mec5035.h +++ b/src/ec/dell/mec5035/mec5035.h -@@ -4,12 +4,15 @@ +@@ -4,6 +4,7 @@ #define _EC_DELL_MEC5035_H_ #include @@ -82,16 +81,17 @@ index 32f791cb01..8d4fded28b 100644 #define NUM_REGISTERS 32 - enum mec5035_cmd { +@@ -11,6 +12,8 @@ enum mec5035_cmd { CMD_MOUSE_TP = 0x1a, CMD_RADIO_CTRL = 0x2b, + CMD_POWER_BUTTON_TO_HOST = 0x3e, + CMD_ACPI_WAKEUP_CHANGE = 0x4a, + CMD_SLEEP_ENABLE = 0x64, CMD_CPU_OK = 0xc2, }; -@@ -33,9 +36,28 @@ enum ec_radio_state { - RADIO_ON +@@ -39,9 +42,28 @@ enum ec_power_button_route { + HOST }; +#define ACPI_WAKEUP_NUM_ARGS 4 diff --git a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch index c1ae05be..47b32744 100644 --- a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch +++ b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch @@ -1,7 +1,7 @@ -From 4a24221fc735117e521cbd7e08d71b6e6a061517 Mon Sep 17 00:00:00 2001 +From 9ca5c919339049518e842980041f528d48d79124 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 4 May 2024 02:00:53 +0100 -Subject: [PATCH 15/40] nb/haswell: lock policy regs when disabling IOMMU +Subject: [PATCH 15/41] nb/haswell: lock policy regs when disabling IOMMU Angel Pons told me I should do it. See comments here: https://review.coreboot.org/c/coreboot/+/81016 diff --git a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch index 7537c1a6..84f3899e 100644 --- a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch +++ b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch @@ -1,7 +1,7 @@ -From 20921eb7165b23e7b78e4c4126ff5bab8725404b Mon Sep 17 00:00:00 2001 +From e74c4ee6a62ef9f91a8efb257658f627498b91fa Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 10 May 2021 22:40:59 +0200 -Subject: [PATCH 16/40] nb/intel/gm45: Make DDR2 raminit work +Subject: [PATCH 16/41] nb/intel/gm45: Make DDR2 raminit work List of changes: - Update some timing and ODT values @@ -20,7 +20,7 @@ Signed-off-by: Angel Pons 3 files changed, 106 insertions(+), 13 deletions(-) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h -index 5d9ac56606..338260ea7a 100644 +index f68bfdee7a..b76117bc3a 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo); @@ -31,9 +31,9 @@ index 5d9ac56606..338260ea7a 100644 +void raminit_rcomp_calibration(int ddr_type, stepping_t stepping); void raminit_reset_readwrite_pointers(void); void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *); - void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume); + void raminit_write_training(const mem_clock_t, const dimminfo_t *, bool s3resume); diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c -index b7e013959a..df8f46fbbc 100644 +index def9e1e331..7b091cc567 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping, @@ -70,7 +70,7 @@ index b7e013959a..df8f46fbbc 100644 } mchbar_write32(CxODT_HIGH(ch), reg); -@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) +@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume) raminit_write_training(timings->mem_clock, dimms, s3resume); } diff --git a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch index 808d90d6..87894700 100644 --- a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch +++ b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch @@ -1,7 +1,7 @@ -From b5fe5366a03f934df87c5537b12f006ccee0d695 Mon Sep 17 00:00:00 2001 +From da433a5d9a7d1d7856b55761b8392864343de5a8 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Tue, 6 Aug 2024 00:50:24 +0100 -Subject: [PATCH 17/40] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards +Subject: [PATCH 17/41] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards We add this patch: @@ -32,7 +32,7 @@ Signed-off-by: Leah Rowe 2 files changed, 88 insertions(+), 82 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c -index df8f46fbbc..433db3a68c 100644 +index 7b091cc567..478898564a 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi @@ -47,7 +47,7 @@ index df8f46fbbc..433db3a68c 100644 } else if (timings->mem_clock != MEM_CLOCK_1067MT) { reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); -@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) +@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume) raminit_write_training(timings->mem_clock, dimms, s3resume); } diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch index b537346e..4b67f8c0 100644 --- a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch +++ b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch @@ -1,7 +1,7 @@ -From c075c12d5549cc6cfaa4fbb6bb3abd5e17503b04 Mon Sep 17 00:00:00 2001 +From b4443cfe4b63a49b8170bdfb6dacbc8d52110eff Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Mon, 20 May 2024 10:24:16 -0600 -Subject: [PATCH 18/40] mb/dell/e6400: Use 100 MHz reference clock for display +Subject: [PATCH 18/41] mb/dell/e6400: Use 100 MHz reference clock for display The E6400 uses a 100 MHz reference clock for spread spectrum support on LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For @@ -19,10 +19,10 @@ Signed-off-by: Nicholas Chin 2 files changed, 6 insertions(+) diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig -index 98ad18849c..4b026be2ba 100644 +index edc79b0d43..5020744990 100644 --- a/src/mainboard/dell/gm45_latitude/Kconfig +++ b/src/mainboard/dell/gm45_latitude/Kconfig -@@ -21,6 +21,8 @@ config BOARD_DELL_E6400 +@@ -22,6 +22,8 @@ config BOARD_DELL_E6400 select BOARD_DELL_GM45_LATITUDE_COMMON if BOARD_DELL_GM45_LATITUDE_COMMON @@ -32,7 +32,7 @@ index 98ad18849c..4b026be2ba 100644 config MAINBOARD_DIR default "dell/gm45_latitude" diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig -index fef0d735b3..fc5df8b11a 100644 +index a776217475..35e89b0c88 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45 diff --git a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch index cd1c919f..061731e3 100644 --- a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch +++ b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch @@ -1,7 +1,7 @@ -From 5833266cabd5dd38596b20d3353eb7b105ffd235 Mon Sep 17 00:00:00 2001 +From d3d97fccab40cfe50eac92796bb7f16bd245b189 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 12 Aug 2024 02:15:24 +0100 -Subject: [PATCH 19/40] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ +Subject: [PATCH 19/41] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ set it to 96MHz. fixes the following build error when building for x4x boards e.g. gigabyte ga-g41m-es2l: @@ -33,7 +33,7 @@ Signed-off-by: Leah Rowe 1 file changed, 4 insertions(+) diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 097e11126c..6430319f6a 100644 +index 6fa4551957..646af3510b 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X diff --git a/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch index 3b2d59ce..b5247da2 100644 --- a/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch +++ b/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch @@ -1,7 +1,7 @@ -From 75620139fe2bd6898d51dd7bd02e1031369feeec Mon Sep 17 00:00:00 2001 +From c2a05f102ca378d8e23f0485d680845584efa290 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Thu, 26 Sep 2024 19:51:25 -0600 -Subject: [PATCH 20/40] mb/dell/gm45_latitudes: Add E4300 variant +Subject: [PATCH 20/41] mb/dell/gm45_latitudes: Add E4300 variant Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2 Signed-off-by: Nicholas Chin @@ -21,10 +21,10 @@ Signed-off-by: Nicholas Chin create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig -index 4b026be2ba..9f0f56e304 100644 +index 5020744990..d27d5728a8 100644 --- a/src/mainboard/dell/gm45_latitude/Kconfig +++ b/src/mainboard/dell/gm45_latitude/Kconfig -@@ -20,6 +20,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON +@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON config BOARD_DELL_E6400 select BOARD_DELL_GM45_LATITUDE_COMMON @@ -34,7 +34,7 @@ index 4b026be2ba..9f0f56e304 100644 if BOARD_DELL_GM45_LATITUDE_COMMON config INTEL_GMA_DPLL_REF_FREQ default 100000000 -@@ -29,12 +32,14 @@ config MAINBOARD_DIR +@@ -30,12 +33,14 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "Latitude E6400" if BOARD_DELL_E6400 diff --git a/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch index dcd75bb6..4db5b691 100644 --- a/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch +++ b/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch @@ -1,7 +1,7 @@ -From 26862554523e08ea1d1cd18cfd09e3434b12e2a3 Mon Sep 17 00:00:00 2001 +From 2305cfb93110003613caa1dec8c5f574b5e400bd Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Fri, 3 May 2024 16:31:12 -0600 -Subject: [PATCH 21/40] mb/dell: Add S3 SMI handler for Dell Latitudes +Subject: [PATCH 21/41] mb/dell: Add S3 SMI handler for Dell Latitudes Integrate the previously added mec5035_smi_sleep() function into mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240. diff --git a/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch new file mode 100644 index 00000000..766b51a3 --- /dev/null +++ b/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch @@ -0,0 +1,31 @@ +From aafddebf91f185d9c72fa1492af9128ee4803239 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 31 Dec 2024 14:42:24 +0000 +Subject: [PATCH 22/41] Disable compression on refcode insertion + +Compression is not reliably reproducible. In an lbmk release +context, this means we cannot rely on vendorfile insertion. + +Therefore, use uncompressed refcode. + +Signed-off-by: Leah Rowe +--- + Makefile.mk | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/Makefile.mk b/Makefile.mk +index 75787b32d4..3616f4fe68 100644 +--- a/Makefile.mk ++++ b/Makefile.mk +@@ -1422,7 +1422,7 @@ endif + cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode + $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB) + $(CONFIG_CBFS_PREFIX)/refcode-type := stage +-$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG) ++$(CONFIG_CBFS_PREFIX)/refcode-compression := none + + cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin + vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE) +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0022-ec-dell-mec5035-Route-power-button-event-to-host.patch b/config/coreboot/default/patches/0022-ec-dell-mec5035-Route-power-button-event-to-host.patch deleted file mode 100644 index ab85a389..00000000 --- a/config/coreboot/default/patches/0022-ec-dell-mec5035-Route-power-button-event-to-host.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 849f0aba544d135e2028092862e5f030813c868e Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Tue, 18 Jun 2024 21:31:08 -0600 -Subject: [PATCH 22/40] ec/dell/mec5035: Route power button event to host - -If command 0x3e with an argument of 1 isn't sent to the EC, pressing the -power button results in the EC powering off the system without letting -the OS cleanly shutting itself down. This command and argument tells the -EC to route power button events to the host so that it can determine -what to do. - -The EC command was identified from the ec/google/wilco code, which is -used for Dell's Latitude Chromebooks. According to the EC_GOOGLE_WILCO -Kconfig help text, those ECs run a modified version of Dell's typical -Latitude EC firmware, so it is likely that the two firmware -implementations use similar commands. Examining LPC traffic between the -host and the EC on the Latitude E6400 did reveal that the same command -was being sent by the vendor firmware to the EC, but this does not -confirm that it has the same meaning as the command from the Wilco code. -Sending the command using inb/outb calls in a userspace C program while -running coreboot without this patch did allow subsequent power button -events to be handled by the host, confirming that the command was indeed -the same. - -Change-Id: I5ded315270c0e1efbbc90cfa9d9d894b872e99a2 -Signed-off-by: Nicholas Chin ---- - src/ec/dell/mec5035/mec5035.c | 8 ++++++++ - src/ec/dell/mec5035/mec5035.h | 7 +++++++ - 2 files changed, 15 insertions(+) - -diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index 85c2ab0140..bdae929a27 100644 ---- a/src/ec/dell/mec5035/mec5035.c -+++ b/src/ec/dell/mec5035/mec5035.c -@@ -94,6 +94,13 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state) - ec_command(CMD_RADIO_CTRL); - } - -+void mec5035_power_button_route(enum ec_power_button_route target) -+{ -+ u8 buf = (u8)target; -+ write_mailbox_regs(&buf, 2, 1); -+ ec_command(CMD_POWER_BUTTON_TO_HOST); -+} -+ - void mec5035_change_wake(u8 source, enum ec_wake_change change) - { - u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40}; -@@ -121,6 +128,7 @@ static void mec5035_init(struct device *dev) - /* Unconditionally use this argument for now as this setting - is probably the most sensible default out of the 3 choices. */ - mec5035_mouse_touchpad(TP_PS2_MOUSE); -+ mec5035_power_button_route(HOST); - - pc_keyboard_init(NO_AUX_DEVICE); - -diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h -index 8d4fded28b..51422598c4 100644 ---- a/src/ec/dell/mec5035/mec5035.h -+++ b/src/ec/dell/mec5035/mec5035.h -@@ -11,6 +11,7 @@ - enum mec5035_cmd { - CMD_MOUSE_TP = 0x1a, - CMD_RADIO_CTRL = 0x2b, -+ CMD_POWER_BUTTON_TO_HOST = 0x3e, - CMD_ACPI_WAKEUP_CHANGE = 0x4a, - CMD_SLEEP_ENABLE = 0x64, - CMD_CPU_OK = 0xc2, -@@ -36,6 +37,11 @@ enum ec_radio_state { - RADIO_ON - }; - -+enum ec_power_button_route { -+ EC = 0, -+ HOST -+}; -+ - #define ACPI_WAKEUP_NUM_ARGS 4 - enum ec_wake_change { - WAKE_OFF = 0, -@@ -55,6 +61,7 @@ u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting); - void mec5035_cpu_ok(void); - void mec5035_early_init(void); - void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state); -+void mec5035_power_button_route(enum ec_power_button_route target); - void mec5035_change_wake(u8 source, enum ec_wake_change change); - void mec5035_sleep_enable(void); - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch deleted file mode 100644 index 17e630e3..00000000 --- a/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 89ecd79ab46f56c65c0b5720d1c84b12698a02b4 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 31 Dec 2024 14:42:24 +0000 -Subject: [PATCH 23/40] Disable compression on refcode insertion - -Compression is not reliably reproducible. In an lbmk release -context, this means we cannot rely on vendorfile insertion. - -Therefore, use uncompressed refcode. - -Signed-off-by: Leah Rowe ---- - Makefile.mk | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/Makefile.mk b/Makefile.mk -index 218e388bb5..a2163c4644 100644 ---- a/Makefile.mk -+++ b/Makefile.mk -@@ -1392,7 +1392,7 @@ endif - cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode - $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB) - $(CONFIG_CBFS_PREFIX)/refcode-type := stage --$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG) -+$(CONFIG_CBFS_PREFIX)/refcode-compression := none - - cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin - vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE) --- -2.47.3 - diff --git a/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch new file mode 100644 index 00000000..8746df0d --- /dev/null +++ b/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch @@ -0,0 +1,187 @@ +From 09febfb85eb176c8bf0e416412ed0b971dc2cefc Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 21 Apr 2025 02:58:47 +0100 +Subject: [PATCH 23/41] nb/intel/*: Disable stack overflow debug options + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/e7505/Kconfig | 9 +++++++++ + src/northbridge/intel/gm45/Kconfig | 9 +++++++++ + src/northbridge/intel/haswell/Kconfig | 9 +++++++++ + src/northbridge/intel/i440bx/Kconfig | 13 +++++++++++++ + src/northbridge/intel/i945/Kconfig | 9 +++++++++ + src/northbridge/intel/ironlake/Kconfig | 9 +++++++++ + src/northbridge/intel/pineview/Kconfig | 9 +++++++++ + src/northbridge/intel/sandybridge/Kconfig | 9 +++++++++ + src/northbridge/intel/x4x/Kconfig | 9 +++++++++ + 9 files changed, 85 insertions(+) + +diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig +index 039a7396f8..ddcb986f10 100644 +--- a/src/northbridge/intel/e7505/Kconfig ++++ b/src/northbridge/intel/e7505/Kconfig +@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505 + select NO_CBFS_MCACHE + select SMM_TSEG + select NEED_SMALL_2MB_PAGE_TABLES ++ ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n +diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig +index 35e89b0c88..c5456d0ddf 100644 +--- a/src/northbridge/intel/gm45/Kconfig ++++ b/src/northbridge/intel/gm45/Kconfig +@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE + config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig +index c57f1ec380..0a5181b183 100644 +--- a/src/northbridge/intel/haswell/Kconfig ++++ b/src/northbridge/intel/haswell/Kconfig +@@ -10,6 +10,15 @@ config NORTHBRIDGE_INTEL_HASWELL + + if NORTHBRIDGE_INTEL_HASWELL + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + config USE_NATIVE_RAMINIT + bool "[NOT COMPLETE] Use native raminit" + default n +diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig +index dbb2d7436b..5e9418b6a9 100644 +--- a/src/northbridge/intel/i440bx/Kconfig ++++ b/src/northbridge/intel/i440bx/Kconfig +@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM + If your board has 4 DIMM slots, you must use select this option, in + your Kconfig file of the board. On boards with 3 DIMM slots, + do _not_ select this option. ++ ++if NORTHBRIDGE_INTEL_I440BX ++ ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ ++endif +diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig +index c4e17f90bf..b12f5be091 100644 +--- a/src/northbridge/intel/i945/Kconfig ++++ b/src/northbridge/intel/i945/Kconfig +@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE + config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig +index 39566a6e5f..f46acf6937 100644 +--- a/src/northbridge/intel/ironlake/Kconfig ++++ b/src/northbridge/intel/ironlake/Kconfig +@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE + config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig +index a05b866dad..50e3a7cdb9 100644 +--- a/src/northbridge/intel/pineview/Kconfig ++++ b/src/northbridge/intel/pineview/Kconfig +@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE + config DOMAIN_RESOURCE_32BIT_LIMIT + default 0xfec00000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig +index 9972a43da0..fe4ac5106c 100644 +--- a/src/northbridge/intel/sandybridge/Kconfig ++++ b/src/northbridge/intel/sandybridge/Kconfig +@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX + default 2 if IGD_DEFAULT_UMA_SIZE_96MB + default 3 if IGD_DEFAULT_UMA_SIZE_128MB + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig +index 646af3510b..069fa0244d 100644 +--- a/src/northbridge/intel/x4x/Kconfig ++++ b/src/northbridge/intel/x4x/Kconfig +@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE + config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch new file mode 100644 index 00000000..4fa676fc --- /dev/null +++ b/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch @@ -0,0 +1,708 @@ +From 70f588b7cc66af2e427d9045d36ac2f5f4835dae Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Mon, 30 Sep 2024 20:44:38 -0400 +Subject: [PATCH 24/41] mb/dell: Add Optiplex 780 MT (x4x/ICH10) + +Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/optiplex_780/Kconfig | 40 ++++ + src/mainboard/dell/optiplex_780/Kconfig.name | 4 + + src/mainboard/dell/optiplex_780/Makefile.mk | 10 + + src/mainboard/dell/optiplex_780/acpi/ec.asl | 5 + + .../dell/optiplex_780/acpi/ich10_pci_irqs.asl | 32 ++++ + .../dell/optiplex_780/acpi/superio.asl | 18 ++ + .../dell/optiplex_780/board_info.txt | 6 + + src/mainboard/dell/optiplex_780/cmos.default | 8 + + src/mainboard/dell/optiplex_780/cmos.layout | 72 ++++++++ + src/mainboard/dell/optiplex_780/cstates.c | 8 + + src/mainboard/dell/optiplex_780/devicetree.cb | 63 +++++++ + src/mainboard/dell/optiplex_780/dsdt.asl | 26 +++ + .../dell/optiplex_780/gma-mainboard.ads | 16 ++ + .../optiplex_780/variants/780_mt/data.vbt | Bin 0 -> 1917 bytes + .../optiplex_780/variants/780_mt/early_init.c | 12 ++ + .../dell/optiplex_780/variants/780_mt/gpio.c | 174 ++++++++++++++++++ + .../optiplex_780/variants/780_mt/hda_verb.c | 26 +++ + .../variants/780_mt/overridetree.cb | 10 + + 18 files changed, 530 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_780/Kconfig + create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name + create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk + create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl + create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl + create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl + create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt + create mode 100644 src/mainboard/dell/optiplex_780/cmos.default + create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout + create mode 100644 src/mainboard/dell/optiplex_780/cstates.c + create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb + create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl + create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb + +diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig +new file mode 100644 +index 0000000000..2d06c75c9a +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/Kconfig +@@ -0,0 +1,40 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_DELL_OPTIPLEX_780_COMMON ++ def_bool n ++ select BOARD_ROMSIZE_KB_8192 ++ select CPU_INTEL_SOCKET_LGA775 ++ select DRIVERS_I2C_CK505 ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ select INTEL_GMA_HAVE_VBT ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select NORTHBRIDGE_INTEL_X4X ++ select PCIEXP_ASPM ++ select PCIEXP_CLK_PM ++ select SOUTHBRIDGE_INTEL_I82801JX ++ ++config BOARD_DELL_OPTIPLEX_780_MT ++ select BOARD_DELL_OPTIPLEX_780_COMMON ++ ++if BOARD_DELL_OPTIPLEX_780_COMMON ++ ++config VGA_BIOS_ID ++ default "8086,2e22" ++ ++config MAINBOARD_DIR ++ default "dell/optiplex_780" ++ ++config MAINBOARD_PART_NUMBER ++ default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT ++ ++config OVERRIDE_DEVICETREE ++ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" ++ ++config VARIANT_DIR ++ default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT ++ ++endif # BOARD_DELL_OPTIPLEX_780_COMMON +diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name +new file mode 100644 +index 0000000000..db7f2e8fe3 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/Kconfig.name +@@ -0,0 +1,4 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_DELL_OPTIPLEX_780_MT ++ bool "OptiPlex 780 MT" +diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk +new file mode 100644 +index 0000000000..d462995d75 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/Makefile.mk +@@ -0,0 +1,10 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++ramstage-y += cstates.c ++romstage-y += variants/$(VARIANT_DIR)/gpio.c ++ ++bootblock-y += variants/$(VARIANT_DIR)/early_init.c ++romstage-y += variants/$(VARIANT_DIR)/early_init.c ++ ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads ++ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl +new file mode 100644 +index 0000000000..479296cb76 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl +@@ -0,0 +1,5 @@ ++/* SPDX-License-Identifier: CC-PDDC */ ++ ++/* Please update the license if adding licensable material. */ ++ ++/* dummy */ +diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl +new file mode 100644 +index 0000000000..b7588dcc41 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* This is board specific information: ++ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 ++ */ ++ ++If (PICM) { ++ Return (Package() { ++ /* PCI slot */ ++ Package() { 0x0001ffff, 0, 0, 0x14}, ++ Package() { 0x0001ffff, 1, 0, 0x15}, ++ Package() { 0x0001ffff, 2, 0, 0x16}, ++ Package() { 0x0001ffff, 3, 0, 0x17}, ++ ++ Package() { 0x0002ffff, 0, 0, 0x15}, ++ Package() { 0x0002ffff, 1, 0, 0x16}, ++ Package() { 0x0002ffff, 2, 0, 0x17}, ++ Package() { 0x0002ffff, 3, 0, 0x14}, ++ }) ++} Else { ++ Return (Package() { ++ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, ++ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, ++ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, ++ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, ++ ++ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, ++ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, ++ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, ++ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, ++ }) ++} +diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl +new file mode 100644 +index 0000000000..9f3900b86c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl +@@ -0,0 +1,18 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#undef SUPERIO_DEV ++#undef SUPERIO_PNP_BASE ++#undef IT8720F_SHOW_SP1 ++#undef IT8720F_SHOW_SP2 ++#undef IT8720F_SHOW_EC ++#undef IT8720F_SHOW_KBCK ++#undef IT8720F_SHOW_KBCM ++#undef IT8720F_SHOW_GPIO ++#undef IT8720F_SHOW_CIR ++#define SUPERIO_DEV SIO0 ++#define SUPERIO_PNP_BASE 0x2e ++#define IT8720F_SHOW_EC 1 ++#define IT8720F_SHOW_KBCK 1 ++#define IT8720F_SHOW_KBCM 1 ++#define IT8720F_SHOW_GPIO 1 ++#include +diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt +new file mode 100644 +index 0000000000..aaf657b583 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/board_info.txt +@@ -0,0 +1,6 @@ ++Category: desktop ++Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1 ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y +diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default +new file mode 100644 +index 0000000000..23f0e55f3e +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/cmos.default +@@ -0,0 +1,8 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Disable ++nmi=Enable ++sata_mode=AHCI ++gfx_uma_size=64M +diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout +new file mode 100644 +index 0000000000..9f5012adb4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/cmos.layout +@@ -0,0 +1,72 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++ ++# coreboot config options: southbridge ++408 1 e 10 sata_mode ++409 2 e 7 power_on_after_fail ++411 1 e 1 nmi ++ ++# coreboot config options: cpu ++ ++# coreboot config options: northbridge ++432 4 e 11 gfx_uma_size ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++2 0 Enable ++2 1 Disable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++10 0 AHCI ++10 1 Compatible ++11 1 4M ++11 2 8M ++11 3 16M ++11 4 32M ++11 5 48M ++11 6 64M ++11 7 128M ++11 8 256M ++11 9 96M ++11 10 160M ++11 11 224M ++11 12 352M ++ ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 983 984 +diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c +new file mode 100644 +index 0000000000..4adf0edc63 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/cstates.c +@@ -0,0 +1,8 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++int get_cst_entries(const acpi_cstate_t **entries) ++{ ++ return 0; ++} +diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb +new file mode 100644 +index 0000000000..95e3bd517c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/devicetree.cb +@@ -0,0 +1,63 @@ ++# SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster ++ device domain 0 on ++ ops x4x_pci_domain_ops # PCI domain ++ subsystemid 0x8086 0x0028 inherit ++ device pci 0.0 on end # Host Bridge ++ device pci 1.0 on end # PCIe x16 2.0 slot ++ device pci 2.0 on end # Integrated graphics controller ++ device pci 2.1 on end # Integrated graphics controller 2 ++ device pci 3.0 off end # ME ++ device pci 3.1 off end # ME ++ chip southbridge/intel/i82801jx # ICH10 ++ register "gpe0_en" = "0x40" ++ ++ # Set AHCI mode. ++ register "sata_port_map" = "0x3f" ++ register "sata_clock_request" = "1" ++ ++ # Enable PCIe ports 0,1 as slots. ++ register "pcie_slot_implemented" = "0x3" ++ ++ device pci 19.0 on end # GBE ++ device pci 1a.0 on end # USB ++ device pci 1a.1 on end # USB ++ device pci 1a.2 on end # USB ++ device pci 1a.7 on end # USB ++ device pci 1b.0 on end # Audio ++ device pci 1c.0 off end # PCIe 1 ++ device pci 1c.1 off end # PCIe 2 ++ device pci 1c.2 off end # PCIe 3 ++ device pci 1c.3 off end # PCIe 4 ++ device pci 1c.4 off end # PCIe 5 ++ device pci 1c.5 off end # PCIe 6 ++ device pci 1d.0 on end # USB ++ device pci 1d.1 on end # USB ++ device pci 1d.2 on end # USB ++ device pci 1d.7 on end # USB ++ device pci 1e.0 on end # PCI bridge ++ device pci 1f.0 on end # LPC bridge ++ device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5) ++ device pci 1f.3 on # SMBus ++ chip drivers/i2c/ck505 # IDT CV194 ++ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff }" ++ register "regs" = "{ 0x15, 0x82, 0xff, 0xff, ++ 0xff, 0x00, 0x00, 0x95, ++ 0x00, 0x65, 0x7d, 0x56, ++ 0x13, 0xc0, 0x00, 0x07, ++ 0x01, 0x0a, 0x64 }" ++ device i2c 69 on end ++ end ++ end ++ device pci 1f.4 off end ++ device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode) ++ device pci 1f.6 off end # Thermal Subsystem ++ end ++ end ++end +diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl +new file mode 100644 +index 0000000000..9ad70469de +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/dsdt.asl +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20090811 // OEM revision ++) ++{ ++ #include ++ ++ OSYS = 2002 ++ // global NVS and variables ++ #include ++ ++ Device (\_SB.PCI0) ++ { ++ #include ++ #include ++ } ++ ++ #include ++} +diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads +new file mode 100644 +index 0000000000..bc81cf4a40 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads +@@ -0,0 +1,16 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (DP2, ++ Analog, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..fefda9d6f226b88ab67c5b044de30a707df22fbf +GIT binary patch +literal 1917 +zcmd6nO>7%Q6vzLwGv0Mv$FUpJ*ik4iQd_wnX*X`M0y3~p?8a$~>ZXxZMU`4dc9RGb +zTXq_i1Bwd~aNr{c4i)r(goF^M-nek+sY0sMa}Sk>xFFy_FTEfX^Y+7unt+OgkeJbX +zznS;`v-5V=o{ZwwmnN>gY?}>{`7^JBpP$l`EBIwbi0*k&aU)n@v)E +znI_A1T57efS5MGNN5_ut +zt=x`G)EjR#mlhURC^2!A3p33TcBg4-d8JyTiF&hfk}|a#&Dfe2%~V^}=4!QavNzBh +z0Pae^5`gfb?7Q)c(LsP)8 +zQy)2gwgG1S^>aw&0D}Z+-SCcJJF;s)yXJeQ|4N{SU?$I`#$HZa9dWBuxA$6X;VK;%W?Y>I;0P`|*vwAK$S(VB2JSq6g4n +z>oEf8XCt;_Y-iYBWz#3T9EmJ +z2x?*GPeN%?=Fj3+fv~4%I(nv~XF7VOqi5RsAt%13JtW>q=<<;0IkLPSUGL%_1h)2kjaZzuV;`43yCV;I=#Jcyyw@xKE8GGX39@am|0GKhH` +zawsKv^FvHqm+c8*FfFsu??w)Oed@;Mg~21%rCZ%d{x!>-zmv4AyWL1E +xfz+CGUnQ7Y^TD}&c_cQRYlBC+`?m?k6Nuw??s04gg4@4`<@FO{XEbO( ++ ++void mb_get_spd_map(u8 spd_map[4]) ++{ ++ // BTX form factor ++ spd_map[0] = 0x53; ++ spd_map[1] = 0x52; ++ spd_map[2] = 0x51; ++ spd_map[3] = 0x50; ++} +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c +new file mode 100644 +index 0000000000..9993f17c55 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c +@@ -0,0 +1,174 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_NATIVE, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_GPIO, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_NATIVE, ++ .gpio8 = GPIO_MODE_NATIVE, ++ .gpio9 = GPIO_MODE_GPIO, ++ .gpio10 = GPIO_MODE_GPIO, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_NATIVE, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_NATIVE, ++ .gpio18 = GPIO_MODE_GPIO, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_GPIO, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio5 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio9 = GPIO_DIR_OUTPUT, ++ .gpio10 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio18 = GPIO_DIR_OUTPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio20 = GPIO_DIR_OUTPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_INPUT, ++ .gpio31 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio9 = GPIO_LEVEL_HIGH, ++ .gpio18 = GPIO_LEVEL_HIGH, ++ .gpio20 = GPIO_LEVEL_HIGH, ++ .gpio28 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio13 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_GPIO, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_NATIVE, ++ .gpio52 = GPIO_MODE_NATIVE, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio32 = GPIO_DIR_INPUT, ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio35 = GPIO_DIR_OUTPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio56 = GPIO_DIR_OUTPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio35 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_HIGH, ++ .gpio56 = GPIO_LEVEL_HIGH, ++ .gpio60 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_NATIVE, ++ .gpio69 = GPIO_MODE_NATIVE, ++ .gpio70 = GPIO_MODE_NATIVE, ++ .gpio71 = GPIO_MODE_NATIVE, ++ .gpio72 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio72 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ }, ++}; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c +new file mode 100644 +index 0000000000..4158bcf899 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header */ ++ 0x11d4194a, /* Analog Devices AD1984A */ ++ 0xbfd40000, /* Subsystem ID */ ++ 10, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ AZALIA_PIN_CFG(0, 0x11, 0x032140f0), ++ AZALIA_PIN_CFG(0, 0x12, 0x21214010), ++ AZALIA_PIN_CFG(0, 0x13, 0x901701f0), ++ AZALIA_PIN_CFG(0, 0x14, 0x03a190f0), ++ AZALIA_PIN_CFG(0, 0x15, 0xb7a70121), ++ AZALIA_PIN_CFG(0, 0x16, 0x9933012e), ++ AZALIA_PIN_CFG(0, 0x17, 0x97a601f0), ++ AZALIA_PIN_CFG(0, 0x1a, 0x90f301f0), ++ AZALIA_PIN_CFG(0, 0x1b, 0x014510f0), ++ AZALIA_PIN_CFG(0, 0x1c, 0x21a19020), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb +new file mode 100644 +index 0000000000..555b1c1f5c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb +@@ -0,0 +1,10 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device domain 0 on ++ chip southbridge/intel/i82801jx ++ device pci 1c.0 on end # PCIe 1 ++ device pci 1c.1 on end # PCIe 2 ++ end ++ end ++end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch deleted file mode 100644 index cc9504e9..00000000 --- a/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch +++ /dev/null @@ -1,187 +0,0 @@ -From df60dac9dbaf0c71008dbead7dc1a8c8881c5e33 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 21 Apr 2025 02:58:47 +0100 -Subject: [PATCH 24/40] nb/intel/*: Disable stack overflow debug options - -Signed-off-by: Leah Rowe ---- - src/northbridge/intel/e7505/Kconfig | 9 +++++++++ - src/northbridge/intel/gm45/Kconfig | 9 +++++++++ - src/northbridge/intel/haswell/Kconfig | 9 +++++++++ - src/northbridge/intel/i440bx/Kconfig | 13 +++++++++++++ - src/northbridge/intel/i945/Kconfig | 9 +++++++++ - src/northbridge/intel/ironlake/Kconfig | 9 +++++++++ - src/northbridge/intel/pineview/Kconfig | 9 +++++++++ - src/northbridge/intel/sandybridge/Kconfig | 9 +++++++++ - src/northbridge/intel/x4x/Kconfig | 9 +++++++++ - 9 files changed, 85 insertions(+) - -diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig -index 039a7396f8..ddcb986f10 100644 ---- a/src/northbridge/intel/e7505/Kconfig -+++ b/src/northbridge/intel/e7505/Kconfig -@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505 - select NO_CBFS_MCACHE - select SMM_TSEG - select NEED_SMALL_2MB_PAGE_TABLES -+ -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig -index fc5df8b11a..95e3644b73 100644 ---- a/src/northbridge/intel/gm45/Kconfig -+++ b/src/northbridge/intel/gm45/Kconfig -@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE - config FIXED_EPBAR_MMIO_BASE - default 0xfed19000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig -index 6191cb6ccf..0f5b5c7241 100644 ---- a/src/northbridge/intel/haswell/Kconfig -+++ b/src/northbridge/intel/haswell/Kconfig -@@ -10,6 +10,15 @@ config NORTHBRIDGE_INTEL_HASWELL - - if NORTHBRIDGE_INTEL_HASWELL - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - config USE_NATIVE_RAMINIT - bool "[NOT COMPLETE] Use native raminit" - default n -diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig -index dbb2d7436b..5e9418b6a9 100644 ---- a/src/northbridge/intel/i440bx/Kconfig -+++ b/src/northbridge/intel/i440bx/Kconfig -@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM - If your board has 4 DIMM slots, you must use select this option, in - your Kconfig file of the board. On boards with 3 DIMM slots, - do _not_ select this option. -+ -+if NORTHBRIDGE_INTEL_I440BX -+ -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ -+endif -diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig -index 32eff1a611..9479d75c07 100644 ---- a/src/northbridge/intel/i945/Kconfig -+++ b/src/northbridge/intel/i945/Kconfig -@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE - config FIXED_EPBAR_MMIO_BASE - default 0xfed19000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig -index 2bafebf92e..16b81705bb 100644 ---- a/src/northbridge/intel/ironlake/Kconfig -+++ b/src/northbridge/intel/ironlake/Kconfig -@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE - config FIXED_EPBAR_MMIO_BASE - default 0xfed19000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig -index 59cfcd5e0a..a3ad8d3425 100644 ---- a/src/northbridge/intel/pineview/Kconfig -+++ b/src/northbridge/intel/pineview/Kconfig -@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE - config DOMAIN_RESOURCE_32BIT_LIMIT - default 0xfec00000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig -index 973eed8bbd..6387cf926d 100644 ---- a/src/northbridge/intel/sandybridge/Kconfig -+++ b/src/northbridge/intel/sandybridge/Kconfig -@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX - default 2 if IGD_DEFAULT_UMA_SIZE_96MB - default 3 if IGD_DEFAULT_UMA_SIZE_128MB - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 6430319f6a..1803ef5733 100644 ---- a/src/northbridge/intel/x4x/Kconfig -+++ b/src/northbridge/intel/x4x/Kconfig -@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE - config FIXED_EPBAR_MMIO_BASE - default 0xfed19000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif --- -2.47.3 - diff --git a/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch deleted file mode 100644 index 70bb9ae9..00000000 --- a/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch +++ /dev/null @@ -1,708 +0,0 @@ -From c3af549f5b6431475f3d180eb3b3041d9bfc5d81 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Mon, 30 Sep 2024 20:44:38 -0400 -Subject: [PATCH 25/40] mb/dell: Add Optiplex 780 MT (x4x/ICH10) - -Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/optiplex_780/Kconfig | 40 ++++ - src/mainboard/dell/optiplex_780/Kconfig.name | 4 + - src/mainboard/dell/optiplex_780/Makefile.mk | 10 + - src/mainboard/dell/optiplex_780/acpi/ec.asl | 5 + - .../dell/optiplex_780/acpi/ich10_pci_irqs.asl | 32 ++++ - .../dell/optiplex_780/acpi/superio.asl | 18 ++ - .../dell/optiplex_780/board_info.txt | 6 + - src/mainboard/dell/optiplex_780/cmos.default | 8 + - src/mainboard/dell/optiplex_780/cmos.layout | 72 ++++++++ - src/mainboard/dell/optiplex_780/cstates.c | 8 + - src/mainboard/dell/optiplex_780/devicetree.cb | 63 +++++++ - src/mainboard/dell/optiplex_780/dsdt.asl | 26 +++ - .../dell/optiplex_780/gma-mainboard.ads | 16 ++ - .../optiplex_780/variants/780_mt/data.vbt | Bin 0 -> 1917 bytes - .../optiplex_780/variants/780_mt/early_init.c | 12 ++ - .../dell/optiplex_780/variants/780_mt/gpio.c | 174 ++++++++++++++++++ - .../optiplex_780/variants/780_mt/hda_verb.c | 26 +++ - .../variants/780_mt/overridetree.cb | 10 + - 18 files changed, 530 insertions(+) - create mode 100644 src/mainboard/dell/optiplex_780/Kconfig - create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name - create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk - create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl - create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl - create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl - create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt - create mode 100644 src/mainboard/dell/optiplex_780/cmos.default - create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout - create mode 100644 src/mainboard/dell/optiplex_780/cstates.c - create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb - create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl - create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb - -diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig -new file mode 100644 -index 0000000000..2d06c75c9a ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/Kconfig -@@ -0,0 +1,40 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_DELL_OPTIPLEX_780_COMMON -+ def_bool n -+ select BOARD_ROMSIZE_KB_8192 -+ select CPU_INTEL_SOCKET_LGA775 -+ select DRIVERS_I2C_CK505 -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ select INTEL_GMA_HAVE_VBT -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_USES_IFD_GBE_REGION -+ select NORTHBRIDGE_INTEL_X4X -+ select PCIEXP_ASPM -+ select PCIEXP_CLK_PM -+ select SOUTHBRIDGE_INTEL_I82801JX -+ -+config BOARD_DELL_OPTIPLEX_780_MT -+ select BOARD_DELL_OPTIPLEX_780_COMMON -+ -+if BOARD_DELL_OPTIPLEX_780_COMMON -+ -+config VGA_BIOS_ID -+ default "8086,2e22" -+ -+config MAINBOARD_DIR -+ default "dell/optiplex_780" -+ -+config MAINBOARD_PART_NUMBER -+ default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT -+ -+config OVERRIDE_DEVICETREE -+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -+ -+config VARIANT_DIR -+ default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT -+ -+endif # BOARD_DELL_OPTIPLEX_780_COMMON -diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name -new file mode 100644 -index 0000000000..db7f2e8fe3 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/Kconfig.name -@@ -0,0 +1,4 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_DELL_OPTIPLEX_780_MT -+ bool "OptiPlex 780 MT" -diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk -new file mode 100644 -index 0000000000..d462995d75 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/Makefile.mk -@@ -0,0 +1,10 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+ramstage-y += cstates.c -+romstage-y += variants/$(VARIANT_DIR)/gpio.c -+ -+bootblock-y += variants/$(VARIANT_DIR)/early_init.c -+romstage-y += variants/$(VARIANT_DIR)/early_init.c -+ -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c -diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl -new file mode 100644 -index 0000000000..479296cb76 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl -@@ -0,0 +1,5 @@ -+/* SPDX-License-Identifier: CC-PDDC */ -+ -+/* Please update the license if adding licensable material. */ -+ -+/* dummy */ -diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl -new file mode 100644 -index 0000000000..b7588dcc41 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl -@@ -0,0 +1,32 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+/* This is board specific information: -+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 -+ */ -+ -+If (PICM) { -+ Return (Package() { -+ /* PCI slot */ -+ Package() { 0x0001ffff, 0, 0, 0x14}, -+ Package() { 0x0001ffff, 1, 0, 0x15}, -+ Package() { 0x0001ffff, 2, 0, 0x16}, -+ Package() { 0x0001ffff, 3, 0, 0x17}, -+ -+ Package() { 0x0002ffff, 0, 0, 0x15}, -+ Package() { 0x0002ffff, 1, 0, 0x16}, -+ Package() { 0x0002ffff, 2, 0, 0x17}, -+ Package() { 0x0002ffff, 3, 0, 0x14}, -+ }) -+} Else { -+ Return (Package() { -+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, -+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, -+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, -+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, -+ -+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, -+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, -+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, -+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, -+ }) -+} -diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl -new file mode 100644 -index 0000000000..9f3900b86c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl -@@ -0,0 +1,18 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#undef SUPERIO_DEV -+#undef SUPERIO_PNP_BASE -+#undef IT8720F_SHOW_SP1 -+#undef IT8720F_SHOW_SP2 -+#undef IT8720F_SHOW_EC -+#undef IT8720F_SHOW_KBCK -+#undef IT8720F_SHOW_KBCM -+#undef IT8720F_SHOW_GPIO -+#undef IT8720F_SHOW_CIR -+#define SUPERIO_DEV SIO0 -+#define SUPERIO_PNP_BASE 0x2e -+#define IT8720F_SHOW_EC 1 -+#define IT8720F_SHOW_KBCK 1 -+#define IT8720F_SHOW_KBCM 1 -+#define IT8720F_SHOW_GPIO 1 -+#include -diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt -new file mode 100644 -index 0000000000..aaf657b583 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/board_info.txt -@@ -0,0 +1,6 @@ -+Category: desktop -+Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1 -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default -new file mode 100644 -index 0000000000..23f0e55f3e ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/cmos.default -@@ -0,0 +1,8 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -+nmi=Enable -+sata_mode=AHCI -+gfx_uma_size=64M -diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout -new file mode 100644 -index 0000000000..9f5012adb4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/cmos.layout -@@ -0,0 +1,72 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+# coreboot config options: southbridge -+408 1 e 10 sata_mode -+409 2 e 7 power_on_after_fail -+411 1 e 1 nmi -+ -+# coreboot config options: cpu -+ -+# coreboot config options: northbridge -+432 4 e 11 gfx_uma_size -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+2 0 Enable -+2 1 Disable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+10 0 AHCI -+10 1 Compatible -+11 1 4M -+11 2 8M -+11 3 16M -+11 4 32M -+11 5 48M -+11 6 64M -+11 7 128M -+11 8 256M -+11 9 96M -+11 10 160M -+11 11 224M -+11 12 352M -+ -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 983 984 -diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c -new file mode 100644 -index 0000000000..4adf0edc63 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/cstates.c -@@ -0,0 +1,8 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+int get_cst_entries(const acpi_cstate_t **entries) -+{ -+ return 0; -+} -diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb -new file mode 100644 -index 0000000000..95e3bd517c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/devicetree.cb -@@ -0,0 +1,63 @@ -+# SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/x4x -+ device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster -+ device domain 0 on -+ ops x4x_pci_domain_ops # PCI domain -+ subsystemid 0x8086 0x0028 inherit -+ device pci 0.0 on end # Host Bridge -+ device pci 1.0 on end # PCIe x16 2.0 slot -+ device pci 2.0 on end # Integrated graphics controller -+ device pci 2.1 on end # Integrated graphics controller 2 -+ device pci 3.0 off end # ME -+ device pci 3.1 off end # ME -+ chip southbridge/intel/i82801jx # ICH10 -+ register "gpe0_en" = "0x40" -+ -+ # Set AHCI mode. -+ register "sata_port_map" = "0x3f" -+ register "sata_clock_request" = "1" -+ -+ # Enable PCIe ports 0,1 as slots. -+ register "pcie_slot_implemented" = "0x3" -+ -+ device pci 19.0 on end # GBE -+ device pci 1a.0 on end # USB -+ device pci 1a.1 on end # USB -+ device pci 1a.2 on end # USB -+ device pci 1a.7 on end # USB -+ device pci 1b.0 on end # Audio -+ device pci 1c.0 off end # PCIe 1 -+ device pci 1c.1 off end # PCIe 2 -+ device pci 1c.2 off end # PCIe 3 -+ device pci 1c.3 off end # PCIe 4 -+ device pci 1c.4 off end # PCIe 5 -+ device pci 1c.5 off end # PCIe 6 -+ device pci 1d.0 on end # USB -+ device pci 1d.1 on end # USB -+ device pci 1d.2 on end # USB -+ device pci 1d.7 on end # USB -+ device pci 1e.0 on end # PCI bridge -+ device pci 1f.0 on end # LPC bridge -+ device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5) -+ device pci 1f.3 on # SMBus -+ chip drivers/i2c/ck505 # IDT CV194 -+ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff }" -+ register "regs" = "{ 0x15, 0x82, 0xff, 0xff, -+ 0xff, 0x00, 0x00, 0x95, -+ 0x00, 0x65, 0x7d, 0x56, -+ 0x13, 0xc0, 0x00, 0x07, -+ 0x01, 0x0a, 0x64 }" -+ device i2c 69 on end -+ end -+ end -+ device pci 1f.4 off end -+ device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode) -+ device pci 1f.6 off end # Thermal Subsystem -+ end -+ end -+end -diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl -new file mode 100644 -index 0000000000..9ad70469de ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/dsdt.asl -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20090811 // OEM revision -+) -+{ -+ #include -+ -+ OSYS = 2002 -+ // global NVS and variables -+ #include -+ -+ Device (\_SB.PCI0) -+ { -+ #include -+ #include -+ } -+ -+ #include -+} -diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads -new file mode 100644 -index 0000000000..bc81cf4a40 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads -@@ -0,0 +1,16 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ (DP2, -+ Analog, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..fefda9d6f226b88ab67c5b044de30a707df22fbf -GIT binary patch -literal 1917 -zcmd6nO>7%Q6vzLwGv0Mv$FUpJ*ik4iQd_wnX*X`M0y3~p?8a$~>ZXxZMU`4dc9RGb -zTXq_i1Bwd~aNr{c4i)r(goF^M-nek+sY0sMa}Sk>xFFy_FTEfX^Y+7unt+OgkeJbX -zznS;`v-5V=o{ZwwmnN>gY?}>{`7^JBpP$l`EBIwbi0*k&aU)n@v)E -znI_A1T57efS5MGNN5_ut -zt=x`G)EjR#mlhURC^2!A3p33TcBg4-d8JyTiF&hfk}|a#&Dfe2%~V^}=4!QavNzBh -z0Pae^5`gfb?7Q)c(LsP)8 -zQy)2gwgG1S^>aw&0D}Z+-SCcJJF;s)yXJeQ|4N{SU?$I`#$HZa9dWBuxA$6X;VK;%W?Y>I;0P`|*vwAK$S(VB2JSq6g4n -z>oEf8XCt;_Y-iYBWz#3T9EmJ -z2x?*GPeN%?=Fj3+fv~4%I(nv~XF7VOqi5RsAt%13JtW>q=<<;0IkLPSUGL%_1h)2kjaZzuV;`43yCV;I=#Jcyyw@xKE8GGX39@am|0GKhH` -zawsKv^FvHqm+c8*FfFsu??w)Oed@;Mg~21%rCZ%d{x!>-zmv4AyWL1E -xfz+CGUnQ7Y^TD}&c_cQRYlBC+`?m?k6Nuw??s04gg4@4`<@FO{XEbO( -+ -+void mb_get_spd_map(u8 spd_map[4]) -+{ -+ // BTX form factor -+ spd_map[0] = 0x53; -+ spd_map[1] = 0x52; -+ spd_map[2] = 0x51; -+ spd_map[3] = 0x50; -+} -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c -new file mode 100644 -index 0000000000..9993f17c55 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c -@@ -0,0 +1,174 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_NATIVE, -+ .gpio1 = GPIO_MODE_NATIVE, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_GPIO, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_NATIVE, -+ .gpio8 = GPIO_MODE_NATIVE, -+ .gpio9 = GPIO_MODE_GPIO, -+ .gpio10 = GPIO_MODE_GPIO, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_NATIVE, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_NATIVE, -+ .gpio18 = GPIO_MODE_GPIO, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_GPIO, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_GPIO, -+ .gpio31 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio5 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio9 = GPIO_DIR_OUTPUT, -+ .gpio10 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio18 = GPIO_DIR_OUTPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio20 = GPIO_DIR_OUTPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_OUTPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+ .gpio30 = GPIO_DIR_INPUT, -+ .gpio31 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio9 = GPIO_LEVEL_HIGH, -+ .gpio18 = GPIO_LEVEL_HIGH, -+ .gpio20 = GPIO_LEVEL_HIGH, -+ .gpio28 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio13 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_GPIO, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_NATIVE, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_NATIVE, -+ .gpio52 = GPIO_MODE_NATIVE, -+ .gpio53 = GPIO_MODE_NATIVE, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_GPIO, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio32 = GPIO_DIR_INPUT, -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_INPUT, -+ .gpio35 = GPIO_DIR_OUTPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_OUTPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio56 = GPIO_DIR_OUTPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio35 = GPIO_LEVEL_LOW, -+ .gpio49 = GPIO_LEVEL_HIGH, -+ .gpio56 = GPIO_LEVEL_HIGH, -+ .gpio60 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_NATIVE, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_NATIVE, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_NATIVE, -+ .gpio69 = GPIO_MODE_NATIVE, -+ .gpio70 = GPIO_MODE_NATIVE, -+ .gpio71 = GPIO_MODE_NATIVE, -+ .gpio72 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio72 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ }, -+}; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c -new file mode 100644 -index 0000000000..4158bcf899 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ /* coreboot specific header */ -+ 0x11d4194a, /* Analog Devices AD1984A */ -+ 0xbfd40000, /* Subsystem ID */ -+ 10, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ AZALIA_PIN_CFG(0, 0x11, 0x032140f0), -+ AZALIA_PIN_CFG(0, 0x12, 0x21214010), -+ AZALIA_PIN_CFG(0, 0x13, 0x901701f0), -+ AZALIA_PIN_CFG(0, 0x14, 0x03a190f0), -+ AZALIA_PIN_CFG(0, 0x15, 0xb7a70121), -+ AZALIA_PIN_CFG(0, 0x16, 0x9933012e), -+ AZALIA_PIN_CFG(0, 0x17, 0x97a601f0), -+ AZALIA_PIN_CFG(0, 0x1a, 0x90f301f0), -+ AZALIA_PIN_CFG(0, 0x1b, 0x014510f0), -+ AZALIA_PIN_CFG(0, 0x1c, 0x21a19020), -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb -new file mode 100644 -index 0000000000..555b1c1f5c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb -@@ -0,0 +1,10 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/x4x -+ device domain 0 on -+ chip southbridge/intel/i82801jx -+ device pci 1c.0 on end # PCIe 1 -+ device pci 1c.1 on end # PCIe 2 -+ end -+ end -+end --- -2.47.3 - diff --git a/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch new file mode 100644 index 00000000..f5a9ce7e --- /dev/null +++ b/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch @@ -0,0 +1,326 @@ +From 463148c9773f3dd44f60c2cf2ac17900c3e68619 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Wed, 30 Oct 2024 20:55:25 -0600 +Subject: [PATCH 25/41] mb/dell/optiplex_780: Add USFF variant + +Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/optiplex_780/Kconfig | 5 + + src/mainboard/dell/optiplex_780/Kconfig.name | 3 + + .../optiplex_780/variants/780_usff/data.vbt | Bin 0 -> 1917 bytes + .../variants/780_usff/early_init.c | 9 + + .../optiplex_780/variants/780_usff/gpio.c | 166 ++++++++++++++++++ + .../optiplex_780/variants/780_usff/hda_verb.c | 26 +++ + .../variants/780_usff/overridetree.cb | 10 ++ + 7 files changed, 219 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb + +diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig +index 2d06c75c9a..fc649e35d5 100644 +--- a/src/mainboard/dell/optiplex_780/Kconfig ++++ b/src/mainboard/dell/optiplex_780/Kconfig +@@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON + config BOARD_DELL_OPTIPLEX_780_MT + select BOARD_DELL_OPTIPLEX_780_COMMON + ++config BOARD_DELL_OPTIPLEX_780_USFF ++ select BOARD_DELL_OPTIPLEX_780_COMMON ++ + if BOARD_DELL_OPTIPLEX_780_COMMON + + config VGA_BIOS_ID +@@ -30,11 +33,13 @@ config MAINBOARD_DIR + + config MAINBOARD_PART_NUMBER + default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT ++ default "OptiPlex 780 USFF" if BOARD_DELL_OPTIPLEX_780_USFF + + config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + + config VARIANT_DIR + default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT ++ default "780_usff" if BOARD_DELL_OPTIPLEX_780_USFF + + endif # BOARD_DELL_OPTIPLEX_780_COMMON +diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name +index db7f2e8fe3..bc84c82a79 100644 +--- a/src/mainboard/dell/optiplex_780/Kconfig.name ++++ b/src/mainboard/dell/optiplex_780/Kconfig.name +@@ -2,3 +2,6 @@ + + config BOARD_DELL_OPTIPLEX_780_MT + bool "OptiPlex 780 MT" ++ ++config BOARD_DELL_OPTIPLEX_780_USFF ++ bool "OptiPlex 780 USFF" +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..dbd764f285ed18f7ee9c54bc777560138bd9b5f7 +GIT binary patch +literal 1917 +zcmd6nO>7%Q6vzLwGv3{}j$^l`v7@w1q*9sEq+2(b3K>`@c5#TSx@iP+W+B10OwbsGtX=N(gc4jSGjKDkP+yIUo^nsel8$^ny^9H?td8Ra=EiCEn=G +z@6DV4?!2AdojnUv^Rirgvs$heXUkGs9S+{Jc2WPhP0buTak^BTFP@&N9-E$(UtuSX +zS{r`=b+EX|Ig`2a*^5oDdG>8jE-1BBxs`*jgrf_sj_fP;%L|PwURRcCFBMCroNRQv +zmp$2TUhc}qJMB(u#jDG@x6(N85thC4%Z=8hiN}lj&zb2~``u3C;?lCrPQOTnInFqB +zhvdwqWv?lxTb=fVEH;~RPHDPw&g*&|s$pU7!7x2mLBtAF!g>K`zPnkx!DpPHuk6{_zc*0qi7)Aet$T +z1ks@8hWS#+6cI5)j1oD86{5PX8Zu2(^OC6M`xo)V)Ow=U6P12c +z=U0uNC9T9v{)-|#h(mSX*hSA8)ZeocL7l4J&!{RSO{6~oTtyn535j!RQh#GA*wTF8 +zvasRbO~d!?*FbM3K`W?lHx=v*(jiARIhWyh4^io|;n?@1H>uqJy>0sjV-Dt)_=%bE +zgNO3D@uE5m+7aqi?Y8b+inye%Z=HUmgBtaZ3Lc%OLt+bo+)5BjVwT<{mxT`nde$vb +zV99s{>`r76L#Hr6XW6r|>HT47I`**Q#Vu0QW!^VP-9S{xXzpq_zS#9k-;aXz?b+S!Ne$Kkk6dq&Hj-x+kx1W-4#E&beDT*S)=&NoSE?<-w!G@~aW()0ZN4O&=Q+nZa)p%Vd$k-_$a= +T#w3FFBiyj ++ ++void mb_get_spd_map(u8 spd_map[4]) ++{ ++ spd_map[0] = 0x50; ++ spd_map[2] = 0x52; ++} +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c +new file mode 100644 +index 0000000000..389f4077d7 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c +@@ -0,0 +1,166 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_NATIVE, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_GPIO, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_NATIVE, ++ .gpio8 = GPIO_MODE_NATIVE, ++ .gpio9 = GPIO_MODE_GPIO, ++ .gpio10 = GPIO_MODE_GPIO, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_NATIVE, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_NATIVE, ++ .gpio18 = GPIO_MODE_GPIO, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_GPIO, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio5 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio9 = GPIO_DIR_OUTPUT, ++ .gpio10 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio18 = GPIO_DIR_OUTPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio20 = GPIO_DIR_OUTPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_INPUT, ++ .gpio31 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio9 = GPIO_LEVEL_HIGH, ++ .gpio18 = GPIO_LEVEL_HIGH, ++ .gpio20 = GPIO_LEVEL_HIGH, ++ .gpio28 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio13 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_GPIO, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_NATIVE, ++ .gpio52 = GPIO_MODE_NATIVE, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio32 = GPIO_DIR_INPUT, ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio35 = GPIO_DIR_OUTPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio56 = GPIO_DIR_OUTPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio35 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_HIGH, ++ .gpio56 = GPIO_LEVEL_HIGH, ++ .gpio60 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio72 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio72 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ }, ++}; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c +new file mode 100644 +index 0000000000..c94e06b156 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header */ ++ 0x11d4194a, /* Analog Devices AD1984A */ ++ 0x10280420, /* Subsystem ID */ ++ 10, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ AZALIA_PIN_CFG(0, 0x11, 0x02214040), ++ AZALIA_PIN_CFG(0, 0x12, 0x01014010), ++ AZALIA_PIN_CFG(0, 0x13, 0x991301f0), ++ AZALIA_PIN_CFG(0, 0x14, 0x02a19020), ++ AZALIA_PIN_CFG(0, 0x15, 0x01813030), ++ AZALIA_PIN_CFG(0, 0x16, 0x413301f0), ++ AZALIA_PIN_CFG(0, 0x17, 0x41a601f0), ++ AZALIA_PIN_CFG(0, 0x1a, 0x41f301f0), ++ AZALIA_PIN_CFG(0, 0x1b, 0x414501f0), ++ AZALIA_PIN_CFG(0, 0x1c, 0x413301f0), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb +new file mode 100644 +index 0000000000..555b1c1f5c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb +@@ -0,0 +1,10 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device domain 0 on ++ chip southbridge/intel/i82801jx ++ device pci 1c.0 on end # PCIe 1 ++ device pci 1c.1 on end # PCIe 2 ++ end ++ end ++end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch deleted file mode 100644 index 231e303e..00000000 --- a/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch +++ /dev/null @@ -1,326 +0,0 @@ -From bb14741af8e4a16d3d098d79fb8df0c3a45e6ccb Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Wed, 30 Oct 2024 20:55:25 -0600 -Subject: [PATCH 26/40] mb/dell/optiplex_780: Add USFF variant - -Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/optiplex_780/Kconfig | 5 + - src/mainboard/dell/optiplex_780/Kconfig.name | 3 + - .../optiplex_780/variants/780_usff/data.vbt | Bin 0 -> 1917 bytes - .../variants/780_usff/early_init.c | 9 + - .../optiplex_780/variants/780_usff/gpio.c | 166 ++++++++++++++++++ - .../optiplex_780/variants/780_usff/hda_verb.c | 26 +++ - .../variants/780_usff/overridetree.cb | 10 ++ - 7 files changed, 219 insertions(+) - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb - -diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig -index 2d06c75c9a..fc649e35d5 100644 ---- a/src/mainboard/dell/optiplex_780/Kconfig -+++ b/src/mainboard/dell/optiplex_780/Kconfig -@@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON - config BOARD_DELL_OPTIPLEX_780_MT - select BOARD_DELL_OPTIPLEX_780_COMMON - -+config BOARD_DELL_OPTIPLEX_780_USFF -+ select BOARD_DELL_OPTIPLEX_780_COMMON -+ - if BOARD_DELL_OPTIPLEX_780_COMMON - - config VGA_BIOS_ID -@@ -30,11 +33,13 @@ config MAINBOARD_DIR - - config MAINBOARD_PART_NUMBER - default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT -+ default "OptiPlex 780 USFF" if BOARD_DELL_OPTIPLEX_780_USFF - - config OVERRIDE_DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" - - config VARIANT_DIR - default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT -+ default "780_usff" if BOARD_DELL_OPTIPLEX_780_USFF - - endif # BOARD_DELL_OPTIPLEX_780_COMMON -diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name -index db7f2e8fe3..bc84c82a79 100644 ---- a/src/mainboard/dell/optiplex_780/Kconfig.name -+++ b/src/mainboard/dell/optiplex_780/Kconfig.name -@@ -2,3 +2,6 @@ - - config BOARD_DELL_OPTIPLEX_780_MT - bool "OptiPlex 780 MT" -+ -+config BOARD_DELL_OPTIPLEX_780_USFF -+ bool "OptiPlex 780 USFF" -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..dbd764f285ed18f7ee9c54bc777560138bd9b5f7 -GIT binary patch -literal 1917 -zcmd6nO>7%Q6vzLwGv3{}j$^l`v7@w1q*9sEq+2(b3K>`@c5#TSx@iP+W+B10OwbsGtX=N(gc4jSGjKDkP+yIUo^nsel8$^ny^9H?td8Ra=EiCEn=G -z@6DV4?!2AdojnUv^Rirgvs$heXUkGs9S+{Jc2WPhP0buTak^BTFP@&N9-E$(UtuSX -zS{r`=b+EX|Ig`2a*^5oDdG>8jE-1BBxs`*jgrf_sj_fP;%L|PwURRcCFBMCroNRQv -zmp$2TUhc}qJMB(u#jDG@x6(N85thC4%Z=8hiN}lj&zb2~``u3C;?lCrPQOTnInFqB -zhvdwqWv?lxTb=fVEH;~RPHDPw&g*&|s$pU7!7x2mLBtAF!g>K`zPnkx!DpPHuk6{_zc*0qi7)Aet$T -z1ks@8hWS#+6cI5)j1oD86{5PX8Zu2(^OC6M`xo)V)Ow=U6P12c -z=U0uNC9T9v{)-|#h(mSX*hSA8)ZeocL7l4J&!{RSO{6~oTtyn535j!RQh#GA*wTF8 -zvasRbO~d!?*FbM3K`W?lHx=v*(jiARIhWyh4^io|;n?@1H>uqJy>0sjV-Dt)_=%bE -zgNO3D@uE5m+7aqi?Y8b+inye%Z=HUmgBtaZ3Lc%OLt+bo+)5BjVwT<{mxT`nde$vb -zV99s{>`r76L#Hr6XW6r|>HT47I`**Q#Vu0QW!^VP-9S{xXzpq_zS#9k-;aXz?b+S!Ne$Kkk6dq&Hj-x+kx1W-4#E&beDT*S)=&NoSE?<-w!G@~aW()0ZN4O&=Q+nZa)p%Vd$k-_$a= -T#w3FFBiyj -+ -+void mb_get_spd_map(u8 spd_map[4]) -+{ -+ spd_map[0] = 0x50; -+ spd_map[2] = 0x52; -+} -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c -new file mode 100644 -index 0000000000..389f4077d7 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c -@@ -0,0 +1,166 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_NATIVE, -+ .gpio1 = GPIO_MODE_NATIVE, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_GPIO, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_NATIVE, -+ .gpio8 = GPIO_MODE_NATIVE, -+ .gpio9 = GPIO_MODE_GPIO, -+ .gpio10 = GPIO_MODE_GPIO, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_NATIVE, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_NATIVE, -+ .gpio18 = GPIO_MODE_GPIO, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_GPIO, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_GPIO, -+ .gpio31 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio5 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio9 = GPIO_DIR_OUTPUT, -+ .gpio10 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio18 = GPIO_DIR_OUTPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio20 = GPIO_DIR_OUTPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_OUTPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+ .gpio30 = GPIO_DIR_INPUT, -+ .gpio31 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio9 = GPIO_LEVEL_HIGH, -+ .gpio18 = GPIO_LEVEL_HIGH, -+ .gpio20 = GPIO_LEVEL_HIGH, -+ .gpio28 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio13 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_GPIO, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_NATIVE, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_NATIVE, -+ .gpio52 = GPIO_MODE_NATIVE, -+ .gpio53 = GPIO_MODE_NATIVE, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_GPIO, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio32 = GPIO_DIR_INPUT, -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_INPUT, -+ .gpio35 = GPIO_DIR_OUTPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_OUTPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio56 = GPIO_DIR_OUTPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio35 = GPIO_LEVEL_LOW, -+ .gpio49 = GPIO_LEVEL_HIGH, -+ .gpio56 = GPIO_LEVEL_HIGH, -+ .gpio60 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio72 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio72 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ }, -+}; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c -new file mode 100644 -index 0000000000..c94e06b156 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ /* coreboot specific header */ -+ 0x11d4194a, /* Analog Devices AD1984A */ -+ 0x10280420, /* Subsystem ID */ -+ 10, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ AZALIA_PIN_CFG(0, 0x11, 0x02214040), -+ AZALIA_PIN_CFG(0, 0x12, 0x01014010), -+ AZALIA_PIN_CFG(0, 0x13, 0x991301f0), -+ AZALIA_PIN_CFG(0, 0x14, 0x02a19020), -+ AZALIA_PIN_CFG(0, 0x15, 0x01813030), -+ AZALIA_PIN_CFG(0, 0x16, 0x413301f0), -+ AZALIA_PIN_CFG(0, 0x17, 0x41a601f0), -+ AZALIA_PIN_CFG(0, 0x1a, 0x41f301f0), -+ AZALIA_PIN_CFG(0, 0x1b, 0x414501f0), -+ AZALIA_PIN_CFG(0, 0x1c, 0x413301f0), -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb -new file mode 100644 -index 0000000000..555b1c1f5c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb -@@ -0,0 +1,10 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/x4x -+ device domain 0 on -+ chip southbridge/intel/i82801jx -+ device pci 1c.0 on end # PCIe 1 -+ device pci 1c.1 on end # PCIe 2 -+ end -+ end -+end --- -2.47.3 - diff --git a/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch new file mode 100644 index 00000000..9769c7e9 --- /dev/null +++ b/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch @@ -0,0 +1,33 @@ +From bf3c3df864cae045c82d1c032ced834a60239401 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 6 Jan 2025 01:53:53 +0000 +Subject: [PATCH 26/41] src/intel/x4x: Disable stack overflow debug + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/x4x/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig +index 069fa0244d..8c70344846 100644 +--- a/src/northbridge/intel/x4x/Kconfig ++++ b/src/northbridge/intel/x4x/Kconfig +@@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER + int + default 256 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + # This number must be equal or lower than what's reported in ACPI PCI _CRS + config DOMAIN_RESOURCE_32BIT_LIMIT + default 0xfec00000 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch new file mode 100644 index 00000000..d91857a9 --- /dev/null +++ b/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch @@ -0,0 +1,42 @@ +From 0ad074869ec2a25508b1d6fc97c6ce61a9982fbd Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 22 Apr 2025 10:21:59 +0100 +Subject: [PATCH 27/41] hp/8300cmt: remove xhci_overcurrent_mapping + +No longer needed, as per the following commit: + +commit a3d1e6c4806e6c0e2e744be3a03fce12f21778d1 +Author: Keith Hui +Date: Tue Dec 31 18:19:31 2024 -0500 + + sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping + +Removing this from the devicetree also allows the +board to compile, otherwise an error is thrown: + +build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:10: error: 'const struct southbridge_intel_bd82x6x_config' has no member named 'xhci_overcurrent_mapping' + 147 | .xhci_overcurrent_mapping = 0x00000c03, + | ^~~~~~~~~~~~~~~~~~~~~~~~ +build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:37: error: excess elements in struct initializer [-Werror] + 147 | .xhci_overcurrent_mapping = 0x00000c03, + +Signed-off-by: Leah Rowe +--- + src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb +index 3d21739b72..3a0b6d5c59 100644 +--- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb +@@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" +- register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 0, 0 }, +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch deleted file mode 100644 index 94186a30..00000000 --- a/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 1685de1beee49456e9f6f578ca6e37219fe7dfff Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 6 Jan 2025 01:53:53 +0000 -Subject: [PATCH 27/40] src/intel/x4x: Disable stack overflow debug - -Signed-off-by: Leah Rowe ---- - src/northbridge/intel/x4x/Kconfig | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 1803ef5733..7129aabf72 100644 ---- a/src/northbridge/intel/x4x/Kconfig -+++ b/src/northbridge/intel/x4x/Kconfig -@@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER - int - default 256 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - # This number must be equal or lower than what's reported in ACPI PCI _CRS - config DOMAIN_RESOURCE_32BIT_LIMIT - default 0xfec00000 --- -2.47.3 - diff --git a/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch b/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch new file mode 100644 index 00000000..b634e107 --- /dev/null +++ b/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch @@ -0,0 +1,47 @@ +From 4739f197ee3d4c95809ba48671bc5c409766b9c7 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Wed, 11 Dec 2024 01:06:01 +0000 +Subject: [PATCH 28/41] dell/3050micro: disable nvme hotplug + +in my testing, when running my 3050micro for a few days, +the nvme would sometimes randomly rename. + +e.g. nvme0n1 renamed to nvme0n2 + +this might cause crashes in linux, if booting only from the +nvme. in my case, i was booting from mdraid (sata+nvme) and +every few days, the nvme would rename at least once, causing +my RAID to become unsynced. since i'm using RAID1, this was +OK and I could simply re-sync the array, but this is quite +precarious indeed. if you're using raid0, that will potentially +corrupt your RAID array indefinitely. + +this same issue manifested on the T480/T480 thinkpads, and +S3 resume would break because of that, when booting from nvme, +because the nvme would be "unplugged" and appear to linux as a +new device (the one that you booted from). + +the fix there was to disable hotplugging on that pci-e slot +for the nvme, so apply the same fix here for 3050 micro + +Signed-off-by: Leah Rowe +--- + .../dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb +index c5f1749b2c..ff48a8121a 100644 +--- a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb ++++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb +@@ -46,7 +46,7 @@ chip soc/intel/skylake + register "PcieRpAdvancedErrorReporting[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" + register "PcieRpClkSrcNumber[20]" = "3" +- register "PcieRpHotPlug[20]" = "1" ++ register "PcieRpHotPlug[20]" = "0" + end + + end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch deleted file mode 100644 index c42b3cf0..00000000 --- a/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 6f54ed4b0622c7772561760ea4b435bd236ac834 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 22 Apr 2025 10:21:59 +0100 -Subject: [PATCH 28/40] hp/8300cmt: remove xhci_overcurrent_mapping - -No longer needed, as per the following commit: - -commit a3d1e6c4806e6c0e2e744be3a03fce12f21778d1 -Author: Keith Hui -Date: Tue Dec 31 18:19:31 2024 -0500 - - sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping - -Removing this from the devicetree also allows the -board to compile, otherwise an error is thrown: - -build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:10: error: 'const struct southbridge_intel_bd82x6x_config' has no member named 'xhci_overcurrent_mapping' - 147 | .xhci_overcurrent_mapping = 0x00000c03, - | ^~~~~~~~~~~~~~~~~~~~~~~~ -build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:37: error: excess elements in struct initializer [-Werror] - 147 | .xhci_overcurrent_mapping = 0x00000c03, - -Signed-off-by: Leah Rowe ---- - src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -index 3d21739b72..3a0b6d5c59 100644 ---- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -@@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - register "superspeed_capable_ports" = "0x0000000f" -- register "xhci_overcurrent_mapping" = "0x00000c03" - register "xhci_switchable_ports" = "0x0000000f" - register "usb_port_config" = "{ - { 1, 0, 0 }, --- -2.47.3 - diff --git a/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch b/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch deleted file mode 100644 index 4b036e02..00000000 --- a/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 17c67799604e0e29192415e97293d71deb457cb2 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Wed, 11 Dec 2024 01:06:01 +0000 -Subject: [PATCH 29/40] dell/3050micro: disable nvme hotplug - -in my testing, when running my 3050micro for a few days, -the nvme would sometimes randomly rename. - -e.g. nvme0n1 renamed to nvme0n2 - -this might cause crashes in linux, if booting only from the -nvme. in my case, i was booting from mdraid (sata+nvme) and -every few days, the nvme would rename at least once, causing -my RAID to become unsynced. since i'm using RAID1, this was -OK and I could simply re-sync the array, but this is quite -precarious indeed. if you're using raid0, that will potentially -corrupt your RAID array indefinitely. - -this same issue manifested on the T480/T480 thinkpads, and -S3 resume would break because of that, when booting from nvme, -because the nvme would be "unplugged" and appear to linux as a -new device (the one that you booted from). - -the fix there was to disable hotplugging on that pci-e slot -for the nvme, so apply the same fix here for 3050 micro - -Signed-off-by: Leah Rowe ---- - src/mainboard/dell/optiplex_3050/devicetree.cb | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb -index 0d2adff74a..829acacab3 100644 ---- a/src/mainboard/dell/optiplex_3050/devicetree.cb -+++ b/src/mainboard/dell/optiplex_3050/devicetree.cb -@@ -44,7 +44,9 @@ chip soc/intel/skylake - register "PcieRpAdvancedErrorReporting[20]" = "1" - register "PcieRpLtrEnable[20]" = "true" - register "PcieRpClkSrcNumber[20]" = "3" -- register "PcieRpHotPlug[20]" = "1" -+# disable hotplug on nvme to prevent renaming e.g. nvme0n1 rename to nvme0n2, -+# which could cause crashes in linux if booting from nvme -+ register "PcieRpHotPlug[20]" = "0" - end - - # Realtek LAN --- -2.47.3 - diff --git a/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch new file mode 100644 index 00000000..f3864a23 --- /dev/null +++ b/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch @@ -0,0 +1,61 @@ +From a6fdf61bb4779775fa330fc3f9b79be651c6854a Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 6 Jan 2025 01:36:23 +0000 +Subject: [PATCH 29/41] src/intel/skylake: Disable stack overflow debug options + +The option was appearing in T480/3050micro configs of lbmk, +after updating on the coreboot/next uprev for 20241206 rev8: + +CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y + +I did some digging. See coreboot commit: + +commit 51cc2bacb6b07279b97e9934d079060475481fb6 +Author: Subrata Banik +Date: Fri Dec 13 13:07:28 2024 +0530 + + soc/intel/pantherlake: Disable stack overflow debug options + +Well now: + +I'm disabling this behaviour on Skylake, for the same +behaviour, because I want as few behaviour changes in general, +as possible, for the rev8 release. + +According to Subrata's patch, which was for Pantherlake, +without this change, stack corruption can occur on verstage +and romstage early on. Please look at that coreboot patch, +referenced above, for clarity. + +I see no harm in disabling this option for Skylake, since +the behaviour that it otherwise enables was not present +before. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/skylake/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig +index 7c530f2c75..70c2a7643c 100644 +--- a/src/soc/intel/skylake/Kconfig ++++ b/src/soc/intel/skylake/Kconfig +@@ -131,6 +131,15 @@ config DCACHE_RAM_SIZE + The size of the cache-as-ram region required during bootblock + and/or romstage. + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + config DCACHE_BSP_STACK_SIZE + hex + default 0x20400 if FSP_USES_CB_STACK +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch new file mode 100644 index 00000000..b886e90e --- /dev/null +++ b/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch @@ -0,0 +1,36 @@ +From 287a6d09ac6f5cdfc8255c2020e37441ddb870c7 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Thu, 26 Dec 2024 19:45:20 +0000 +Subject: [PATCH 30/41] soc/intel/skylake: Don't compress FSP-S + +Build systems like lbmk need to reproducibly insert +certain vendor files on release images. + +Compression isn't always reproducible, and making it +so costs a lot more time than simply disabling compression. + +With this change, the FSP-S module will now be inserted +without compression, which means that there will now be +about 40KB of extra space used in the flash. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/skylake/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig +index 70c2a7643c..a2854923e7 100644 +--- a/src/soc/intel/skylake/Kconfig ++++ b/src/soc/intel/skylake/Kconfig +@@ -14,7 +14,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE + select DRAM_SUPPORT_DDR4 + select DRIVERS_USB_ACPI + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 +- select FSP_COMPRESS_FSP_S_LZ4 ++# select FSP_COMPRESS_FSP_S_LZ4 + select FSP_M_XIP + select GENERIC_GPIO_LIB + select HAVE_FSP_GOP +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0030-soc-intel-skylake-configure-usb-acpi.patch b/config/coreboot/default/patches/0030-soc-intel-skylake-configure-usb-acpi.patch deleted file mode 100644 index 8a328251..00000000 --- a/config/coreboot/default/patches/0030-soc-intel-skylake-configure-usb-acpi.patch +++ /dev/null @@ -1,94 +0,0 @@ -From 819fe0e89e426d3d875cf8ab4d2de439ba716848 Mon Sep 17 00:00:00 2001 -From: Felix Singer -Date: Wed, 26 Jun 2024 04:24:31 +0200 -Subject: [PATCH 30/40] soc/intel/skylake: configure usb acpi - -Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d -Signed-off-by: Felix Singer ---- - src/soc/intel/skylake/Kconfig | 1 + - src/soc/intel/skylake/chipset.cb | 56 +++++++++++++++++++++++++++++++- - 2 files changed, 56 insertions(+), 1 deletion(-) - -diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 4ad33496b2..9191ed0ff8 100644 ---- a/src/soc/intel/skylake/Kconfig -+++ b/src/soc/intel/skylake/Kconfig -@@ -10,6 +10,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE - select CPU_INTEL_COMMON - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select CPU_SUPPORTS_PM_TIMER_EMULATION -+ select DRIVERS_USB_ACPI - select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 - select FSP_COMPRESS_FSP_S_LZ4 - select FSP_M_XIP -diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb -index 6538a1475b..dfb81d496e 100644 ---- a/src/soc/intel/skylake/chipset.cb -+++ b/src/soc/intel/skylake/chipset.cb -@@ -13,7 +13,61 @@ chip soc/intel/skylake - device pci 07.0 alias chap off end - device pci 08.0 alias gmm off end # Gaussian Mixture Model - device pci 13.0 alias ish off end # SensorHub -- device pci 14.0 alias south_xhci off ops usb_xhci_ops end -+ device pci 14.0 alias south_xhci off ops usb_xhci_ops -+ chip drivers/usb/acpi -+ register "type" = "UPC_TYPE_HUB" -+ device usb 0.0 alias xhci_root_hub off -+ chip drivers/usb/acpi -+ device usb 2.0 alias usb2_port1 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.1 alias usb2_port2 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.2 alias usb2_port3 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.3 alias usb2_port4 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.4 alias usb2_port5 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.5 alias usb2_port6 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.6 alias usb2_port7 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.7 alias usb2_port8 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.8 alias usb2_port9 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.9 alias usb2_port10 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.0 alias usb3_port1 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.1 alias usb3_port2 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.2 alias usb3_port3 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.3 alias usb3_port4 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.4 alias usb3_port5 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.5 alias usb3_port6 off end -+ end -+ end -+ end -+ end - device pci 14.1 alias south_xdci off ops usb_xdci_ops end - device pci 14.2 alias thermal off end - device pci 14.3 alias cio off end --- -2.47.3 - diff --git a/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch new file mode 100644 index 00000000..bf878964 --- /dev/null +++ b/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch @@ -0,0 +1,78 @@ +From c0bb0e62f169e07ab11c434fbd79a6a26b4e7690 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Wed, 18 Dec 2024 02:06:18 +0000 +Subject: [PATCH 31/41] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN + +This is used by lbmk to know where a tb.bin file goes, +when extracting and padding TBT.bin from Lenovo ThunderBolt +firmware updates on T480/T480s and other machines, grabbing +Lenovo update files. + +Not used in any builds, so it's not relevant for ./mk inject + +However, the ThunderBolt firmware is now auto-downloaded on +T480/T480s. This is not inserted, because it doesn't go in +the main flash, but the resulting ROM image can be flashed +on the TB controller's separate flash chip. + +Locations are as follows: + +vendorfiles/t480s/tb.bin +vendorfiles/t480/tb.bin + +This can be used for other affected ThinkPads when they're +added to Libreboot, but note that Lenovo provides different +TB firmware files for each machine. + +Since I assume it's the same TB controller on all of those +machines, I have to wonder: what difference is there between +the various TBT.bin files provided by Lenovo, and how do they +differ in terms of actual flashed configuration? + +We simply flash the padded TBT.bin when updating the firmware, +flashing externally. That's what this patch is for, so that +lbmk can auto-download them. + +Signed-off-by: Leah Rowe +--- + src/mainboard/lenovo/Kconfig | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig +index 2ffbaab85f..512b326381 100644 +--- a/src/mainboard/lenovo/Kconfig ++++ b/src/mainboard/lenovo/Kconfig +@@ -18,4 +18,30 @@ config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + ++config LENOVO_TBFW_BIN ++ string "Lenovo ThunderBolt firmware bin file" ++ default "" ++ help ++ ThunderBolt firmware for certain ThinkPad models e.g. T480. ++ Not used in the actual build. Libreboot's build system uses this ++ along with config/vendor/*/pkg.cfg entries defining a URL to the ++ Lenovo download link and hash. The resulting file when processed by ++ lbmk can be flashed to the ThunderBolt firmware's 25XX NOR device. ++ Earlier versions of this firmware had debug commands enabled that ++ sent logs to said flash IC, and it would quickly fill up, bricking ++ the ThunderBolt controller. With these updates, flashed externally, ++ you can fix the issue if present or otherwise prevent it. The benefit ++ here is that you then don't need to use Windows or a boot disk. You ++ can flash the TB firmware while flashing Libreboot firmware. Easy! ++ Look for these variables in lbmk: ++ TBFW_url TBFW_url_bkup TBFW_hash and look at how it handles that and ++ CONFIG_LENOVO_TBFW_BIN, in lbmk's include/vendor.sh file. ++ The path set by CONFIG_LENOVO_TBFW_BIN is used by lbmk when extracting ++ the firmware, putting it at that desired location. In this way, lbmk ++ can auto-download such firmware. E.g. ./mk -d coreboot t480_fsp_16mb ++ and it appears at vendorfiles/t480/tb.bin fully padded and everything! ++ ++ Just leave this blank if you don't care about this option. It's not ++ useful for every ThinkPad, only certain models. ++ + endif # VENDOR_LENOVO +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0031-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0031-src-intel-skylake-Disable-stack-overflow-debug-optio.patch deleted file mode 100644 index 916e54dc..00000000 --- a/config/coreboot/default/patches/0031-src-intel-skylake-Disable-stack-overflow-debug-optio.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 7194444fbddcf6567d0c82f0986e5deeacaea680 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 6 Jan 2025 01:36:23 +0000 -Subject: [PATCH 31/40] src/intel/skylake: Disable stack overflow debug options - -The option was appearing in T480/3050micro configs of lbmk, -after updating on the coreboot/next uprev for 20241206 rev8: - -CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y - -I did some digging. See coreboot commit: - -commit 51cc2bacb6b07279b97e9934d079060475481fb6 -Author: Subrata Banik -Date: Fri Dec 13 13:07:28 2024 +0530 - - soc/intel/pantherlake: Disable stack overflow debug options - -Well now: - -I'm disabling this behaviour on Skylake, for the same -behaviour, because I want as few behaviour changes in general, -as possible, for the rev8 release. - -According to Subrata's patch, which was for Pantherlake, -without this change, stack corruption can occur on verstage -and romstage early on. Please look at that coreboot patch, -referenced above, for clarity. - -I see no harm in disabling this option for Skylake, since -the behaviour that it otherwise enables was not present -before. - -Signed-off-by: Leah Rowe ---- - src/soc/intel/skylake/Kconfig | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 9191ed0ff8..493a2d835a 100644 ---- a/src/soc/intel/skylake/Kconfig -+++ b/src/soc/intel/skylake/Kconfig -@@ -129,6 +129,15 @@ config DCACHE_RAM_SIZE - The size of the cache-as-ram region required during bootblock - and/or romstage. - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - config DCACHE_BSP_STACK_SIZE - hex - default 0x20400 if FSP_USES_CB_STACK --- -2.47.3 - diff --git a/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch b/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch new file mode 100644 index 00000000..ec1bce88 --- /dev/null +++ b/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch @@ -0,0 +1,37 @@ +From c25cf16fb0d278354c7e2c19f534a04e27ac46dd Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 21 Apr 2025 05:14:45 +0100 +Subject: [PATCH 32/41] Conditional TBFW setting for kabylake thinkpads + +Otherwise, other boards will define it, which +might trigger the vendor download script, and +lead to a non-zero exit. + +Signed-off-by: Leah Rowe +--- + src/mainboard/lenovo/Kconfig | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig +index 512b326381..b2c7763198 100644 +--- a/src/mainboard/lenovo/Kconfig ++++ b/src/mainboard/lenovo/Kconfig +@@ -18,6 +18,8 @@ config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + ++if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580 ++ + config LENOVO_TBFW_BIN + string "Lenovo ThunderBolt firmware bin file" + default "" +@@ -44,4 +46,6 @@ config LENOVO_TBFW_BIN + Just leave this blank if you don't care about this option. It's not + useful for every ThinkPad, only certain models. + ++endif # BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580 ++ + endif # VENDOR_LENOVO +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0032-soc-intel-skylake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0032-soc-intel-skylake-Don-t-compress-FSP-S.patch deleted file mode 100644 index cd1ed452..00000000 --- a/config/coreboot/default/patches/0032-soc-intel-skylake-Don-t-compress-FSP-S.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 81360b8c28293856e964934d1f356b1312b39ff2 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Thu, 26 Dec 2024 19:45:20 +0000 -Subject: [PATCH 32/40] soc/intel/skylake: Don't compress FSP-S - -Build systems like lbmk need to reproducibly insert -certain vendor files on release images. - -Compression isn't always reproducible, and making it -so costs a lot more time than simply disabling compression. - -With this change, the FSP-S module will now be inserted -without compression, which means that there will now be -about 40KB of extra space used in the flash. - -Signed-off-by: Leah Rowe ---- - src/soc/intel/skylake/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 493a2d835a..42af82a5d8 100644 ---- a/src/soc/intel/skylake/Kconfig -+++ b/src/soc/intel/skylake/Kconfig -@@ -12,7 +12,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE - select CPU_SUPPORTS_PM_TIMER_EMULATION - select DRIVERS_USB_ACPI - select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 -- select FSP_COMPRESS_FSP_S_LZ4 -+# select FSP_COMPRESS_FSP_S_LZ4 - select FSP_M_XIP - select GENERIC_GPIO_LIB - select HAVE_FSP_GOP --- -2.47.3 - diff --git a/config/coreboot/default/patches/0033-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/coreboot/default/patches/0033-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch deleted file mode 100644 index 487b32a2..00000000 --- a/config/coreboot/default/patches/0033-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 25ff99ff021312387734a10836232a5f3a2d2a12 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Wed, 18 Dec 2024 02:06:18 +0000 -Subject: [PATCH 33/40] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN - -This is used by lbmk to know where a tb.bin file goes, -when extracting and padding TBT.bin from Lenovo ThunderBolt -firmware updates on T480/T480s and other machines, grabbing -Lenovo update files. - -Not used in any builds, so it's not relevant for ./mk inject - -However, the ThunderBolt firmware is now auto-downloaded on -T480/T480s. This is not inserted, because it doesn't go in -the main flash, but the resulting ROM image can be flashed -on the TB controller's separate flash chip. - -Locations are as follows: - -vendorfiles/t480s/tb.bin -vendorfiles/t480/tb.bin - -This can be used for other affected ThinkPads when they're -added to Libreboot, but note that Lenovo provides different -TB firmware files for each machine. - -Since I assume it's the same TB controller on all of those -machines, I have to wonder: what difference is there between -the various TBT.bin files provided by Lenovo, and how do they -differ in terms of actual flashed configuration? - -We simply flash the padded TBT.bin when updating the firmware, -flashing externally. That's what this patch is for, so that -lbmk can auto-download them. - -Signed-off-by: Leah Rowe ---- - src/mainboard/lenovo/Kconfig | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig -index 2ffbaab85f..512b326381 100644 ---- a/src/mainboard/lenovo/Kconfig -+++ b/src/mainboard/lenovo/Kconfig -@@ -18,4 +18,30 @@ config MAINBOARD_FAMILY - string - default MAINBOARD_PART_NUMBER - -+config LENOVO_TBFW_BIN -+ string "Lenovo ThunderBolt firmware bin file" -+ default "" -+ help -+ ThunderBolt firmware for certain ThinkPad models e.g. T480. -+ Not used in the actual build. Libreboot's build system uses this -+ along with config/vendor/*/pkg.cfg entries defining a URL to the -+ Lenovo download link and hash. The resulting file when processed by -+ lbmk can be flashed to the ThunderBolt firmware's 25XX NOR device. -+ Earlier versions of this firmware had debug commands enabled that -+ sent logs to said flash IC, and it would quickly fill up, bricking -+ the ThunderBolt controller. With these updates, flashed externally, -+ you can fix the issue if present or otherwise prevent it. The benefit -+ here is that you then don't need to use Windows or a boot disk. You -+ can flash the TB firmware while flashing Libreboot firmware. Easy! -+ Look for these variables in lbmk: -+ TBFW_url TBFW_url_bkup TBFW_hash and look at how it handles that and -+ CONFIG_LENOVO_TBFW_BIN, in lbmk's include/vendor.sh file. -+ The path set by CONFIG_LENOVO_TBFW_BIN is used by lbmk when extracting -+ the firmware, putting it at that desired location. In this way, lbmk -+ can auto-download such firmware. E.g. ./mk -d coreboot t480_fsp_16mb -+ and it appears at vendorfiles/t480/tb.bin fully padded and everything! -+ -+ Just leave this blank if you don't care about this option. It's not -+ useful for every ThinkPad, only certain models. -+ - endif # VENDOR_LENOVO --- -2.47.3 - diff --git a/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch b/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch new file mode 100644 index 00000000..fa279613 --- /dev/null +++ b/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch @@ -0,0 +1,30 @@ +From 2c3a31547a14eb1b1145a5d153289b2eef6d71d8 Mon Sep 17 00:00:00 2001 +From: Riku Viitanen +Date: Sat, 27 Sep 2025 23:30:46 +0300 +Subject: [PATCH 33/41] soc/intel/alderlake: Disable + MRC_CACHE_USING_MRC_VERSION + +There's some issue with building against the FSP headers in src/vendorcode. +Headers in 3rdparty/fsp work, but since FspProducerDataHeaer.h is missing +from there, we need to disable MRC_CACHE_USING_MRC_VERSION by force. + +Signed-off-by: Riku Viitanen +--- + src/soc/intel/alderlake/Kconfig | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index 97c2ecca70..a2074fe05a 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -36,7 +36,6 @@ config SOC_INTEL_ALDERLAKE + select INTEL_GMA_VERSION_2 + select INTEL_TXT_LIB + select MP_SERVICES_PPI_V2 +- select MRC_CACHE_USING_MRC_VERSION if (SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_RAPTORLAKE) && !FSP_USE_REPO + select MRC_SETTINGS_PROTECT + select PARALLEL_MP_AP_WORK + select PLATFORM_USES_FSP2_2 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0034-Conditional-TBFW-setting-for-T480-T480S.patch b/config/coreboot/default/patches/0034-Conditional-TBFW-setting-for-T480-T480S.patch deleted file mode 100644 index 1aeae433..00000000 --- a/config/coreboot/default/patches/0034-Conditional-TBFW-setting-for-T480-T480S.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 57630265c7ba2429a8215757330348733c087db3 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 21 Apr 2025 05:14:45 +0100 -Subject: [PATCH 34/40] Conditional TBFW setting for T480/T480S - -Otherwise, other boards will define it, which -might trigger the vendor download script, and -lead to a non-zero exit. - -Signed-off-by: Leah Rowe ---- - src/mainboard/lenovo/Kconfig | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig -index 512b326381..3d3490b35d 100644 ---- a/src/mainboard/lenovo/Kconfig -+++ b/src/mainboard/lenovo/Kconfig -@@ -18,6 +18,8 @@ config MAINBOARD_FAMILY - string - default MAINBOARD_PART_NUMBER - -+if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S -+ - config LENOVO_TBFW_BIN - string "Lenovo ThunderBolt firmware bin file" - default "" -@@ -44,4 +46,6 @@ config LENOVO_TBFW_BIN - Just leave this blank if you don't care about this option. It's not - useful for every ThinkPad, only certain models. - -+endif # BOARD LENOVO_T480 || BOARD_LENOVO_T480S -+ - endif # VENDOR_LENOVO --- -2.47.3 - diff --git a/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch b/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch new file mode 100644 index 00000000..f02f2f71 --- /dev/null +++ b/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch @@ -0,0 +1,76 @@ +From 8eeb1de057b19938f1221b85e00699c58de90069 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sun, 28 Sep 2025 03:17:50 +0100 +Subject: [PATCH 34/41] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) + +if you pass -k (keep fptr modules), don't use -r, don't +use -t, you can essentially just use me_cleaner to +extract a ME image without changing it. this is useful +when for example, you just want to set the HAP bit. + +however, me_cleaner still performs a FPTR check. + +on some newer ME versions, it's always invalid according +to me_cleaner, because for example it doesn't handle +ME16 very well yet. + +this patch adds an option to override the FPTR check + +either pass -p or --pass-fptr + +NOTE: we probably won't use this on coreboot's me_cleaner, +which is the corna version. we only need it on the newer +me_cleaner versions for e.g. ME16, on certain setups. +still, it's best to have the patch here too, just in case. + +Signed-off-by: Leah Rowe +--- + util/me_cleaner/me_cleaner.py | 14 ++++++++++---- + 1 file changed, 10 insertions(+), 4 deletions(-) + +diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py +index fae5e56732..228bac899f 100755 +--- a/util/me_cleaner/me_cleaner.py ++++ b/util/me_cleaner/me_cleaner.py +@@ -246,8 +246,10 @@ def check_partition_signature(f, offset): + return "{:#x}".format(decrypted_sig).endswith(sha256.hexdigest()) # FIXME + + +-def print_check_partition_signature(f, offset): +- if check_partition_signature(f, offset): ++def print_check_partition_signature(f, offset, pass_fptr): ++ if pass_fptr: ++ print("Skipping FPTR checks because the user told us to") ++ elif check_partition_signature(f, offset): + print("VALID") + else: + print("INVALID!!") +@@ -486,6 +488,8 @@ if __name__ == "__main__": + "--extract-me)", action="store_true") + parser.add_argument("-k", "--keep-modules", help="don't remove the FTPR " + "modules, even when possible", action="store_true") ++ parser.add_argument("-p", "--pass-fptr", help="skip FTPR signature checks" ++ "regardless of other operations", action="store_true") + bw_list.add_argument("-w", "--whitelist", metavar="whitelist", + help="Comma separated list of additional partitions " + "to keep in the final image. This can be used to " +@@ -871,12 +875,14 @@ if __name__ == "__main__": + print("Checking the FTPR RSA signature of the extracted ME " + "image... ", end="") + print_check_partition_signature(mef_copy, +- ftpr_offset + ftpr_mn2_offset) ++ ftpr_offset + ftpr_mn2_offset, ++ args.pass_fptr) + mef_copy.close() + + if not me6_ignition: + print("Checking the FTPR RSA signature... ", end="") +- print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset) ++ print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset, ++ args.pass_fptr) + + f.close() + +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0035-mb-topton-adl-Add-TWL-variant-X2E_N150.patch b/config/coreboot/default/patches/0035-mb-topton-adl-Add-TWL-variant-X2E_N150.patch deleted file mode 100644 index 1edd0d27..00000000 --- a/config/coreboot/default/patches/0035-mb-topton-adl-Add-TWL-variant-X2E_N150.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 0a98ff0cbd20484ced53b15f16f8b77d881ffb9e Mon Sep 17 00:00:00 2001 -From: Riku Viitanen -Date: Thu, 25 Sep 2025 22:45:37 +0300 -Subject: [PATCH 35/40] mb/topton/adl: Add TWL variant (X2E_N150) - -Seems to be the same board but with a Twin Lake processor. -VBT extracted from vendor firmware. This makes HDMI and -DisplayPort work. - -Change-Id: I1018042802cbb8010888847226a2117fd9dfaeb0 -Signed-off-by: Riku Viitanen ---- - src/mainboard/topton/adl/Kconfig | 12 +++++++++--- - src/mainboard/topton/adl/Kconfig.name | 3 +++ - src/mainboard/topton/adl/data_twl.vbt | Bin 0 -> 9216 bytes - 3 files changed, 12 insertions(+), 3 deletions(-) - create mode 100644 src/mainboard/topton/adl/data_twl.vbt - -diff --git a/src/mainboard/topton/adl/Kconfig b/src/mainboard/topton/adl/Kconfig -index ffdfae1eee..331e1d624d 100644 ---- a/src/mainboard/topton/adl/Kconfig -+++ b/src/mainboard/topton/adl/Kconfig -@@ -1,6 +1,6 @@ - ## SPDX-License-Identifier: GPL-2.0-or-later - --if BOARD_TOPTON_X2F_N100 -+if BOARD_TOPTON_X2F_N100 || BOARD_TOPTON_X2E_N150 - - config BOARD_SPECIFIC_OPTIONS - def_bool y -@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS - select SUPERIO_ITE_IT8625E - select DRIVERS_UART_8250IO - select SOC_INTEL_ALDERLAKE_PCH_N -+ select SOC_INTEL_TWINLAKE if BOARD_TOPTON_X2E_N150 - select INTEL_GMA_HAVE_VBT - select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select HAVE_INTEL_PTT -@@ -20,7 +21,12 @@ config BOARD_SPECIFIC_OPTIONS - config MAINBOARD_DIR - default "topton/adl" - -+config INTEL_GMA_VBT_FILE -+ default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" if BOARD_TOPTON_X2F_N100 -+ default "src/mainboard/\$(MAINBOARDDIR)/data_twl.vbt" if BOARD_TOPTON_X2E_N150 -+ - config MAINBOARD_PART_NUMBER -- default "X2F_N100" -+ default "X2F_N100" if BOARD_TOPTON_X2F_N100 -+ default "X2E_N150" if BOARD_TOPTON_X2E_N150 - --endif # BOARD_TOPTON_X2F_N100 -+endif # BOARD_TOPTON_X2F_N100 || BOARD_TOPTON_X2E_N150 -diff --git a/src/mainboard/topton/adl/Kconfig.name b/src/mainboard/topton/adl/Kconfig.name -index 5b8b5ff602..db0eef29be 100644 ---- a/src/mainboard/topton/adl/Kconfig.name -+++ b/src/mainboard/topton/adl/Kconfig.name -@@ -2,3 +2,6 @@ - - config BOARD_TOPTON_X2F_N100 - bool "X2F_N100" -+ -+config BOARD_TOPTON_X2E_N150 -+ bool "X2E_N150" -diff --git a/src/mainboard/topton/adl/data_twl.vbt b/src/mainboard/topton/adl/data_twl.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..05fbd5807365b3343e55ecedbd12fabb8a3199e9 -GIT binary patch -literal 9216 -zcmeHML2MgE6#cVnZ(QS$EeWj~+AvA0;DjbwJ8eiKOI^oKsN1BmoiuVKP~6mpM!1bh -zQ-Yxy%kGfKuNJT}pSCPw^f^OP{x=@8F?Y -zXJ{ZeG8_pH1;)Z7$LUCnhQgzP(b0k7{-KjJ5*s-Z?hlU*gle4?Aq1y07iXqkJu^!^ -z!8Yo{>vV8l?lKKd&ty7jAf2W$hB;4Tsq?9sH&V&YS|=mQfx|`sh!g5^fCVPE`#}a9 -zsHlL)`xD_Z5wN|-v938@Q^cwq64R22!kSk4V-#wPQx09BB@^Ooa4i9{41s33Sk2r< -zK0;0ZS^b&{U!7sNmrWe<2^=R^;wVES?xKmSE&7)*aR%uczZ&8$o4D-&c5Imgt&)#j -zgzP8uj_HJ4#(k}A8x&g7&B1>2or#( -ziF#Md@5Pn7>QZ(mOru^zeFybj)b~+8Lj4T&3)C-BzefEI^=H&yQ2#*v6Lnh>DFxmU -z59?S!aef1(d!$e(MzK{(u6j6%x1#9q&+q23oB$|%*suhW@fW~f4DlZ4N5b|@rvv%T&)C=`C!rs;HbkL*aa7_FOnF5%qI$}TF#h0PhVbrihu-PEHslo*T| -z99(Q}+MFS|3)BF#D(;0IgTdW%N#t7rWUzycG5B%K+c*lP9TuaYs7eOcR3;b&He@B& -zoV~FshB+E-lvVi-2BNcNyjq4&yXID-jjd{YvFroU*#ZwPRa&mXha-noWpdf4s<|?Q -z1bnyS8n;)I$yb`km!i<54C-cIuuSTFpM|belZUrD^=zWCNmZ!X7nn(#zKutr)l?IO -z$FF5G%X^WbowYLhLg$OFD{G&xVmw@J%jTo=ElT9d&Ju$NPp~p(vKj`ZU0q4cClz;; -zj{)w3h=YkS+~=6YJcxihK*nIFRYY;45wa1wQ*kLl*2?ff$NLc(w3=Q%9@rq?cvK60 -zn)~(M4mI9U?h6s>I0HC9+Wfv~Qz4;2eL|LTPs)TxA+wTeXfQGnIdv|TK7Q(K>M{7k -zf_m6eC_L{a($N)=;!6+j$o8psiXaG2p_YVgTOUN(ob({-SSOoheg7otGLoy;J9W`0zO4@q-WH -z{1Fq+)|Jb-v$Fl~kFcA>_$}1`^HRBIDoYZV-fPCLpwhO*{~d}sCBEO<;&E8+TN$u2 -zU}eC{fRzC&16BsC4E&E7==)gM4KGasXo8NfuM)6I_LyJ%*vCx(^#cGZ0`Y(bal{hi -z4KBA`zl{K!O5Cu3Z?s$S#hJuI(eSwX3BIqkFA@bZh*7W|KFgxyP?>GcPKk`RMw?t= -z(|=;NRT76qw6#{)@^b>Hk|LaVNGa=cOUUd~sv!9nfp*sPOaZ+xVs0fuGXx2U0!y!oLUb -SeEwbkJq|WZn +Date: Sat, 4 Oct 2025 21:57:43 +0100 +Subject: [PATCH 35/41] soc/intel/alderlake: Don't compress FSP-S + +Build systems like lbmk need to reproducibly insert +certain vendor files on release images. + +Compression isn't always reproducible, and making it +so costs a lot more time than simply disabling compression. + +With this change, FSP-S uses slightly more space inside +the flash, but it's not that much. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/alderlake/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index a2074fe05a..08137d2706 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -16,7 +16,7 @@ config SOC_INTEL_ALDERLAKE + select DRAM_SUPPORT_DDR5 + select DRIVERS_USB_ACPI + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 +- select FSP_COMPRESS_FSP_S_LZ4 ++# select FSP_COMPRESS_FSP_S_LZ4 + select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW + select FSP_M_XIP + select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch b/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch new file mode 100644 index 00000000..638620a9 --- /dev/null +++ b/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch @@ -0,0 +1,33 @@ +From 226df168b34467ca8555e953b6d793f273c0b82c Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 4 Oct 2025 22:20:11 +0100 +Subject: [PATCH 36/41] alderlake: don't require full fsp repo for fd path + +Signed-off-by: Leah Rowe +--- + src/soc/intel/alderlake/Kconfig | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index 08137d2706..67e47c2e36 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -417,7 +417,14 @@ config FSP_HEADER_PATH + + config FSP_FD_PATH + string +- depends on FSP_USE_REPO ++# dependency removed for lbmk purposes, so that the path is present ++# in the config regardless of whether it's used. this is for ./mk -d ++# on alderlake boards, which is used by lbmk to manually split fsp, ++# even though the result is identical to what coreboot produces, because ++# this enables lbmk to strip the fsp in release archives, and re-insert ++# for compliance reasons (due to technicalities in intel's licensing), ++# and to enable lbmk's advanced checksum verification of vendor files ++# depends on FSP_USE_REPO + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0036-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch b/config/coreboot/default/patches/0036-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch deleted file mode 100644 index 565be85a..00000000 --- a/config/coreboot/default/patches/0036-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 8e191c71f11de4cb3d08fe585537f15043cacb1b Mon Sep 17 00:00:00 2001 -From: Riku Viitanen -Date: Sat, 27 Sep 2025 23:30:46 +0300 -Subject: [PATCH 36/40] soc/intel/alderlake: Disable - MRC_CACHE_USING_MRC_VERSION - -There's some issue with building against the FSP headers in src/vendorcode. -Headers in 3rdparty/fsp work, but since FspProducerDataHeaer.h is missing -from there, we need to disable MRC_CACHE_USING_MRC_VERSION by force. - -Signed-off-by: Riku Viitanen ---- - src/soc/intel/alderlake/Kconfig | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 51bdf98b9d..739faa3808 100644 ---- a/src/soc/intel/alderlake/Kconfig -+++ b/src/soc/intel/alderlake/Kconfig -@@ -34,7 +34,6 @@ config SOC_INTEL_ALDERLAKE - select INTEL_GMA_VERSION_2 - select INTEL_TXT_LIB - select MP_SERVICES_PPI_V2 -- select MRC_CACHE_USING_MRC_VERSION if (SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_RAPTORLAKE) && !FSP_USE_REPO - select MRC_SETTINGS_PROTECT - select PARALLEL_MP_AP_WORK - select PLATFORM_USES_FSP2_2 --- -2.47.3 - diff --git a/config/coreboot/default/patches/0037-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch b/config/coreboot/default/patches/0037-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch deleted file mode 100644 index 8cff0c56..00000000 --- a/config/coreboot/default/patches/0037-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch +++ /dev/null @@ -1,76 +0,0 @@ -From 8ab86ffd25fc013790c260e564c8b770c13a5342 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sun, 28 Sep 2025 03:17:50 +0100 -Subject: [PATCH 37/40] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) - -if you pass -k (keep fptr modules), don't use -r, don't -use -t, you can essentially just use me_cleaner to -extract a ME image without changing it. this is useful -when for example, you just want to set the HAP bit. - -however, me_cleaner still performs a FPTR check. - -on some newer ME versions, it's always invalid according -to me_cleaner, because for example it doesn't handle -ME16 very well yet. - -this patch adds an option to override the FPTR check - -either pass -p or --pass-fptr - -NOTE: we probably won't use this on coreboot's me_cleaner, -which is the corna version. we only need it on the newer -me_cleaner versions for e.g. ME16, on certain setups. -still, it's best to have the patch here too, just in case. - -Signed-off-by: Leah Rowe ---- - util/me_cleaner/me_cleaner.py | 14 ++++++++++---- - 1 file changed, 10 insertions(+), 4 deletions(-) - -diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py -index fae5e56732..228bac899f 100755 ---- a/util/me_cleaner/me_cleaner.py -+++ b/util/me_cleaner/me_cleaner.py -@@ -246,8 +246,10 @@ def check_partition_signature(f, offset): - return "{:#x}".format(decrypted_sig).endswith(sha256.hexdigest()) # FIXME - - --def print_check_partition_signature(f, offset): -- if check_partition_signature(f, offset): -+def print_check_partition_signature(f, offset, pass_fptr): -+ if pass_fptr: -+ print("Skipping FPTR checks because the user told us to") -+ elif check_partition_signature(f, offset): - print("VALID") - else: - print("INVALID!!") -@@ -486,6 +488,8 @@ if __name__ == "__main__": - "--extract-me)", action="store_true") - parser.add_argument("-k", "--keep-modules", help="don't remove the FTPR " - "modules, even when possible", action="store_true") -+ parser.add_argument("-p", "--pass-fptr", help="skip FTPR signature checks" -+ "regardless of other operations", action="store_true") - bw_list.add_argument("-w", "--whitelist", metavar="whitelist", - help="Comma separated list of additional partitions " - "to keep in the final image. This can be used to " -@@ -871,12 +875,14 @@ if __name__ == "__main__": - print("Checking the FTPR RSA signature of the extracted ME " - "image... ", end="") - print_check_partition_signature(mef_copy, -- ftpr_offset + ftpr_mn2_offset) -+ ftpr_offset + ftpr_mn2_offset, -+ args.pass_fptr) - mef_copy.close() - - if not me6_ignition: - print("Checking the FTPR RSA signature... ", end="") -- print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset) -+ print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset, -+ args.pass_fptr) - - f.close() - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch b/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch new file mode 100644 index 00000000..4f296fbd --- /dev/null +++ b/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch @@ -0,0 +1,46 @@ +From 30366be45e5b7521b93475f68c7143bd683b25f3 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 6 Oct 2025 04:47:06 +0100 +Subject: [PATCH 37/41] soc/alderlake: disable stack overflow debug option + +same as on other boards. based on this commit: + +commit 51cc2bacb6b07279b97e9934d079060475481fb6 +Author: Subrata Banik +Author: Subrata Banik +Date: Fri Dec 13 13:07:28 2024 +0530 + + soc/intel/pantherlake: Disable stack overflow debug options + +yeah, i've been replicating this change per platform. + +we do alderlake now in libreboot, so let's set that here too. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/alderlake/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index 67e47c2e36..e9c56fc6b9 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -331,6 +331,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ + int + default 19200000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch b/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch new file mode 100644 index 00000000..cd6d5f02 --- /dev/null +++ b/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch @@ -0,0 +1,92 @@ +From 90332fe96aca0de4d99d58d1593048c77e1bdecf Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Sun, 11 May 2025 15:41:22 -0600 +Subject: [PATCH 38/41] ec/dell/mec5035: Add command to disable EC-initiated + thermal shutdown + +If command 0xBF isn't sent, the EC shuts down the system without warning +as soon as the CPU temperature reaches about 87 degrees, without letting +the CPU thermal throttle to try and reduce the temperature. With vendor +firmware, the CPU is able to reach around 100 degrees before thermal +throttling. + +This command was found by collecting EC commands by logging the LPC bus +while running with vendor firmware and then replaying observed commands +from coreboot. By systematically replaying subsets of commands in a +binary search pattern and then stress testing the system, the command to +disable the shutdown was isolated. + +The exact meaning of the parameters for this command are unknown at this +time, but do seem to differ between different generations of these +laptops. Due to this, the commmand should be called by mainboard +specific code which passes the specific parameter value used. + +The Google Wilco EC code, which runs on Latitude Chromebooks and shares +many commands with the standard Latitude ECs, suggests that command 0xBF +tells the EC about the processors CPUID. However, the values observed in +LPC bus logs do not seem to correspond with any CPUID values on the +non-Chromebook systems I tested. + +Observed command parameter values (sent on mailbox registers 2-4): +- E6430 (Ivy Bridge): 0x07, 0x00, 0x00 +- M6800 (Haswell): 0x14, 0x00, 0x00 + +Change-Id: I42f09a3ef681007f64d9c5b1a29248b594737a86 +Signed-off-by: Nicholas Chin +--- + src/ec/dell/mec5035/mec5035.c | 19 +++++++++++++++++++ + src/ec/dell/mec5035/mec5035.h | 2 ++ + 2 files changed, 21 insertions(+) + +diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c +index c5067c16f6..b316fa4989 100644 +--- a/src/ec/dell/mec5035/mec5035.c ++++ b/src/ec/dell/mec5035/mec5035.c +@@ -114,6 +114,25 @@ void mec5035_sleep_enable(void) + ec_command(CMD_SLEEP_ENABLE); + } + ++void mec5035_cmd_bf(u8 i) ++{ ++ /* ++ * If this command isn't sent, the EC shuts down the system as soon as ++ * the CPU temperature reaches about 87 degrees. It is unknown exactly ++ * what the parameters represent. The Google Wilco EC code, which runs ++ * on Latitude Chromebooks and shares some commands with the standard ++ * Latitude EC code, suggests command 0xBF tells the EC the CPUID, but ++ * the values observed in LPC bus logs don't seem to match any CPUID ++ * values of the normal Latitudes this was tested with. ++ * Observed i values: ++ * - E6430 (Ivy Bridge): 0x7 ++ * - M6800 (Haswell): 0x14 ++ */ ++ u8 buf[3] = {i, 0, 0}; ++ write_mailbox_regs(buf, 2, 3); ++ ec_command(CMD_BF); ++} ++ + void mec5035_early_init(void) + { + /* If this isn't sent the EC shuts down the system after about 15 +diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h +index 5cd907bf71..71d1a71075 100644 +--- a/src/ec/dell/mec5035/mec5035.h ++++ b/src/ec/dell/mec5035/mec5035.h +@@ -14,6 +14,7 @@ enum mec5035_cmd { + CMD_POWER_BUTTON_TO_HOST = 0x3e, + CMD_ACPI_WAKEUP_CHANGE = 0x4a, + CMD_SLEEP_ENABLE = 0x64, ++ CMD_BF = 0xbf, + CMD_CPU_OK = 0xc2, + }; + +@@ -65,5 +66,6 @@ void mec5035_change_wake(u8 source, enum ec_wake_change change); + void mec5035_sleep_enable(void); + + void mec5035_smi_sleep(int slp_type); ++void mec5035_cmd_bf(u8 i); + + #endif /* _EC_DELL_MEC5035_H_ */ +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0038-soc-intel-alderlake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0038-soc-intel-alderlake-Don-t-compress-FSP-S.patch deleted file mode 100644 index 545f2076..00000000 --- a/config/coreboot/default/patches/0038-soc-intel-alderlake-Don-t-compress-FSP-S.patch +++ /dev/null @@ -1,35 +0,0 @@ -From c36ed52f7573563a9eaeeedd6e6c0ee75973a39d Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 4 Oct 2025 21:57:43 +0100 -Subject: [PATCH 38/40] soc/intel/alderlake: Don't compress FSP-S - -Build systems like lbmk need to reproducibly insert -certain vendor files on release images. - -Compression isn't always reproducible, and making it -so costs a lot more time than simply disabling compression. - -With this change, FSP-S uses slightly more space inside -the flash, but it's not that much. - -Signed-off-by: Leah Rowe ---- - src/soc/intel/alderlake/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 739faa3808..1f6a1dca7d 100644 ---- a/src/soc/intel/alderlake/Kconfig -+++ b/src/soc/intel/alderlake/Kconfig -@@ -14,7 +14,7 @@ config SOC_INTEL_ALDERLAKE - select DISPLAY_FSP_VERSION_INFO - select DRIVERS_USB_ACPI - select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 -- select FSP_COMPRESS_FSP_S_LZ4 -+# select FSP_COMPRESS_FSP_S_LZ4 - select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW - select FSP_M_XIP - select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN --- -2.47.3 - diff --git a/config/coreboot/default/patches/0039-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch b/config/coreboot/default/patches/0039-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch deleted file mode 100644 index ed7d98e0..00000000 --- a/config/coreboot/default/patches/0039-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch +++ /dev/null @@ -1,33 +0,0 @@ -From e564490781b0b829da43534c6c2a1b26aeb3282f Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 4 Oct 2025 22:20:11 +0100 -Subject: [PATCH 39/40] alderlake: don't require full fsp repo for fd path - -Signed-off-by: Leah Rowe ---- - src/soc/intel/alderlake/Kconfig | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - -diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 1f6a1dca7d..3979d9e162 100644 ---- a/src/soc/intel/alderlake/Kconfig -+++ b/src/soc/intel/alderlake/Kconfig -@@ -415,7 +415,14 @@ config FSP_HEADER_PATH - - config FSP_FD_PATH - string -- depends on FSP_USE_REPO -+# dependency removed for lbmk purposes, so that the path is present -+# in the config regardless of whether it's used. this is for ./mk -d -+# on alderlake boards, which is used by lbmk to manually split fsp, -+# even though the result is identical to what coreboot produces, because -+# this enables lbmk to strip the fsp in release archives, and re-insert -+# for compliance reasons (due to technicalities in intel's licensing), -+# and to enable lbmk's advanced checksum verification of vendor files -+# depends on FSP_USE_REPO - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P --- -2.47.3 - diff --git a/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch b/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch new file mode 100644 index 00000000..ccf93fd7 --- /dev/null +++ b/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch @@ -0,0 +1,36 @@ +From 68048f4afe369ece02143f9a4a7da2104ff2d10b Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Sun, 11 May 2025 16:28:23 -0600 +Subject: [PATCH 39/41] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown + at 87 degrees + +If command 0xBF isn't sent, the EC will shut down the system without +warning once the CPU reaches approximately 87 degrees, without the +system thermal throttling first. Call the newly added function from the +MEC5035 code to send this command and disable this behavior. + +Tested on the Latitude E6430. + +Change-Id: I2b2dc1e3ab115e05d05eaac06892343394d37fdf +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/snb_ivb_latitude/early_init.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/src/mainboard/dell/snb_ivb_latitude/early_init.c b/src/mainboard/dell/snb_ivb_latitude/early_init.c +index ff83db095b..ef385a0a70 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/early_init.c ++++ b/src/mainboard/dell/snb_ivb_latitude/early_init.c +@@ -11,4 +11,9 @@ void bootblock_mainboard_early_init(void) + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); ++ ++ /* Observed from LPC logs with vendor firmware. Seems to disable ++ * EC-initiated shutdown when the CPU reaches approximately 87 degrees. ++ * The exact meaning of the parameter is currently unknown. */ ++ mec5035_cmd_bf(0x07); + } +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0040-Haswell-NRI-Implement-SMBIOS-type-16-17.patch b/config/coreboot/default/patches/0040-Haswell-NRI-Implement-SMBIOS-type-16-17.patch deleted file mode 100644 index 4fdf2476..00000000 --- a/config/coreboot/default/patches/0040-Haswell-NRI-Implement-SMBIOS-type-16-17.patch +++ /dev/null @@ -1,184 +0,0 @@ -From 0fdb23e899e31b17a774ae9151410b11ccf13022 Mon Sep 17 00:00:00 2001 -From: Ron Nazarov -Date: Tue, 30 Sep 2025 22:36:53 +0100 -Subject: [PATCH 40/40] Haswell NRI: Implement SMBIOS type 16/17 - -Based on the implementation from Ivy/Sandy Bridge NRI. - -Tested on a Dell OptiPlex 9020 SFF with libreboot. - -Change-Id: I5e153258f9f88726f54c98baac0b1788a839f934 -Signed-off-by: Ron Nazarov ---- - .../haswell/native_raminit/raminit_main.c | 6 +- - .../haswell/native_raminit/raminit_native.c | 83 +++++++++++++++++-- - .../haswell/native_raminit/raminit_native.h | 2 +- - 3 files changed, 81 insertions(+), 10 deletions(-) - -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 84db33ebdf..328f777ee1 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -245,7 +245,7 @@ static enum raminit_status try_raminit( - return status; - } - --void raminit_main(const enum raminit_boot_mode bootmode) -+const struct sysinfo *raminit_main(const enum raminit_boot_mode bootmode) - { - /* - * The mighty_ctrl struct. Will happily nuke the pre-RAM stack -@@ -261,7 +261,7 @@ void raminit_main(const enum raminit_boot_mode bootmode) - if (bootmode != BOOTMODE_COLD) { - status = try_raminit(&mighty_ctrl, fast_boot, ARRAY_SIZE(fast_boot)); - if (status == RAMINIT_STATUS_SUCCESS) -- return; -+ return &mighty_ctrl; - } - - /** TODO: Try more than once **/ -@@ -269,4 +269,6 @@ void raminit_main(const enum raminit_boot_mode bootmode) - - if (status != RAMINIT_STATUS_SUCCESS) - die("Memory initialization was met with utmost failure and misery\n"); -+ -+ return &mighty_ctrl; - } -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index 3ad8ce29e7..73532592e8 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -16,6 +16,73 @@ - - #include "raminit_native.h" - -+static uint8_t nb_get_ecc_type(const uint32_t capid0_a) -+{ -+ return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; -+} -+ -+static uint16_t nb_slots_per_channel(const uint32_t capid0_a) -+{ -+ return !(capid0_a & CAPID_DDPCD) + 1; -+} -+ -+static uint16_t nb_number_of_channels(const uint32_t capid0_a) -+{ -+ return !(capid0_a & CAPID_PDCD) + 1; -+} -+ -+static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) -+{ -+ uint32_t ddrsz; -+ -+ /* Values from documentation, which assume two DIMMs per channel */ -+ switch (CAPID_DDRSZ(capid0_a)) { -+ case 1: -+ ddrsz = 8192; -+ break; -+ case 2: -+ ddrsz = 2048; -+ break; -+ case 3: -+ ddrsz = 512; -+ break; -+ default: -+ ddrsz = 16384; -+ break; -+ } -+ -+ /* Account for the maximum number of DIMMs per channel */ -+ return (ddrsz / 2) * nb_slots_per_channel(capid0_a); -+} -+ -+/* Fill cbmem with information for SMBIOS type 16 and type 17 */ -+static void setup_sdram_meminfo(const struct sysinfo *ctrl) -+{ -+ const u16 ddr_freq = (1000 << 8) / ctrl->tCK; -+ -+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { -+ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) { -+ enum cb_err ret = spd_add_smbios17(channel, slot, ddr_freq, -+ &ctrl->dimms[channel][slot].data); -+ if (ret != CB_SUCCESS) -+ printk(BIOS_ERR, "RAMINIT: Failed to add SMBIOS17\n"); -+ } -+ } -+ -+ /* The 'spd_add_smbios17' function allocates this CBMEM area */ -+ struct memory_info *m = cbmem_find(CBMEM_ID_MEMINFO); -+ if (!m) -+ return; -+ -+ const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); -+ -+ const uint16_t channels = nb_number_of_channels(capid0_a); -+ -+ m->ecc_type = nb_get_ecc_type(capid0_a); -+ m->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); -+ m->number_of_devices = channels * nb_slots_per_channel(capid0_a); -+} -+ - static void wait_txt_clear(void) - { - const struct cpuid_result cpuid = cpuid_ext(1, 0); -@@ -90,7 +157,8 @@ static void raminit_reset(void) - static enum raminit_boot_mode do_actual_raminit( - const bool s3resume, - const bool cpu_replaced, -- const enum raminit_boot_mode orig_bootmode) -+ const enum raminit_boot_mode orig_bootmode, -+ const struct sysinfo **ctrl) - { - struct mrc_data md = prepare_mrc_cache(); - -@@ -158,7 +226,7 @@ static enum raminit_boot_mode do_actual_raminit( - * And now, the actual memory initialization thing. - */ - printk(RAM_DEBUG, "\nStarting native raminit\n"); -- raminit_main(bootmode); -+ *ctrl = raminit_main(bootmode); - - return bootmode; - } -@@ -176,8 +244,9 @@ void perform_raminit(const int s3resume) - wait_txt_clear(); - wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0}); - -+ const struct sysinfo *ctrl; - const enum raminit_boot_mode bootmode = -- do_actual_raminit(s3resume, cpu_replaced, orig_bootmode); -+ do_actual_raminit(s3resume, cpu_replaced, orig_bootmode, &ctrl); - - /** TODO: report_memory_config **/ - -@@ -204,9 +273,9 @@ void perform_raminit(const int s3resume) - system_reset(); - } - -- /* Save training data on non-S3 resumes */ -- if (!s3resume) -+ /* Save training data and set up SMBIOS type 16/17 on non-S3 resumes */ -+ if (!s3resume) { - save_mrc_data(); -- -- /** TODO: setup_sdram_meminfo **/ -+ setup_sdram_meminfo(ctrl); -+ } - } -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index b9e84a11df..1401feedc5 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -476,7 +476,7 @@ static inline void mchbar_write64(const uintptr_t x, const uint64_t v) - "m"(mmxsave)); - } - --void raminit_main(enum raminit_boot_mode bootmode); -+const struct sysinfo *raminit_main(enum raminit_boot_mode bootmode); - - enum raminit_status collect_spd_info(struct sysinfo *ctrl); - enum raminit_status initialise_mpll(struct sysinfo *ctrl); --- -2.47.3 - diff --git a/config/coreboot/default/patches/0040-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch b/config/coreboot/default/patches/0040-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch new file mode 100644 index 00000000..9fe5d3da --- /dev/null +++ b/config/coreboot/default/patches/0040-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch @@ -0,0 +1,358 @@ +From 0792e39c1684216860b228e6c0935066be1a21b6 Mon Sep 17 00:00:00 2001 +From: Jeremy Soller +Date: Fri, 31 May 2024 13:58:00 -0600 +Subject: [PATCH 40/41] drivers/intel/dtbt: Add discrete Thunderbolt driver + +Add a new driver which enables basic TBT support for the Alpine Ridge, +Titan Ridge, and Maple Ridge discrete Thunderbolt controllers. + +This driver will initially be used on the Lenovo T480/T480s and +System76 RPL-HX platform boards. It currently only supports a single +dTBT controller. + +Ref: edk2-platforms KabylakeOpenBoardPkg reference implementation +Ref: Titan Ridge BIOS Implementation Guide v1.4 +Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472) + +Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364 +Signed-off-by: Jeremy Soller +Signed-off-by: Tim Crawford +Signed-off-by: Matt DeVillier +--- + src/drivers/intel/dtbt/Kconfig | 6 + + src/drivers/intel/dtbt/Makefile.mk | 3 + + src/drivers/intel/dtbt/chip.h | 8 ++ + src/drivers/intel/dtbt/dtbt.c | 202 +++++++++++++++++++++++++++++ + src/drivers/intel/dtbt/dtbt.h | 73 +++++++++++ + 5 files changed, 292 insertions(+) + create mode 100644 src/drivers/intel/dtbt/Kconfig + create mode 100644 src/drivers/intel/dtbt/Makefile.mk + create mode 100644 src/drivers/intel/dtbt/chip.h + create mode 100644 src/drivers/intel/dtbt/dtbt.c + create mode 100644 src/drivers/intel/dtbt/dtbt.h + +diff --git a/src/drivers/intel/dtbt/Kconfig b/src/drivers/intel/dtbt/Kconfig +new file mode 100644 +index 0000000000..d895dbd288 +--- /dev/null ++++ b/src/drivers/intel/dtbt/Kconfig +@@ -0,0 +1,6 @@ ++config DRIVERS_INTEL_DTBT ++ def_bool n ++ help ++ Support for discrete Thunderbolt controllers. ++ Currently only supports a single dTBT controller from the ++ Alpine Ridge, Titan Ridge, and Maple Ridge families. +diff --git a/src/drivers/intel/dtbt/Makefile.mk b/src/drivers/intel/dtbt/Makefile.mk +new file mode 100644 +index 0000000000..1b5252dda0 +--- /dev/null ++++ b/src/drivers/intel/dtbt/Makefile.mk +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c +diff --git a/src/drivers/intel/dtbt/chip.h b/src/drivers/intel/dtbt/chip.h +new file mode 100644 +index 0000000000..2b1dfa70a5 +--- /dev/null ++++ b/src/drivers/intel/dtbt/chip.h +@@ -0,0 +1,8 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_ ++#define _DRIVERS_INTEL_DTBT_CHIP_H_ ++ ++struct drivers_intel_dtbt_config {}; ++ ++#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */ +diff --git a/src/drivers/intel/dtbt/dtbt.c b/src/drivers/intel/dtbt/dtbt.c +new file mode 100644 +index 0000000000..8613eee5e0 +--- /dev/null ++++ b/src/drivers/intel/dtbt/dtbt.c +@@ -0,0 +1,202 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "chip.h" ++#include "dtbt.h" ++ ++ ++/* ++ * We only want to enable the first/primary bridge device, ++ * as sending mailbox commands to secondary ones will fail, ++ * and we only want to create a single ACPI device in the SSDT. ++ */ ++static bool enable_done; ++static bool ssdt_done; ++ ++static void dtbt_cmd(struct device *dev, u32 command, u32 data, u32 timeout) ++{ ++ u32 reg = (data << 8) | (command << 1) | PCIE2TBT_VALID; ++ u32 status; ++ ++ printk(BIOS_SPEW, "dTBT send command 0x%x\n", command); ++ /* Send command */ ++ pci_write_config32(dev, PCIE2TBT, reg); ++ /* Wait for done bit to be cleared */ ++ if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) ++ printk(BIOS_ERR, "dTBT command 0x%x send timeout, status 0x%x\n", command, status); ++ /* Clear valid bit */ ++ pci_write_config32(dev, PCIE2TBT, 0); ++ /* Wait for done bit to be cleared */ ++ if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) ++ printk(BIOS_ERR, "dTBT command 0x%x clear valid bit timeout, status 0x%x\n", command, status); ++} ++ ++static void dtbt_write_dsd(void) ++{ ++ struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); ++ ++ acpi_device_add_hotplug_support_in_d3(dsd); ++ acpi_device_add_external_facing_port(dsd); ++ acpi_dp_write(dsd); ++} ++ ++static void dtbt_write_opregion(const struct bus *bus) ++{ ++ uintptr_t mmconf_base = (uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS ++ + (((uintptr_t)(bus->secondary)) << 20); ++ const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, mmconf_base, 0x1000); ++ const struct fieldlist fieldlist[] = { ++ FIELDLIST_OFFSET(TBT2PCIE), ++ FIELDLIST_NAMESTR("TB2P", 32), ++ FIELDLIST_OFFSET(PCIE2TBT), ++ FIELDLIST_NAMESTR("P2TB", 32), ++ }; ++ ++ acpigen_write_opregion(&opregion); ++ acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), ++ FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); ++} ++ ++static void dtbt_fill_ssdt(const struct device *dev) ++{ ++ struct bus *bus; ++ struct device *parent; ++ const char *parent_scope; ++ const char *dev_name = acpi_device_name(dev); ++ ++ if (ssdt_done) ++ return; ++ ++ bus = dev->upstream; ++ if (!bus) { ++ printk(BIOS_ERR, "dTBT bus invalid\n"); ++ return; ++ } ++ ++ parent = bus->dev; ++ if (!parent || !is_pci(parent)) { ++ printk(BIOS_ERR, "dTBT parent invalid\n"); ++ return; ++ } ++ ++ parent_scope = acpi_device_path(parent); ++ if (!parent_scope) { ++ printk(BIOS_ERR, "dTBT parent scope not valid\n"); ++ return; ++ } ++ ++ /* Scope */ ++ acpigen_write_scope(parent_scope); ++ dtbt_write_dsd(); ++ ++ /* Device */ ++ acpigen_write_device(dev_name); ++ acpigen_write_name_integer("_ADR", 0); ++ dtbt_write_opregion(bus); ++ ++ /* PTS Method */ ++ acpigen_write_method_serialized("PTS", 0); ++ ++ acpigen_write_debug_string("dTBT prepare to sleep"); ++ acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE << 1, "P2TB"); ++ acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", PCIE2TBT_GO2SX_NO_WAKE << 1); ++ ++ acpigen_write_debug_namestr("TB2P"); ++ acpigen_write_store_int_to_namestr(0, "P2TB"); ++ acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", 0); ++ acpigen_write_debug_namestr("TB2P"); ++ ++ acpigen_write_method_end(); ++ acpigen_write_device_end(); ++ acpigen_write_scope_end(); ++ ++ // \.TBTS Method ++ acpigen_write_scope("\\"); ++ acpigen_write_method("TBTS", 0); ++ acpigen_emit_namestring(acpi_device_path_join(dev, "PTS")); ++ acpigen_write_method_end(); ++ acpigen_write_scope_end(); ++ ++ printk(BIOS_INFO, "%s.%s %s\n", parent_scope, dev_name, dev_path(dev)); ++ ssdt_done = true; ++} ++ ++static const char *dtbt_acpi_name(const struct device *dev) ++{ ++ return "DTBT"; ++} ++ ++static void dtbt_enable(struct device *dev) ++{ ++ if (!is_dev_enabled(dev) || enable_done) ++ return; ++ ++ printk(BIOS_INFO, "dTBT controller found at %s\n", dev_path(dev)); ++ ++ // XXX: Recommendation is to set SL1 ("User Authorization") ++ printk(BIOS_DEBUG, "dTBT set security level SL0\n"); ++ /* Set security level */ ++ dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL, SEC_LEVEL_NONE, MBOX_TIMEOUT_MS); ++ ++ if (acpi_is_wakeup_s3()) { ++ printk(BIOS_DEBUG, "dTBT SX exit\n"); ++ dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED, 0, MBOX_TIMEOUT_MS); ++ /* Read TBT2PCIE register, verify not invalid */ ++ if (pci_read_config32(dev, TBT2PCIE) == 0xffffffff) ++ printk(BIOS_ERR, "dTBT S3 resume failure.\n"); ++ } else { ++ printk(BIOS_DEBUG, "dTBT set boot on\n"); ++ dtbt_cmd(dev, PCIE2TBT_BOOT_ON, 0, MBOX_TIMEOUT_MS); ++ printk(BIOS_DEBUG, "dTBT set USB on\n"); ++ dtbt_cmd(dev, PCIE2TBT_USB_ON, 0, MBOX_TIMEOUT_MS); ++ } ++ enable_done = true; ++} ++ ++static struct pci_operations dtbt_device_ops_pci = { ++ .set_subsystem = 0, ++}; ++ ++static struct device_operations dtbt_device_ops = { ++ .read_resources = pci_bus_read_resources, ++ .set_resources = pci_dev_set_resources, ++ .enable_resources = pci_bus_enable_resources, ++ .acpi_fill_ssdt = dtbt_fill_ssdt, ++ .acpi_name = dtbt_acpi_name, ++ .scan_bus = pciexp_scan_bridge, ++ .reset_bus = pci_bus_reset, ++ .ops_pci = &dtbt_device_ops_pci, ++ .enable = dtbt_enable ++}; ++ ++/* We only want to match the (first) bridge device */ ++static const unsigned short pci_device_ids[] = { ++ AR_2C_BRG, ++ AR_4C_BRG, ++ AR_LP_BRG, ++ AR_4C_C0_BRG, ++ AR_2C_C0_BRG, ++ TR_2C_BRG, ++ TR_4C_BRG, ++ TR_DD_BRG, ++ MR_2C_BRG, ++ MR_4C_BRG, ++ 0 ++}; ++ ++static const struct pci_driver intel_dtbt_driver __pci_driver = { ++ .ops = &dtbt_device_ops, ++ .vendor = PCI_VID_INTEL, ++ .devices = pci_device_ids, ++}; ++ ++struct chip_operations drivers_intel_dtbt_ops = { ++ .name = "Intel Discrete Thunderbolt", ++}; +diff --git a/src/drivers/intel/dtbt/dtbt.h b/src/drivers/intel/dtbt/dtbt.h +new file mode 100644 +index 0000000000..d01d3a35ef +--- /dev/null ++++ b/src/drivers/intel/dtbt/dtbt.h +@@ -0,0 +1,73 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef _DRIVERS_INTEL_DTBT_H_ ++#define _DRIVERS_INTEL_DTBT_H_ ++ ++/* Alpine Ridge device IDs */ ++#define AR_2C_NHI 0x1575 ++#define AR_2C_BRG 0x1576 ++#define AR_2C_USB 0x15B5 ++#define AR_4C_NHI 0x1577 ++#define AR_4C_BRG 0x1578 ++#define AR_4C_USB 0x15B6 ++#define AR_LP_NHI 0x15BF ++#define AR_LP_BRG 0x15C0 ++#define AR_LP_USB 0x15C1 ++#define AR_4C_C0_NHI 0x15D2 ++#define AR_4C_C0_BRG 0x15D3 ++#define AR_4C_C0_USB 0x15D4 ++#define AR_2C_C0_NHI 0x15D9 ++#define AR_2C_C0_BRG 0x15DA ++#define AR_2C_C0_USB 0x15DB ++ ++/* Titan Ridge device IDs */ ++#define TR_2C_BRG 0x15E7 ++#define TR_2C_NHI 0x15E8 ++#define TR_2C_USB 0x15E9 ++#define TR_4C_BRG 0x15EA ++#define TR_4C_NHI 0x15EB ++#define TR_4C_USB 0x15EC ++#define TR_DD_BRG 0x15EF ++#define TR_DD_USB 0x15F0 ++ ++/* Maple Ridge device IDs */ ++#define MR_2C_BRG 0x1133 ++#define MR_2C_NHI 0x1134 ++#define MR_2C_USB 0x1135 ++#define MR_4C_BRG 0x1136 ++#define MR_4C_NHI 0x1137 ++#define MR_4C_USB 0x1138 ++ ++/* Security Levels */ ++#define SEC_LEVEL_NONE 0 ++#define SEC_LEVEL_USER 1 ++#define SEC_LEVEL_AUTH 2 ++#define SEC_LEVEL_DP_ONLY 3 ++ ++#define PCIE2TBT 0x54C ++#define PCIE2TBT_VALID BIT(0) ++#define PCIE2TBT_GO2SX 2 ++#define PCIE2TBT_GO2SX_NO_WAKE 3 ++#define PCIE2TBT_SX_EXIT_TBT_CONNECTED 4 ++#define PCIE2TBT_OS_UP 6 ++#define PCIE2TBT_SET_SECURITY_LEVEL 8 ++#define PCIE2TBT_GET_SECURITY_LEVEL 9 ++#define PCIE2TBT_BOOT_ON 24 ++#define PCIE2TBT_USB_ON 25 ++#define PCIE2TBT_GET_ENUMERATION_METHOD 26 ++#define PCIE2TBT_SET_ENUMERATION_METHOD 27 ++#define PCIE2TBT_POWER_CYCLE 28 ++#define PCIE2TBT_SX_START 29 ++#define PCIE2TBT_ACL_BOOT 30 ++#define PCIE2TBT_CONNECT_TOPOLOGY 31 ++ ++#define TBT2PCIE 0x548 ++#define TBT2PCIE_DONE BIT(0) ++ ++// Timeout for mailbox commands unless otherwise specified. ++#define MBOX_TIMEOUT_MS 5000 ++ ++// Timeout for controller to ack GO2SX/GO2SX_NO_WAKE mailbox command. ++#define GO2SX_TIMEOUT_MS 600 ++ ++#endif /* _DRIVERS_INTEL_DTBT_H_ */ +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0041-mb-lenovo-t480-s-Enable-TBT-support.patch b/config/coreboot/default/patches/0041-mb-lenovo-t480-s-Enable-TBT-support.patch new file mode 100644 index 00000000..77edba57 --- /dev/null +++ b/config/coreboot/default/patches/0041-mb-lenovo-t480-s-Enable-TBT-support.patch @@ -0,0 +1,117 @@ +From 890eafaa914317b2a67a4b0df9c3a5ea04d88f05 Mon Sep 17 00:00:00 2001 +From: Matt DeVillier +Date: Fri, 18 Jul 2025 14:24:05 -0500 +Subject: [PATCH 41/41] mb/lenovo/t480(s): Enable TBT support + +Select the discrete TBT controller driver, and configure the necessary +GPIOs for the Alpine Ridge TBT controller to be fully functional. +Update the documentation w/r/t TBT functionality. + +TEST=build/boot Lenovo T480, boot Linux, verify all TBT-related PCI +devices populated, lower USB-C port works for USB data and PCIe. + +Change-Id: Ie5586fa72ed6819b9d1c37373c21605d39bad7b4 +Signed-off-by: Matt DeVillier +--- + Documentation/mainboard/lenovo/skylake.md | 3 +-- + src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 2 ++ + src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c | 8 ++++---- + .../lenovo/sklkbl_thinkpad/variants/t480s/gpio.c | 8 ++++---- + 4 files changed, 11 insertions(+), 10 deletions(-) + +diff --git a/Documentation/mainboard/lenovo/skylake.md b/Documentation/mainboard/lenovo/skylake.md +index 64e075e2cd..352d91b3ef 100644 +--- a/Documentation/mainboard/lenovo/skylake.md ++++ b/Documentation/mainboard/lenovo/skylake.md +@@ -193,8 +193,6 @@ binaries if only flashing the `bios` region. + + ## Known Issues + +-- Alpine Ridge Thunderbolt 3 controller does not work +- - Lower (right) USB-C port only works for charging/DP alt mode, not USB/PCIe data + - Some Fn+F{1-12} keys aren't handled correctly + - Nvidia dGPU is finicky + - Needs option ROM +@@ -206,6 +204,7 @@ binaries if only flashing the `bios` region. + + ## Verified Working + ++- Alpine Ridge Thunderbolt 3 controller + - Integrated graphics init with libgfxinit + - video output: internal (eDP), miniDP + - ACPI support +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +index d69d94f638..c60b85af08 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +@@ -33,6 +33,7 @@ config BOARD_LENOVO_T480 + bool + select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON + select SOC_INTEL_KABYLAKE ++ select DRIVERS_INTEL_DTBT + select MEC1653_HAS_DEBUG_UNLOCK + select VARIANT_HAS_DGPU + +@@ -40,6 +41,7 @@ config BOARD_LENOVO_T480S + bool + select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON + select SOC_INTEL_KABYLAKE ++ select DRIVERS_INTEL_DTBT + select VARIANT_HAS_DGPU + + config BOARD_LENOVO_T580 +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c +index f337843fd9..ffd2841e49 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c +@@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = { + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ +- PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ ++ PAD_CFG_GPO(GPP_C21, 1, PLTRST), /* TBT_FORCE_PWR */ + PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ + +@@ -191,9 +191,9 @@ static const struct pad_config gpio_table[] = { + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), +- PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ +- PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ +- PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ ++ PAD_CFG_GPO(GPP_G4, 1, PLTRST), /* TBT_RTD3_PWR_EN */ ++ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* TBT_FORCE_USB_PWR */ ++ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* -TBT_PERST */ + PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ + }; + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c +index 4f1c57390d..c24c1abb07 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c +@@ -82,7 +82,7 @@ static const struct pad_config gpio_table[] = { + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ +- PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ ++ PAD_CFG_GPO(GPP_C21, 1, PLTRST), /* TBT_FORCE_PWR */ + PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ + +@@ -187,9 +187,9 @@ static const struct pad_config gpio_table[] = { + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), +- PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ +- PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ +- PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ ++ PAD_CFG_GPO(GPP_G4, 1, PLTRST), /* TBT_RTD3_PWR_EN */ ++ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* TBT_FORCE_USB_PWR */ ++ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* -TBT_PERST */ + PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ + }; + +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0041-soc-alderlake-disable-stack-overflow-debug-option.patch b/config/coreboot/default/patches/0041-soc-alderlake-disable-stack-overflow-debug-option.patch deleted file mode 100644 index 979eff9b..00000000 --- a/config/coreboot/default/patches/0041-soc-alderlake-disable-stack-overflow-debug-option.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 9936228e74ef8bccbf6adb8640040901d395cda0 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 6 Oct 2025 04:47:06 +0100 -Subject: [PATCH 1/1] soc/alderlake: disable stack overflow debug option - -same as on other boards. based on this commit: - -commit 51cc2bacb6b07279b97e9934d079060475481fb6 -Author: Subrata Banik -Author: Subrata Banik -Date: Fri Dec 13 13:07:28 2024 +0530 - - soc/intel/pantherlake: Disable stack overflow debug options - -yeah, i've been replicating this change per platform. - -we do alderlake now in libreboot, so let's set that here too. - -Signed-off-by: Leah Rowe ---- - src/soc/intel/alderlake/Kconfig | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 3979d9e162..a47a27dfaf 100644 ---- a/src/soc/intel/alderlake/Kconfig -+++ b/src/soc/intel/alderlake/Kconfig -@@ -329,6 +329,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ - int - default 19200000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ - int - default 133 --- -2.47.3 - diff --git a/config/coreboot/default/patches/0042-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch b/config/coreboot/default/patches/0042-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch deleted file mode 100644 index b4ebd870..00000000 --- a/config/coreboot/default/patches/0042-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 732819a85ea6cca637350192fbab9d459dc68439 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Sun, 11 May 2025 15:41:22 -0600 -Subject: [PATCH 1/2] ec/dell/mec5035: Add command to disable EC-initiated - thermal shutdown - -If command 0xBF isn't sent, the EC shuts down the system without warning -as soon as the CPU temperature reaches about 87 degrees, without letting -the CPU thermal throttle to try and reduce the temperature. With vendor -firmware, the CPU is able to reach around 100 degrees before thermal -throttling. - -This command was found by collecting EC commands by logging the LPC bus -while running with vendor firmware and then replaying observed commands -from coreboot. By systematically replaying subsets of commands in a -binary search pattern and then stress testing the system, the command to -disable the shutdown was isolated. - -The exact meaning of the parameters for this command are unknown at this -time, but do seem to differ between different generations of these -laptops. Due to this, the commmand should be called by mainboard -specific code which passes the specific parameter value used. - -The Google Wilco EC code, which runs on Latitude Chromebooks and shares -many commands with the standard Latitude ECs, suggests that command 0xBF -tells the EC about the processors CPUID. However, the values observed in -LPC bus logs do not seem to correspond with any CPUID values on the -non-Chromebook systems I tested. - -Observed command parameter values (sent on mailbox registers 2-4): -- E6430 (Ivy Bridge): 0x07, 0x00, 0x00 -- M6800 (Haswell): 0x14, 0x00, 0x00 - -Change-Id: I42f09a3ef681007f64d9c5b1a29248b594737a86 -Signed-off-by: Nicholas Chin ---- - src/ec/dell/mec5035/mec5035.c | 19 +++++++++++++++++++ - src/ec/dell/mec5035/mec5035.h | 2 ++ - 2 files changed, 21 insertions(+) - -diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index bdae929a27..b3574611a7 100644 ---- a/src/ec/dell/mec5035/mec5035.c -+++ b/src/ec/dell/mec5035/mec5035.c -@@ -115,6 +115,25 @@ void mec5035_sleep_enable(void) - ec_command(CMD_SLEEP_ENABLE); - } - -+void mec5035_cmd_bf(u8 i) -+{ -+ /* -+ * If this command isn't sent, the EC shuts down the system as soon as -+ * the CPU temperature reaches about 87 degrees. It is unknown exactly -+ * what the parameters represent. The Google Wilco EC code, which runs -+ * on Latitude Chromebooks and shares some commands with the standard -+ * Latitude EC code, suggests command 0xBF tells the EC the CPUID, but -+ * the values observed in LPC bus logs don't seem to match any CPUID -+ * values of the normal Latitudes this was tested with. -+ * Observed i values: -+ * - E6430 (Ivy Bridge): 0x7 -+ * - M6800 (Haswell): 0x14 -+ */ -+ u8 buf[3] = {i, 0, 0}; -+ write_mailbox_regs(buf, 2, 3); -+ ec_command(CMD_BF); -+} -+ - void mec5035_early_init(void) - { - /* If this isn't sent the EC shuts down the system after about 15 -diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h -index 51422598c4..f1d8c43051 100644 ---- a/src/ec/dell/mec5035/mec5035.h -+++ b/src/ec/dell/mec5035/mec5035.h -@@ -14,6 +14,7 @@ enum mec5035_cmd { - CMD_POWER_BUTTON_TO_HOST = 0x3e, - CMD_ACPI_WAKEUP_CHANGE = 0x4a, - CMD_SLEEP_ENABLE = 0x64, -+ CMD_BF = 0xbf, - CMD_CPU_OK = 0xc2, - }; - -@@ -66,5 +67,6 @@ void mec5035_change_wake(u8 source, enum ec_wake_change change); - void mec5035_sleep_enable(void); - - void mec5035_smi_sleep(int slp_type); -+void mec5035_cmd_bf(u8 i); - - #endif /* _EC_DELL_MEC5035_H_ */ --- -2.47.3 - diff --git a/config/coreboot/default/patches/0043-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch b/config/coreboot/default/patches/0043-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch deleted file mode 100644 index 25074d11..00000000 --- a/config/coreboot/default/patches/0043-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch +++ /dev/null @@ -1,36 +0,0 @@ -From b93835414970c3b3e5a3f9ccaa82e2ae80756f82 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Sun, 11 May 2025 16:28:23 -0600 -Subject: [PATCH 2/2] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown - at 87 degrees - -If command 0xBF isn't sent, the EC will shut down the system without -warning once the CPU reaches approximately 87 degrees, without the -system thermal throttling first. Call the newly added function from the -MEC5035 code to send this command and disable this behavior. - -Tested on the Latitude E6430. - -Change-Id: I2b2dc1e3ab115e05d05eaac06892343394d37fdf -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/snb_ivb_latitude/early_init.c | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/src/mainboard/dell/snb_ivb_latitude/early_init.c b/src/mainboard/dell/snb_ivb_latitude/early_init.c -index ff83db095b..ef385a0a70 100644 ---- a/src/mainboard/dell/snb_ivb_latitude/early_init.c -+++ b/src/mainboard/dell/snb_ivb_latitude/early_init.c -@@ -11,4 +11,9 @@ void bootblock_mainboard_early_init(void) - | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN - | COMB_LPC_EN | COMA_LPC_EN); - mec5035_early_init(); -+ -+ /* Observed from LPC logs with vendor firmware. Seems to disable -+ * EC-initiated shutdown when the CPU reaches approximately 87 degrees. -+ * The exact meaning of the parameter is currently unknown. */ -+ mec5035_cmd_bf(0x07); - } --- -2.47.3 - diff --git a/config/coreboot/default/patches/0044-mb-lenovo-t480-Fix-headphone-jack.patch b/config/coreboot/default/patches/0044-mb-lenovo-t480-Fix-headphone-jack.patch deleted file mode 100644 index 92e18e57..00000000 --- a/config/coreboot/default/patches/0044-mb-lenovo-t480-Fix-headphone-jack.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 5d463e5e0c33f1788d329ba07ebc20dad552c49e Mon Sep 17 00:00:00 2001 -From: Arthur Heymans -Date: Thu, 13 Nov 2025 15:45:46 +0100 -Subject: [PATCH] mb/lenovo/t480: Fix headphone jack - -Add additional register configuration for the Realtek ALC257 audio -codec on the Lenovo ThinkPad T480. This includes: - -- Hidden register SW reset sequence -- ClassD 2W amplifier configuration -- Jack detection (JD1) setup for headphone port -- Silence data mode threshold setting at -84dB - -Shamelessly taken from google/brya/variants/pujjolo/hda_verb.c - -Change-Id: Ib77138d782ceb9feeaef82935bc1c0d5c3066183 -Signed-off-by: Arthur Heymans -Reviewed-on: https://review.coreboot.org/c/coreboot/+/90023 -Tested-by: build bot (Jenkins) -Reviewed-by: Paul Menzel -Reviewed-by: Elyes Haouas ---- - .../sklkbl_thinkpad/variants/t480/hda_verb.c | 37 ++++++++++++++++++- - 1 file changed, 36 insertions(+), 1 deletion(-) - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c -index 3a951ce0da..fc8cac8680 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c -@@ -5,7 +5,7 @@ - const u32 cim_verb_data[] = { - 0x10ec0257, // Vendor/Device ID: Realtek ALC257 - 0x17aa225d, // Subsystem ID -- 11, -+ 18, - AZALIA_SUBVENDOR(0, 0x17aa225d), - - AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( -@@ -51,6 +51,41 @@ const u32 cim_verb_data[] = { - 1, 15 - )), - -+ //==========Widget node 0x20 - 0 :Hidden register SW reset -+ 0x0205001A, -+ 0x0204C003, -+ 0x0205001A, -+ 0x0204C003, -+ 0x05850000, -+ 0x0584F880, -+ 0x05850000, -+ 0x0584F880, -+ //==========Widget node 0x20 - 1 : ClassD 2W -+ 0x02050038, -+ 0x02048981, -+ 0x0205001B, -+ 0x02040A4B, -+ //==========Widget node 0x20 - 2 -+ 0x0205003C, -+ 0x02043154, -+ 0x0205003C, -+ 0x02043114, -+ //==========Widget node 0x20 - 3 : -+ 0x02050046, -+ 0x02040004, -+ 0x05750003, -+ 0x057409A3, -+ //==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD -+ 0x02050009, -+ 0x02046003, -+ 0x0205000A, -+ 0x02047770, -+ //==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB) -+ 0x02050037, -+ 0x0204FE15, -+ 0x02050030, -+ 0x02049004, -+ - 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI - 0x80860101, // Subsystem ID - 4, --- -2.52.0 - diff --git a/config/coreboot/default/patches/0045-mb-lenovo-t480s-Fix-headphone-jack.patch b/config/coreboot/default/patches/0045-mb-lenovo-t480s-Fix-headphone-jack.patch deleted file mode 100644 index aa75f0ad..00000000 --- a/config/coreboot/default/patches/0045-mb-lenovo-t480s-Fix-headphone-jack.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 8a9e9a2c66e90f916c891a80ffe2db0767bd0ae8 Mon Sep 17 00:00:00 2001 -From: Matt DeVillier -Date: Wed, 10 Dec 2025 11:02:30 -0600 -Subject: [PATCH 1/1] mb/lenovo/t480s: Fix headphone jack - -Add additional register configuration for the Realtek ALC257 audio -codec on the Lenovo ThinkPad T480s. This includes: - -- Hidden register SW reset sequence -- ClassD 2W amplifier configuration -- Jack detection (JD1) setup for headphone port -- Silence data mode threshold setting at -84dB - -Copied from the T480, originally sourced from -mb/google/brya/variants/pujjolo/hda_verb.c - -Addresses issue #619 - -Change-Id: I0ddea39b40566d6966e89c77352c0904b3c60da9 -Signed-off-by: Matt DeVillier ---- - .../sklkbl_thinkpad/variants/t480s/hda_verb.c | 37 ++++++++++++++++++- - 1 file changed, 36 insertions(+), 1 deletion(-) - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c -index b1d96c5a76..9eb9287f9b 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c -@@ -5,7 +5,7 @@ - const u32 cim_verb_data[] = { - 0x10ec0257, // Vendor/Device ID: Realtek ALC257 - 0x17aa2258, // Subsystem ID -- 11, -+ 18, - AZALIA_SUBVENDOR(0, 0x17aa2258), - - AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( -@@ -51,6 +51,41 @@ const u32 cim_verb_data[] = { - 1, 15 - )), - -+ //==========Widget node 0x20 - 0 :Hidden register SW reset -+ 0x0205001A, -+ 0x0204C003, -+ 0x0205001A, -+ 0x0204C003, -+ 0x05850000, -+ 0x0584F880, -+ 0x05850000, -+ 0x0584F880, -+ //==========Widget node 0x20 - 1 : ClassD 2W -+ 0x02050038, -+ 0x02048981, -+ 0x0205001B, -+ 0x02040A4B, -+ //==========Widget node 0x20 - 2 -+ 0x0205003C, -+ 0x02043154, -+ 0x0205003C, -+ 0x02043114, -+ //==========Widget node 0x20 - 3 : -+ 0x02050046, -+ 0x02040004, -+ 0x05750003, -+ 0x057409A3, -+ //==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD -+ 0x02050009, -+ 0x02046003, -+ 0x0205000A, -+ 0x02047770, -+ //==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB) -+ 0x02050037, -+ 0x0204FE15, -+ 0x02050030, -+ 0x02049004, -+ - 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI - 0x80860101, // Subsystem ID - 4, --- -2.47.3 - diff --git a/config/coreboot/default/patches/0046-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch b/config/coreboot/default/patches/0046-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch deleted file mode 100644 index c7042f94..00000000 --- a/config/coreboot/default/patches/0046-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch +++ /dev/null @@ -1,358 +0,0 @@ -From a656a385e2c5b3945ff29a45b4129a2516f4b168 Mon Sep 17 00:00:00 2001 -From: Jeremy Soller -Date: Fri, 31 May 2024 13:58:00 -0600 -Subject: [PATCH 1/2] drivers/intel/dtbt: Add discrete Thunderbolt driver - -Add a new driver which enables basic TBT support for the Alpine Ridge, -Titan Ridge, and Maple Ridge discrete Thunderbolt controllers. - -This driver will initially be used on the Lenovo T480/T480s and -System76 RPL-HX platform boards. It currently only supports a single -dTBT controller. - -Ref: edk2-platforms KabylakeOpenBoardPkg reference implementation -Ref: Titan Ridge BIOS Implementation Guide v1.4 -Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472) - -Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364 -Signed-off-by: Jeremy Soller -Signed-off-by: Tim Crawford -Signed-off-by: Matt DeVillier ---- - src/drivers/intel/dtbt/Kconfig | 6 + - src/drivers/intel/dtbt/Makefile.mk | 3 + - src/drivers/intel/dtbt/chip.h | 8 ++ - src/drivers/intel/dtbt/dtbt.c | 202 +++++++++++++++++++++++++++++ - src/drivers/intel/dtbt/dtbt.h | 73 +++++++++++ - 5 files changed, 292 insertions(+) - create mode 100644 src/drivers/intel/dtbt/Kconfig - create mode 100644 src/drivers/intel/dtbt/Makefile.mk - create mode 100644 src/drivers/intel/dtbt/chip.h - create mode 100644 src/drivers/intel/dtbt/dtbt.c - create mode 100644 src/drivers/intel/dtbt/dtbt.h - -diff --git a/src/drivers/intel/dtbt/Kconfig b/src/drivers/intel/dtbt/Kconfig -new file mode 100644 -index 0000000000..d895dbd288 ---- /dev/null -+++ b/src/drivers/intel/dtbt/Kconfig -@@ -0,0 +1,6 @@ -+config DRIVERS_INTEL_DTBT -+ def_bool n -+ help -+ Support for discrete Thunderbolt controllers. -+ Currently only supports a single dTBT controller from the -+ Alpine Ridge, Titan Ridge, and Maple Ridge families. -diff --git a/src/drivers/intel/dtbt/Makefile.mk b/src/drivers/intel/dtbt/Makefile.mk -new file mode 100644 -index 0000000000..1b5252dda0 ---- /dev/null -+++ b/src/drivers/intel/dtbt/Makefile.mk -@@ -0,0 +1,3 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c -diff --git a/src/drivers/intel/dtbt/chip.h b/src/drivers/intel/dtbt/chip.h -new file mode 100644 -index 0000000000..2b1dfa70a5 ---- /dev/null -+++ b/src/drivers/intel/dtbt/chip.h -@@ -0,0 +1,8 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_ -+#define _DRIVERS_INTEL_DTBT_CHIP_H_ -+ -+struct drivers_intel_dtbt_config {}; -+ -+#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */ -diff --git a/src/drivers/intel/dtbt/dtbt.c b/src/drivers/intel/dtbt/dtbt.c -new file mode 100644 -index 0000000000..8613eee5e0 ---- /dev/null -+++ b/src/drivers/intel/dtbt/dtbt.c -@@ -0,0 +1,202 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "chip.h" -+#include "dtbt.h" -+ -+ -+/* -+ * We only want to enable the first/primary bridge device, -+ * as sending mailbox commands to secondary ones will fail, -+ * and we only want to create a single ACPI device in the SSDT. -+ */ -+static bool enable_done; -+static bool ssdt_done; -+ -+static void dtbt_cmd(struct device *dev, u32 command, u32 data, u32 timeout) -+{ -+ u32 reg = (data << 8) | (command << 1) | PCIE2TBT_VALID; -+ u32 status; -+ -+ printk(BIOS_SPEW, "dTBT send command 0x%x\n", command); -+ /* Send command */ -+ pci_write_config32(dev, PCIE2TBT, reg); -+ /* Wait for done bit to be cleared */ -+ if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) -+ printk(BIOS_ERR, "dTBT command 0x%x send timeout, status 0x%x\n", command, status); -+ /* Clear valid bit */ -+ pci_write_config32(dev, PCIE2TBT, 0); -+ /* Wait for done bit to be cleared */ -+ if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) -+ printk(BIOS_ERR, "dTBT command 0x%x clear valid bit timeout, status 0x%x\n", command, status); -+} -+ -+static void dtbt_write_dsd(void) -+{ -+ struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); -+ -+ acpi_device_add_hotplug_support_in_d3(dsd); -+ acpi_device_add_external_facing_port(dsd); -+ acpi_dp_write(dsd); -+} -+ -+static void dtbt_write_opregion(const struct bus *bus) -+{ -+ uintptr_t mmconf_base = (uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS -+ + (((uintptr_t)(bus->secondary)) << 20); -+ const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, mmconf_base, 0x1000); -+ const struct fieldlist fieldlist[] = { -+ FIELDLIST_OFFSET(TBT2PCIE), -+ FIELDLIST_NAMESTR("TB2P", 32), -+ FIELDLIST_OFFSET(PCIE2TBT), -+ FIELDLIST_NAMESTR("P2TB", 32), -+ }; -+ -+ acpigen_write_opregion(&opregion); -+ acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), -+ FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); -+} -+ -+static void dtbt_fill_ssdt(const struct device *dev) -+{ -+ struct bus *bus; -+ struct device *parent; -+ const char *parent_scope; -+ const char *dev_name = acpi_device_name(dev); -+ -+ if (ssdt_done) -+ return; -+ -+ bus = dev->upstream; -+ if (!bus) { -+ printk(BIOS_ERR, "dTBT bus invalid\n"); -+ return; -+ } -+ -+ parent = bus->dev; -+ if (!parent || !is_pci(parent)) { -+ printk(BIOS_ERR, "dTBT parent invalid\n"); -+ return; -+ } -+ -+ parent_scope = acpi_device_path(parent); -+ if (!parent_scope) { -+ printk(BIOS_ERR, "dTBT parent scope not valid\n"); -+ return; -+ } -+ -+ /* Scope */ -+ acpigen_write_scope(parent_scope); -+ dtbt_write_dsd(); -+ -+ /* Device */ -+ acpigen_write_device(dev_name); -+ acpigen_write_name_integer("_ADR", 0); -+ dtbt_write_opregion(bus); -+ -+ /* PTS Method */ -+ acpigen_write_method_serialized("PTS", 0); -+ -+ acpigen_write_debug_string("dTBT prepare to sleep"); -+ acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE << 1, "P2TB"); -+ acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", PCIE2TBT_GO2SX_NO_WAKE << 1); -+ -+ acpigen_write_debug_namestr("TB2P"); -+ acpigen_write_store_int_to_namestr(0, "P2TB"); -+ acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", 0); -+ acpigen_write_debug_namestr("TB2P"); -+ -+ acpigen_write_method_end(); -+ acpigen_write_device_end(); -+ acpigen_write_scope_end(); -+ -+ // \.TBTS Method -+ acpigen_write_scope("\\"); -+ acpigen_write_method("TBTS", 0); -+ acpigen_emit_namestring(acpi_device_path_join(dev, "PTS")); -+ acpigen_write_method_end(); -+ acpigen_write_scope_end(); -+ -+ printk(BIOS_INFO, "%s.%s %s\n", parent_scope, dev_name, dev_path(dev)); -+ ssdt_done = true; -+} -+ -+static const char *dtbt_acpi_name(const struct device *dev) -+{ -+ return "DTBT"; -+} -+ -+static void dtbt_enable(struct device *dev) -+{ -+ if (!is_dev_enabled(dev) || enable_done) -+ return; -+ -+ printk(BIOS_INFO, "dTBT controller found at %s\n", dev_path(dev)); -+ -+ // XXX: Recommendation is to set SL1 ("User Authorization") -+ printk(BIOS_DEBUG, "dTBT set security level SL0\n"); -+ /* Set security level */ -+ dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL, SEC_LEVEL_NONE, MBOX_TIMEOUT_MS); -+ -+ if (acpi_is_wakeup_s3()) { -+ printk(BIOS_DEBUG, "dTBT SX exit\n"); -+ dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED, 0, MBOX_TIMEOUT_MS); -+ /* Read TBT2PCIE register, verify not invalid */ -+ if (pci_read_config32(dev, TBT2PCIE) == 0xffffffff) -+ printk(BIOS_ERR, "dTBT S3 resume failure.\n"); -+ } else { -+ printk(BIOS_DEBUG, "dTBT set boot on\n"); -+ dtbt_cmd(dev, PCIE2TBT_BOOT_ON, 0, MBOX_TIMEOUT_MS); -+ printk(BIOS_DEBUG, "dTBT set USB on\n"); -+ dtbt_cmd(dev, PCIE2TBT_USB_ON, 0, MBOX_TIMEOUT_MS); -+ } -+ enable_done = true; -+} -+ -+static struct pci_operations dtbt_device_ops_pci = { -+ .set_subsystem = 0, -+}; -+ -+static struct device_operations dtbt_device_ops = { -+ .read_resources = pci_bus_read_resources, -+ .set_resources = pci_dev_set_resources, -+ .enable_resources = pci_bus_enable_resources, -+ .acpi_fill_ssdt = dtbt_fill_ssdt, -+ .acpi_name = dtbt_acpi_name, -+ .scan_bus = pciexp_scan_bridge, -+ .reset_bus = pci_bus_reset, -+ .ops_pci = &dtbt_device_ops_pci, -+ .enable = dtbt_enable -+}; -+ -+/* We only want to match the (first) bridge device */ -+static const unsigned short pci_device_ids[] = { -+ AR_2C_BRG, -+ AR_4C_BRG, -+ AR_LP_BRG, -+ AR_4C_C0_BRG, -+ AR_2C_C0_BRG, -+ TR_2C_BRG, -+ TR_4C_BRG, -+ TR_DD_BRG, -+ MR_2C_BRG, -+ MR_4C_BRG, -+ 0 -+}; -+ -+static const struct pci_driver intel_dtbt_driver __pci_driver = { -+ .ops = &dtbt_device_ops, -+ .vendor = PCI_VID_INTEL, -+ .devices = pci_device_ids, -+}; -+ -+struct chip_operations drivers_intel_dtbt_ops = { -+ .name = "Intel Discrete Thunderbolt", -+}; -diff --git a/src/drivers/intel/dtbt/dtbt.h b/src/drivers/intel/dtbt/dtbt.h -new file mode 100644 -index 0000000000..d01d3a35ef ---- /dev/null -+++ b/src/drivers/intel/dtbt/dtbt.h -@@ -0,0 +1,73 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef _DRIVERS_INTEL_DTBT_H_ -+#define _DRIVERS_INTEL_DTBT_H_ -+ -+/* Alpine Ridge device IDs */ -+#define AR_2C_NHI 0x1575 -+#define AR_2C_BRG 0x1576 -+#define AR_2C_USB 0x15B5 -+#define AR_4C_NHI 0x1577 -+#define AR_4C_BRG 0x1578 -+#define AR_4C_USB 0x15B6 -+#define AR_LP_NHI 0x15BF -+#define AR_LP_BRG 0x15C0 -+#define AR_LP_USB 0x15C1 -+#define AR_4C_C0_NHI 0x15D2 -+#define AR_4C_C0_BRG 0x15D3 -+#define AR_4C_C0_USB 0x15D4 -+#define AR_2C_C0_NHI 0x15D9 -+#define AR_2C_C0_BRG 0x15DA -+#define AR_2C_C0_USB 0x15DB -+ -+/* Titan Ridge device IDs */ -+#define TR_2C_BRG 0x15E7 -+#define TR_2C_NHI 0x15E8 -+#define TR_2C_USB 0x15E9 -+#define TR_4C_BRG 0x15EA -+#define TR_4C_NHI 0x15EB -+#define TR_4C_USB 0x15EC -+#define TR_DD_BRG 0x15EF -+#define TR_DD_USB 0x15F0 -+ -+/* Maple Ridge device IDs */ -+#define MR_2C_BRG 0x1133 -+#define MR_2C_NHI 0x1134 -+#define MR_2C_USB 0x1135 -+#define MR_4C_BRG 0x1136 -+#define MR_4C_NHI 0x1137 -+#define MR_4C_USB 0x1138 -+ -+/* Security Levels */ -+#define SEC_LEVEL_NONE 0 -+#define SEC_LEVEL_USER 1 -+#define SEC_LEVEL_AUTH 2 -+#define SEC_LEVEL_DP_ONLY 3 -+ -+#define PCIE2TBT 0x54C -+#define PCIE2TBT_VALID BIT(0) -+#define PCIE2TBT_GO2SX 2 -+#define PCIE2TBT_GO2SX_NO_WAKE 3 -+#define PCIE2TBT_SX_EXIT_TBT_CONNECTED 4 -+#define PCIE2TBT_OS_UP 6 -+#define PCIE2TBT_SET_SECURITY_LEVEL 8 -+#define PCIE2TBT_GET_SECURITY_LEVEL 9 -+#define PCIE2TBT_BOOT_ON 24 -+#define PCIE2TBT_USB_ON 25 -+#define PCIE2TBT_GET_ENUMERATION_METHOD 26 -+#define PCIE2TBT_SET_ENUMERATION_METHOD 27 -+#define PCIE2TBT_POWER_CYCLE 28 -+#define PCIE2TBT_SX_START 29 -+#define PCIE2TBT_ACL_BOOT 30 -+#define PCIE2TBT_CONNECT_TOPOLOGY 31 -+ -+#define TBT2PCIE 0x548 -+#define TBT2PCIE_DONE BIT(0) -+ -+// Timeout for mailbox commands unless otherwise specified. -+#define MBOX_TIMEOUT_MS 5000 -+ -+// Timeout for controller to ack GO2SX/GO2SX_NO_WAKE mailbox command. -+#define GO2SX_TIMEOUT_MS 600 -+ -+#endif /* _DRIVERS_INTEL_DTBT_H_ */ --- -2.47.3 - diff --git a/config/coreboot/default/patches/0047-mb-lenovo-t480-s-Enable-TBT-support.patch b/config/coreboot/default/patches/0047-mb-lenovo-t480-s-Enable-TBT-support.patch deleted file mode 100644 index 02d73f79..00000000 --- a/config/coreboot/default/patches/0047-mb-lenovo-t480-s-Enable-TBT-support.patch +++ /dev/null @@ -1,123 +0,0 @@ -From 5249bfd28ffcdab2d54c3c111ec6d3dc567ad090 Mon Sep 17 00:00:00 2001 -From: Matt DeVillier -Date: Fri, 18 Jul 2025 14:24:05 -0500 -Subject: [PATCH 2/2] mb/lenovo/t480(s): Enable TBT support - -Select the discrete TBT controller driver, and configure the necessary -GPIOs for the Alpine Ridge TBT controller to be fully functional. -Update the documentation w/r/t TBT functionality. - -TEST=build/boot Lenovo T480, boot Linux, verify all TBT-related PCI -devices populated, lower USB-C port works for USB data and PCIe. - -Change-Id: Ie5586fa72ed6819b9d1c37373c21605d39bad7b4 -Signed-off-by: Matt DeVillier ---- - Documentation/mainboard/lenovo/t480.md | 5 ++--- - src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 2 ++ - src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c | 8 ++++---- - .../lenovo/sklkbl_thinkpad/variants/t480s/gpio.c | 8 ++++---- - 4 files changed, 12 insertions(+), 11 deletions(-) - -diff --git a/Documentation/mainboard/lenovo/t480.md b/Documentation/mainboard/lenovo/t480.md -index 9ebce8ff7d..4c3408c4aa 100644 ---- a/Documentation/mainboard/lenovo/t480.md -+++ b/Documentation/mainboard/lenovo/t480.md -@@ -162,8 +162,6 @@ binaries if only flashing the `bios` region. - - ## Known Issues - --- Alpine Ridge Thunderbolt 3 controller does not work -- - Lower (right) USB-C port only works for charging/DP alt mode, not USB/PCIe data - - Some Fn+F{1-12} keys aren't handled correctly - - Nvidia dGPU is finicky - - Needs option ROM -@@ -175,6 +173,7 @@ binaries if only flashing the `bios` region. - - ## Verified Working - -+- Alpine Ridge Thunderbolt 3 controller - - Integrated graphics init with libgfxinit - - video output: internal (eDP), miniDP - - ACPI support -@@ -196,4 +195,4 @@ binaries if only flashing the `bios` region. - [from Lenovo's site]: https://pcsupport.lenovo.com/gb/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480s-type-20l7-20l8/solutions/ht508988-critical-intel-thunderbolt-software-and-firmware-updates-thinkpad - [how to externally flash the TB3 firmware]: https://libreboot.org/docs/install/t480.html#thunderbolt-issue-read-this-before-flashing - [Dell firmware updater]: https://web.archive.org/web/20241110222323/https://dl.dell.com/FOLDER04573471M/1/Inspiron_5468_1.3.0.exe --[Dell_PFS_Extract.py]: https://github.com/vuquangtrong/Dell-PFS-BIOS-Assembler/blob/master/Dell_PFS_Extract.py -\ No newline at end of file -+[Dell_PFS_Extract.py]: https://github.com/vuquangtrong/Dell-PFS-BIOS-Assembler/blob/master/Dell_PFS_Extract.py -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -index 6036ceb06d..e6fb950d66 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -@@ -26,12 +26,14 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON - config BOARD_LENOVO_T480 - bool - select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON -+ select DRIVERS_INTEL_DTBT - select MEC1653_HAS_DEBUG_UNLOCK - select VARIANT_HAS_DGPU - - config BOARD_LENOVO_T480S - bool - select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON -+ select DRIVERS_INTEL_DTBT - select VARIANT_HAS_DGPU - - if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c -index f337843fd9..ffd2841e49 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c -@@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_C18, NONE), - PAD_NC(GPP_C19, NONE), - PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ -- PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ -+ PAD_CFG_GPO(GPP_C21, 1, PLTRST), /* TBT_FORCE_PWR */ - PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ - PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ - -@@ -191,9 +191,9 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_G1, NONE), - PAD_NC(GPP_G2, NONE), - PAD_NC(GPP_G3, NONE), -- PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ -- PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ -- PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ -+ PAD_CFG_GPO(GPP_G4, 1, PLTRST), /* TBT_RTD3_PWR_EN */ -+ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* TBT_FORCE_USB_PWR */ -+ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* -TBT_PERST */ - PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ - }; - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c -index 4f1c57390d..c24c1abb07 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c -@@ -82,7 +82,7 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_C18, NONE), - PAD_NC(GPP_C19, NONE), - PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ -- PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ -+ PAD_CFG_GPO(GPP_C21, 1, PLTRST), /* TBT_FORCE_PWR */ - PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ - PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ - -@@ -187,9 +187,9 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_G1, NONE), - PAD_NC(GPP_G2, NONE), - PAD_NC(GPP_G3, NONE), -- PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ -- PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ -- PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ -+ PAD_CFG_GPO(GPP_G4, 1, PLTRST), /* TBT_RTD3_PWR_EN */ -+ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* TBT_FORCE_USB_PWR */ -+ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* -TBT_PERST */ - PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ - }; - --- -2.47.3 - -- cgit v1.2.1