From c7569a67145a9534b14f477e088bb60e4330f9be Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 21 Apr 2025 05:03:07 +0100 Subject: coreboot/next: merge with coreboot/default I also cherry-picked a patch from Heads, that fixes build issues caused by the hacks in the T480 port; several changes made by Mate are now ifdef'd based on whether a KabyLake ThinkPad is specified in defconfig. Signed-off-by: Leah Rowe --- ...kylake-Disable-stack-overflow-debug-optio.patch | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 config/coreboot/default/patches/0035-src-intel-skylake-Disable-stack-overflow-debug-optio.patch (limited to 'config/coreboot/default/patches/0035-src-intel-skylake-Disable-stack-overflow-debug-optio.patch') diff --git a/config/coreboot/default/patches/0035-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0035-src-intel-skylake-Disable-stack-overflow-debug-optio.patch new file mode 100644 index 00000000..eb5f0028 --- /dev/null +++ b/config/coreboot/default/patches/0035-src-intel-skylake-Disable-stack-overflow-debug-optio.patch @@ -0,0 +1,61 @@ +From 18f4e970ebda43dd538f74398aea463a67040dd3 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 6 Jan 2025 01:36:23 +0000 +Subject: [PATCH 35/37] src/intel/skylake: Disable stack overflow debug options + +The option was appearing in T480/3050micro configs of lbmk, +after updating on the coreboot/next uprev for 20241206 rev8: + +CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y + +I did some digging. See coreboot commit: + +commit 51cc2bacb6b07279b97e9934d079060475481fb6 +Author: Subrata Banik +Date: Fri Dec 13 13:07:28 2024 +0530 + + soc/intel/pantherlake: Disable stack overflow debug options + +Well now: + +I'm disabling this behaviour on Skylake, for the same +behaviour, because I want as few behaviour changes in general, +as possible, for the rev8 release. + +According to Subrata's patch, which was for Pantherlake, +without this change, stack corruption can occur on verstage +and romstage early on. Please look at that coreboot patch, +referenced above, for clarity. + +I see no harm in disabling this option for Skylake, since +the behaviour that it otherwise enables was not present +before. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/skylake/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig +index d51ffaef7b..42af82a5d8 100644 +--- a/src/soc/intel/skylake/Kconfig ++++ b/src/soc/intel/skylake/Kconfig +@@ -129,6 +129,15 @@ config DCACHE_RAM_SIZE + The size of the cache-as-ram region required during bootblock + and/or romstage. + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + config DCACHE_BSP_STACK_SIZE + hex + default 0x20400 if FSP_USES_CB_STACK +-- +2.39.5 + -- cgit v1.2.1