From 14b4838d49556eb544c0f6a96d72128c3480ec2c Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 1 Nov 2024 15:59:30 +0000 Subject: coreboot/default: Re-base all patches There were a lot of unnecessary patches, such as the VRAM patches; as Nicholas Chin has explained to me, the drivers for these machines will just allocate what RAM they want anyway, so in a lot of cases the extra allocated Video RAM simply reduces the total amount of memory for other uses. In general, we have a lot of patches that have existed for years. A much more aggressive sweep will be done in the next major audit, especially when the revisions are updated again. Signed-off-by: Leah Rowe --- ...3-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch | 442 --------------------- 1 file changed, 442 deletions(-) delete mode 100644 config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch (limited to 'config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch') diff --git a/config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch b/config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch deleted file mode 100644 index 4a7a6bf9..00000000 --- a/config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch +++ /dev/null @@ -1,442 +0,0 @@ -From f781a8bac250d4902ec3e7caa0628c77836a8ae3 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Mon, 4 Mar 2024 18:05:43 -0700 -Subject: [PATCH 23/65] mb/dell: Add Latitude E5420 (Sandy Bridge) - -Mainboard is Krug 14". I do not physically have this system; someone -with physical access to one sent me the output of autoport which I then -modified to produce this port. I was also sent the VBT binary, which was -obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version -A02 of the vendor firmware. - -This was originally tested and found to be working as a standalone board -port in Libreboot, but this variant based port in upstream coreboot has -not been tested. - -This can be internally flashed by sending a command to the EC, which -causes the EC to pull the FDO pin low and the firmware to skip setting -up any chipset based write protections [1]. The EC is the SMSC MEC5055, -which seems to be compatible with the existing MEC5035 code. - -[1] https://gitlab.com/nic3-14159/dell-flash-unlock - -Change-Id: I0283653156083768e1fd451bcf539b4e028589f4 -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/snb_ivb_latitude/Kconfig | 10 +- - .../dell/snb_ivb_latitude/Kconfig.name | 3 + - .../snb_ivb_latitude/variants/e5420/data.vbt | Bin 0 -> 6144 bytes - .../variants/e5420/early_init.c | 14 ++ - .../snb_ivb_latitude/variants/e5420/gpio.c | 195 ++++++++++++++++++ - .../variants/e5420/hda_verb.c | 32 +++ - .../variants/e5420/overridetree.cb | 39 ++++ - 7 files changed, 292 insertions(+), 1 deletion(-) - create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt - create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c - create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c - create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c - create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb - -diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig -index 4e94a7ef80..e6a21ffb99 100644 ---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig -+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig -@@ -17,6 +17,11 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON - select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT - -+config BOARD_DELL_LATITUDE_E5420 -+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON -+ select BOARD_ROMSIZE_KB_6144 -+ select SOUTHBRIDGE_INTEL_BD82X6X -+ - config BOARD_DELL_LATITUDE_E5520 - select BOARD_DELL_SNB_IVB_LATITUDE_COMMON - select BOARD_ROMSIZE_KB_6144 -@@ -60,6 +65,7 @@ config MAINBOARD_DIR - default "dell/snb_ivb_latitude" - - config MAINBOARD_PART_NUMBER -+ default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420 - default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520 - default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 - default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520 -@@ -74,6 +80,7 @@ config USBDEBUG_HCD_INDEX - default 2 - - config VARIANT_DIR -+ default "e5420" if BOARD_DELL_LATITUDE_E5420 - default "e5520" if BOARD_DELL_LATITUDE_E5520 - default "e6420" if BOARD_DELL_LATITUDE_E6420 - default "e6520" if BOARD_DELL_LATITUDE_E6520 -@@ -82,7 +89,8 @@ config VARIANT_DIR - default "e6530" if BOARD_DELL_LATITUDE_E6530 - - config VGA_BIOS_ID -- default "8086,0116" if BOARD_DELL_LATITUDE_E6520 -+ default "8086,0116" if BOARD_DELL_LATITUDE_E6520 \ -+ || BOARD_DELL_LATITUDE_E5420 - default "8086,0166" if BOARD_DELL_LATITUDE_E5530 - default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \ - || BOARD_DELL_LATITUDE_E5520 -diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name -index 7976691f21..a3fa2b1837 100644 ---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name -+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name -@@ -1,5 +1,8 @@ - ## SPDX-License-Identifier: GPL-2.0-only - -+config BOARD_DELL_LATITUDE_E5420 -+ bool "Latitude E5420" -+ - config BOARD_DELL_LATITUDE_E5520 - bool "Latitude E5520" - -diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..98b82fe6110fd295b5749041ec7f8c084ace5f57 -GIT binary patch -literal 6144 -zcmeHKeQZ-z6hE);wSBvNZ!2$ObQ^;MgV6zl*Rhp}BXnCCMZU^_r7jRwT!kfLo8?3H -zk9)u(7?cb(hChhTM57@QFfmbMB!G!dNsO6BW5OSp5EGF^jHnTTdhUBI+h`e+1ft1q -z^SfW?+;h)4_uO+|XEfEV$91)}c;!*XQ5O -z)OU7u$J@4U+lk)#GSW%c%c)v`%R6?`w)LIyu6bD7-j0o&X9qUMcEsYlW3BU4rZRvt -zqAUpjf*qXuLCCsU0YM2I5@gB1WKd)f1+Yt?%HWd0DZxYumP(Ke?=ER{f^&}W<0k@mxff(?6+Stw+s6y%k1mM$cLk#^FWWI*9bE1GY -z&VY9?WC1u#23^3^UYw5?H0x2S2gN`x18Fko6_x(#MKyuCU_DV -zdkf*li41yW3p$*0Oo3+63kO6S91*KwP#l2i4jnc)JkUirL^$k}VbH0;CBh#BS=OLf -zW-yE3BRon75gG{_2~QIC5cUzCC%i)FCmbidM>tIwAPf>N5Pl?FC0r*+Sq!oXj!keQ -zVKcyK>TL+gc7oLco$28+FpeeXkEP}_Sea=mk#IWUR^m$!BogvszLPu83FJm0k6K*}ACcP}M4exU`*MKVwl5+t6JBpTkmm}xWflKUe~7}`!#%z#gAo{NxUrpDAndYktu -zI0}VLU`J7^xmF1AFiz5S^uzp*DPI$%$qq!(ikh0kP+(GKzF|@N?Y%_#Vp@M+xHr$F -z=%+18z`-fT%z)9-TS$~Dh@2yeN7!UIt0h`fWxUu`JvA_ra*8P48l%7KR0&c1;0R75 -z4f0oz(xQ3MWqz5>qW5M4tZWExHs8X@p!@CBU=7e{5^Jl{s7by`po-AJqM2l -znk(=^0bHkF0rUw7)^7j;$=_UIs8`6P6b-;vPDZ#U9L)W1_PAYRDP9k~;5$stt5ZiV -zD0>;i-?OlYY2}P9WVnfGos4xee2r=EGWHR}ADH$VV>cO=xU?!4TjIi)OMBYI_PX#b -zm-eBHed5BOT-x6*W>;{IqAga~G6lCQT93k>Q}CpsomJR*1%FjEkv?fuT%c-8RklXO -zU8;6KWk*zeU)4TW+1D!mrE0EhHZfbBeN{4S7X@Pig%};A99QTdA~wZruL*8y?K!jP -zG5R*k=);S}ZnA}on(uzNF -zyu>BcjA})C@bg%<;+Eh2;Sz4heFFCbZ@C{FrXMIbYzu>?Bi-|vZ}JSFU%JA>7$7et -z0Yo%CnOVZm#ZA}4kWZOn15};h5*#OM3b+6vHzgruMP>=5MNJK1y42{YgveP-!j%#( -z0rGe@8t%!=66Ti%K4|Gx=o7gFp83wQ;+s3H7+r^SKlpp3KKcr!3@|n;NCH_=qL=3T -zq3WH?en`b+W-HR-fnrhw*9aZ%M}lHX7@H?E>!6wv_&YQFEHdA$%Z1R--yub>=c@p? -z6@7Fc$&>sAxwiz{BE$1kb$K9Co=ozlA973y^i(^BM|EZ$$^y`0KyHiMJ%O*XbfEX1 -ziZaH>W(1pWL0bo|T!x__N$^$DpmxI=bL6WUK3JGyn?rw-qC4ZA$yGjIB}N(=ldD2O -zAJ@bxp2>n}u*mUIYFd>}O_wuwBD^r9<#=!0 -X1LGbT_rSOZ#yv3ZfpHH!G!Og(1Xg~J - -literal 0 -HcmV?d00001 - -diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c -new file mode 100644 -index 0000000000..ff83db095b ---- /dev/null -+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c -@@ -0,0 +1,14 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include -+ -+void bootblock_mainboard_early_init(void) -+{ -+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN -+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN -+ | COMB_LPC_EN | COMA_LPC_EN); -+ mec5035_early_init(); -+} -diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c -new file mode 100644 -index 0000000000..f76b93d9f0 ---- /dev/null -+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c -@@ -0,0 +1,195 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_GPIO, -+ .gpio1 = GPIO_MODE_NATIVE, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_NATIVE, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_GPIO, -+ .gpio8 = GPIO_MODE_GPIO, -+ .gpio9 = GPIO_MODE_NATIVE, -+ .gpio10 = GPIO_MODE_NATIVE, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_GPIO, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_GPIO, -+ .gpio16 = GPIO_MODE_NATIVE, -+ .gpio17 = GPIO_MODE_GPIO, -+ .gpio18 = GPIO_MODE_NATIVE, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_NATIVE, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_GPIO, -+ .gpio31 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio0 = GPIO_DIR_INPUT, -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio7 = GPIO_DIR_INPUT, -+ .gpio8 = GPIO_DIR_INPUT, -+ .gpio12 = GPIO_DIR_OUTPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio15 = GPIO_DIR_INPUT, -+ .gpio17 = GPIO_DIR_INPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_INPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+ .gpio30 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio12 = GPIO_LEVEL_HIGH, -+ .gpio30 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_reset = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio0 = GPIO_INVERT, -+ .gpio8 = GPIO_INVERT, -+ .gpio14 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_NATIVE, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_NATIVE, -+ .gpio46 = GPIO_MODE_GPIO, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_NATIVE, -+ .gpio50 = GPIO_MODE_GPIO, -+ .gpio51 = GPIO_MODE_GPIO, -+ .gpio52 = GPIO_MODE_GPIO, -+ .gpio53 = GPIO_MODE_GPIO, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_GPIO, -+ .gpio56 = GPIO_MODE_GPIO, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_OUTPUT, -+ .gpio35 = GPIO_DIR_INPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_OUTPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio46 = GPIO_DIR_OUTPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio50 = GPIO_DIR_OUTPUT, -+ .gpio51 = GPIO_DIR_OUTPUT, -+ .gpio52 = GPIO_DIR_INPUT, -+ .gpio53 = GPIO_DIR_INPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio55 = GPIO_DIR_OUTPUT, -+ .gpio56 = GPIO_DIR_INPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio34 = GPIO_LEVEL_LOW, -+ .gpio37 = GPIO_LEVEL_LOW, -+ .gpio46 = GPIO_LEVEL_HIGH, -+ .gpio50 = GPIO_LEVEL_HIGH, -+ .gpio51 = GPIO_LEVEL_LOW, -+ .gpio55 = GPIO_LEVEL_LOW, -+ .gpio60 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_reset = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_NATIVE, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_NATIVE, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_NATIVE, -+ .gpio69 = GPIO_MODE_NATIVE, -+ .gpio70 = GPIO_MODE_NATIVE, -+ .gpio71 = GPIO_MODE_NATIVE, -+ .gpio72 = GPIO_MODE_NATIVE, -+ .gpio73 = GPIO_MODE_NATIVE, -+ .gpio74 = GPIO_MODE_GPIO, -+ .gpio75 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio74 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_reset = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ .reset = &pch_gpio_set1_reset, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ .reset = &pch_gpio_set2_reset, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ .reset = &pch_gpio_set3_reset, -+ }, -+}; -diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c -new file mode 100644 -index 0000000000..0bc6c35a63 ---- /dev/null -+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c -@@ -0,0 +1,32 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */ -+ 0x1028049b, /* Subsystem ID */ -+ 11, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(0, 0x1028049b), -+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), -+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), -+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), -+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), -+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), -+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), -+ AZALIA_PIN_CFG(0, 0x11, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), -+ AZALIA_PIN_CFG(0, 0x20, 0xd5a30130), -+ -+ 0x80862805, /* Codec Vendor / Device ID: Intel */ -+ 0x80860101, /* Subsystem ID */ -+ 4, /* Number of 4 dword sets */ -+ AZALIA_SUBVENDOR(3, 0x80860101), -+ AZALIA_PIN_CFG(3, 0x05, 0x18560010), -+ AZALIA_PIN_CFG(3, 0x06, 0x18560020), -+ AZALIA_PIN_CFG(3, 0x07, 0x18560030), -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb -new file mode 100644 -index 0000000000..3f55bfd49d ---- /dev/null -+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb -@@ -0,0 +1,39 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/sandybridge -+ device domain 0 on -+ subsystemid 0x1028 0x049b inherit -+ -+ device ref igd on -+ register "gpu_cpu_backlight" = "0x00000c31" -+ register "gpu_pch_backlight" = "0x13121312" -+ end -+ -+ chip southbridge/intel/bd82x6x -+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }" -+ register "usb_port_config" = "{ -+ { 1, 1, 0 }, -+ { 1, 1, 0 }, -+ { 1, 1, 1 }, -+ { 1, 1, 1 }, -+ { 1, 1, 2 }, -+ { 1, 1, 2 }, -+ { 1, 1, 3 }, -+ { 1, 1, 3 }, -+ { 1, 1, 5 }, -+ { 1, 1, 5 }, -+ { 1, 1, 7 }, -+ { 1, 1, 6 }, -+ { 1, 1, 6 }, -+ { 1, 1, 7 }, -+ }" -+ -+ device ref gbe off end -+ device ref pcie_rp4 off end -+ device ref pcie_rp7 on end # Broadcom BCM5761 Gigabit Ethernet -+ device ref sata1 on -+ register "sata_port_map" = "0x3b" -+ end -+ end -+ end -+end --- -2.39.5 - -- cgit v1.2.1