From 14b4838d49556eb544c0f6a96d72128c3480ec2c Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 1 Nov 2024 15:59:30 +0000 Subject: coreboot/default: Re-base all patches There were a lot of unnecessary patches, such as the VRAM patches; as Nicholas Chin has explained to me, the drivers for these machines will just allocate what RAM they want anyway, so in a lot of cases the extra allocated Video RAM simply reduces the total amount of memory for other uses. In general, we have a lot of patches that have existed for years. A much more aggressive sweep will be done in the next major audit, especially when the revisions are updated again. Signed-off-by: Leah Rowe --- ...00-Enable-01.0-device-in-devicetree-for-d.patch | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch (limited to 'config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch') diff --git a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch new file mode 100644 index 00000000..71f2f22d --- /dev/null +++ b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -0,0 +1,28 @@ +From a5bc59037dabd95b6595c5aaf38b83da2a91de54 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Sat, 6 May 2023 15:53:41 -0600 +Subject: [PATCH 06/51] mb/dell/e6400: Enable 01.0 device in devicetree for + dGPU models + +Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/e6400/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb +index bb954cbd7b..e9f3915d17 100644 +--- a/src/mainboard/dell/e6400/devicetree.cb ++++ b/src/mainboard/dell/e6400/devicetree.cb +@@ -19,7 +19,7 @@ chip northbridge/intel/gm45 + ops gm45_pci_domain_ops + + device pci 00.0 on end # host bridge +- device pci 01.0 off end ++ device pci 01.0 on end + device pci 02.0 on end # VGA + device pci 02.1 on end # Display + device pci 03.0 on end # ME +-- +2.39.5 + -- cgit v1.2.1