From f60350344a56fa2b9db2b0653f69a7b036da8aab Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 23 Apr 2026 23:14:25 +0100 Subject: consolidate haswell iommu patches Signed-off-by: Leah Rowe --- ...01-add-c3-and-clockgen-to-apple-macbook21.patch | 2 +- ...-mb-lenovo-t430-Merge-into-t430-into-t530.patch | 2 +- .../0003-lenovo-t400-Enable-all-SATA-ports.patch | 2 +- ...230-set-me_state-Disabled-in-cmos.default.patch | 2 +- ..._state-Disabled-on-all-cmos.default-files.patch | 2 +- ...-ifdtool-add-nuke-flag-all-0xFF-on-region.patch | 2 +- ...00-Enable-01.0-device-in-devicetree-for-d.patch | 2 +- ...ing-for-coreboot-images-built-without-a-p.patch | 2 +- ...CK-Disable-coreboot-related-BL31-features.patch | 2 +- ...-dell-e6430-use-ME-Soft-Temporary-Disable.patch | 2 +- ...0011-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch | 2 +- ...intel-haswell-make-IOMMU-a-runtime-option.patch | 56 +- ...ll-optiplex_9020-Disable-IOMMU-by-default.patch | 2 +- ...well-Fully-disable-iGPU-when-dGPU-is-used.patch | 2 +- ...c-dell-mec5035-Add-S3-suspend-SMI-handler.patch | 2 +- ...ell-lock-policy-regs-when-disabling-IOMMU.patch | 54 - ...0016-nb-intel-gm45-Make-DDR2-raminit-work.patch | 223 +++ ...Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch | 240 +++ ...0017-nb-intel-gm45-Make-DDR2-raminit-work.patch | 223 --- ...00-Use-100-MHz-reference-clock-for-displa.patch | 51 + ...Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch | 240 --- ...00-Use-100-MHz-reference-clock-for-displa.patch | 51 - ...019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch | 52 + ...-mb-dell-gm45_latitudes-Add-E4300-variant.patch | 332 +++++ ...020-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch | 52 - ...ell-Add-S3-SMI-handler-for-Dell-Latitudes.patch | 70 + ...-mb-dell-gm45_latitudes-Add-E4300-variant.patch | 332 ----- ...-Disable-compression-on-refcode-insertion.patch | 31 + ...ell-Add-S3-SMI-handler-for-Dell-Latitudes.patch | 70 - ...-Disable-compression-on-refcode-insertion.patch | 31 - ...ntel-Disable-stack-overflow-debug-options.patch | 187 +++ ...024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch | 708 +++++++++ ...ntel-Disable-stack-overflow-debug-options.patch | 187 --- ...025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch | 708 --------- ...025-mb-dell-optiplex_780-Add-USFF-variant.patch | 326 +++++ ...026-mb-dell-optiplex_780-Add-USFF-variant.patch | 326 ----- ...rc-intel-x4x-Disable-stack-overflow-debug.patch | 33 + ...p-8300cmt-remove-xhci_overcurrent_mapping.patch | 42 + ...rc-intel-x4x-Disable-stack-overflow-debug.patch | 33 - .../0028-dell-3050micro-disable-nvme-hotplug.patch | 47 + ...p-8300cmt-remove-xhci_overcurrent_mapping.patch | 42 - .../0029-dell-3050micro-disable-nvme-hotplug.patch | 47 - ...kylake-Disable-stack-overflow-debug-optio.patch | 61 + ...30-soc-intel-skylake-Don-t-compress-FSP-S.patch | 36 + ...kylake-Disable-stack-overflow-debug-optio.patch | 61 - ...Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch | 78 + ...31-soc-intel-skylake-Don-t-compress-FSP-S.patch | 36 - ...ional-TBFW-setting-for-kabylake-thinkpads.patch | 37 + ...Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch | 78 - ...ional-TBFW-setting-for-kabylake-thinkpads.patch | 37 - ...lderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch | 30 + ...PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch | 76 + ...lderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch | 30 - ...PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch | 76 - ...-soc-intel-alderlake-Don-t-compress-FSP-S.patch | 35 + ...e-don-t-require-full-fsp-repo-for-fd-path.patch | 33 + ...-soc-intel-alderlake-Don-t-compress-FSP-S.patch | 35 - ...e-don-t-require-full-fsp-repo-for-fd-path.patch | 33 - ...rlake-disable-stack-overflow-debug-option.patch | 46 + ...5035-Add-command-to-disable-EC-initiated-.patch | 92 ++ ...rlake-disable-stack-overflow-debug-option.patch | 46 - ...5035-Add-command-to-disable-EC-initiated-.patch | 92 -- ..._ivb_latitude-Disable-EC-initiated-shutdo.patch | 36 + .../default/patches/0040-fix-ifdtool-build.patch | 28 + ..._ivb_latitude-Disable-EC-initiated-shutdo.patch | 36 - .../default/patches/0041-fix-ifdtool-build.patch | 28 - ...akefile.mk-use-3rdparty-cmocka-by-default.patch | 30 + ...ll-optiplex_780-use-legacy-HDA-verb-table.patch | 51 + ...akefile.mk-use-3rdparty-cmocka-by-default.patch | 30 - .../0043-hp8300cmt-use-legacy-verb-table.patch | 30 + ...ll-optiplex_780-use-legacy-HDA-verb-table.patch | 51 - .../0044-hp8300cmt-use-legacy-verb-table.patch | 30 - .../patches/0044-topton-x2e-n150-use-old-fsp.patch | 34 + ...ro-x11-lga1151-series-Disable-ME-HECI-in-.patch | 31 + .../patches/0045-topton-x2e-n150-use-old-fsp.patch | 34 - ...ro-x11-lga1151-series-Disable-ME-HECI-in-.patch | 31 - ...l-ifdtool-option-to-allow-region-override.patch | 68 + ...0047-me_cleaner-don-t-modify-if-k-is-used.patch | 44 + ...l-ifdtool-option-to-allow-region-override.patch | 68 - ...klkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch | 600 ++++++++ ...0048-me_cleaner-don-t-modify-if-k-is-used.patch | 44 - ...klkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch | 600 -------- ...ovo-x270-Provide-correct-vbt-and-hda_verb.patch | 129 ++ ...-OptiPlex-3040-Micro-port-upstream-compat.patch | 1530 ++++++++++++++++++++ ...ovo-x270-Provide-correct-vbt-and-hda_verb.patch | 129 -- ...sable-Werror-in-the-coreboot-build-system.patch | 411 ++++++ ...-OptiPlex-3040-Micro-port-upstream-compat.patch | 1530 -------------------- ...sable-Werror-in-the-coreboot-build-system.patch | 411 ------ 88 files changed, 5936 insertions(+), 5978 deletions(-) delete mode 100644 config/coreboot/default/patches/0016-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch create mode 100644 config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch create mode 100644 config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch delete mode 100644 config/coreboot/default/patches/0017-nb-intel-gm45-Make-DDR2-raminit-work.patch create mode 100644 config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch delete mode 100644 config/coreboot/default/patches/0018-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch delete mode 100644 config/coreboot/default/patches/0019-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch create mode 100644 config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch create mode 100644 config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch delete mode 100644 config/coreboot/default/patches/0020-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch create mode 100644 config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch delete mode 100644 config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch create mode 100644 config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch delete mode 100644 config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch delete mode 100644 config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch create mode 100644 config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch create mode 100644 config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch delete mode 100644 config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch delete mode 100644 config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch create mode 100644 config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch delete mode 100644 config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch create mode 100644 config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch create mode 100644 config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch delete mode 100644 config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch create mode 100644 config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch delete mode 100644 config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch delete mode 100644 config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch create mode 100644 config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch create mode 100644 config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch delete mode 100644 config/coreboot/default/patches/0030-src-intel-skylake-Disable-stack-overflow-debug-optio.patch create mode 100644 config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch delete mode 100644 config/coreboot/default/patches/0031-soc-intel-skylake-Don-t-compress-FSP-S.patch create mode 100644 config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch delete mode 100644 config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch delete mode 100644 config/coreboot/default/patches/0033-Conditional-TBFW-setting-for-kabylake-thinkpads.patch create mode 100644 config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch create mode 100644 config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch delete mode 100644 config/coreboot/default/patches/0034-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch delete mode 100644 config/coreboot/default/patches/0035-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch create mode 100644 config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch create mode 100644 config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch delete mode 100644 config/coreboot/default/patches/0036-soc-intel-alderlake-Don-t-compress-FSP-S.patch delete mode 100644 config/coreboot/default/patches/0037-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch create mode 100644 config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch create mode 100644 config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch delete mode 100644 config/coreboot/default/patches/0038-soc-alderlake-disable-stack-overflow-debug-option.patch delete mode 100644 config/coreboot/default/patches/0039-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch create mode 100644 config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch create mode 100644 config/coreboot/default/patches/0040-fix-ifdtool-build.patch delete mode 100644 config/coreboot/default/patches/0040-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch delete mode 100644 config/coreboot/default/patches/0041-fix-ifdtool-build.patch create mode 100644 config/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch create mode 100644 config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch delete mode 100644 config/coreboot/default/patches/0042-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch create mode 100644 config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch delete mode 100644 config/coreboot/default/patches/0043-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch delete mode 100644 config/coreboot/default/patches/0044-hp8300cmt-use-legacy-verb-table.patch create mode 100644 config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch create mode 100644 config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch delete mode 100644 config/coreboot/default/patches/0045-topton-x2e-n150-use-old-fsp.patch delete mode 100644 config/coreboot/default/patches/0046-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch create mode 100644 config/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch create mode 100644 config/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch delete mode 100644 config/coreboot/default/patches/0047-util-ifdtool-option-to-allow-region-override.patch create mode 100644 config/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch delete mode 100644 config/coreboot/default/patches/0048-me_cleaner-don-t-modify-if-k-is-used.patch delete mode 100644 config/coreboot/default/patches/0049-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch create mode 100644 config/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch create mode 100644 config/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch delete mode 100644 config/coreboot/default/patches/0050-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch create mode 100644 config/coreboot/default/patches/0051-disable-Werror-in-the-coreboot-build-system.patch delete mode 100644 config/coreboot/default/patches/0051-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch delete mode 100644 config/coreboot/default/patches/0052-disable-Werror-in-the-coreboot-build-system.patch diff --git a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch index 5fc4b8b5..aca14691 100644 --- a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch +++ b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch @@ -1,4 +1,4 @@ -From 11f759cb05a4d9f4656982a8afea40d7dadfb93e Mon Sep 17 00:00:00 2001 +From b6cbef6dc28cfe5c376310391a7bc0869ea5ffdb Mon Sep 17 00:00:00 2001 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> Date: Wed, 27 Oct 2021 13:36:01 +0200 Subject: [PATCH 01/51] add c3 and clockgen to apple/macbook21 diff --git a/config/coreboot/default/patches/0002-Revert-mb-lenovo-t430-Merge-into-t430-into-t530.patch b/config/coreboot/default/patches/0002-Revert-mb-lenovo-t430-Merge-into-t430-into-t530.patch index d905e5cf..d6304f7c 100644 --- a/config/coreboot/default/patches/0002-Revert-mb-lenovo-t430-Merge-into-t430-into-t530.patch +++ b/config/coreboot/default/patches/0002-Revert-mb-lenovo-t430-Merge-into-t430-into-t530.patch @@ -1,4 +1,4 @@ -From 3c5b15f0aa0ba2c9e7d4db6f893e13978c045032 Mon Sep 17 00:00:00 2001 +From 09cde063eed6777948ee3a2ad7ba5db71531f37e Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 23 Apr 2026 20:00:33 +0100 Subject: [PATCH 02/51] Revert "mb/lenovo/t430: Merge into t430 into t530" diff --git a/config/coreboot/default/patches/0003-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0003-lenovo-t400-Enable-all-SATA-ports.patch index bad82d0f..38607262 100644 --- a/config/coreboot/default/patches/0003-lenovo-t400-Enable-all-SATA-ports.patch +++ b/config/coreboot/default/patches/0003-lenovo-t400-Enable-all-SATA-ports.patch @@ -1,4 +1,4 @@ -From 33b89af06765839c0f9a6e599789c520e794a22a Mon Sep 17 00:00:00 2001 +From c1fd80b55e3ab8f651c2ad6e6eec6cdcb3922f9b Mon Sep 17 00:00:00 2001 From: persmule Date: Sun, 31 Oct 2021 23:33:26 +0000 Subject: [PATCH 03/51] lenovo/t400: Enable all SATA ports diff --git a/config/coreboot/default/patches/0004-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0004-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch index 2d4b145c..f77ca8e2 100644 --- a/config/coreboot/default/patches/0004-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch +++ b/config/coreboot/default/patches/0004-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -1,4 +1,4 @@ -From 6bf8a87bdea4b7d5876e20f734821e6496b51cb9 Mon Sep 17 00:00:00 2001 +From bf1bb17d48b43ca468bca0b2d31315450f8cf8c6 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 3 Jan 2022 19:06:22 +0000 Subject: [PATCH 04/51] lenovo/x230: set me_state=Disabled in cmos.default diff --git a/config/coreboot/default/patches/0005-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0005-set-me_state-Disabled-on-all-cmos.default-files.patch index 5ada54ef..3c4e617a 100644 --- a/config/coreboot/default/patches/0005-set-me_state-Disabled-on-all-cmos.default-files.patch +++ b/config/coreboot/default/patches/0005-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -1,4 +1,4 @@ -From 05f20d18bf572ebe80875d506dd686efd3eb7e4e Mon Sep 17 00:00:00 2001 +From c0b5b390507c1a46af3224bd61f5c971e99607a2 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 2 Mar 2022 21:50:01 +0000 Subject: [PATCH 05/51] set me_state=Disabled on all cmos.default files! diff --git a/config/coreboot/default/patches/0006-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0006-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch index 7b5c1a3d..843e3ba1 100644 --- a/config/coreboot/default/patches/0006-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ b/config/coreboot/default/patches/0006-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -1,4 +1,4 @@ -From 68e1738c5a46181b1fd1fcd44fe314da297b95d0 Mon Sep 17 00:00:00 2001 +From 75892a195d53054ceee67e23c487c4103f559332 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 19 Feb 2023 18:21:43 +0000 Subject: [PATCH 06/51] util/ifdtool: add --nuke flag (all 0xFF on region) diff --git a/config/coreboot/default/patches/0007-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0007-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch index bdab3fa6..7435ddf4 100644 --- a/config/coreboot/default/patches/0007-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ b/config/coreboot/default/patches/0007-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -1,4 +1,4 @@ -From 6c626f71a4ec9f887d1b82da071011423a3fd24e Mon Sep 17 00:00:00 2001 +From e4682c184ded28dc9daf7ae6cae9d121f3803bef Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Sat, 6 May 2023 15:53:41 -0600 Subject: [PATCH 07/51] mb/dell/e6400: Enable 01.0 device in devicetree for diff --git a/config/coreboot/default/patches/0008-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0008-Remove-warning-for-coreboot-images-built-without-a-p.patch index 03401a8b..2fc85527 100644 --- a/config/coreboot/default/patches/0008-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/default/patches/0008-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,4 +1,4 @@ -From bd349e86429cd0e83bbd6251ec507f3273b80854 Mon Sep 17 00:00:00 2001 +From 83a4706b4948797ff57f314c9518f256aea08e79 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Fri, 12 May 2023 19:55:15 -0600 Subject: [PATCH 08/51] Remove warning for coreboot images built without a diff --git a/config/coreboot/default/patches/0009-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0009-HACK-Disable-coreboot-related-BL31-features.patch index 158ff60b..04373130 100644 --- a/config/coreboot/default/patches/0009-HACK-Disable-coreboot-related-BL31-features.patch +++ b/config/coreboot/default/patches/0009-HACK-Disable-coreboot-related-BL31-features.patch @@ -1,4 +1,4 @@ -From bd98f54b50b66d291641f88ec3169b9518855862 Mon Sep 17 00:00:00 2001 +From 9dbbefa5297329f316adeb95c2a78267be146509 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Thu, 22 Jun 2023 16:44:27 +0300 Subject: [PATCH 09/51] HACK: Disable coreboot related BL31 features diff --git a/config/coreboot/default/patches/0010-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0010-dell-e6430-use-ME-Soft-Temporary-Disable.patch index 3451cc67..5ffd10c2 100644 --- a/config/coreboot/default/patches/0010-dell-e6430-use-ME-Soft-Temporary-Disable.patch +++ b/config/coreboot/default/patches/0010-dell-e6430-use-ME-Soft-Temporary-Disable.patch @@ -1,4 +1,4 @@ -From ae01730cad059bb3707b6d938a082dee9494bde5 Mon Sep 17 00:00:00 2001 +From 6b112300df5d4538cf19e3f914f0a44628733204 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 5 Nov 2023 11:41:41 +0000 Subject: [PATCH 10/51] dell/e6430: use ME Soft Temporary Disable diff --git a/config/coreboot/default/patches/0011-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0011-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch index c3fee8c7..8a83950f 100644 --- a/config/coreboot/default/patches/0011-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch +++ b/config/coreboot/default/patches/0011-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch @@ -1,4 +1,4 @@ -From ae7d23355be8efbbe3a1216d8e28c30a07e2e0ef Mon Sep 17 00:00:00 2001 +From 42e64e41ec9ce997f6615b7a67655715a67651b4 Mon Sep 17 00:00:00 2001 From: Riku Viitanen Date: Sat, 23 Dec 2023 19:02:10 +0200 Subject: [PATCH 11/51] mb/hp: Add Compaq Elite 8300 CMT port diff --git a/config/coreboot/default/patches/0012-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0012-nb-intel-haswell-make-IOMMU-a-runtime-option.patch index 883590fc..8bd1c972 100644 --- a/config/coreboot/default/patches/0012-nb-intel-haswell-make-IOMMU-a-runtime-option.patch +++ b/config/coreboot/default/patches/0012-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -1,4 +1,4 @@ -From 0d418d44f61dda7670cfe02226150c2e5d3d6308 Mon Sep 17 00:00:00 2001 +From 601661d628ff7b8ffee8c1ed13307caa23d489ce Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 2 Mar 2024 22:51:09 +0000 Subject: [PATCH 12/51] nb/intel/haswell: make IOMMU a runtime option @@ -19,23 +19,23 @@ performed, and the IOMMU will be left disabled. This option has been added to all current Haswell boards, though it is recommended to leave the IOMMU turned on in most setups. -Signed-off-by: Leah Rowe +Signed-off-by: Leah Rowe --- - src/mainboard/asrock/b85m_pro4/cmos.default | 1 + - src/mainboard/asrock/b85m_pro4/cmos.layout | 3 +++ - src/mainboard/asrock/h81m-hds/cmos.default | 1 + - src/mainboard/asrock/h81m-hds/cmos.layout | 6 ++++++ - src/mainboard/dell/optiplex_9020/cmos.default | 1 + - src/mainboard/dell/optiplex_9020/cmos.layout | 6 ++++++ - src/mainboard/google/beltino/cmos.layout | 5 +++++ - src/mainboard/google/slippy/cmos.layout | 5 +++++ - src/mainboard/intel/baskingridge/cmos.layout | 4 ++++ - src/mainboard/lenovo/haswell/cmos.default | 1 + - src/mainboard/lenovo/haswell/cmos.layout | 3 +++ - src/mainboard/supermicro/x10slm-f/cmos.default | 1 + - src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++ - src/northbridge/intel/haswell/early_init.c | 6 ++++++ - 14 files changed, 49 insertions(+) + src/mainboard/asrock/b85m_pro4/cmos.default | 1 + + src/mainboard/asrock/b85m_pro4/cmos.layout | 3 +++ + src/mainboard/asrock/h81m-hds/cmos.default | 1 + + src/mainboard/asrock/h81m-hds/cmos.layout | 6 ++++++ + src/mainboard/dell/optiplex_9020/cmos.default | 1 + + src/mainboard/dell/optiplex_9020/cmos.layout | 6 ++++++ + src/mainboard/google/beltino/cmos.layout | 5 +++++ + src/mainboard/google/slippy/cmos.layout | 5 +++++ + src/mainboard/intel/baskingridge/cmos.layout | 4 ++++ + src/mainboard/lenovo/haswell/cmos.default | 1 + + src/mainboard/lenovo/haswell/cmos.layout | 3 +++ + src/mainboard/supermicro/x10slm-f/cmos.default | 1 + + src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++ + src/northbridge/intel/haswell/early_init.c | 15 ++++++++++----- + 14 files changed, 53 insertions(+), 5 deletions(-) diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default index 01bf20ad16..dfc8b80fb0 100644 @@ -265,7 +265,7 @@ index 38ba87aa45..24d39e97ee 100644 checksums diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c -index 6a5ce53a40..5f07fa0b17 100644 +index 6a5ce53a40..e0007f72ee 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -6,6 +6,7 @@ @@ -276,18 +276,30 @@ index 6a5ce53a40..5f07fa0b17 100644 #include "haswell.h" -@@ -80,6 +81,11 @@ static void haswell_setup_misc(void) +@@ -80,14 +81,18 @@ static void haswell_setup_misc(void) static void northbridge_setup_iommu(void) { const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); + u8 enable_iommu = get_uint_option("iommu", 1); -+ -+ if (!enable_iommu) -+ return; + if (capid0_a & VTD_DISABLE) return; +- /* Setup BARs: zeroize top 32 bits; set enable bit */ +- mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); +- mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); +- mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); +- mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); ++ if (enable_iommu) { ++ /* Setup BARs: zeroize top 32 bits; set enable bit */ ++ mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); ++ mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); ++ mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); ++ mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); ++ } + + if (cpu_is_haswell()) { + /* -- 2.47.3 diff --git a/config/coreboot/default/patches/0013-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0013-dell-optiplex_9020-Disable-IOMMU-by-default.patch index a5eb5de2..e5108928 100644 --- a/config/coreboot/default/patches/0013-dell-optiplex_9020-Disable-IOMMU-by-default.patch +++ b/config/coreboot/default/patches/0013-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -1,4 +1,4 @@ -From 2bd978a08ffee969bbf61af8f145b9e6b050d321 Mon Sep 17 00:00:00 2001 +From 1586b045a75b9cf8cd68a44739beefa501e6cbd3 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 2 Mar 2024 23:00:09 +0000 Subject: [PATCH 13/51] dell/optiplex_9020: Disable IOMMU by default diff --git a/config/coreboot/default/patches/0014-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0014-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch index aa5483c8..6c780252 100644 --- a/config/coreboot/default/patches/0014-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch +++ b/config/coreboot/default/patches/0014-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -1,4 +1,4 @@ -From 1179f45055fffb383fffe806e313a315de7c4205 Mon Sep 17 00:00:00 2001 +From 64e0140fec07d7062b147419781e200509c63053 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 6 Apr 2024 01:22:47 +0100 Subject: [PATCH 14/51] nb/haswell: Fully disable iGPU when dGPU is used diff --git a/config/coreboot/default/patches/0015-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0015-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch index 7cadcb56..0ab978f6 100644 --- a/config/coreboot/default/patches/0015-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch +++ b/config/coreboot/default/patches/0015-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch @@ -1,4 +1,4 @@ -From 59b741bf1b74a2c4e108755fbfd1580894c7d783 Mon Sep 17 00:00:00 2001 +From f19a3eb6eee94881ac1c6c6fe28c1f523a12dcda Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Fri, 3 May 2024 11:03:32 -0600 Subject: [PATCH 15/51] ec/dell/mec5035: Add S3 suspend SMI handler diff --git a/config/coreboot/default/patches/0016-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0016-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch deleted file mode 100644 index 17cfdac2..00000000 --- a/config/coreboot/default/patches/0016-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 3c1416797f2deafbd6b56774d890706aaea3614f Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 4 May 2024 02:00:53 +0100 -Subject: [PATCH 16/51] nb/haswell: lock policy regs when disabling IOMMU - -Angel Pons told me I should do it. See comments here: -https://review.coreboot.org/c/coreboot/+/81016 - -I see no harm in complying with the request. I'll merge -this into the main patch at a later date and try to -get this upstreamed. - -Just a reminder: on Optiplex 9020 variants, Xorg locks up -under Linux when tested with a graphics card; disabling -IOMMU works around the issue. Intel graphics work just fine -with IOMMU turned on. Libreboot disables IOMMU by default, -on the 9020, so that users can install graphics cards easily. - -Signed-off-by: Leah Rowe ---- - src/northbridge/intel/haswell/early_init.c | 14 ++++++++------ - 1 file changed, 8 insertions(+), 6 deletions(-) - -diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c -index 5f07fa0b17..30660e3903 100644 ---- a/src/northbridge/intel/haswell/early_init.c -+++ b/src/northbridge/intel/haswell/early_init.c -@@ -86,15 +86,17 @@ static void northbridge_setup_iommu(void) - if (!enable_iommu) - return; - -+ if (enable_iommu) { -+ /* Setup BARs: zeroize top 32 bits; set enable bit */ -+ mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); -+ mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); -+ mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); -+ mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); -+ } -+ - if (capid0_a & VTD_DISABLE) - return; - -- /* Setup BARs: zeroize top 32 bits; set enable bit */ -- mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); -- mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); -- mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); -- mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); -- - if (cpu_is_haswell()) { - /* - * Intel Document 492662 (Haswell System Agent BIOS Spec), Rev 1.6.0 --- -2.47.3 - diff --git a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch new file mode 100644 index 00000000..3e922093 --- /dev/null +++ b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch @@ -0,0 +1,223 @@ +From c99ef7e409f450dbc66d2de930160f29a0c0d68e Mon Sep 17 00:00:00 2001 +From: Angel Pons +Date: Mon, 10 May 2021 22:40:59 +0200 +Subject: [PATCH 16/51] nb/intel/gm45: Make DDR2 raminit work + +List of changes: + - Update some timing and ODT values + - Patch RCOMP calibration to better match what MRC binaries do + - Replay a hardcoded list of RCOMP codes after RcvEn + +This makes raminit work at DDR2-800 speeds and fixes S3 resume as well. +Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs. + +Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c +Signed-off-by: Angel Pons +--- + src/northbridge/intel/gm45/gm45.h | 2 +- + src/northbridge/intel/gm45/raminit.c | 90 +++++++++++++++++-- + .../intel/gm45/raminit_rcomp_calibration.c | 27 ++++-- + 3 files changed, 106 insertions(+), 13 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h +index 90ab570524..d537ef82af 100644 +--- a/src/northbridge/intel/gm45/gm45.h ++++ b/src/northbridge/intel/gm45/gm45.h +@@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo); + int raminit_read_vco_index(void); + u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank); + +-void raminit_rcomp_calibration(stepping_t stepping); ++void raminit_rcomp_calibration(int ddr_type, stepping_t stepping); + void raminit_reset_readwrite_pointers(void); + void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *); + void raminit_write_training(const mem_clock_t, const dimminfo_t *, bool s3resume); +diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c +index def9e1e331..7b091cc567 100644 +--- a/src/northbridge/intel/gm45/raminit.c ++++ b/src/northbridge/intel/gm45/raminit.c +@@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping, + } + + /* Perform RCOMP calibration for DDR3. */ +- raminit_rcomp_calibration(stepping); ++ raminit_rcomp_calibration(spd_type, stepping); + + /* Run initial RCOMP. */ + mchbar_setbits32(0x418, 1 << 17); +@@ -1117,7 +1117,7 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi + reg = (reg & ~(0xf << 10)) | (2 << 10); + else + reg = (reg & ~(0xf << 10)) | (3 << 10); +- reg = (reg & ~(0x7 << 5)) | (3 << 5); ++ reg = (reg & ~(0x7 << 5)) | (2 << 5); + } else if (timings->mem_clock != MEM_CLOCK_1067MT) { + reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); + reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); +@@ -1286,11 +1286,11 @@ static void ddr2_odt_setup(const timings_t *const timings, const int sff) + reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32)); + reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32)); + if (timings->mem_clock == MEM_CLOCK_667MT) { +- reg = (reg & ~(0xf << (36 - 32))) | (4 << (36 - 32)); +- reg = (reg & ~(0xf << (32 - 32))) | (4 << (32 - 32)); ++ reg = (reg & ~(0xf << (36 - 32))) | (8 << (36 - 32)); ++ reg = (reg & ~(0xf << (32 - 32))) | (8 << (32 - 32)); + } else { +- reg = (reg & ~(0xf << (36 - 32))) | (5 << (36 - 32)); +- reg = (reg & ~(0xf << (32 - 32))) | (5 << (32 - 32)); ++ reg = (reg & ~(0xf << (36 - 32))) | (9 << (36 - 32)); ++ reg = (reg & ~(0xf << (32 - 32))) | (9 << (32 - 32)); + } + mchbar_write32(CxODT_HIGH(ch), reg); + +@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume) + raminit_write_training(timings->mem_clock, dimms, s3resume); + } + ++ /* ++ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done ++ * after receiver enable calibration, otherwise raminit sometimes ++ * completes with non-working memory. ++ */ ++ mchbar_write32(0x0530, 0x06060005); ++ mchbar_write32(0x0680, 0x06060606); ++ mchbar_write32(0x0684, 0x08070606); ++ mchbar_write32(0x0688, 0x0e0e0c0a); ++ mchbar_write32(0x068c, 0x0e0e0e0e); ++ mchbar_write32(0x0698, 0x06060606); ++ mchbar_write32(0x069c, 0x08070606); ++ mchbar_write32(0x06a0, 0x0c0c0b0a); ++ mchbar_write32(0x06a4, 0x0c0c0c0c); ++ ++ mchbar_write32(0x06c0, 0x02020202); ++ mchbar_write32(0x06c4, 0x03020202); ++ mchbar_write32(0x06c8, 0x04040403); ++ mchbar_write32(0x06cc, 0x04040404); ++ mchbar_write32(0x06d8, 0x02020202); ++ mchbar_write32(0x06dc, 0x03020202); ++ mchbar_write32(0x06e0, 0x04040403); ++ mchbar_write32(0x06e4, 0x04040404); ++ ++ mchbar_write32(0x0700, 0x02020202); ++ mchbar_write32(0x0704, 0x03020202); ++ mchbar_write32(0x0708, 0x04040403); ++ mchbar_write32(0x070c, 0x04040404); ++ mchbar_write32(0x0718, 0x02020202); ++ mchbar_write32(0x071c, 0x03020202); ++ mchbar_write32(0x0720, 0x04040403); ++ mchbar_write32(0x0724, 0x04040404); ++ ++ mchbar_write32(0x0740, 0x02020202); ++ mchbar_write32(0x0744, 0x03020202); ++ mchbar_write32(0x0748, 0x04040403); ++ mchbar_write32(0x074c, 0x04040404); ++ mchbar_write32(0x0758, 0x02020202); ++ mchbar_write32(0x075c, 0x03020202); ++ mchbar_write32(0x0760, 0x04040403); ++ mchbar_write32(0x0764, 0x04040404); ++ ++ mchbar_write32(0x0780, 0x06060606); ++ mchbar_write32(0x0784, 0x09070606); ++ mchbar_write32(0x0788, 0x0e0e0c0b); ++ mchbar_write32(0x078c, 0x0e0e0e0e); ++ mchbar_write32(0x0798, 0x06060606); ++ mchbar_write32(0x079c, 0x09070606); ++ mchbar_write32(0x07a0, 0x0d0d0c0b); ++ mchbar_write32(0x07a4, 0x0d0d0d0d); ++ ++ mchbar_write32(0x07c0, 0x06060606); ++ mchbar_write32(0x07c4, 0x09070606); ++ mchbar_write32(0x07c8, 0x0e0e0c0b); ++ mchbar_write32(0x07cc, 0x0e0e0e0e); ++ mchbar_write32(0x07d8, 0x06060606); ++ mchbar_write32(0x07dc, 0x09070606); ++ mchbar_write32(0x07e0, 0x0d0d0c0b); ++ mchbar_write32(0x07e4, 0x0d0d0d0d); ++ ++ mchbar_write32(0x0840, 0x06060606); ++ mchbar_write32(0x0844, 0x08070606); ++ mchbar_write32(0x0848, 0x0e0e0c0a); ++ mchbar_write32(0x084c, 0x0e0e0e0e); ++ mchbar_write32(0x0858, 0x06060606); ++ mchbar_write32(0x085c, 0x08070606); ++ mchbar_write32(0x0860, 0x0c0c0b0a); ++ mchbar_write32(0x0864, 0x0c0c0c0c); ++ ++ mchbar_write32(0x0880, 0x02020202); ++ mchbar_write32(0x0884, 0x03020202); ++ mchbar_write32(0x0888, 0x04040403); ++ mchbar_write32(0x088c, 0x04040404); ++ mchbar_write32(0x0898, 0x02020202); ++ mchbar_write32(0x089c, 0x03020202); ++ mchbar_write32(0x08a0, 0x04040403); ++ mchbar_write32(0x08a4, 0x04040404); ++ + igd_compute_ggc(sysinfo); + + /* Program final memory map (with real values). */ +diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +index aef863f05a..b74765fd9c 100644 +--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c ++++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +@@ -161,11 +161,13 @@ static void lookup_and_write(const int a1step, + mchbar += 4; + } + } +-void raminit_rcomp_calibration(const stepping_t stepping) { ++void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { + const int a1step = stepping >= STEPPING_CONVERSION_A1; + + int i; + ++ char magic_comp[2] = {0}; ++ + enum { + PULL_UP = 0, + PULL_DOWN = 1, +@@ -196,6 +198,10 @@ void raminit_rcomp_calibration(const stepping_t stepping) { + reg = mchbar_read32(0x518); + lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f; + lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f; ++ if (i == 1) { ++ magic_comp[0] = (reg >> 8) & 0x3f; ++ magic_comp[1] = (reg >> 0) & 0x3f; ++ } + } + /* Cleanup? */ + mchbar_setbits32(0x400, 1 << 3); +@@ -216,13 +222,19 @@ void raminit_rcomp_calibration(const stepping_t stepping) { + for (channel = 0; channel < 2; ++channel) { + for (group = 0; group < 6; ++group) { + for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) { +- lookup_and_write( +- a1step, +- lut_idx[channel][group][pu_pd] - 7, +- ddr3_lookup_schedule[group][pu_pd], +- mchbar); ++ if (ddr_type == DDR3) { ++ lookup_and_write( ++ a1step, ++ lut_idx[channel][group][pu_pd] - 7, ++ ddr3_lookup_schedule[group][pu_pd], ++ mchbar); ++ } + mchbar += 0x0018; + } ++ if (ddr_type == DDR2) { ++ mchbar_clrsetbits32(mchbar + 0, 0x7f << 24, lut_idx[channel][group][PULL_DOWN] << 24); ++ mchbar_clrsetbits32(mchbar + 4, 0x7f << 0, lut_idx[channel][group][PULL_UP] << 0); ++ } + mchbar += 0x0010; + /* Channel B knows only the first two groups. */ + if ((1 == channel) && (1 == group)) +@@ -230,4 +242,7 @@ void raminit_rcomp_calibration(const stepping_t stepping) { + } + mchbar += 0x0040; + } ++ ++ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); ++ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); + } +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch new file mode 100644 index 00000000..1fe4494d --- /dev/null +++ b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch @@ -0,0 +1,240 @@ +From fcfd8484d5b7a50c170a7f5cc8a973c890e48afc Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 6 Aug 2024 00:50:24 +0100 +Subject: [PATCH 17/51] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards + +We add this patch: + +commit commit_id_here +Author: Angel Pons +Date: Mon May 10 22:40:59 2021 +0200 + + nb/intel/gm45: Make DDR2 raminit work + +This patch was original applied, in lbmk, only on coreboot/dell, +separately from coreboot/default, which was wasteful because it +meant having an entire coreboot tree just for a single board. We +did this, because the DDR2 RCOMP fix happened to break DDR3 init +on other boards. + +What *this* new patch does on top of Angel's patch, is make sure +that their changes only apply to DDR2, while DDR3 behaviour remains +unchanged. This means that the Dell Latitude E6400 can be supported +in the main coreboot tree, within lbmk. + +Essentially, this patch restores the old behaviour, prior to applying +Angel's patch, only when DDR3 memory is used. + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/gm45/raminit.c | 161 +++++++++--------- + .../intel/gm45/raminit_rcomp_calibration.c | 9 +- + 2 files changed, 88 insertions(+), 82 deletions(-) + +diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c +index 7b091cc567..478898564a 100644 +--- a/src/northbridge/intel/gm45/raminit.c ++++ b/src/northbridge/intel/gm45/raminit.c +@@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi + reg = (reg & ~(0xf << 10)) | (2 << 10); + else + reg = (reg & ~(0xf << 10)) | (3 << 10); +- reg = (reg & ~(0x7 << 5)) | (2 << 5); ++ if (spd_type == DDR2) ++ reg = (reg & ~(0x7 << 5)) | (2 << 5); ++ else ++ reg = (reg & ~(0x7 << 5)) | (3 << 5); + } else if (timings->mem_clock != MEM_CLOCK_1067MT) { + reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); + reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); +@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume) + raminit_write_training(timings->mem_clock, dimms, s3resume); + } + +- /* +- * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done +- * after receiver enable calibration, otherwise raminit sometimes +- * completes with non-working memory. +- */ +- mchbar_write32(0x0530, 0x06060005); +- mchbar_write32(0x0680, 0x06060606); +- mchbar_write32(0x0684, 0x08070606); +- mchbar_write32(0x0688, 0x0e0e0c0a); +- mchbar_write32(0x068c, 0x0e0e0e0e); +- mchbar_write32(0x0698, 0x06060606); +- mchbar_write32(0x069c, 0x08070606); +- mchbar_write32(0x06a0, 0x0c0c0b0a); +- mchbar_write32(0x06a4, 0x0c0c0c0c); +- +- mchbar_write32(0x06c0, 0x02020202); +- mchbar_write32(0x06c4, 0x03020202); +- mchbar_write32(0x06c8, 0x04040403); +- mchbar_write32(0x06cc, 0x04040404); +- mchbar_write32(0x06d8, 0x02020202); +- mchbar_write32(0x06dc, 0x03020202); +- mchbar_write32(0x06e0, 0x04040403); +- mchbar_write32(0x06e4, 0x04040404); +- +- mchbar_write32(0x0700, 0x02020202); +- mchbar_write32(0x0704, 0x03020202); +- mchbar_write32(0x0708, 0x04040403); +- mchbar_write32(0x070c, 0x04040404); +- mchbar_write32(0x0718, 0x02020202); +- mchbar_write32(0x071c, 0x03020202); +- mchbar_write32(0x0720, 0x04040403); +- mchbar_write32(0x0724, 0x04040404); +- +- mchbar_write32(0x0740, 0x02020202); +- mchbar_write32(0x0744, 0x03020202); +- mchbar_write32(0x0748, 0x04040403); +- mchbar_write32(0x074c, 0x04040404); +- mchbar_write32(0x0758, 0x02020202); +- mchbar_write32(0x075c, 0x03020202); +- mchbar_write32(0x0760, 0x04040403); +- mchbar_write32(0x0764, 0x04040404); +- +- mchbar_write32(0x0780, 0x06060606); +- mchbar_write32(0x0784, 0x09070606); +- mchbar_write32(0x0788, 0x0e0e0c0b); +- mchbar_write32(0x078c, 0x0e0e0e0e); +- mchbar_write32(0x0798, 0x06060606); +- mchbar_write32(0x079c, 0x09070606); +- mchbar_write32(0x07a0, 0x0d0d0c0b); +- mchbar_write32(0x07a4, 0x0d0d0d0d); +- +- mchbar_write32(0x07c0, 0x06060606); +- mchbar_write32(0x07c4, 0x09070606); +- mchbar_write32(0x07c8, 0x0e0e0c0b); +- mchbar_write32(0x07cc, 0x0e0e0e0e); +- mchbar_write32(0x07d8, 0x06060606); +- mchbar_write32(0x07dc, 0x09070606); +- mchbar_write32(0x07e0, 0x0d0d0c0b); +- mchbar_write32(0x07e4, 0x0d0d0d0d); +- +- mchbar_write32(0x0840, 0x06060606); +- mchbar_write32(0x0844, 0x08070606); +- mchbar_write32(0x0848, 0x0e0e0c0a); +- mchbar_write32(0x084c, 0x0e0e0e0e); +- mchbar_write32(0x0858, 0x06060606); +- mchbar_write32(0x085c, 0x08070606); +- mchbar_write32(0x0860, 0x0c0c0b0a); +- mchbar_write32(0x0864, 0x0c0c0c0c); +- +- mchbar_write32(0x0880, 0x02020202); +- mchbar_write32(0x0884, 0x03020202); +- mchbar_write32(0x0888, 0x04040403); +- mchbar_write32(0x088c, 0x04040404); +- mchbar_write32(0x0898, 0x02020202); +- mchbar_write32(0x089c, 0x03020202); +- mchbar_write32(0x08a0, 0x04040403); +- mchbar_write32(0x08a4, 0x04040404); ++ if (sysinfo->spd_type == DDR2) { ++ /* ++ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done ++ * after receiver enable calibration, otherwise raminit sometimes ++ * completes with non-working memory. ++ */ ++ mchbar_write32(0x0530, 0x06060005); ++ mchbar_write32(0x0680, 0x06060606); ++ mchbar_write32(0x0684, 0x08070606); ++ mchbar_write32(0x0688, 0x0e0e0c0a); ++ mchbar_write32(0x068c, 0x0e0e0e0e); ++ mchbar_write32(0x0698, 0x06060606); ++ mchbar_write32(0x069c, 0x08070606); ++ mchbar_write32(0x06a0, 0x0c0c0b0a); ++ mchbar_write32(0x06a4, 0x0c0c0c0c); ++ ++ mchbar_write32(0x06c0, 0x02020202); ++ mchbar_write32(0x06c4, 0x03020202); ++ mchbar_write32(0x06c8, 0x04040403); ++ mchbar_write32(0x06cc, 0x04040404); ++ mchbar_write32(0x06d8, 0x02020202); ++ mchbar_write32(0x06dc, 0x03020202); ++ mchbar_write32(0x06e0, 0x04040403); ++ mchbar_write32(0x06e4, 0x04040404); ++ ++ mchbar_write32(0x0700, 0x02020202); ++ mchbar_write32(0x0704, 0x03020202); ++ mchbar_write32(0x0708, 0x04040403); ++ mchbar_write32(0x070c, 0x04040404); ++ mchbar_write32(0x0718, 0x02020202); ++ mchbar_write32(0x071c, 0x03020202); ++ mchbar_write32(0x0720, 0x04040403); ++ mchbar_write32(0x0724, 0x04040404); ++ ++ mchbar_write32(0x0740, 0x02020202); ++ mchbar_write32(0x0744, 0x03020202); ++ mchbar_write32(0x0748, 0x04040403); ++ mchbar_write32(0x074c, 0x04040404); ++ mchbar_write32(0x0758, 0x02020202); ++ mchbar_write32(0x075c, 0x03020202); ++ mchbar_write32(0x0760, 0x04040403); ++ mchbar_write32(0x0764, 0x04040404); ++ ++ mchbar_write32(0x0780, 0x06060606); ++ mchbar_write32(0x0784, 0x09070606); ++ mchbar_write32(0x0788, 0x0e0e0c0b); ++ mchbar_write32(0x078c, 0x0e0e0e0e); ++ mchbar_write32(0x0798, 0x06060606); ++ mchbar_write32(0x079c, 0x09070606); ++ mchbar_write32(0x07a0, 0x0d0d0c0b); ++ mchbar_write32(0x07a4, 0x0d0d0d0d); ++ ++ mchbar_write32(0x07c0, 0x06060606); ++ mchbar_write32(0x07c4, 0x09070606); ++ mchbar_write32(0x07c8, 0x0e0e0c0b); ++ mchbar_write32(0x07cc, 0x0e0e0e0e); ++ mchbar_write32(0x07d8, 0x06060606); ++ mchbar_write32(0x07dc, 0x09070606); ++ mchbar_write32(0x07e0, 0x0d0d0c0b); ++ mchbar_write32(0x07e4, 0x0d0d0d0d); ++ ++ mchbar_write32(0x0840, 0x06060606); ++ mchbar_write32(0x0844, 0x08070606); ++ mchbar_write32(0x0848, 0x0e0e0c0a); ++ mchbar_write32(0x084c, 0x0e0e0e0e); ++ mchbar_write32(0x0858, 0x06060606); ++ mchbar_write32(0x085c, 0x08070606); ++ mchbar_write32(0x0860, 0x0c0c0b0a); ++ mchbar_write32(0x0864, 0x0c0c0c0c); ++ ++ mchbar_write32(0x0880, 0x02020202); ++ mchbar_write32(0x0884, 0x03020202); ++ mchbar_write32(0x0888, 0x04040403); ++ mchbar_write32(0x088c, 0x04040404); ++ mchbar_write32(0x0898, 0x02020202); ++ mchbar_write32(0x089c, 0x03020202); ++ mchbar_write32(0x08a0, 0x04040403); ++ mchbar_write32(0x08a4, 0x04040404); ++ } + + igd_compute_ggc(sysinfo); + +diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +index b74765fd9c..5d4505e063 100644 +--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c ++++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +@@ -198,7 +198,7 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { + reg = mchbar_read32(0x518); + lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f; + lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f; +- if (i == 1) { ++ if ((i == 1) && (ddr_type == DDR2)) { + magic_comp[0] = (reg >> 8) & 0x3f; + magic_comp[1] = (reg >> 0) & 0x3f; + } +@@ -242,7 +242,8 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { + } + mchbar += 0x0040; + } +- +- mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); +- mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); ++ if (ddr_type == DDR2) { ++ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); ++ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); ++ } + } +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0017-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0017-nb-intel-gm45-Make-DDR2-raminit-work.patch deleted file mode 100644 index 6161d4f8..00000000 --- a/config/coreboot/default/patches/0017-nb-intel-gm45-Make-DDR2-raminit-work.patch +++ /dev/null @@ -1,223 +0,0 @@ -From 4347eae3a819dff7b6715630208d4be74b8245e4 Mon Sep 17 00:00:00 2001 -From: Angel Pons -Date: Mon, 10 May 2021 22:40:59 +0200 -Subject: [PATCH 17/51] nb/intel/gm45: Make DDR2 raminit work - -List of changes: - - Update some timing and ODT values - - Patch RCOMP calibration to better match what MRC binaries do - - Replay a hardcoded list of RCOMP codes after RcvEn - -This makes raminit work at DDR2-800 speeds and fixes S3 resume as well. -Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs. - -Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c -Signed-off-by: Angel Pons ---- - src/northbridge/intel/gm45/gm45.h | 2 +- - src/northbridge/intel/gm45/raminit.c | 90 +++++++++++++++++-- - .../intel/gm45/raminit_rcomp_calibration.c | 27 ++++-- - 3 files changed, 106 insertions(+), 13 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h -index 90ab570524..d537ef82af 100644 ---- a/src/northbridge/intel/gm45/gm45.h -+++ b/src/northbridge/intel/gm45/gm45.h -@@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo); - int raminit_read_vco_index(void); - u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank); - --void raminit_rcomp_calibration(stepping_t stepping); -+void raminit_rcomp_calibration(int ddr_type, stepping_t stepping); - void raminit_reset_readwrite_pointers(void); - void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *); - void raminit_write_training(const mem_clock_t, const dimminfo_t *, bool s3resume); -diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c -index def9e1e331..7b091cc567 100644 ---- a/src/northbridge/intel/gm45/raminit.c -+++ b/src/northbridge/intel/gm45/raminit.c -@@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping, - } - - /* Perform RCOMP calibration for DDR3. */ -- raminit_rcomp_calibration(stepping); -+ raminit_rcomp_calibration(spd_type, stepping); - - /* Run initial RCOMP. */ - mchbar_setbits32(0x418, 1 << 17); -@@ -1117,7 +1117,7 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi - reg = (reg & ~(0xf << 10)) | (2 << 10); - else - reg = (reg & ~(0xf << 10)) | (3 << 10); -- reg = (reg & ~(0x7 << 5)) | (3 << 5); -+ reg = (reg & ~(0x7 << 5)) | (2 << 5); - } else if (timings->mem_clock != MEM_CLOCK_1067MT) { - reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); - reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); -@@ -1286,11 +1286,11 @@ static void ddr2_odt_setup(const timings_t *const timings, const int sff) - reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32)); - reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32)); - if (timings->mem_clock == MEM_CLOCK_667MT) { -- reg = (reg & ~(0xf << (36 - 32))) | (4 << (36 - 32)); -- reg = (reg & ~(0xf << (32 - 32))) | (4 << (32 - 32)); -+ reg = (reg & ~(0xf << (36 - 32))) | (8 << (36 - 32)); -+ reg = (reg & ~(0xf << (32 - 32))) | (8 << (32 - 32)); - } else { -- reg = (reg & ~(0xf << (36 - 32))) | (5 << (36 - 32)); -- reg = (reg & ~(0xf << (32 - 32))) | (5 << (32 - 32)); -+ reg = (reg & ~(0xf << (36 - 32))) | (9 << (36 - 32)); -+ reg = (reg & ~(0xf << (32 - 32))) | (9 << (32 - 32)); - } - mchbar_write32(CxODT_HIGH(ch), reg); - -@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume) - raminit_write_training(timings->mem_clock, dimms, s3resume); - } - -+ /* -+ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done -+ * after receiver enable calibration, otherwise raminit sometimes -+ * completes with non-working memory. -+ */ -+ mchbar_write32(0x0530, 0x06060005); -+ mchbar_write32(0x0680, 0x06060606); -+ mchbar_write32(0x0684, 0x08070606); -+ mchbar_write32(0x0688, 0x0e0e0c0a); -+ mchbar_write32(0x068c, 0x0e0e0e0e); -+ mchbar_write32(0x0698, 0x06060606); -+ mchbar_write32(0x069c, 0x08070606); -+ mchbar_write32(0x06a0, 0x0c0c0b0a); -+ mchbar_write32(0x06a4, 0x0c0c0c0c); -+ -+ mchbar_write32(0x06c0, 0x02020202); -+ mchbar_write32(0x06c4, 0x03020202); -+ mchbar_write32(0x06c8, 0x04040403); -+ mchbar_write32(0x06cc, 0x04040404); -+ mchbar_write32(0x06d8, 0x02020202); -+ mchbar_write32(0x06dc, 0x03020202); -+ mchbar_write32(0x06e0, 0x04040403); -+ mchbar_write32(0x06e4, 0x04040404); -+ -+ mchbar_write32(0x0700, 0x02020202); -+ mchbar_write32(0x0704, 0x03020202); -+ mchbar_write32(0x0708, 0x04040403); -+ mchbar_write32(0x070c, 0x04040404); -+ mchbar_write32(0x0718, 0x02020202); -+ mchbar_write32(0x071c, 0x03020202); -+ mchbar_write32(0x0720, 0x04040403); -+ mchbar_write32(0x0724, 0x04040404); -+ -+ mchbar_write32(0x0740, 0x02020202); -+ mchbar_write32(0x0744, 0x03020202); -+ mchbar_write32(0x0748, 0x04040403); -+ mchbar_write32(0x074c, 0x04040404); -+ mchbar_write32(0x0758, 0x02020202); -+ mchbar_write32(0x075c, 0x03020202); -+ mchbar_write32(0x0760, 0x04040403); -+ mchbar_write32(0x0764, 0x04040404); -+ -+ mchbar_write32(0x0780, 0x06060606); -+ mchbar_write32(0x0784, 0x09070606); -+ mchbar_write32(0x0788, 0x0e0e0c0b); -+ mchbar_write32(0x078c, 0x0e0e0e0e); -+ mchbar_write32(0x0798, 0x06060606); -+ mchbar_write32(0x079c, 0x09070606); -+ mchbar_write32(0x07a0, 0x0d0d0c0b); -+ mchbar_write32(0x07a4, 0x0d0d0d0d); -+ -+ mchbar_write32(0x07c0, 0x06060606); -+ mchbar_write32(0x07c4, 0x09070606); -+ mchbar_write32(0x07c8, 0x0e0e0c0b); -+ mchbar_write32(0x07cc, 0x0e0e0e0e); -+ mchbar_write32(0x07d8, 0x06060606); -+ mchbar_write32(0x07dc, 0x09070606); -+ mchbar_write32(0x07e0, 0x0d0d0c0b); -+ mchbar_write32(0x07e4, 0x0d0d0d0d); -+ -+ mchbar_write32(0x0840, 0x06060606); -+ mchbar_write32(0x0844, 0x08070606); -+ mchbar_write32(0x0848, 0x0e0e0c0a); -+ mchbar_write32(0x084c, 0x0e0e0e0e); -+ mchbar_write32(0x0858, 0x06060606); -+ mchbar_write32(0x085c, 0x08070606); -+ mchbar_write32(0x0860, 0x0c0c0b0a); -+ mchbar_write32(0x0864, 0x0c0c0c0c); -+ -+ mchbar_write32(0x0880, 0x02020202); -+ mchbar_write32(0x0884, 0x03020202); -+ mchbar_write32(0x0888, 0x04040403); -+ mchbar_write32(0x088c, 0x04040404); -+ mchbar_write32(0x0898, 0x02020202); -+ mchbar_write32(0x089c, 0x03020202); -+ mchbar_write32(0x08a0, 0x04040403); -+ mchbar_write32(0x08a4, 0x04040404); -+ - igd_compute_ggc(sysinfo); - - /* Program final memory map (with real values). */ -diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -index aef863f05a..b74765fd9c 100644 ---- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -@@ -161,11 +161,13 @@ static void lookup_and_write(const int a1step, - mchbar += 4; - } - } --void raminit_rcomp_calibration(const stepping_t stepping) { -+void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { - const int a1step = stepping >= STEPPING_CONVERSION_A1; - - int i; - -+ char magic_comp[2] = {0}; -+ - enum { - PULL_UP = 0, - PULL_DOWN = 1, -@@ -196,6 +198,10 @@ void raminit_rcomp_calibration(const stepping_t stepping) { - reg = mchbar_read32(0x518); - lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f; - lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f; -+ if (i == 1) { -+ magic_comp[0] = (reg >> 8) & 0x3f; -+ magic_comp[1] = (reg >> 0) & 0x3f; -+ } - } - /* Cleanup? */ - mchbar_setbits32(0x400, 1 << 3); -@@ -216,13 +222,19 @@ void raminit_rcomp_calibration(const stepping_t stepping) { - for (channel = 0; channel < 2; ++channel) { - for (group = 0; group < 6; ++group) { - for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) { -- lookup_and_write( -- a1step, -- lut_idx[channel][group][pu_pd] - 7, -- ddr3_lookup_schedule[group][pu_pd], -- mchbar); -+ if (ddr_type == DDR3) { -+ lookup_and_write( -+ a1step, -+ lut_idx[channel][group][pu_pd] - 7, -+ ddr3_lookup_schedule[group][pu_pd], -+ mchbar); -+ } - mchbar += 0x0018; - } -+ if (ddr_type == DDR2) { -+ mchbar_clrsetbits32(mchbar + 0, 0x7f << 24, lut_idx[channel][group][PULL_DOWN] << 24); -+ mchbar_clrsetbits32(mchbar + 4, 0x7f << 0, lut_idx[channel][group][PULL_UP] << 0); -+ } - mchbar += 0x0010; - /* Channel B knows only the first two groups. */ - if ((1 == channel) && (1 == group)) -@@ -230,4 +242,7 @@ void raminit_rcomp_calibration(const stepping_t stepping) { - } - mchbar += 0x0040; - } -+ -+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); -+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); - } --- -2.47.3 - diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch new file mode 100644 index 00000000..5b1d4d75 --- /dev/null +++ b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch @@ -0,0 +1,51 @@ +From 499885b662b703c472309f64c123d99e65ebe9d2 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Mon, 20 May 2024 10:24:16 -0600 +Subject: [PATCH 18/51] mb/dell/e6400: Use 100 MHz reference clock for display + +The E6400 uses a 100 MHz reference clock for spread spectrum support on +LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For +the more common 1280 x 800 display panels, the numerical error was not +large enough to cause noticable issues, but the actual pixel clock +frequency derived from a 100 MHz reference using PLL configs calculated +assuming a 96 MHz reference was not close enough for 1440 x 900 panels, +which require a much higher pixel clock. This resulted in a garbled +display in the pre-OS graphics environment provided by libgfxinit. + +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/gm45_latitude/Kconfig | 2 ++ + src/northbridge/intel/gm45/Kconfig | 4 ++++ + 2 files changed, 6 insertions(+) + +diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig +index edc79b0d43..5020744990 100644 +--- a/src/mainboard/dell/gm45_latitude/Kconfig ++++ b/src/mainboard/dell/gm45_latitude/Kconfig +@@ -22,6 +22,8 @@ config BOARD_DELL_E6400 + select BOARD_DELL_GM45_LATITUDE_COMMON + + if BOARD_DELL_GM45_LATITUDE_COMMON ++config INTEL_GMA_DPLL_REF_FREQ ++ default 100000000 + + config MAINBOARD_DIR + default "dell/gm45_latitude" +diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig +index a776217475..35e89b0c88 100644 +--- a/src/northbridge/intel/gm45/Kconfig ++++ b/src/northbridge/intel/gm45/Kconfig +@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45 + + if NORTHBRIDGE_INTEL_GM45 + ++config INTEL_GMA_DPLL_REF_FREQ ++ int ++ default 96000000 ++ + config VBOOT + select VBOOT_STARTS_IN_BOOTBLOCK + +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0018-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0018-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch deleted file mode 100644 index 04b00c86..00000000 --- a/config/coreboot/default/patches/0018-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch +++ /dev/null @@ -1,240 +0,0 @@ -From 8effb91216e331655ab64bc0aa114a3b38baec9c Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 6 Aug 2024 00:50:24 +0100 -Subject: [PATCH 18/51] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards - -We add this patch: - -commit commit_id_here -Author: Angel Pons -Date: Mon May 10 22:40:59 2021 +0200 - - nb/intel/gm45: Make DDR2 raminit work - -This patch was original applied, in lbmk, only on coreboot/dell, -separately from coreboot/default, which was wasteful because it -meant having an entire coreboot tree just for a single board. We -did this, because the DDR2 RCOMP fix happened to break DDR3 init -on other boards. - -What *this* new patch does on top of Angel's patch, is make sure -that their changes only apply to DDR2, while DDR3 behaviour remains -unchanged. This means that the Dell Latitude E6400 can be supported -in the main coreboot tree, within lbmk. - -Essentially, this patch restores the old behaviour, prior to applying -Angel's patch, only when DDR3 memory is used. - -Signed-off-by: Leah Rowe ---- - src/northbridge/intel/gm45/raminit.c | 161 +++++++++--------- - .../intel/gm45/raminit_rcomp_calibration.c | 9 +- - 2 files changed, 88 insertions(+), 82 deletions(-) - -diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c -index 7b091cc567..478898564a 100644 ---- a/src/northbridge/intel/gm45/raminit.c -+++ b/src/northbridge/intel/gm45/raminit.c -@@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi - reg = (reg & ~(0xf << 10)) | (2 << 10); - else - reg = (reg & ~(0xf << 10)) | (3 << 10); -- reg = (reg & ~(0x7 << 5)) | (2 << 5); -+ if (spd_type == DDR2) -+ reg = (reg & ~(0x7 << 5)) | (2 << 5); -+ else -+ reg = (reg & ~(0x7 << 5)) | (3 << 5); - } else if (timings->mem_clock != MEM_CLOCK_1067MT) { - reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); - reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); -@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume) - raminit_write_training(timings->mem_clock, dimms, s3resume); - } - -- /* -- * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done -- * after receiver enable calibration, otherwise raminit sometimes -- * completes with non-working memory. -- */ -- mchbar_write32(0x0530, 0x06060005); -- mchbar_write32(0x0680, 0x06060606); -- mchbar_write32(0x0684, 0x08070606); -- mchbar_write32(0x0688, 0x0e0e0c0a); -- mchbar_write32(0x068c, 0x0e0e0e0e); -- mchbar_write32(0x0698, 0x06060606); -- mchbar_write32(0x069c, 0x08070606); -- mchbar_write32(0x06a0, 0x0c0c0b0a); -- mchbar_write32(0x06a4, 0x0c0c0c0c); -- -- mchbar_write32(0x06c0, 0x02020202); -- mchbar_write32(0x06c4, 0x03020202); -- mchbar_write32(0x06c8, 0x04040403); -- mchbar_write32(0x06cc, 0x04040404); -- mchbar_write32(0x06d8, 0x02020202); -- mchbar_write32(0x06dc, 0x03020202); -- mchbar_write32(0x06e0, 0x04040403); -- mchbar_write32(0x06e4, 0x04040404); -- -- mchbar_write32(0x0700, 0x02020202); -- mchbar_write32(0x0704, 0x03020202); -- mchbar_write32(0x0708, 0x04040403); -- mchbar_write32(0x070c, 0x04040404); -- mchbar_write32(0x0718, 0x02020202); -- mchbar_write32(0x071c, 0x03020202); -- mchbar_write32(0x0720, 0x04040403); -- mchbar_write32(0x0724, 0x04040404); -- -- mchbar_write32(0x0740, 0x02020202); -- mchbar_write32(0x0744, 0x03020202); -- mchbar_write32(0x0748, 0x04040403); -- mchbar_write32(0x074c, 0x04040404); -- mchbar_write32(0x0758, 0x02020202); -- mchbar_write32(0x075c, 0x03020202); -- mchbar_write32(0x0760, 0x04040403); -- mchbar_write32(0x0764, 0x04040404); -- -- mchbar_write32(0x0780, 0x06060606); -- mchbar_write32(0x0784, 0x09070606); -- mchbar_write32(0x0788, 0x0e0e0c0b); -- mchbar_write32(0x078c, 0x0e0e0e0e); -- mchbar_write32(0x0798, 0x06060606); -- mchbar_write32(0x079c, 0x09070606); -- mchbar_write32(0x07a0, 0x0d0d0c0b); -- mchbar_write32(0x07a4, 0x0d0d0d0d); -- -- mchbar_write32(0x07c0, 0x06060606); -- mchbar_write32(0x07c4, 0x09070606); -- mchbar_write32(0x07c8, 0x0e0e0c0b); -- mchbar_write32(0x07cc, 0x0e0e0e0e); -- mchbar_write32(0x07d8, 0x06060606); -- mchbar_write32(0x07dc, 0x09070606); -- mchbar_write32(0x07e0, 0x0d0d0c0b); -- mchbar_write32(0x07e4, 0x0d0d0d0d); -- -- mchbar_write32(0x0840, 0x06060606); -- mchbar_write32(0x0844, 0x08070606); -- mchbar_write32(0x0848, 0x0e0e0c0a); -- mchbar_write32(0x084c, 0x0e0e0e0e); -- mchbar_write32(0x0858, 0x06060606); -- mchbar_write32(0x085c, 0x08070606); -- mchbar_write32(0x0860, 0x0c0c0b0a); -- mchbar_write32(0x0864, 0x0c0c0c0c); -- -- mchbar_write32(0x0880, 0x02020202); -- mchbar_write32(0x0884, 0x03020202); -- mchbar_write32(0x0888, 0x04040403); -- mchbar_write32(0x088c, 0x04040404); -- mchbar_write32(0x0898, 0x02020202); -- mchbar_write32(0x089c, 0x03020202); -- mchbar_write32(0x08a0, 0x04040403); -- mchbar_write32(0x08a4, 0x04040404); -+ if (sysinfo->spd_type == DDR2) { -+ /* -+ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done -+ * after receiver enable calibration, otherwise raminit sometimes -+ * completes with non-working memory. -+ */ -+ mchbar_write32(0x0530, 0x06060005); -+ mchbar_write32(0x0680, 0x06060606); -+ mchbar_write32(0x0684, 0x08070606); -+ mchbar_write32(0x0688, 0x0e0e0c0a); -+ mchbar_write32(0x068c, 0x0e0e0e0e); -+ mchbar_write32(0x0698, 0x06060606); -+ mchbar_write32(0x069c, 0x08070606); -+ mchbar_write32(0x06a0, 0x0c0c0b0a); -+ mchbar_write32(0x06a4, 0x0c0c0c0c); -+ -+ mchbar_write32(0x06c0, 0x02020202); -+ mchbar_write32(0x06c4, 0x03020202); -+ mchbar_write32(0x06c8, 0x04040403); -+ mchbar_write32(0x06cc, 0x04040404); -+ mchbar_write32(0x06d8, 0x02020202); -+ mchbar_write32(0x06dc, 0x03020202); -+ mchbar_write32(0x06e0, 0x04040403); -+ mchbar_write32(0x06e4, 0x04040404); -+ -+ mchbar_write32(0x0700, 0x02020202); -+ mchbar_write32(0x0704, 0x03020202); -+ mchbar_write32(0x0708, 0x04040403); -+ mchbar_write32(0x070c, 0x04040404); -+ mchbar_write32(0x0718, 0x02020202); -+ mchbar_write32(0x071c, 0x03020202); -+ mchbar_write32(0x0720, 0x04040403); -+ mchbar_write32(0x0724, 0x04040404); -+ -+ mchbar_write32(0x0740, 0x02020202); -+ mchbar_write32(0x0744, 0x03020202); -+ mchbar_write32(0x0748, 0x04040403); -+ mchbar_write32(0x074c, 0x04040404); -+ mchbar_write32(0x0758, 0x02020202); -+ mchbar_write32(0x075c, 0x03020202); -+ mchbar_write32(0x0760, 0x04040403); -+ mchbar_write32(0x0764, 0x04040404); -+ -+ mchbar_write32(0x0780, 0x06060606); -+ mchbar_write32(0x0784, 0x09070606); -+ mchbar_write32(0x0788, 0x0e0e0c0b); -+ mchbar_write32(0x078c, 0x0e0e0e0e); -+ mchbar_write32(0x0798, 0x06060606); -+ mchbar_write32(0x079c, 0x09070606); -+ mchbar_write32(0x07a0, 0x0d0d0c0b); -+ mchbar_write32(0x07a4, 0x0d0d0d0d); -+ -+ mchbar_write32(0x07c0, 0x06060606); -+ mchbar_write32(0x07c4, 0x09070606); -+ mchbar_write32(0x07c8, 0x0e0e0c0b); -+ mchbar_write32(0x07cc, 0x0e0e0e0e); -+ mchbar_write32(0x07d8, 0x06060606); -+ mchbar_write32(0x07dc, 0x09070606); -+ mchbar_write32(0x07e0, 0x0d0d0c0b); -+ mchbar_write32(0x07e4, 0x0d0d0d0d); -+ -+ mchbar_write32(0x0840, 0x06060606); -+ mchbar_write32(0x0844, 0x08070606); -+ mchbar_write32(0x0848, 0x0e0e0c0a); -+ mchbar_write32(0x084c, 0x0e0e0e0e); -+ mchbar_write32(0x0858, 0x06060606); -+ mchbar_write32(0x085c, 0x08070606); -+ mchbar_write32(0x0860, 0x0c0c0b0a); -+ mchbar_write32(0x0864, 0x0c0c0c0c); -+ -+ mchbar_write32(0x0880, 0x02020202); -+ mchbar_write32(0x0884, 0x03020202); -+ mchbar_write32(0x0888, 0x04040403); -+ mchbar_write32(0x088c, 0x04040404); -+ mchbar_write32(0x0898, 0x02020202); -+ mchbar_write32(0x089c, 0x03020202); -+ mchbar_write32(0x08a0, 0x04040403); -+ mchbar_write32(0x08a4, 0x04040404); -+ } - - igd_compute_ggc(sysinfo); - -diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -index b74765fd9c..5d4505e063 100644 ---- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -@@ -198,7 +198,7 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { - reg = mchbar_read32(0x518); - lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f; - lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f; -- if (i == 1) { -+ if ((i == 1) && (ddr_type == DDR2)) { - magic_comp[0] = (reg >> 8) & 0x3f; - magic_comp[1] = (reg >> 0) & 0x3f; - } -@@ -242,7 +242,8 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { - } - mchbar += 0x0040; - } -- -- mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); -- mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); -+ if (ddr_type == DDR2) { -+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); -+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); -+ } - } --- -2.47.3 - diff --git a/config/coreboot/default/patches/0019-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0019-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch deleted file mode 100644 index 8ed6a3f4..00000000 --- a/config/coreboot/default/patches/0019-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch +++ /dev/null @@ -1,51 +0,0 @@ -From c7b85347f892432b31000c67efccc02c84d9394a Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Mon, 20 May 2024 10:24:16 -0600 -Subject: [PATCH 19/51] mb/dell/e6400: Use 100 MHz reference clock for display - -The E6400 uses a 100 MHz reference clock for spread spectrum support on -LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For -the more common 1280 x 800 display panels, the numerical error was not -large enough to cause noticable issues, but the actual pixel clock -frequency derived from a 100 MHz reference using PLL configs calculated -assuming a 96 MHz reference was not close enough for 1440 x 900 panels, -which require a much higher pixel clock. This resulted in a garbled -display in the pre-OS graphics environment provided by libgfxinit. - -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/gm45_latitude/Kconfig | 2 ++ - src/northbridge/intel/gm45/Kconfig | 4 ++++ - 2 files changed, 6 insertions(+) - -diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig -index edc79b0d43..5020744990 100644 ---- a/src/mainboard/dell/gm45_latitude/Kconfig -+++ b/src/mainboard/dell/gm45_latitude/Kconfig -@@ -22,6 +22,8 @@ config BOARD_DELL_E6400 - select BOARD_DELL_GM45_LATITUDE_COMMON - - if BOARD_DELL_GM45_LATITUDE_COMMON -+config INTEL_GMA_DPLL_REF_FREQ -+ default 100000000 - - config MAINBOARD_DIR - default "dell/gm45_latitude" -diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig -index a776217475..35e89b0c88 100644 ---- a/src/northbridge/intel/gm45/Kconfig -+++ b/src/northbridge/intel/gm45/Kconfig -@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45 - - if NORTHBRIDGE_INTEL_GM45 - -+config INTEL_GMA_DPLL_REF_FREQ -+ int -+ default 96000000 -+ - config VBOOT - select VBOOT_STARTS_IN_BOOTBLOCK - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch new file mode 100644 index 00000000..ff92bb08 --- /dev/null +++ b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch @@ -0,0 +1,52 @@ +From db3148d6762fb16ca79d9bfb3df51210e04a580e Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 12 Aug 2024 02:15:24 +0100 +Subject: [PATCH 19/51] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ + +set it to 96MHz. fixes the following build error when +building for x4x boards e.g. gigabyte ga-g41m-es2l: + +hw-gfx-gma-plls.adb:465:46: error: "INTEL_GMA_DPLL_REF_FREQ" not declared in "Config" +make: *** [Makefile:423: build/ramstage/libgfxinit/common/g45/hw-gfx-gma-plls.o] Error 1 + +this error was introduced when merging coreboot/dell +into coreboot/default in lbmk. nicholas chin's fix in lbmk +was as follows: + +commit 8629873a6043067affc137be275b7aa69cb1f10c +Author: Nicholas Chin +Date: Mon May 20 10:46:25 2024 -0600 + + Fix E6400 display issue with 1440 x 900 panel + +this currently corresponds to the patch in lbmk, +as of 12 august 2024: + +0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch + +The assumption prior to Nicholas's fix was 96MHz, so set +it accordingly on x4x northbridge. + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/x4x/Kconfig | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig +index 6fa4551957..646af3510b 100644 +--- a/src/northbridge/intel/x4x/Kconfig ++++ b/src/northbridge/intel/x4x/Kconfig +@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X + + if NORTHBRIDGE_INTEL_X4X + ++config INTEL_GMA_DPLL_REF_FREQ ++ int ++ default 96000000 ++ + config CBFS_SIZE + default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX + +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch new file mode 100644 index 00000000..d81a380d --- /dev/null +++ b/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch @@ -0,0 +1,332 @@ +From da070b56c01b5ffe35d8dfdac2e7681be5392fc2 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Thu, 26 Sep 2024 19:51:25 -0600 +Subject: [PATCH 20/51] mb/dell/gm45_latitudes: Add E4300 variant + +Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2 +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/gm45_latitude/Kconfig | 5 + + src/mainboard/dell/gm45_latitude/Kconfig.name | 3 + + .../gm45_latitude/variants/e4300/data.vbt | Bin 0 -> 3881 bytes + .../variants/e4300/gma-mainboard.ads | 17 +++ + .../dell/gm45_latitude/variants/e4300/gpio.c | 138 ++++++++++++++++++ + .../gm45_latitude/variants/e4300/hda_verb.c | 37 +++++ + .../variants/e4300/overridetree.cb | 10 ++ + 7 files changed, 210 insertions(+) + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb + +diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig +index 5020744990..d27d5728a8 100644 +--- a/src/mainboard/dell/gm45_latitude/Kconfig ++++ b/src/mainboard/dell/gm45_latitude/Kconfig +@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON + config BOARD_DELL_E6400 + select BOARD_DELL_GM45_LATITUDE_COMMON + ++config BOARD_DELL_E4300 ++ select BOARD_DELL_GM45_LATITUDE_COMMON ++ + if BOARD_DELL_GM45_LATITUDE_COMMON + config INTEL_GMA_DPLL_REF_FREQ + default 100000000 +@@ -30,12 +33,14 @@ config MAINBOARD_DIR + + config MAINBOARD_PART_NUMBER + default "Latitude E6400" if BOARD_DELL_E6400 ++ default "Latitude E4300" if BOARD_DELL_E4300 + + config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + + config VARIANT_DIR + default "e6400" if BOARD_DELL_E6400 ++ default "e4300" if BOARD_DELL_E4300 + + config USBDEBUG_HCD_INDEX + default 1 +diff --git a/src/mainboard/dell/gm45_latitude/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name +index aefe777109..4dc95f46be 100644 +--- a/src/mainboard/dell/gm45_latitude/Kconfig.name ++++ b/src/mainboard/dell/gm45_latitude/Kconfig.name +@@ -1,4 +1,7 @@ + ## SPDX-License-Identifier: GPL-2.0-only + ++config BOARD_DELL_E4300 ++ bool "Latitude E4300" ++ + config BOARD_DELL_E6400 + bool "Latitude E6400" +diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..fa2f3db13f688b5687df16a155781d8674ea26f3 +GIT binary patch +literal 3881 +zcmdT`eQXp(6#wnV-R;foUbovquV-n84`GWGmlkRzXWaG>Td6>yG#51CN?M@?>DeM+ +zBI$}GlK6F+nD{}Y|ClJzh>3}Rm=N?2Y5aNhx3i7B*>RjEs#PQ-s5C6@#q~ze8SUuLOHbzw$htxKlQYWCt9NZmC +zVLO$_s2tQZ9MvqmM&%tUr>K0RF`T3FGnHSdOj6O}3>K9-D$(bpDh$)OQqAIh6jOwCxuw)qvS0N+Nk!? +zI~I-~3&u$!iZQuCQ3;=xYZQ&}1^JS!6aFCSvPt-}q{`KV7o=aLI=_ERh8gM+`g(-E +z9-*&C=<5;sdVc?y{2iwmrKs|~Kw5}Heji&vYYqJOG&As1`1?G0hsr2Y&r%2qq-H)u +z>=c836bj~sR4T<{m@IvjLaC(P1v(j%W}uLfs)L~qi^ +z4yaW6zjKK*SSa$dvbC#eRZDAgQ@dDEfr?l)G{1I8}OhGtOw#1e$Fn9wsUmbC8g}vF{$V$Y~rFp!qRJP)Z!2NYEhIpf^PzD_^ptxacQ#R+9@(N>ibe6 +z@|mz|d=bjIxSe3u0>+jxdmFQMG4?34k2C9i#y(>91!n!pSR`S$B&>T9Y*WHMl(1e% +zuvZiInS^yV!G28GmAbW9XHB~OfNnjavje*Qrfz+xvyXNAl5R-`OBnW@hPA<9+YI|D +z!+P0Z#|`^S!}`Hs7Yw^5X*DKUOVaL7TBAv}d|dV9^O8rYn%=4o&5GjdSWeb`yeyf7 +zk&0z-2#I*9^ljWL^79K!Ex#yORz2-nxRYGT$+NdKUcs>{SI2Fyx@<{2w?w*#&%hG* +zeY&DumV{4Nw4(1*^g5r`avbR44Nj-miiQs;Ii;O}*rL^|oYl8hQ9P@{Qf5}Gn;uRg +zI{c?gKNv~R$&eHj8!uus22Br_GkCD$Q)pf! +zGh%f}_&(hXOZrW-WCWJVw`DdrczV_sXGaOvzjt%F!O;{7J-K`tJBTNGZHe^T`VrkY0pv~u^?l~DG9UD8p8(692 Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c +new file mode 100644 +index 0000000000..b50f8da0b5 +--- /dev/null ++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c +@@ -0,0 +1,138 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_NATIVE, ++ .gpio1 = GPIO_MODE_GPIO, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_GPIO, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_NATIVE, ++ .gpio16 = GPIO_MODE_NATIVE, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_GPIO, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_GPIO, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_NATIVE, ++ .gpio30 = GPIO_MODE_NATIVE, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio1 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio5 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio18 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio20 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio1 = GPIO_INVERT, ++ .gpio7 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_NATIVE, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_NATIVE, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_GPIO, ++ .gpio54 = GPIO_MODE_NATIVE, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_INPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio53 = GPIO_DIR_INPUT, ++ .gpio56 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ }, ++}; +diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c +new file mode 100644 +index 0000000000..a9948a93dd +--- /dev/null ++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c +@@ -0,0 +1,37 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header */ ++ 0x111d76b2, /* IDT 92HD71B7X */ ++ 0x1028024d, /* Subsystem ID */ ++ 13, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ ++ AZALIA_PIN_CFG(0, 0x0a, 0x0421101f), ++ AZALIA_PIN_CFG(0, 0x0b, 0x04a11021), ++ AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x14, 0x40f000f2), ++ AZALIA_PIN_CFG(0, 0x18, 0x90a601a0), ++ AZALIA_PIN_CFG(0, 0x19, 0x40f000f4), ++ AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5), ++ AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6), ++ AZALIA_PIN_CFG(0, 0x20, 0x40f000f7), ++ AZALIA_PIN_CFG(0, 0x27, 0x40f000f0), ++}; ++ ++const u32 pc_beep_verbs[] = { ++ 0x00170500, /* power up codec */ ++ 0x00d70500, /* power up speakers */ ++ 0x00d70102, /* select mixer (input 0x2) for speakers */ ++ 0x00d70740, /* enable speakers output */ ++ 0x02770720, /* enable beep input */ ++ 0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */ ++ 0x00d37000, /* unmute speakers */ ++}; ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb +new file mode 100644 +index 0000000000..20dfa245fb +--- /dev/null ++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb +@@ -0,0 +1,10 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/gm45 ++ device domain 0 on ++ subsystemid 0x1028 0x024d inherit ++ chip southbridge/intel/i82801ix ++ device pci 1c.2 off end # PCIe Port #3 ++ end ++ end ++end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0020-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0020-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch deleted file mode 100644 index 753e8c6f..00000000 --- a/config/coreboot/default/patches/0020-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 6d1cbaedc747afe4acd8b13240c56232ba870639 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 12 Aug 2024 02:15:24 +0100 -Subject: [PATCH 20/51] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ - -set it to 96MHz. fixes the following build error when -building for x4x boards e.g. gigabyte ga-g41m-es2l: - -hw-gfx-gma-plls.adb:465:46: error: "INTEL_GMA_DPLL_REF_FREQ" not declared in "Config" -make: *** [Makefile:423: build/ramstage/libgfxinit/common/g45/hw-gfx-gma-plls.o] Error 1 - -this error was introduced when merging coreboot/dell -into coreboot/default in lbmk. nicholas chin's fix in lbmk -was as follows: - -commit 8629873a6043067affc137be275b7aa69cb1f10c -Author: Nicholas Chin -Date: Mon May 20 10:46:25 2024 -0600 - - Fix E6400 display issue with 1440 x 900 panel - -this currently corresponds to the patch in lbmk, -as of 12 august 2024: - -0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch - -The assumption prior to Nicholas's fix was 96MHz, so set -it accordingly on x4x northbridge. - -Signed-off-by: Leah Rowe ---- - src/northbridge/intel/x4x/Kconfig | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 6fa4551957..646af3510b 100644 ---- a/src/northbridge/intel/x4x/Kconfig -+++ b/src/northbridge/intel/x4x/Kconfig -@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X - - if NORTHBRIDGE_INTEL_X4X - -+config INTEL_GMA_DPLL_REF_FREQ -+ int -+ default 96000000 -+ - config CBFS_SIZE - default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch new file mode 100644 index 00000000..e59fde3c --- /dev/null +++ b/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch @@ -0,0 +1,70 @@ +From 78cf7a8186ad389f6402da9e55f94830f368fcea Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Fri, 3 May 2024 16:31:12 -0600 +Subject: [PATCH 21/51] mb/dell: Add S3 SMI handler for Dell Latitudes + +Integrate the previously added mec5035_smi_sleep() function into +mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240. +The E6400 does not require the EC command to sucessfully suspend and +resume from S3, though sending it does enable the breathing effect on +the power LED while in S3. Without it, all LEDs turn off during S3. + +Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283 +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/gm45_latitude/smihandler.c | 9 +++++++++ + src/mainboard/dell/haswell_latitude/smihandler.c | 9 +++++++++ + src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++ + 3 files changed, 27 insertions(+) + create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c + create mode 100644 src/mainboard/dell/haswell_latitude/smihandler.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c + +diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c +new file mode 100644 +index 0000000000..00e55b51db +--- /dev/null ++++ b/src/mainboard/dell/gm45_latitude/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_smi_sleep(slp_typ); ++} +diff --git a/src/mainboard/dell/haswell_latitude/smihandler.c b/src/mainboard/dell/haswell_latitude/smihandler.c +new file mode 100644 +index 0000000000..00e55b51db +--- /dev/null ++++ b/src/mainboard/dell/haswell_latitude/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_smi_sleep(slp_typ); ++} +diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c +new file mode 100644 +index 0000000000..00e55b51db +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_smi_sleep(slp_typ); ++} +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch deleted file mode 100644 index 7266646e..00000000 --- a/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch +++ /dev/null @@ -1,332 +0,0 @@ -From bd1594c9025dbd84cdce4aac02152b809b67b108 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Thu, 26 Sep 2024 19:51:25 -0600 -Subject: [PATCH 21/51] mb/dell/gm45_latitudes: Add E4300 variant - -Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2 -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/gm45_latitude/Kconfig | 5 + - src/mainboard/dell/gm45_latitude/Kconfig.name | 3 + - .../gm45_latitude/variants/e4300/data.vbt | Bin 0 -> 3881 bytes - .../variants/e4300/gma-mainboard.ads | 17 +++ - .../dell/gm45_latitude/variants/e4300/gpio.c | 138 ++++++++++++++++++ - .../gm45_latitude/variants/e4300/hda_verb.c | 37 +++++ - .../variants/e4300/overridetree.cb | 10 ++ - 7 files changed, 210 insertions(+) - create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt - create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads - create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c - create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c - create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb - -diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig -index 5020744990..d27d5728a8 100644 ---- a/src/mainboard/dell/gm45_latitude/Kconfig -+++ b/src/mainboard/dell/gm45_latitude/Kconfig -@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON - config BOARD_DELL_E6400 - select BOARD_DELL_GM45_LATITUDE_COMMON - -+config BOARD_DELL_E4300 -+ select BOARD_DELL_GM45_LATITUDE_COMMON -+ - if BOARD_DELL_GM45_LATITUDE_COMMON - config INTEL_GMA_DPLL_REF_FREQ - default 100000000 -@@ -30,12 +33,14 @@ config MAINBOARD_DIR - - config MAINBOARD_PART_NUMBER - default "Latitude E6400" if BOARD_DELL_E6400 -+ default "Latitude E4300" if BOARD_DELL_E4300 - - config OVERRIDE_DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" - - config VARIANT_DIR - default "e6400" if BOARD_DELL_E6400 -+ default "e4300" if BOARD_DELL_E4300 - - config USBDEBUG_HCD_INDEX - default 1 -diff --git a/src/mainboard/dell/gm45_latitude/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name -index aefe777109..4dc95f46be 100644 ---- a/src/mainboard/dell/gm45_latitude/Kconfig.name -+++ b/src/mainboard/dell/gm45_latitude/Kconfig.name -@@ -1,4 +1,7 @@ - ## SPDX-License-Identifier: GPL-2.0-only - -+config BOARD_DELL_E4300 -+ bool "Latitude E4300" -+ - config BOARD_DELL_E6400 - bool "Latitude E6400" -diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..fa2f3db13f688b5687df16a155781d8674ea26f3 -GIT binary patch -literal 3881 -zcmdT`eQXp(6#wnV-R;foUbovquV-n84`GWGmlkRzXWaG>Td6>yG#51CN?M@?>DeM+ -zBI$}GlK6F+nD{}Y|ClJzh>3}Rm=N?2Y5aNhx3i7B*>RjEs#PQ-s5C6@#q~ze8SUuLOHbzw$htxKlQYWCt9NZmC -zVLO$_s2tQZ9MvqmM&%tUr>K0RF`T3FGnHSdOj6O}3>K9-D$(bpDh$)OQqAIh6jOwCxuw)qvS0N+Nk!? -zI~I-~3&u$!iZQuCQ3;=xYZQ&}1^JS!6aFCSvPt-}q{`KV7o=aLI=_ERh8gM+`g(-E -z9-*&C=<5;sdVc?y{2iwmrKs|~Kw5}Heji&vYYqJOG&As1`1?G0hsr2Y&r%2qq-H)u -z>=c836bj~sR4T<{m@IvjLaC(P1v(j%W}uLfs)L~qi^ -z4yaW6zjKK*SSa$dvbC#eRZDAgQ@dDEfr?l)G{1I8}OhGtOw#1e$Fn9wsUmbC8g}vF{$V$Y~rFp!qRJP)Z!2NYEhIpf^PzD_^ptxacQ#R+9@(N>ibe6 -z@|mz|d=bjIxSe3u0>+jxdmFQMG4?34k2C9i#y(>91!n!pSR`S$B&>T9Y*WHMl(1e% -zuvZiInS^yV!G28GmAbW9XHB~OfNnjavje*Qrfz+xvyXNAl5R-`OBnW@hPA<9+YI|D -z!+P0Z#|`^S!}`Hs7Yw^5X*DKUOVaL7TBAv}d|dV9^O8rYn%=4o&5GjdSWeb`yeyf7 -zk&0z-2#I*9^ljWL^79K!Ex#yORz2-nxRYGT$+NdKUcs>{SI2Fyx@<{2w?w*#&%hG* -zeY&DumV{4Nw4(1*^g5r`avbR44Nj-miiQs;Ii;O}*rL^|oYl8hQ9P@{Qf5}Gn;uRg -zI{c?gKNv~R$&eHj8!uus22Br_GkCD$Q)pf! -zGh%f}_&(hXOZrW-WCWJVw`DdrczV_sXGaOvzjt%F!O;{7J-K`tJBTNGZHe^T`VrkY0pv~u^?l~DG9UD8p8(692 Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c -new file mode 100644 -index 0000000000..b50f8da0b5 ---- /dev/null -+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c -@@ -0,0 +1,138 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_NATIVE, -+ .gpio1 = GPIO_MODE_GPIO, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_GPIO, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_GPIO, -+ .gpio8 = GPIO_MODE_GPIO, -+ .gpio9 = GPIO_MODE_NATIVE, -+ .gpio10 = GPIO_MODE_NATIVE, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_NATIVE, -+ .gpio16 = GPIO_MODE_NATIVE, -+ .gpio17 = GPIO_MODE_GPIO, -+ .gpio18 = GPIO_MODE_GPIO, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_GPIO, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_NATIVE, -+ .gpio30 = GPIO_MODE_NATIVE, -+ .gpio31 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio1 = GPIO_DIR_INPUT, -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio5 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio7 = GPIO_DIR_INPUT, -+ .gpio8 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio17 = GPIO_DIR_INPUT, -+ .gpio18 = GPIO_DIR_INPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio20 = GPIO_DIR_INPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio1 = GPIO_INVERT, -+ .gpio7 = GPIO_INVERT, -+ .gpio8 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_NATIVE, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_NATIVE, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_NATIVE, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_NATIVE, -+ .gpio52 = GPIO_MODE_GPIO, -+ .gpio53 = GPIO_MODE_GPIO, -+ .gpio54 = GPIO_MODE_NATIVE, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_GPIO, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_INPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_INPUT, -+ .gpio52 = GPIO_DIR_INPUT, -+ .gpio53 = GPIO_DIR_INPUT, -+ .gpio56 = GPIO_DIR_INPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ }, -+}; -diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c -new file mode 100644 -index 0000000000..a9948a93dd ---- /dev/null -+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c -@@ -0,0 +1,37 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ /* coreboot specific header */ -+ 0x111d76b2, /* IDT 92HD71B7X */ -+ 0x1028024d, /* Subsystem ID */ -+ 13, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ -+ AZALIA_PIN_CFG(0, 0x0a, 0x0421101f), -+ AZALIA_PIN_CFG(0, 0x0b, 0x04a11021), -+ AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0), -+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), -+ AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e), -+ AZALIA_PIN_CFG(0, 0x0f, 0x23011050), -+ AZALIA_PIN_CFG(0, 0x14, 0x40f000f2), -+ AZALIA_PIN_CFG(0, 0x18, 0x90a601a0), -+ AZALIA_PIN_CFG(0, 0x19, 0x40f000f4), -+ AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5), -+ AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6), -+ AZALIA_PIN_CFG(0, 0x20, 0x40f000f7), -+ AZALIA_PIN_CFG(0, 0x27, 0x40f000f0), -+}; -+ -+const u32 pc_beep_verbs[] = { -+ 0x00170500, /* power up codec */ -+ 0x00d70500, /* power up speakers */ -+ 0x00d70102, /* select mixer (input 0x2) for speakers */ -+ 0x00d70740, /* enable speakers output */ -+ 0x02770720, /* enable beep input */ -+ 0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */ -+ 0x00d37000, /* unmute speakers */ -+}; -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb -new file mode 100644 -index 0000000000..20dfa245fb ---- /dev/null -+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb -@@ -0,0 +1,10 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/gm45 -+ device domain 0 on -+ subsystemid 0x1028 0x024d inherit -+ chip southbridge/intel/i82801ix -+ device pci 1c.2 off end # PCIe Port #3 -+ end -+ end -+end --- -2.47.3 - diff --git a/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch new file mode 100644 index 00000000..9667d4ac --- /dev/null +++ b/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch @@ -0,0 +1,31 @@ +From 7f131cd791eb2dcf68f0e1e9049cc5b4c301232b Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 31 Dec 2024 14:42:24 +0000 +Subject: [PATCH 22/51] Disable compression on refcode insertion + +Compression is not reliably reproducible. In an lbmk release +context, this means we cannot rely on vendorfile insertion. + +Therefore, use uncompressed refcode. + +Signed-off-by: Leah Rowe +--- + Makefile.mk | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/Makefile.mk b/Makefile.mk +index dbad313911..8f541ad187 100644 +--- a/Makefile.mk ++++ b/Makefile.mk +@@ -1432,7 +1432,7 @@ endif + cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode + $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB) + $(CONFIG_CBFS_PREFIX)/refcode-type := stage +-$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG) ++$(CONFIG_CBFS_PREFIX)/refcode-compression := none + + cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin + vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE) +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch deleted file mode 100644 index cc67346f..00000000 --- a/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 7fda207316f80a5bdffe428309df32a278d13c93 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Fri, 3 May 2024 16:31:12 -0600 -Subject: [PATCH 22/51] mb/dell: Add S3 SMI handler for Dell Latitudes - -Integrate the previously added mec5035_smi_sleep() function into -mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240. -The E6400 does not require the EC command to sucessfully suspend and -resume from S3, though sending it does enable the breathing effect on -the power LED while in S3. Without it, all LEDs turn off during S3. - -Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283 -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/gm45_latitude/smihandler.c | 9 +++++++++ - src/mainboard/dell/haswell_latitude/smihandler.c | 9 +++++++++ - src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++ - 3 files changed, 27 insertions(+) - create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c - create mode 100644 src/mainboard/dell/haswell_latitude/smihandler.c - create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c - -diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c -new file mode 100644 -index 0000000000..00e55b51db ---- /dev/null -+++ b/src/mainboard/dell/gm45_latitude/smihandler.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+ -+void mainboard_smi_sleep(u8 slp_typ) -+{ -+ mec5035_smi_sleep(slp_typ); -+} -diff --git a/src/mainboard/dell/haswell_latitude/smihandler.c b/src/mainboard/dell/haswell_latitude/smihandler.c -new file mode 100644 -index 0000000000..00e55b51db ---- /dev/null -+++ b/src/mainboard/dell/haswell_latitude/smihandler.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+ -+void mainboard_smi_sleep(u8 slp_typ) -+{ -+ mec5035_smi_sleep(slp_typ); -+} -diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c -new file mode 100644 -index 0000000000..00e55b51db ---- /dev/null -+++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+ -+void mainboard_smi_sleep(u8 slp_typ) -+{ -+ mec5035_smi_sleep(slp_typ); -+} --- -2.47.3 - diff --git a/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch deleted file mode 100644 index 1205b3bf..00000000 --- a/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 8f5399ac24599f6d0f1912d46f253a91d67536cf Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 31 Dec 2024 14:42:24 +0000 -Subject: [PATCH 23/51] Disable compression on refcode insertion - -Compression is not reliably reproducible. In an lbmk release -context, this means we cannot rely on vendorfile insertion. - -Therefore, use uncompressed refcode. - -Signed-off-by: Leah Rowe ---- - Makefile.mk | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/Makefile.mk b/Makefile.mk -index dbad313911..8f541ad187 100644 ---- a/Makefile.mk -+++ b/Makefile.mk -@@ -1432,7 +1432,7 @@ endif - cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode - $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB) - $(CONFIG_CBFS_PREFIX)/refcode-type := stage --$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG) -+$(CONFIG_CBFS_PREFIX)/refcode-compression := none - - cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin - vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE) --- -2.47.3 - diff --git a/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch new file mode 100644 index 00000000..22220553 --- /dev/null +++ b/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch @@ -0,0 +1,187 @@ +From 0ef9596d987ae2f9d5d63f7961b60e7d05529d1b Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 21 Apr 2025 02:58:47 +0100 +Subject: [PATCH 23/51] nb/intel/*: Disable stack overflow debug options + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/e7505/Kconfig | 9 +++++++++ + src/northbridge/intel/gm45/Kconfig | 9 +++++++++ + src/northbridge/intel/haswell/Kconfig | 9 +++++++++ + src/northbridge/intel/i440bx/Kconfig | 13 +++++++++++++ + src/northbridge/intel/i945/Kconfig | 9 +++++++++ + src/northbridge/intel/ironlake/Kconfig | 9 +++++++++ + src/northbridge/intel/pineview/Kconfig | 9 +++++++++ + src/northbridge/intel/sandybridge/Kconfig | 9 +++++++++ + src/northbridge/intel/x4x/Kconfig | 9 +++++++++ + 9 files changed, 85 insertions(+) + +diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig +index 039a7396f8..ddcb986f10 100644 +--- a/src/northbridge/intel/e7505/Kconfig ++++ b/src/northbridge/intel/e7505/Kconfig +@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505 + select NO_CBFS_MCACHE + select SMM_TSEG + select NEED_SMALL_2MB_PAGE_TABLES ++ ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n +diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig +index 35e89b0c88..c5456d0ddf 100644 +--- a/src/northbridge/intel/gm45/Kconfig ++++ b/src/northbridge/intel/gm45/Kconfig +@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE + config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig +index d67cc14660..fa22e35ccb 100644 +--- a/src/northbridge/intel/haswell/Kconfig ++++ b/src/northbridge/intel/haswell/Kconfig +@@ -9,6 +9,15 @@ config NORTHBRIDGE_INTEL_HASWELL + + if NORTHBRIDGE_INTEL_HASWELL + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + config USE_NATIVE_RAMINIT + bool "[NOT COMPLETE] Use native raminit" + default n +diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig +index dbb2d7436b..5e9418b6a9 100644 +--- a/src/northbridge/intel/i440bx/Kconfig ++++ b/src/northbridge/intel/i440bx/Kconfig +@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM + If your board has 4 DIMM slots, you must use select this option, in + your Kconfig file of the board. On boards with 3 DIMM slots, + do _not_ select this option. ++ ++if NORTHBRIDGE_INTEL_I440BX ++ ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ ++endif +diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig +index c4e17f90bf..b12f5be091 100644 +--- a/src/northbridge/intel/i945/Kconfig ++++ b/src/northbridge/intel/i945/Kconfig +@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE + config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig +index 39566a6e5f..f46acf6937 100644 +--- a/src/northbridge/intel/ironlake/Kconfig ++++ b/src/northbridge/intel/ironlake/Kconfig +@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE + config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig +index a05b866dad..50e3a7cdb9 100644 +--- a/src/northbridge/intel/pineview/Kconfig ++++ b/src/northbridge/intel/pineview/Kconfig +@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE + config DOMAIN_RESOURCE_32BIT_LIMIT + default 0xfec00000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig +index 9972a43da0..fe4ac5106c 100644 +--- a/src/northbridge/intel/sandybridge/Kconfig ++++ b/src/northbridge/intel/sandybridge/Kconfig +@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX + default 2 if IGD_DEFAULT_UMA_SIZE_96MB + default 3 if IGD_DEFAULT_UMA_SIZE_128MB + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig +index 646af3510b..069fa0244d 100644 +--- a/src/northbridge/intel/x4x/Kconfig ++++ b/src/northbridge/intel/x4x/Kconfig +@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE + config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + endif +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch new file mode 100644 index 00000000..c30e1a53 --- /dev/null +++ b/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch @@ -0,0 +1,708 @@ +From 57f57075c69ce6e1caf9d0daf991b1f373d7f04b Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Mon, 30 Sep 2024 20:44:38 -0400 +Subject: [PATCH 24/51] mb/dell: Add Optiplex 780 MT (x4x/ICH10) + +Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/optiplex_780/Kconfig | 40 ++++ + src/mainboard/dell/optiplex_780/Kconfig.name | 4 + + src/mainboard/dell/optiplex_780/Makefile.mk | 10 + + src/mainboard/dell/optiplex_780/acpi/ec.asl | 5 + + .../dell/optiplex_780/acpi/ich10_pci_irqs.asl | 32 ++++ + .../dell/optiplex_780/acpi/superio.asl | 18 ++ + .../dell/optiplex_780/board_info.txt | 6 + + src/mainboard/dell/optiplex_780/cmos.default | 8 + + src/mainboard/dell/optiplex_780/cmos.layout | 72 ++++++++ + src/mainboard/dell/optiplex_780/cstates.c | 8 + + src/mainboard/dell/optiplex_780/devicetree.cb | 63 +++++++ + src/mainboard/dell/optiplex_780/dsdt.asl | 26 +++ + .../dell/optiplex_780/gma-mainboard.ads | 16 ++ + .../optiplex_780/variants/780_mt/data.vbt | Bin 0 -> 1917 bytes + .../optiplex_780/variants/780_mt/early_init.c | 12 ++ + .../dell/optiplex_780/variants/780_mt/gpio.c | 174 ++++++++++++++++++ + .../optiplex_780/variants/780_mt/hda_verb.c | 26 +++ + .../variants/780_mt/overridetree.cb | 10 + + 18 files changed, 530 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_780/Kconfig + create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name + create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk + create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl + create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl + create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl + create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt + create mode 100644 src/mainboard/dell/optiplex_780/cmos.default + create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout + create mode 100644 src/mainboard/dell/optiplex_780/cstates.c + create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb + create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl + create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb + +diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig +new file mode 100644 +index 0000000000..2d06c75c9a +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/Kconfig +@@ -0,0 +1,40 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_DELL_OPTIPLEX_780_COMMON ++ def_bool n ++ select BOARD_ROMSIZE_KB_8192 ++ select CPU_INTEL_SOCKET_LGA775 ++ select DRIVERS_I2C_CK505 ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ select INTEL_GMA_HAVE_VBT ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select NORTHBRIDGE_INTEL_X4X ++ select PCIEXP_ASPM ++ select PCIEXP_CLK_PM ++ select SOUTHBRIDGE_INTEL_I82801JX ++ ++config BOARD_DELL_OPTIPLEX_780_MT ++ select BOARD_DELL_OPTIPLEX_780_COMMON ++ ++if BOARD_DELL_OPTIPLEX_780_COMMON ++ ++config VGA_BIOS_ID ++ default "8086,2e22" ++ ++config MAINBOARD_DIR ++ default "dell/optiplex_780" ++ ++config MAINBOARD_PART_NUMBER ++ default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT ++ ++config OVERRIDE_DEVICETREE ++ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" ++ ++config VARIANT_DIR ++ default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT ++ ++endif # BOARD_DELL_OPTIPLEX_780_COMMON +diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name +new file mode 100644 +index 0000000000..db7f2e8fe3 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/Kconfig.name +@@ -0,0 +1,4 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_DELL_OPTIPLEX_780_MT ++ bool "OptiPlex 780 MT" +diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk +new file mode 100644 +index 0000000000..d462995d75 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/Makefile.mk +@@ -0,0 +1,10 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++ramstage-y += cstates.c ++romstage-y += variants/$(VARIANT_DIR)/gpio.c ++ ++bootblock-y += variants/$(VARIANT_DIR)/early_init.c ++romstage-y += variants/$(VARIANT_DIR)/early_init.c ++ ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads ++ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl +new file mode 100644 +index 0000000000..479296cb76 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl +@@ -0,0 +1,5 @@ ++/* SPDX-License-Identifier: CC-PDDC */ ++ ++/* Please update the license if adding licensable material. */ ++ ++/* dummy */ +diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl +new file mode 100644 +index 0000000000..b7588dcc41 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* This is board specific information: ++ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 ++ */ ++ ++If (PICM) { ++ Return (Package() { ++ /* PCI slot */ ++ Package() { 0x0001ffff, 0, 0, 0x14}, ++ Package() { 0x0001ffff, 1, 0, 0x15}, ++ Package() { 0x0001ffff, 2, 0, 0x16}, ++ Package() { 0x0001ffff, 3, 0, 0x17}, ++ ++ Package() { 0x0002ffff, 0, 0, 0x15}, ++ Package() { 0x0002ffff, 1, 0, 0x16}, ++ Package() { 0x0002ffff, 2, 0, 0x17}, ++ Package() { 0x0002ffff, 3, 0, 0x14}, ++ }) ++} Else { ++ Return (Package() { ++ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, ++ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, ++ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, ++ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, ++ ++ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, ++ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, ++ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, ++ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, ++ }) ++} +diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl +new file mode 100644 +index 0000000000..9f3900b86c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl +@@ -0,0 +1,18 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#undef SUPERIO_DEV ++#undef SUPERIO_PNP_BASE ++#undef IT8720F_SHOW_SP1 ++#undef IT8720F_SHOW_SP2 ++#undef IT8720F_SHOW_EC ++#undef IT8720F_SHOW_KBCK ++#undef IT8720F_SHOW_KBCM ++#undef IT8720F_SHOW_GPIO ++#undef IT8720F_SHOW_CIR ++#define SUPERIO_DEV SIO0 ++#define SUPERIO_PNP_BASE 0x2e ++#define IT8720F_SHOW_EC 1 ++#define IT8720F_SHOW_KBCK 1 ++#define IT8720F_SHOW_KBCM 1 ++#define IT8720F_SHOW_GPIO 1 ++#include +diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt +new file mode 100644 +index 0000000000..aaf657b583 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/board_info.txt +@@ -0,0 +1,6 @@ ++Category: desktop ++Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1 ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y +diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default +new file mode 100644 +index 0000000000..23f0e55f3e +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/cmos.default +@@ -0,0 +1,8 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Disable ++nmi=Enable ++sata_mode=AHCI ++gfx_uma_size=64M +diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout +new file mode 100644 +index 0000000000..9f5012adb4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/cmos.layout +@@ -0,0 +1,72 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++ ++# coreboot config options: southbridge ++408 1 e 10 sata_mode ++409 2 e 7 power_on_after_fail ++411 1 e 1 nmi ++ ++# coreboot config options: cpu ++ ++# coreboot config options: northbridge ++432 4 e 11 gfx_uma_size ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++2 0 Enable ++2 1 Disable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++10 0 AHCI ++10 1 Compatible ++11 1 4M ++11 2 8M ++11 3 16M ++11 4 32M ++11 5 48M ++11 6 64M ++11 7 128M ++11 8 256M ++11 9 96M ++11 10 160M ++11 11 224M ++11 12 352M ++ ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 983 984 +diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c +new file mode 100644 +index 0000000000..4adf0edc63 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/cstates.c +@@ -0,0 +1,8 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++int get_cst_entries(const acpi_cstate_t **entries) ++{ ++ return 0; ++} +diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb +new file mode 100644 +index 0000000000..95e3bd517c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/devicetree.cb +@@ -0,0 +1,63 @@ ++# SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster ++ device domain 0 on ++ ops x4x_pci_domain_ops # PCI domain ++ subsystemid 0x8086 0x0028 inherit ++ device pci 0.0 on end # Host Bridge ++ device pci 1.0 on end # PCIe x16 2.0 slot ++ device pci 2.0 on end # Integrated graphics controller ++ device pci 2.1 on end # Integrated graphics controller 2 ++ device pci 3.0 off end # ME ++ device pci 3.1 off end # ME ++ chip southbridge/intel/i82801jx # ICH10 ++ register "gpe0_en" = "0x40" ++ ++ # Set AHCI mode. ++ register "sata_port_map" = "0x3f" ++ register "sata_clock_request" = "1" ++ ++ # Enable PCIe ports 0,1 as slots. ++ register "pcie_slot_implemented" = "0x3" ++ ++ device pci 19.0 on end # GBE ++ device pci 1a.0 on end # USB ++ device pci 1a.1 on end # USB ++ device pci 1a.2 on end # USB ++ device pci 1a.7 on end # USB ++ device pci 1b.0 on end # Audio ++ device pci 1c.0 off end # PCIe 1 ++ device pci 1c.1 off end # PCIe 2 ++ device pci 1c.2 off end # PCIe 3 ++ device pci 1c.3 off end # PCIe 4 ++ device pci 1c.4 off end # PCIe 5 ++ device pci 1c.5 off end # PCIe 6 ++ device pci 1d.0 on end # USB ++ device pci 1d.1 on end # USB ++ device pci 1d.2 on end # USB ++ device pci 1d.7 on end # USB ++ device pci 1e.0 on end # PCI bridge ++ device pci 1f.0 on end # LPC bridge ++ device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5) ++ device pci 1f.3 on # SMBus ++ chip drivers/i2c/ck505 # IDT CV194 ++ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff }" ++ register "regs" = "{ 0x15, 0x82, 0xff, 0xff, ++ 0xff, 0x00, 0x00, 0x95, ++ 0x00, 0x65, 0x7d, 0x56, ++ 0x13, 0xc0, 0x00, 0x07, ++ 0x01, 0x0a, 0x64 }" ++ device i2c 69 on end ++ end ++ end ++ device pci 1f.4 off end ++ device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode) ++ device pci 1f.6 off end # Thermal Subsystem ++ end ++ end ++end +diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl +new file mode 100644 +index 0000000000..9ad70469de +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/dsdt.asl +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20090811 // OEM revision ++) ++{ ++ #include ++ ++ OSYS = 2002 ++ // global NVS and variables ++ #include ++ ++ Device (\_SB.PCI0) ++ { ++ #include ++ #include ++ } ++ ++ #include ++} +diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads +new file mode 100644 +index 0000000000..bc81cf4a40 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads +@@ -0,0 +1,16 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (DP2, ++ Analog, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..fefda9d6f226b88ab67c5b044de30a707df22fbf +GIT binary patch +literal 1917 +zcmd6nO>7%Q6vzLwGv0Mv$FUpJ*ik4iQd_wnX*X`M0y3~p?8a$~>ZXxZMU`4dc9RGb +zTXq_i1Bwd~aNr{c4i)r(goF^M-nek+sY0sMa}Sk>xFFy_FTEfX^Y+7unt+OgkeJbX +zznS;`v-5V=o{ZwwmnN>gY?}>{`7^JBpP$l`EBIwbi0*k&aU)n@v)E +znI_A1T57efS5MGNN5_ut +zt=x`G)EjR#mlhURC^2!A3p33TcBg4-d8JyTiF&hfk}|a#&Dfe2%~V^}=4!QavNzBh +z0Pae^5`gfb?7Q)c(LsP)8 +zQy)2gwgG1S^>aw&0D}Z+-SCcJJF;s)yXJeQ|4N{SU?$I`#$HZa9dWBuxA$6X;VK;%W?Y>I;0P`|*vwAK$S(VB2JSq6g4n +z>oEf8XCt;_Y-iYBWz#3T9EmJ +z2x?*GPeN%?=Fj3+fv~4%I(nv~XF7VOqi5RsAt%13JtW>q=<<;0IkLPSUGL%_1h)2kjaZzuV;`43yCV;I=#Jcyyw@xKE8GGX39@am|0GKhH` +zawsKv^FvHqm+c8*FfFsu??w)Oed@;Mg~21%rCZ%d{x!>-zmv4AyWL1E +xfz+CGUnQ7Y^TD}&c_cQRYlBC+`?m?k6Nuw??s04gg4@4`<@FO{XEbO( ++ ++void mb_get_spd_map(u8 spd_map[4]) ++{ ++ // BTX form factor ++ spd_map[0] = 0x53; ++ spd_map[1] = 0x52; ++ spd_map[2] = 0x51; ++ spd_map[3] = 0x50; ++} +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c +new file mode 100644 +index 0000000000..9993f17c55 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c +@@ -0,0 +1,174 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_NATIVE, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_GPIO, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_NATIVE, ++ .gpio8 = GPIO_MODE_NATIVE, ++ .gpio9 = GPIO_MODE_GPIO, ++ .gpio10 = GPIO_MODE_GPIO, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_NATIVE, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_NATIVE, ++ .gpio18 = GPIO_MODE_GPIO, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_GPIO, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio5 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio9 = GPIO_DIR_OUTPUT, ++ .gpio10 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio18 = GPIO_DIR_OUTPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio20 = GPIO_DIR_OUTPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_INPUT, ++ .gpio31 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio9 = GPIO_LEVEL_HIGH, ++ .gpio18 = GPIO_LEVEL_HIGH, ++ .gpio20 = GPIO_LEVEL_HIGH, ++ .gpio28 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio13 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_GPIO, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_NATIVE, ++ .gpio52 = GPIO_MODE_NATIVE, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio32 = GPIO_DIR_INPUT, ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio35 = GPIO_DIR_OUTPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio56 = GPIO_DIR_OUTPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio35 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_HIGH, ++ .gpio56 = GPIO_LEVEL_HIGH, ++ .gpio60 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_NATIVE, ++ .gpio69 = GPIO_MODE_NATIVE, ++ .gpio70 = GPIO_MODE_NATIVE, ++ .gpio71 = GPIO_MODE_NATIVE, ++ .gpio72 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio72 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ }, ++}; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c +new file mode 100644 +index 0000000000..4158bcf899 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header */ ++ 0x11d4194a, /* Analog Devices AD1984A */ ++ 0xbfd40000, /* Subsystem ID */ ++ 10, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ AZALIA_PIN_CFG(0, 0x11, 0x032140f0), ++ AZALIA_PIN_CFG(0, 0x12, 0x21214010), ++ AZALIA_PIN_CFG(0, 0x13, 0x901701f0), ++ AZALIA_PIN_CFG(0, 0x14, 0x03a190f0), ++ AZALIA_PIN_CFG(0, 0x15, 0xb7a70121), ++ AZALIA_PIN_CFG(0, 0x16, 0x9933012e), ++ AZALIA_PIN_CFG(0, 0x17, 0x97a601f0), ++ AZALIA_PIN_CFG(0, 0x1a, 0x90f301f0), ++ AZALIA_PIN_CFG(0, 0x1b, 0x014510f0), ++ AZALIA_PIN_CFG(0, 0x1c, 0x21a19020), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb +new file mode 100644 +index 0000000000..555b1c1f5c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb +@@ -0,0 +1,10 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device domain 0 on ++ chip southbridge/intel/i82801jx ++ device pci 1c.0 on end # PCIe 1 ++ device pci 1c.1 on end # PCIe 2 ++ end ++ end ++end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch deleted file mode 100644 index 2d4b8dad..00000000 --- a/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch +++ /dev/null @@ -1,187 +0,0 @@ -From 1e3e9ea40f4b43b9ffbb390222d8c4a4a67dd332 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 21 Apr 2025 02:58:47 +0100 -Subject: [PATCH 24/51] nb/intel/*: Disable stack overflow debug options - -Signed-off-by: Leah Rowe ---- - src/northbridge/intel/e7505/Kconfig | 9 +++++++++ - src/northbridge/intel/gm45/Kconfig | 9 +++++++++ - src/northbridge/intel/haswell/Kconfig | 9 +++++++++ - src/northbridge/intel/i440bx/Kconfig | 13 +++++++++++++ - src/northbridge/intel/i945/Kconfig | 9 +++++++++ - src/northbridge/intel/ironlake/Kconfig | 9 +++++++++ - src/northbridge/intel/pineview/Kconfig | 9 +++++++++ - src/northbridge/intel/sandybridge/Kconfig | 9 +++++++++ - src/northbridge/intel/x4x/Kconfig | 9 +++++++++ - 9 files changed, 85 insertions(+) - -diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig -index 039a7396f8..ddcb986f10 100644 ---- a/src/northbridge/intel/e7505/Kconfig -+++ b/src/northbridge/intel/e7505/Kconfig -@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505 - select NO_CBFS_MCACHE - select SMM_TSEG - select NEED_SMALL_2MB_PAGE_TABLES -+ -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig -index 35e89b0c88..c5456d0ddf 100644 ---- a/src/northbridge/intel/gm45/Kconfig -+++ b/src/northbridge/intel/gm45/Kconfig -@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE - config FIXED_EPBAR_MMIO_BASE - default 0xfed19000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig -index d67cc14660..fa22e35ccb 100644 ---- a/src/northbridge/intel/haswell/Kconfig -+++ b/src/northbridge/intel/haswell/Kconfig -@@ -9,6 +9,15 @@ config NORTHBRIDGE_INTEL_HASWELL - - if NORTHBRIDGE_INTEL_HASWELL - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - config USE_NATIVE_RAMINIT - bool "[NOT COMPLETE] Use native raminit" - default n -diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig -index dbb2d7436b..5e9418b6a9 100644 ---- a/src/northbridge/intel/i440bx/Kconfig -+++ b/src/northbridge/intel/i440bx/Kconfig -@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM - If your board has 4 DIMM slots, you must use select this option, in - your Kconfig file of the board. On boards with 3 DIMM slots, - do _not_ select this option. -+ -+if NORTHBRIDGE_INTEL_I440BX -+ -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ -+endif -diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig -index c4e17f90bf..b12f5be091 100644 ---- a/src/northbridge/intel/i945/Kconfig -+++ b/src/northbridge/intel/i945/Kconfig -@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE - config FIXED_EPBAR_MMIO_BASE - default 0xfed19000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig -index 39566a6e5f..f46acf6937 100644 ---- a/src/northbridge/intel/ironlake/Kconfig -+++ b/src/northbridge/intel/ironlake/Kconfig -@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE - config FIXED_EPBAR_MMIO_BASE - default 0xfed19000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig -index a05b866dad..50e3a7cdb9 100644 ---- a/src/northbridge/intel/pineview/Kconfig -+++ b/src/northbridge/intel/pineview/Kconfig -@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE - config DOMAIN_RESOURCE_32BIT_LIMIT - default 0xfec00000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig -index 9972a43da0..fe4ac5106c 100644 ---- a/src/northbridge/intel/sandybridge/Kconfig -+++ b/src/northbridge/intel/sandybridge/Kconfig -@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX - default 2 if IGD_DEFAULT_UMA_SIZE_96MB - default 3 if IGD_DEFAULT_UMA_SIZE_128MB - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 646af3510b..069fa0244d 100644 ---- a/src/northbridge/intel/x4x/Kconfig -+++ b/src/northbridge/intel/x4x/Kconfig -@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE - config FIXED_EPBAR_MMIO_BASE - default 0xfed19000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - endif --- -2.47.3 - diff --git a/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch deleted file mode 100644 index 28df4126..00000000 --- a/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch +++ /dev/null @@ -1,708 +0,0 @@ -From d83715448c0f7467ddf94e5c0a53560c5ff3b86b Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Mon, 30 Sep 2024 20:44:38 -0400 -Subject: [PATCH 25/51] mb/dell: Add Optiplex 780 MT (x4x/ICH10) - -Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/optiplex_780/Kconfig | 40 ++++ - src/mainboard/dell/optiplex_780/Kconfig.name | 4 + - src/mainboard/dell/optiplex_780/Makefile.mk | 10 + - src/mainboard/dell/optiplex_780/acpi/ec.asl | 5 + - .../dell/optiplex_780/acpi/ich10_pci_irqs.asl | 32 ++++ - .../dell/optiplex_780/acpi/superio.asl | 18 ++ - .../dell/optiplex_780/board_info.txt | 6 + - src/mainboard/dell/optiplex_780/cmos.default | 8 + - src/mainboard/dell/optiplex_780/cmos.layout | 72 ++++++++ - src/mainboard/dell/optiplex_780/cstates.c | 8 + - src/mainboard/dell/optiplex_780/devicetree.cb | 63 +++++++ - src/mainboard/dell/optiplex_780/dsdt.asl | 26 +++ - .../dell/optiplex_780/gma-mainboard.ads | 16 ++ - .../optiplex_780/variants/780_mt/data.vbt | Bin 0 -> 1917 bytes - .../optiplex_780/variants/780_mt/early_init.c | 12 ++ - .../dell/optiplex_780/variants/780_mt/gpio.c | 174 ++++++++++++++++++ - .../optiplex_780/variants/780_mt/hda_verb.c | 26 +++ - .../variants/780_mt/overridetree.cb | 10 + - 18 files changed, 530 insertions(+) - create mode 100644 src/mainboard/dell/optiplex_780/Kconfig - create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name - create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk - create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl - create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl - create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl - create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt - create mode 100644 src/mainboard/dell/optiplex_780/cmos.default - create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout - create mode 100644 src/mainboard/dell/optiplex_780/cstates.c - create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb - create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl - create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb - -diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig -new file mode 100644 -index 0000000000..2d06c75c9a ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/Kconfig -@@ -0,0 +1,40 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_DELL_OPTIPLEX_780_COMMON -+ def_bool n -+ select BOARD_ROMSIZE_KB_8192 -+ select CPU_INTEL_SOCKET_LGA775 -+ select DRIVERS_I2C_CK505 -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ select INTEL_GMA_HAVE_VBT -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_USES_IFD_GBE_REGION -+ select NORTHBRIDGE_INTEL_X4X -+ select PCIEXP_ASPM -+ select PCIEXP_CLK_PM -+ select SOUTHBRIDGE_INTEL_I82801JX -+ -+config BOARD_DELL_OPTIPLEX_780_MT -+ select BOARD_DELL_OPTIPLEX_780_COMMON -+ -+if BOARD_DELL_OPTIPLEX_780_COMMON -+ -+config VGA_BIOS_ID -+ default "8086,2e22" -+ -+config MAINBOARD_DIR -+ default "dell/optiplex_780" -+ -+config MAINBOARD_PART_NUMBER -+ default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT -+ -+config OVERRIDE_DEVICETREE -+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -+ -+config VARIANT_DIR -+ default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT -+ -+endif # BOARD_DELL_OPTIPLEX_780_COMMON -diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name -new file mode 100644 -index 0000000000..db7f2e8fe3 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/Kconfig.name -@@ -0,0 +1,4 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_DELL_OPTIPLEX_780_MT -+ bool "OptiPlex 780 MT" -diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk -new file mode 100644 -index 0000000000..d462995d75 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/Makefile.mk -@@ -0,0 +1,10 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+ramstage-y += cstates.c -+romstage-y += variants/$(VARIANT_DIR)/gpio.c -+ -+bootblock-y += variants/$(VARIANT_DIR)/early_init.c -+romstage-y += variants/$(VARIANT_DIR)/early_init.c -+ -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c -diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl -new file mode 100644 -index 0000000000..479296cb76 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl -@@ -0,0 +1,5 @@ -+/* SPDX-License-Identifier: CC-PDDC */ -+ -+/* Please update the license if adding licensable material. */ -+ -+/* dummy */ -diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl -new file mode 100644 -index 0000000000..b7588dcc41 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl -@@ -0,0 +1,32 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+/* This is board specific information: -+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 -+ */ -+ -+If (PICM) { -+ Return (Package() { -+ /* PCI slot */ -+ Package() { 0x0001ffff, 0, 0, 0x14}, -+ Package() { 0x0001ffff, 1, 0, 0x15}, -+ Package() { 0x0001ffff, 2, 0, 0x16}, -+ Package() { 0x0001ffff, 3, 0, 0x17}, -+ -+ Package() { 0x0002ffff, 0, 0, 0x15}, -+ Package() { 0x0002ffff, 1, 0, 0x16}, -+ Package() { 0x0002ffff, 2, 0, 0x17}, -+ Package() { 0x0002ffff, 3, 0, 0x14}, -+ }) -+} Else { -+ Return (Package() { -+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, -+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, -+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, -+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, -+ -+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, -+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, -+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, -+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, -+ }) -+} -diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl -new file mode 100644 -index 0000000000..9f3900b86c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl -@@ -0,0 +1,18 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#undef SUPERIO_DEV -+#undef SUPERIO_PNP_BASE -+#undef IT8720F_SHOW_SP1 -+#undef IT8720F_SHOW_SP2 -+#undef IT8720F_SHOW_EC -+#undef IT8720F_SHOW_KBCK -+#undef IT8720F_SHOW_KBCM -+#undef IT8720F_SHOW_GPIO -+#undef IT8720F_SHOW_CIR -+#define SUPERIO_DEV SIO0 -+#define SUPERIO_PNP_BASE 0x2e -+#define IT8720F_SHOW_EC 1 -+#define IT8720F_SHOW_KBCK 1 -+#define IT8720F_SHOW_KBCM 1 -+#define IT8720F_SHOW_GPIO 1 -+#include -diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt -new file mode 100644 -index 0000000000..aaf657b583 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/board_info.txt -@@ -0,0 +1,6 @@ -+Category: desktop -+Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1 -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default -new file mode 100644 -index 0000000000..23f0e55f3e ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/cmos.default -@@ -0,0 +1,8 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -+nmi=Enable -+sata_mode=AHCI -+gfx_uma_size=64M -diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout -new file mode 100644 -index 0000000000..9f5012adb4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/cmos.layout -@@ -0,0 +1,72 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+# coreboot config options: southbridge -+408 1 e 10 sata_mode -+409 2 e 7 power_on_after_fail -+411 1 e 1 nmi -+ -+# coreboot config options: cpu -+ -+# coreboot config options: northbridge -+432 4 e 11 gfx_uma_size -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+2 0 Enable -+2 1 Disable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+10 0 AHCI -+10 1 Compatible -+11 1 4M -+11 2 8M -+11 3 16M -+11 4 32M -+11 5 48M -+11 6 64M -+11 7 128M -+11 8 256M -+11 9 96M -+11 10 160M -+11 11 224M -+11 12 352M -+ -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 983 984 -diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c -new file mode 100644 -index 0000000000..4adf0edc63 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/cstates.c -@@ -0,0 +1,8 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+int get_cst_entries(const acpi_cstate_t **entries) -+{ -+ return 0; -+} -diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb -new file mode 100644 -index 0000000000..95e3bd517c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/devicetree.cb -@@ -0,0 +1,63 @@ -+# SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/x4x -+ device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster -+ device domain 0 on -+ ops x4x_pci_domain_ops # PCI domain -+ subsystemid 0x8086 0x0028 inherit -+ device pci 0.0 on end # Host Bridge -+ device pci 1.0 on end # PCIe x16 2.0 slot -+ device pci 2.0 on end # Integrated graphics controller -+ device pci 2.1 on end # Integrated graphics controller 2 -+ device pci 3.0 off end # ME -+ device pci 3.1 off end # ME -+ chip southbridge/intel/i82801jx # ICH10 -+ register "gpe0_en" = "0x40" -+ -+ # Set AHCI mode. -+ register "sata_port_map" = "0x3f" -+ register "sata_clock_request" = "1" -+ -+ # Enable PCIe ports 0,1 as slots. -+ register "pcie_slot_implemented" = "0x3" -+ -+ device pci 19.0 on end # GBE -+ device pci 1a.0 on end # USB -+ device pci 1a.1 on end # USB -+ device pci 1a.2 on end # USB -+ device pci 1a.7 on end # USB -+ device pci 1b.0 on end # Audio -+ device pci 1c.0 off end # PCIe 1 -+ device pci 1c.1 off end # PCIe 2 -+ device pci 1c.2 off end # PCIe 3 -+ device pci 1c.3 off end # PCIe 4 -+ device pci 1c.4 off end # PCIe 5 -+ device pci 1c.5 off end # PCIe 6 -+ device pci 1d.0 on end # USB -+ device pci 1d.1 on end # USB -+ device pci 1d.2 on end # USB -+ device pci 1d.7 on end # USB -+ device pci 1e.0 on end # PCI bridge -+ device pci 1f.0 on end # LPC bridge -+ device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5) -+ device pci 1f.3 on # SMBus -+ chip drivers/i2c/ck505 # IDT CV194 -+ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff }" -+ register "regs" = "{ 0x15, 0x82, 0xff, 0xff, -+ 0xff, 0x00, 0x00, 0x95, -+ 0x00, 0x65, 0x7d, 0x56, -+ 0x13, 0xc0, 0x00, 0x07, -+ 0x01, 0x0a, 0x64 }" -+ device i2c 69 on end -+ end -+ end -+ device pci 1f.4 off end -+ device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode) -+ device pci 1f.6 off end # Thermal Subsystem -+ end -+ end -+end -diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl -new file mode 100644 -index 0000000000..9ad70469de ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/dsdt.asl -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20090811 // OEM revision -+) -+{ -+ #include -+ -+ OSYS = 2002 -+ // global NVS and variables -+ #include -+ -+ Device (\_SB.PCI0) -+ { -+ #include -+ #include -+ } -+ -+ #include -+} -diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads -new file mode 100644 -index 0000000000..bc81cf4a40 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads -@@ -0,0 +1,16 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ (DP2, -+ Analog, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..fefda9d6f226b88ab67c5b044de30a707df22fbf -GIT binary patch -literal 1917 -zcmd6nO>7%Q6vzLwGv0Mv$FUpJ*ik4iQd_wnX*X`M0y3~p?8a$~>ZXxZMU`4dc9RGb -zTXq_i1Bwd~aNr{c4i)r(goF^M-nek+sY0sMa}Sk>xFFy_FTEfX^Y+7unt+OgkeJbX -zznS;`v-5V=o{ZwwmnN>gY?}>{`7^JBpP$l`EBIwbi0*k&aU)n@v)E -znI_A1T57efS5MGNN5_ut -zt=x`G)EjR#mlhURC^2!A3p33TcBg4-d8JyTiF&hfk}|a#&Dfe2%~V^}=4!QavNzBh -z0Pae^5`gfb?7Q)c(LsP)8 -zQy)2gwgG1S^>aw&0D}Z+-SCcJJF;s)yXJeQ|4N{SU?$I`#$HZa9dWBuxA$6X;VK;%W?Y>I;0P`|*vwAK$S(VB2JSq6g4n -z>oEf8XCt;_Y-iYBWz#3T9EmJ -z2x?*GPeN%?=Fj3+fv~4%I(nv~XF7VOqi5RsAt%13JtW>q=<<;0IkLPSUGL%_1h)2kjaZzuV;`43yCV;I=#Jcyyw@xKE8GGX39@am|0GKhH` -zawsKv^FvHqm+c8*FfFsu??w)Oed@;Mg~21%rCZ%d{x!>-zmv4AyWL1E -xfz+CGUnQ7Y^TD}&c_cQRYlBC+`?m?k6Nuw??s04gg4@4`<@FO{XEbO( -+ -+void mb_get_spd_map(u8 spd_map[4]) -+{ -+ // BTX form factor -+ spd_map[0] = 0x53; -+ spd_map[1] = 0x52; -+ spd_map[2] = 0x51; -+ spd_map[3] = 0x50; -+} -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c -new file mode 100644 -index 0000000000..9993f17c55 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c -@@ -0,0 +1,174 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_NATIVE, -+ .gpio1 = GPIO_MODE_NATIVE, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_GPIO, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_NATIVE, -+ .gpio8 = GPIO_MODE_NATIVE, -+ .gpio9 = GPIO_MODE_GPIO, -+ .gpio10 = GPIO_MODE_GPIO, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_NATIVE, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_NATIVE, -+ .gpio18 = GPIO_MODE_GPIO, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_GPIO, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_GPIO, -+ .gpio31 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio5 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio9 = GPIO_DIR_OUTPUT, -+ .gpio10 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio18 = GPIO_DIR_OUTPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio20 = GPIO_DIR_OUTPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_OUTPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+ .gpio30 = GPIO_DIR_INPUT, -+ .gpio31 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio9 = GPIO_LEVEL_HIGH, -+ .gpio18 = GPIO_LEVEL_HIGH, -+ .gpio20 = GPIO_LEVEL_HIGH, -+ .gpio28 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio13 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_GPIO, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_NATIVE, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_NATIVE, -+ .gpio52 = GPIO_MODE_NATIVE, -+ .gpio53 = GPIO_MODE_NATIVE, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_GPIO, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio32 = GPIO_DIR_INPUT, -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_INPUT, -+ .gpio35 = GPIO_DIR_OUTPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_OUTPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio56 = GPIO_DIR_OUTPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio35 = GPIO_LEVEL_LOW, -+ .gpio49 = GPIO_LEVEL_HIGH, -+ .gpio56 = GPIO_LEVEL_HIGH, -+ .gpio60 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_NATIVE, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_NATIVE, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_NATIVE, -+ .gpio69 = GPIO_MODE_NATIVE, -+ .gpio70 = GPIO_MODE_NATIVE, -+ .gpio71 = GPIO_MODE_NATIVE, -+ .gpio72 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio72 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ }, -+}; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c -new file mode 100644 -index 0000000000..4158bcf899 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ /* coreboot specific header */ -+ 0x11d4194a, /* Analog Devices AD1984A */ -+ 0xbfd40000, /* Subsystem ID */ -+ 10, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ AZALIA_PIN_CFG(0, 0x11, 0x032140f0), -+ AZALIA_PIN_CFG(0, 0x12, 0x21214010), -+ AZALIA_PIN_CFG(0, 0x13, 0x901701f0), -+ AZALIA_PIN_CFG(0, 0x14, 0x03a190f0), -+ AZALIA_PIN_CFG(0, 0x15, 0xb7a70121), -+ AZALIA_PIN_CFG(0, 0x16, 0x9933012e), -+ AZALIA_PIN_CFG(0, 0x17, 0x97a601f0), -+ AZALIA_PIN_CFG(0, 0x1a, 0x90f301f0), -+ AZALIA_PIN_CFG(0, 0x1b, 0x014510f0), -+ AZALIA_PIN_CFG(0, 0x1c, 0x21a19020), -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb -new file mode 100644 -index 0000000000..555b1c1f5c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb -@@ -0,0 +1,10 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/x4x -+ device domain 0 on -+ chip southbridge/intel/i82801jx -+ device pci 1c.0 on end # PCIe 1 -+ device pci 1c.1 on end # PCIe 2 -+ end -+ end -+end --- -2.47.3 - diff --git a/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch new file mode 100644 index 00000000..8810cdd7 --- /dev/null +++ b/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch @@ -0,0 +1,326 @@ +From e1ed4a9739d2cfc691d71c165d984ef171a2ea76 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Wed, 30 Oct 2024 20:55:25 -0600 +Subject: [PATCH 25/51] mb/dell/optiplex_780: Add USFF variant + +Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/optiplex_780/Kconfig | 5 + + src/mainboard/dell/optiplex_780/Kconfig.name | 3 + + .../optiplex_780/variants/780_usff/data.vbt | Bin 0 -> 1917 bytes + .../variants/780_usff/early_init.c | 9 + + .../optiplex_780/variants/780_usff/gpio.c | 166 ++++++++++++++++++ + .../optiplex_780/variants/780_usff/hda_verb.c | 26 +++ + .../variants/780_usff/overridetree.cb | 10 ++ + 7 files changed, 219 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb + +diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig +index 2d06c75c9a..fc649e35d5 100644 +--- a/src/mainboard/dell/optiplex_780/Kconfig ++++ b/src/mainboard/dell/optiplex_780/Kconfig +@@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON + config BOARD_DELL_OPTIPLEX_780_MT + select BOARD_DELL_OPTIPLEX_780_COMMON + ++config BOARD_DELL_OPTIPLEX_780_USFF ++ select BOARD_DELL_OPTIPLEX_780_COMMON ++ + if BOARD_DELL_OPTIPLEX_780_COMMON + + config VGA_BIOS_ID +@@ -30,11 +33,13 @@ config MAINBOARD_DIR + + config MAINBOARD_PART_NUMBER + default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT ++ default "OptiPlex 780 USFF" if BOARD_DELL_OPTIPLEX_780_USFF + + config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + + config VARIANT_DIR + default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT ++ default "780_usff" if BOARD_DELL_OPTIPLEX_780_USFF + + endif # BOARD_DELL_OPTIPLEX_780_COMMON +diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name +index db7f2e8fe3..bc84c82a79 100644 +--- a/src/mainboard/dell/optiplex_780/Kconfig.name ++++ b/src/mainboard/dell/optiplex_780/Kconfig.name +@@ -2,3 +2,6 @@ + + config BOARD_DELL_OPTIPLEX_780_MT + bool "OptiPlex 780 MT" ++ ++config BOARD_DELL_OPTIPLEX_780_USFF ++ bool "OptiPlex 780 USFF" +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..dbd764f285ed18f7ee9c54bc777560138bd9b5f7 +GIT binary patch +literal 1917 +zcmd6nO>7%Q6vzLwGv3{}j$^l`v7@w1q*9sEq+2(b3K>`@c5#TSx@iP+W+B10OwbsGtX=N(gc4jSGjKDkP+yIUo^nsel8$^ny^9H?td8Ra=EiCEn=G +z@6DV4?!2AdojnUv^Rirgvs$heXUkGs9S+{Jc2WPhP0buTak^BTFP@&N9-E$(UtuSX +zS{r`=b+EX|Ig`2a*^5oDdG>8jE-1BBxs`*jgrf_sj_fP;%L|PwURRcCFBMCroNRQv +zmp$2TUhc}qJMB(u#jDG@x6(N85thC4%Z=8hiN}lj&zb2~``u3C;?lCrPQOTnInFqB +zhvdwqWv?lxTb=fVEH;~RPHDPw&g*&|s$pU7!7x2mLBtAF!g>K`zPnkx!DpPHuk6{_zc*0qi7)Aet$T +z1ks@8hWS#+6cI5)j1oD86{5PX8Zu2(^OC6M`xo)V)Ow=U6P12c +z=U0uNC9T9v{)-|#h(mSX*hSA8)ZeocL7l4J&!{RSO{6~oTtyn535j!RQh#GA*wTF8 +zvasRbO~d!?*FbM3K`W?lHx=v*(jiARIhWyh4^io|;n?@1H>uqJy>0sjV-Dt)_=%bE +zgNO3D@uE5m+7aqi?Y8b+inye%Z=HUmgBtaZ3Lc%OLt+bo+)5BjVwT<{mxT`nde$vb +zV99s{>`r76L#Hr6XW6r|>HT47I`**Q#Vu0QW!^VP-9S{xXzpq_zS#9k-;aXz?b+S!Ne$Kkk6dq&Hj-x+kx1W-4#E&beDT*S)=&NoSE?<-w!G@~aW()0ZN4O&=Q+nZa)p%Vd$k-_$a= +T#w3FFBiyj ++ ++void mb_get_spd_map(u8 spd_map[4]) ++{ ++ spd_map[0] = 0x50; ++ spd_map[2] = 0x52; ++} +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c +new file mode 100644 +index 0000000000..389f4077d7 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c +@@ -0,0 +1,166 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_NATIVE, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_GPIO, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_NATIVE, ++ .gpio8 = GPIO_MODE_NATIVE, ++ .gpio9 = GPIO_MODE_GPIO, ++ .gpio10 = GPIO_MODE_GPIO, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_NATIVE, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_NATIVE, ++ .gpio18 = GPIO_MODE_GPIO, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_GPIO, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio5 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio9 = GPIO_DIR_OUTPUT, ++ .gpio10 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio18 = GPIO_DIR_OUTPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio20 = GPIO_DIR_OUTPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_INPUT, ++ .gpio31 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio9 = GPIO_LEVEL_HIGH, ++ .gpio18 = GPIO_LEVEL_HIGH, ++ .gpio20 = GPIO_LEVEL_HIGH, ++ .gpio28 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio13 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_GPIO, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_NATIVE, ++ .gpio52 = GPIO_MODE_NATIVE, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio32 = GPIO_DIR_INPUT, ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio35 = GPIO_DIR_OUTPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio56 = GPIO_DIR_OUTPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio35 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_HIGH, ++ .gpio56 = GPIO_LEVEL_HIGH, ++ .gpio60 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio72 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio72 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ }, ++}; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c +new file mode 100644 +index 0000000000..c94e06b156 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header */ ++ 0x11d4194a, /* Analog Devices AD1984A */ ++ 0x10280420, /* Subsystem ID */ ++ 10, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ AZALIA_PIN_CFG(0, 0x11, 0x02214040), ++ AZALIA_PIN_CFG(0, 0x12, 0x01014010), ++ AZALIA_PIN_CFG(0, 0x13, 0x991301f0), ++ AZALIA_PIN_CFG(0, 0x14, 0x02a19020), ++ AZALIA_PIN_CFG(0, 0x15, 0x01813030), ++ AZALIA_PIN_CFG(0, 0x16, 0x413301f0), ++ AZALIA_PIN_CFG(0, 0x17, 0x41a601f0), ++ AZALIA_PIN_CFG(0, 0x1a, 0x41f301f0), ++ AZALIA_PIN_CFG(0, 0x1b, 0x414501f0), ++ AZALIA_PIN_CFG(0, 0x1c, 0x413301f0), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb +new file mode 100644 +index 0000000000..555b1c1f5c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb +@@ -0,0 +1,10 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device domain 0 on ++ chip southbridge/intel/i82801jx ++ device pci 1c.0 on end # PCIe 1 ++ device pci 1c.1 on end # PCIe 2 ++ end ++ end ++end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch deleted file mode 100644 index 8948aee7..00000000 --- a/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch +++ /dev/null @@ -1,326 +0,0 @@ -From 3a5fa257c1b74c6e9e3556147114fc7691dc9e49 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Wed, 30 Oct 2024 20:55:25 -0600 -Subject: [PATCH 26/51] mb/dell/optiplex_780: Add USFF variant - -Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/optiplex_780/Kconfig | 5 + - src/mainboard/dell/optiplex_780/Kconfig.name | 3 + - .../optiplex_780/variants/780_usff/data.vbt | Bin 0 -> 1917 bytes - .../variants/780_usff/early_init.c | 9 + - .../optiplex_780/variants/780_usff/gpio.c | 166 ++++++++++++++++++ - .../optiplex_780/variants/780_usff/hda_verb.c | 26 +++ - .../variants/780_usff/overridetree.cb | 10 ++ - 7 files changed, 219 insertions(+) - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb - -diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig -index 2d06c75c9a..fc649e35d5 100644 ---- a/src/mainboard/dell/optiplex_780/Kconfig -+++ b/src/mainboard/dell/optiplex_780/Kconfig -@@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON - config BOARD_DELL_OPTIPLEX_780_MT - select BOARD_DELL_OPTIPLEX_780_COMMON - -+config BOARD_DELL_OPTIPLEX_780_USFF -+ select BOARD_DELL_OPTIPLEX_780_COMMON -+ - if BOARD_DELL_OPTIPLEX_780_COMMON - - config VGA_BIOS_ID -@@ -30,11 +33,13 @@ config MAINBOARD_DIR - - config MAINBOARD_PART_NUMBER - default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT -+ default "OptiPlex 780 USFF" if BOARD_DELL_OPTIPLEX_780_USFF - - config OVERRIDE_DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" - - config VARIANT_DIR - default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT -+ default "780_usff" if BOARD_DELL_OPTIPLEX_780_USFF - - endif # BOARD_DELL_OPTIPLEX_780_COMMON -diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name -index db7f2e8fe3..bc84c82a79 100644 ---- a/src/mainboard/dell/optiplex_780/Kconfig.name -+++ b/src/mainboard/dell/optiplex_780/Kconfig.name -@@ -2,3 +2,6 @@ - - config BOARD_DELL_OPTIPLEX_780_MT - bool "OptiPlex 780 MT" -+ -+config BOARD_DELL_OPTIPLEX_780_USFF -+ bool "OptiPlex 780 USFF" -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..dbd764f285ed18f7ee9c54bc777560138bd9b5f7 -GIT binary patch -literal 1917 -zcmd6nO>7%Q6vzLwGv3{}j$^l`v7@w1q*9sEq+2(b3K>`@c5#TSx@iP+W+B10OwbsGtX=N(gc4jSGjKDkP+yIUo^nsel8$^ny^9H?td8Ra=EiCEn=G -z@6DV4?!2AdojnUv^Rirgvs$heXUkGs9S+{Jc2WPhP0buTak^BTFP@&N9-E$(UtuSX -zS{r`=b+EX|Ig`2a*^5oDdG>8jE-1BBxs`*jgrf_sj_fP;%L|PwURRcCFBMCroNRQv -zmp$2TUhc}qJMB(u#jDG@x6(N85thC4%Z=8hiN}lj&zb2~``u3C;?lCrPQOTnInFqB -zhvdwqWv?lxTb=fVEH;~RPHDPw&g*&|s$pU7!7x2mLBtAF!g>K`zPnkx!DpPHuk6{_zc*0qi7)Aet$T -z1ks@8hWS#+6cI5)j1oD86{5PX8Zu2(^OC6M`xo)V)Ow=U6P12c -z=U0uNC9T9v{)-|#h(mSX*hSA8)ZeocL7l4J&!{RSO{6~oTtyn535j!RQh#GA*wTF8 -zvasRbO~d!?*FbM3K`W?lHx=v*(jiARIhWyh4^io|;n?@1H>uqJy>0sjV-Dt)_=%bE -zgNO3D@uE5m+7aqi?Y8b+inye%Z=HUmgBtaZ3Lc%OLt+bo+)5BjVwT<{mxT`nde$vb -zV99s{>`r76L#Hr6XW6r|>HT47I`**Q#Vu0QW!^VP-9S{xXzpq_zS#9k-;aXz?b+S!Ne$Kkk6dq&Hj-x+kx1W-4#E&beDT*S)=&NoSE?<-w!G@~aW()0ZN4O&=Q+nZa)p%Vd$k-_$a= -T#w3FFBiyj -+ -+void mb_get_spd_map(u8 spd_map[4]) -+{ -+ spd_map[0] = 0x50; -+ spd_map[2] = 0x52; -+} -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c -new file mode 100644 -index 0000000000..389f4077d7 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c -@@ -0,0 +1,166 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_NATIVE, -+ .gpio1 = GPIO_MODE_NATIVE, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_GPIO, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_NATIVE, -+ .gpio8 = GPIO_MODE_NATIVE, -+ .gpio9 = GPIO_MODE_GPIO, -+ .gpio10 = GPIO_MODE_GPIO, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_NATIVE, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_NATIVE, -+ .gpio18 = GPIO_MODE_GPIO, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_GPIO, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_GPIO, -+ .gpio31 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio5 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio9 = GPIO_DIR_OUTPUT, -+ .gpio10 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio18 = GPIO_DIR_OUTPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio20 = GPIO_DIR_OUTPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_OUTPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+ .gpio30 = GPIO_DIR_INPUT, -+ .gpio31 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio9 = GPIO_LEVEL_HIGH, -+ .gpio18 = GPIO_LEVEL_HIGH, -+ .gpio20 = GPIO_LEVEL_HIGH, -+ .gpio28 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio13 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_GPIO, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_NATIVE, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_NATIVE, -+ .gpio52 = GPIO_MODE_NATIVE, -+ .gpio53 = GPIO_MODE_NATIVE, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_GPIO, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio32 = GPIO_DIR_INPUT, -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_INPUT, -+ .gpio35 = GPIO_DIR_OUTPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_OUTPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio56 = GPIO_DIR_OUTPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio35 = GPIO_LEVEL_LOW, -+ .gpio49 = GPIO_LEVEL_HIGH, -+ .gpio56 = GPIO_LEVEL_HIGH, -+ .gpio60 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio72 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio72 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ }, -+}; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c -new file mode 100644 -index 0000000000..c94e06b156 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ /* coreboot specific header */ -+ 0x11d4194a, /* Analog Devices AD1984A */ -+ 0x10280420, /* Subsystem ID */ -+ 10, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ AZALIA_PIN_CFG(0, 0x11, 0x02214040), -+ AZALIA_PIN_CFG(0, 0x12, 0x01014010), -+ AZALIA_PIN_CFG(0, 0x13, 0x991301f0), -+ AZALIA_PIN_CFG(0, 0x14, 0x02a19020), -+ AZALIA_PIN_CFG(0, 0x15, 0x01813030), -+ AZALIA_PIN_CFG(0, 0x16, 0x413301f0), -+ AZALIA_PIN_CFG(0, 0x17, 0x41a601f0), -+ AZALIA_PIN_CFG(0, 0x1a, 0x41f301f0), -+ AZALIA_PIN_CFG(0, 0x1b, 0x414501f0), -+ AZALIA_PIN_CFG(0, 0x1c, 0x413301f0), -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb -new file mode 100644 -index 0000000000..555b1c1f5c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb -@@ -0,0 +1,10 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/x4x -+ device domain 0 on -+ chip southbridge/intel/i82801jx -+ device pci 1c.0 on end # PCIe 1 -+ device pci 1c.1 on end # PCIe 2 -+ end -+ end -+end --- -2.47.3 - diff --git a/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch new file mode 100644 index 00000000..cc8f90d5 --- /dev/null +++ b/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch @@ -0,0 +1,33 @@ +From 55a33798ec9aadd38222f736d4c1b77f9902f3f4 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 6 Jan 2025 01:53:53 +0000 +Subject: [PATCH 26/51] src/intel/x4x: Disable stack overflow debug + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/x4x/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig +index 069fa0244d..8c70344846 100644 +--- a/src/northbridge/intel/x4x/Kconfig ++++ b/src/northbridge/intel/x4x/Kconfig +@@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER + int + default 256 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + # This number must be equal or lower than what's reported in ACPI PCI _CRS + config DOMAIN_RESOURCE_32BIT_LIMIT + default 0xfec00000 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch new file mode 100644 index 00000000..d1ac34e2 --- /dev/null +++ b/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch @@ -0,0 +1,42 @@ +From 56a581aeadb4efafc62efaba742b06b25852ccf8 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 22 Apr 2025 10:21:59 +0100 +Subject: [PATCH 27/51] hp/8300cmt: remove xhci_overcurrent_mapping + +No longer needed, as per the following commit: + +commit a3d1e6c4806e6c0e2e744be3a03fce12f21778d1 +Author: Keith Hui +Date: Tue Dec 31 18:19:31 2024 -0500 + + sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping + +Removing this from the devicetree also allows the +board to compile, otherwise an error is thrown: + +build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:10: error: 'const struct southbridge_intel_bd82x6x_config' has no member named 'xhci_overcurrent_mapping' + 147 | .xhci_overcurrent_mapping = 0x00000c03, + | ^~~~~~~~~~~~~~~~~~~~~~~~ +build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:37: error: excess elements in struct initializer [-Werror] + 147 | .xhci_overcurrent_mapping = 0x00000c03, + +Signed-off-by: Leah Rowe +--- + src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb +index 3d21739b72..3a0b6d5c59 100644 +--- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb +@@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" +- register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 0, 0 }, +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch deleted file mode 100644 index 1cbae3bf..00000000 --- a/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 5573eeadf45023d49f09606c6219004e20ba4b3c Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 6 Jan 2025 01:53:53 +0000 -Subject: [PATCH 27/51] src/intel/x4x: Disable stack overflow debug - -Signed-off-by: Leah Rowe ---- - src/northbridge/intel/x4x/Kconfig | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 069fa0244d..8c70344846 100644 ---- a/src/northbridge/intel/x4x/Kconfig -+++ b/src/northbridge/intel/x4x/Kconfig -@@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER - int - default 256 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - # This number must be equal or lower than what's reported in ACPI PCI _CRS - config DOMAIN_RESOURCE_32BIT_LIMIT - default 0xfec00000 --- -2.47.3 - diff --git a/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch b/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch new file mode 100644 index 00000000..de8bc790 --- /dev/null +++ b/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch @@ -0,0 +1,47 @@ +From 4470d8fb6760173090c43e6a82a8865f5917dd9b Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Wed, 11 Dec 2024 01:06:01 +0000 +Subject: [PATCH 28/51] dell/3050micro: disable nvme hotplug + +in my testing, when running my 3050micro for a few days, +the nvme would sometimes randomly rename. + +e.g. nvme0n1 renamed to nvme0n2 + +this might cause crashes in linux, if booting only from the +nvme. in my case, i was booting from mdraid (sata+nvme) and +every few days, the nvme would rename at least once, causing +my RAID to become unsynced. since i'm using RAID1, this was +OK and I could simply re-sync the array, but this is quite +precarious indeed. if you're using raid0, that will potentially +corrupt your RAID array indefinitely. + +this same issue manifested on the T480/T480 thinkpads, and +S3 resume would break because of that, when booting from nvme, +because the nvme would be "unplugged" and appear to linux as a +new device (the one that you booted from). + +the fix there was to disable hotplugging on that pci-e slot +for the nvme, so apply the same fix here for 3050 micro + +Signed-off-by: Leah Rowe +--- + .../dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb +index c5f1749b2c..ff48a8121a 100644 +--- a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb ++++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb +@@ -46,7 +46,7 @@ chip soc/intel/skylake + register "PcieRpAdvancedErrorReporting[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" + register "PcieRpClkSrcNumber[20]" = "3" +- register "PcieRpHotPlug[20]" = "1" ++ register "PcieRpHotPlug[20]" = "0" + end + + end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch deleted file mode 100644 index d42b03fc..00000000 --- a/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 2973ad1738fb6c1ebd2a92d008e1cbd39c74abb2 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 22 Apr 2025 10:21:59 +0100 -Subject: [PATCH 28/51] hp/8300cmt: remove xhci_overcurrent_mapping - -No longer needed, as per the following commit: - -commit a3d1e6c4806e6c0e2e744be3a03fce12f21778d1 -Author: Keith Hui -Date: Tue Dec 31 18:19:31 2024 -0500 - - sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping - -Removing this from the devicetree also allows the -board to compile, otherwise an error is thrown: - -build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:10: error: 'const struct southbridge_intel_bd82x6x_config' has no member named 'xhci_overcurrent_mapping' - 147 | .xhci_overcurrent_mapping = 0x00000c03, - | ^~~~~~~~~~~~~~~~~~~~~~~~ -build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:37: error: excess elements in struct initializer [-Werror] - 147 | .xhci_overcurrent_mapping = 0x00000c03, - -Signed-off-by: Leah Rowe ---- - src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -index 3d21739b72..3a0b6d5c59 100644 ---- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -@@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - register "superspeed_capable_ports" = "0x0000000f" -- register "xhci_overcurrent_mapping" = "0x00000c03" - register "xhci_switchable_ports" = "0x0000000f" - register "usb_port_config" = "{ - { 1, 0, 0 }, --- -2.47.3 - diff --git a/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch b/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch deleted file mode 100644 index fcfdf827..00000000 --- a/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch +++ /dev/null @@ -1,47 +0,0 @@ -From ff57e763d1f966584ac9b68fa1a1f204626a577b Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Wed, 11 Dec 2024 01:06:01 +0000 -Subject: [PATCH 29/51] dell/3050micro: disable nvme hotplug - -in my testing, when running my 3050micro for a few days, -the nvme would sometimes randomly rename. - -e.g. nvme0n1 renamed to nvme0n2 - -this might cause crashes in linux, if booting only from the -nvme. in my case, i was booting from mdraid (sata+nvme) and -every few days, the nvme would rename at least once, causing -my RAID to become unsynced. since i'm using RAID1, this was -OK and I could simply re-sync the array, but this is quite -precarious indeed. if you're using raid0, that will potentially -corrupt your RAID array indefinitely. - -this same issue manifested on the T480/T480 thinkpads, and -S3 resume would break because of that, when booting from nvme, -because the nvme would be "unplugged" and appear to linux as a -new device (the one that you booted from). - -the fix there was to disable hotplugging on that pci-e slot -for the nvme, so apply the same fix here for 3050 micro - -Signed-off-by: Leah Rowe ---- - .../dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb -index c5f1749b2c..ff48a8121a 100644 ---- a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb -+++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb -@@ -46,7 +46,7 @@ chip soc/intel/skylake - register "PcieRpAdvancedErrorReporting[20]" = "1" - register "PcieRpLtrEnable[20]" = "true" - register "PcieRpClkSrcNumber[20]" = "3" -- register "PcieRpHotPlug[20]" = "1" -+ register "PcieRpHotPlug[20]" = "0" - end - - end --- -2.47.3 - diff --git a/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch new file mode 100644 index 00000000..4f127867 --- /dev/null +++ b/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch @@ -0,0 +1,61 @@ +From f6b82e0483d7f9e47f465bb4884b199cfd9fe04b Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 6 Jan 2025 01:36:23 +0000 +Subject: [PATCH 29/51] src/intel/skylake: Disable stack overflow debug options + +The option was appearing in T480/3050micro configs of lbmk, +after updating on the coreboot/next uprev for 20241206 rev8: + +CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y + +I did some digging. See coreboot commit: + +commit 51cc2bacb6b07279b97e9934d079060475481fb6 +Author: Subrata Banik +Date: Fri Dec 13 13:07:28 2024 +0530 + + soc/intel/pantherlake: Disable stack overflow debug options + +Well now: + +I'm disabling this behaviour on Skylake, for the same +behaviour, because I want as few behaviour changes in general, +as possible, for the rev8 release. + +According to Subrata's patch, which was for Pantherlake, +without this change, stack corruption can occur on verstage +and romstage early on. Please look at that coreboot patch, +referenced above, for clarity. + +I see no harm in disabling this option for Skylake, since +the behaviour that it otherwise enables was not present +before. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/skylake/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig +index c76239936a..f8ff8cfa7a 100644 +--- a/src/soc/intel/skylake/Kconfig ++++ b/src/soc/intel/skylake/Kconfig +@@ -136,6 +136,15 @@ config DCACHE_RAM_SIZE + The size of the cache-as-ram region required during bootblock + and/or romstage. + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + config DCACHE_BSP_STACK_SIZE + hex + default 0x20400 if FSP_USES_CB_STACK +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch new file mode 100644 index 00000000..95c018a0 --- /dev/null +++ b/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch @@ -0,0 +1,36 @@ +From 025eae54ed31b728866db1279a7cd86d7280dc58 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Thu, 26 Dec 2024 19:45:20 +0000 +Subject: [PATCH 30/51] soc/intel/skylake: Don't compress FSP-S + +Build systems like lbmk need to reproducibly insert +certain vendor files on release images. + +Compression isn't always reproducible, and making it +so costs a lot more time than simply disabling compression. + +With this change, the FSP-S module will now be inserted +without compression, which means that there will now be +about 40KB of extra space used in the flash. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/skylake/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig +index f8ff8cfa7a..97354cdaa5 100644 +--- a/src/soc/intel/skylake/Kconfig ++++ b/src/soc/intel/skylake/Kconfig +@@ -15,7 +15,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE + select DRAM_SUPPORT_DDR4 + select DRIVERS_USB_ACPI + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 +- select FSP_COMPRESS_FSP_S_LZ4 ++# select FSP_COMPRESS_FSP_S_LZ4 + select FSP_M_XIP + select GENERIC_GPIO_LIB + select HAVE_FSP_GOP +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0030-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0030-src-intel-skylake-Disable-stack-overflow-debug-optio.patch deleted file mode 100644 index 695a03a7..00000000 --- a/config/coreboot/default/patches/0030-src-intel-skylake-Disable-stack-overflow-debug-optio.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 7c4df892425e076b1d2768f9b99362f58e7872dc Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 6 Jan 2025 01:36:23 +0000 -Subject: [PATCH 30/51] src/intel/skylake: Disable stack overflow debug options - -The option was appearing in T480/3050micro configs of lbmk, -after updating on the coreboot/next uprev for 20241206 rev8: - -CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y - -I did some digging. See coreboot commit: - -commit 51cc2bacb6b07279b97e9934d079060475481fb6 -Author: Subrata Banik -Date: Fri Dec 13 13:07:28 2024 +0530 - - soc/intel/pantherlake: Disable stack overflow debug options - -Well now: - -I'm disabling this behaviour on Skylake, for the same -behaviour, because I want as few behaviour changes in general, -as possible, for the rev8 release. - -According to Subrata's patch, which was for Pantherlake, -without this change, stack corruption can occur on verstage -and romstage early on. Please look at that coreboot patch, -referenced above, for clarity. - -I see no harm in disabling this option for Skylake, since -the behaviour that it otherwise enables was not present -before. - -Signed-off-by: Leah Rowe ---- - src/soc/intel/skylake/Kconfig | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index c76239936a..f8ff8cfa7a 100644 ---- a/src/soc/intel/skylake/Kconfig -+++ b/src/soc/intel/skylake/Kconfig -@@ -136,6 +136,15 @@ config DCACHE_RAM_SIZE - The size of the cache-as-ram region required during bootblock - and/or romstage. - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - config DCACHE_BSP_STACK_SIZE - hex - default 0x20400 if FSP_USES_CB_STACK --- -2.47.3 - diff --git a/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch new file mode 100644 index 00000000..e8bc3470 --- /dev/null +++ b/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch @@ -0,0 +1,78 @@ +From ca198ab68579cee7297c3675b440c0fd78ed7511 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Wed, 18 Dec 2024 02:06:18 +0000 +Subject: [PATCH 31/51] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN + +This is used by lbmk to know where a tb.bin file goes, +when extracting and padding TBT.bin from Lenovo ThunderBolt +firmware updates on T480/T480s and other machines, grabbing +Lenovo update files. + +Not used in any builds, so it's not relevant for ./mk inject + +However, the ThunderBolt firmware is now auto-downloaded on +T480/T480s. This is not inserted, because it doesn't go in +the main flash, but the resulting ROM image can be flashed +on the TB controller's separate flash chip. + +Locations are as follows: + +vendorfiles/t480s/tb.bin +vendorfiles/t480/tb.bin + +This can be used for other affected ThinkPads when they're +added to Libreboot, but note that Lenovo provides different +TB firmware files for each machine. + +Since I assume it's the same TB controller on all of those +machines, I have to wonder: what difference is there between +the various TBT.bin files provided by Lenovo, and how do they +differ in terms of actual flashed configuration? + +We simply flash the padded TBT.bin when updating the firmware, +flashing externally. That's what this patch is for, so that +lbmk can auto-download them. + +Signed-off-by: Leah Rowe +--- + src/mainboard/lenovo/Kconfig | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig +index 2ffbaab85f..512b326381 100644 +--- a/src/mainboard/lenovo/Kconfig ++++ b/src/mainboard/lenovo/Kconfig +@@ -18,4 +18,30 @@ config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + ++config LENOVO_TBFW_BIN ++ string "Lenovo ThunderBolt firmware bin file" ++ default "" ++ help ++ ThunderBolt firmware for certain ThinkPad models e.g. T480. ++ Not used in the actual build. Libreboot's build system uses this ++ along with config/vendor/*/pkg.cfg entries defining a URL to the ++ Lenovo download link and hash. The resulting file when processed by ++ lbmk can be flashed to the ThunderBolt firmware's 25XX NOR device. ++ Earlier versions of this firmware had debug commands enabled that ++ sent logs to said flash IC, and it would quickly fill up, bricking ++ the ThunderBolt controller. With these updates, flashed externally, ++ you can fix the issue if present or otherwise prevent it. The benefit ++ here is that you then don't need to use Windows or a boot disk. You ++ can flash the TB firmware while flashing Libreboot firmware. Easy! ++ Look for these variables in lbmk: ++ TBFW_url TBFW_url_bkup TBFW_hash and look at how it handles that and ++ CONFIG_LENOVO_TBFW_BIN, in lbmk's include/vendor.sh file. ++ The path set by CONFIG_LENOVO_TBFW_BIN is used by lbmk when extracting ++ the firmware, putting it at that desired location. In this way, lbmk ++ can auto-download such firmware. E.g. ./mk -d coreboot t480_fsp_16mb ++ and it appears at vendorfiles/t480/tb.bin fully padded and everything! ++ ++ Just leave this blank if you don't care about this option. It's not ++ useful for every ThinkPad, only certain models. ++ + endif # VENDOR_LENOVO +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0031-soc-intel-skylake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0031-soc-intel-skylake-Don-t-compress-FSP-S.patch deleted file mode 100644 index 42578730..00000000 --- a/config/coreboot/default/patches/0031-soc-intel-skylake-Don-t-compress-FSP-S.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 564634f7f83f4118e44972c91e391125a7aa6e27 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Thu, 26 Dec 2024 19:45:20 +0000 -Subject: [PATCH 31/51] soc/intel/skylake: Don't compress FSP-S - -Build systems like lbmk need to reproducibly insert -certain vendor files on release images. - -Compression isn't always reproducible, and making it -so costs a lot more time than simply disabling compression. - -With this change, the FSP-S module will now be inserted -without compression, which means that there will now be -about 40KB of extra space used in the flash. - -Signed-off-by: Leah Rowe ---- - src/soc/intel/skylake/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index f8ff8cfa7a..97354cdaa5 100644 ---- a/src/soc/intel/skylake/Kconfig -+++ b/src/soc/intel/skylake/Kconfig -@@ -15,7 +15,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE - select DRAM_SUPPORT_DDR4 - select DRIVERS_USB_ACPI - select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 -- select FSP_COMPRESS_FSP_S_LZ4 -+# select FSP_COMPRESS_FSP_S_LZ4 - select FSP_M_XIP - select GENERIC_GPIO_LIB - select HAVE_FSP_GOP --- -2.47.3 - diff --git a/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch b/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch new file mode 100644 index 00000000..2f804c3f --- /dev/null +++ b/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch @@ -0,0 +1,37 @@ +From cb3b76b4805886d5afc5846d351a292639b91bc6 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 21 Apr 2025 05:14:45 +0100 +Subject: [PATCH 32/51] Conditional TBFW setting for kabylake thinkpads + +Otherwise, other boards will define it, which +might trigger the vendor download script, and +lead to a non-zero exit. + +Signed-off-by: Leah Rowe +--- + src/mainboard/lenovo/Kconfig | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig +index 512b326381..b2c7763198 100644 +--- a/src/mainboard/lenovo/Kconfig ++++ b/src/mainboard/lenovo/Kconfig +@@ -18,6 +18,8 @@ config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + ++if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580 ++ + config LENOVO_TBFW_BIN + string "Lenovo ThunderBolt firmware bin file" + default "" +@@ -44,4 +46,6 @@ config LENOVO_TBFW_BIN + Just leave this blank if you don't care about this option. It's not + useful for every ThinkPad, only certain models. + ++endif # BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580 ++ + endif # VENDOR_LENOVO +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch deleted file mode 100644 index b5f1435e..00000000 --- a/config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 9e50b19e8d892819bebbebafe25c175f5a8faece Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Wed, 18 Dec 2024 02:06:18 +0000 -Subject: [PATCH 32/51] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN - -This is used by lbmk to know where a tb.bin file goes, -when extracting and padding TBT.bin from Lenovo ThunderBolt -firmware updates on T480/T480s and other machines, grabbing -Lenovo update files. - -Not used in any builds, so it's not relevant for ./mk inject - -However, the ThunderBolt firmware is now auto-downloaded on -T480/T480s. This is not inserted, because it doesn't go in -the main flash, but the resulting ROM image can be flashed -on the TB controller's separate flash chip. - -Locations are as follows: - -vendorfiles/t480s/tb.bin -vendorfiles/t480/tb.bin - -This can be used for other affected ThinkPads when they're -added to Libreboot, but note that Lenovo provides different -TB firmware files for each machine. - -Since I assume it's the same TB controller on all of those -machines, I have to wonder: what difference is there between -the various TBT.bin files provided by Lenovo, and how do they -differ in terms of actual flashed configuration? - -We simply flash the padded TBT.bin when updating the firmware, -flashing externally. That's what this patch is for, so that -lbmk can auto-download them. - -Signed-off-by: Leah Rowe ---- - src/mainboard/lenovo/Kconfig | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig -index 2ffbaab85f..512b326381 100644 ---- a/src/mainboard/lenovo/Kconfig -+++ b/src/mainboard/lenovo/Kconfig -@@ -18,4 +18,30 @@ config MAINBOARD_FAMILY - string - default MAINBOARD_PART_NUMBER - -+config LENOVO_TBFW_BIN -+ string "Lenovo ThunderBolt firmware bin file" -+ default "" -+ help -+ ThunderBolt firmware for certain ThinkPad models e.g. T480. -+ Not used in the actual build. Libreboot's build system uses this -+ along with config/vendor/*/pkg.cfg entries defining a URL to the -+ Lenovo download link and hash. The resulting file when processed by -+ lbmk can be flashed to the ThunderBolt firmware's 25XX NOR device. -+ Earlier versions of this firmware had debug commands enabled that -+ sent logs to said flash IC, and it would quickly fill up, bricking -+ the ThunderBolt controller. With these updates, flashed externally, -+ you can fix the issue if present or otherwise prevent it. The benefit -+ here is that you then don't need to use Windows or a boot disk. You -+ can flash the TB firmware while flashing Libreboot firmware. Easy! -+ Look for these variables in lbmk: -+ TBFW_url TBFW_url_bkup TBFW_hash and look at how it handles that and -+ CONFIG_LENOVO_TBFW_BIN, in lbmk's include/vendor.sh file. -+ The path set by CONFIG_LENOVO_TBFW_BIN is used by lbmk when extracting -+ the firmware, putting it at that desired location. In this way, lbmk -+ can auto-download such firmware. E.g. ./mk -d coreboot t480_fsp_16mb -+ and it appears at vendorfiles/t480/tb.bin fully padded and everything! -+ -+ Just leave this blank if you don't care about this option. It's not -+ useful for every ThinkPad, only certain models. -+ - endif # VENDOR_LENOVO --- -2.47.3 - diff --git a/config/coreboot/default/patches/0033-Conditional-TBFW-setting-for-kabylake-thinkpads.patch b/config/coreboot/default/patches/0033-Conditional-TBFW-setting-for-kabylake-thinkpads.patch deleted file mode 100644 index a5a69887..00000000 --- a/config/coreboot/default/patches/0033-Conditional-TBFW-setting-for-kabylake-thinkpads.patch +++ /dev/null @@ -1,37 +0,0 @@ -From eb332dd2c30c54a78cd0ce573c3358df458ad8c5 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 21 Apr 2025 05:14:45 +0100 -Subject: [PATCH 33/51] Conditional TBFW setting for kabylake thinkpads - -Otherwise, other boards will define it, which -might trigger the vendor download script, and -lead to a non-zero exit. - -Signed-off-by: Leah Rowe ---- - src/mainboard/lenovo/Kconfig | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig -index 512b326381..b2c7763198 100644 ---- a/src/mainboard/lenovo/Kconfig -+++ b/src/mainboard/lenovo/Kconfig -@@ -18,6 +18,8 @@ config MAINBOARD_FAMILY - string - default MAINBOARD_PART_NUMBER - -+if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580 -+ - config LENOVO_TBFW_BIN - string "Lenovo ThunderBolt firmware bin file" - default "" -@@ -44,4 +46,6 @@ config LENOVO_TBFW_BIN - Just leave this blank if you don't care about this option. It's not - useful for every ThinkPad, only certain models. - -+endif # BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580 -+ - endif # VENDOR_LENOVO --- -2.47.3 - diff --git a/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch b/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch new file mode 100644 index 00000000..ff8a2f4b --- /dev/null +++ b/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch @@ -0,0 +1,30 @@ +From bb04b8f8db08f06100f801ddeb076f165c3d503a Mon Sep 17 00:00:00 2001 +From: Riku Viitanen +Date: Sat, 27 Sep 2025 23:30:46 +0300 +Subject: [PATCH 33/51] soc/intel/alderlake: Disable + MRC_CACHE_USING_MRC_VERSION + +There's some issue with building against the FSP headers in src/vendorcode. +Headers in 3rdparty/fsp work, but since FspProducerDataHeaer.h is missing +from there, we need to disable MRC_CACHE_USING_MRC_VERSION by force. + +Signed-off-by: Riku Viitanen +--- + src/soc/intel/alderlake/Kconfig | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index 334ea26e5b..0f1404ea49 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -36,7 +36,6 @@ config SOC_INTEL_ALDERLAKE + select INTEL_GMA_VERSION_2 + select INTEL_TXT_LIB + select MP_SERVICES_PPI_V2 +- select MRC_CACHE_USING_MRC_VERSION if (SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_RAPTORLAKE) && !FSP_USE_REPO + select MRC_SETTINGS_PROTECT + select PARALLEL_MP_AP_WORK + select PLATFORM_USES_FSP2_2 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch b/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch new file mode 100644 index 00000000..e78ea07c --- /dev/null +++ b/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch @@ -0,0 +1,76 @@ +From de90c8706495b73e24e362dd7c80f211581a2ad6 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sun, 28 Sep 2025 03:17:50 +0100 +Subject: [PATCH 34/51] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) + +if you pass -k (keep fptr modules), don't use -r, don't +use -t, you can essentially just use me_cleaner to +extract a ME image without changing it. this is useful +when for example, you just want to set the HAP bit. + +however, me_cleaner still performs a FPTR check. + +on some newer ME versions, it's always invalid according +to me_cleaner, because for example it doesn't handle +ME16 very well yet. + +this patch adds an option to override the FPTR check + +either pass -p or --pass-fptr + +NOTE: we probably won't use this on coreboot's me_cleaner, +which is the corna version. we only need it on the newer +me_cleaner versions for e.g. ME16, on certain setups. +still, it's best to have the patch here too, just in case. + +Signed-off-by: Leah Rowe +--- + util/me_cleaner/me_cleaner.py | 14 ++++++++++---- + 1 file changed, 10 insertions(+), 4 deletions(-) + +diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py +index fae5e56732..228bac899f 100755 +--- a/util/me_cleaner/me_cleaner.py ++++ b/util/me_cleaner/me_cleaner.py +@@ -246,8 +246,10 @@ def check_partition_signature(f, offset): + return "{:#x}".format(decrypted_sig).endswith(sha256.hexdigest()) # FIXME + + +-def print_check_partition_signature(f, offset): +- if check_partition_signature(f, offset): ++def print_check_partition_signature(f, offset, pass_fptr): ++ if pass_fptr: ++ print("Skipping FPTR checks because the user told us to") ++ elif check_partition_signature(f, offset): + print("VALID") + else: + print("INVALID!!") +@@ -486,6 +488,8 @@ if __name__ == "__main__": + "--extract-me)", action="store_true") + parser.add_argument("-k", "--keep-modules", help="don't remove the FTPR " + "modules, even when possible", action="store_true") ++ parser.add_argument("-p", "--pass-fptr", help="skip FTPR signature checks" ++ "regardless of other operations", action="store_true") + bw_list.add_argument("-w", "--whitelist", metavar="whitelist", + help="Comma separated list of additional partitions " + "to keep in the final image. This can be used to " +@@ -871,12 +875,14 @@ if __name__ == "__main__": + print("Checking the FTPR RSA signature of the extracted ME " + "image... ", end="") + print_check_partition_signature(mef_copy, +- ftpr_offset + ftpr_mn2_offset) ++ ftpr_offset + ftpr_mn2_offset, ++ args.pass_fptr) + mef_copy.close() + + if not me6_ignition: + print("Checking the FTPR RSA signature... ", end="") +- print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset) ++ print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset, ++ args.pass_fptr) + + f.close() + +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0034-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch b/config/coreboot/default/patches/0034-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch deleted file mode 100644 index fabd23d4..00000000 --- a/config/coreboot/default/patches/0034-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 97c167555bec5e8a69b90379c3350766fc5b1107 Mon Sep 17 00:00:00 2001 -From: Riku Viitanen -Date: Sat, 27 Sep 2025 23:30:46 +0300 -Subject: [PATCH 34/51] soc/intel/alderlake: Disable - MRC_CACHE_USING_MRC_VERSION - -There's some issue with building against the FSP headers in src/vendorcode. -Headers in 3rdparty/fsp work, but since FspProducerDataHeaer.h is missing -from there, we need to disable MRC_CACHE_USING_MRC_VERSION by force. - -Signed-off-by: Riku Viitanen ---- - src/soc/intel/alderlake/Kconfig | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 334ea26e5b..0f1404ea49 100644 ---- a/src/soc/intel/alderlake/Kconfig -+++ b/src/soc/intel/alderlake/Kconfig -@@ -36,7 +36,6 @@ config SOC_INTEL_ALDERLAKE - select INTEL_GMA_VERSION_2 - select INTEL_TXT_LIB - select MP_SERVICES_PPI_V2 -- select MRC_CACHE_USING_MRC_VERSION if (SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_RAPTORLAKE) && !FSP_USE_REPO - select MRC_SETTINGS_PROTECT - select PARALLEL_MP_AP_WORK - select PLATFORM_USES_FSP2_2 --- -2.47.3 - diff --git a/config/coreboot/default/patches/0035-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch b/config/coreboot/default/patches/0035-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch deleted file mode 100644 index 8d5fa92f..00000000 --- a/config/coreboot/default/patches/0035-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch +++ /dev/null @@ -1,76 +0,0 @@ -From fd552921d0a34b8ac2f9c21f8c1abf47f2f0c160 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sun, 28 Sep 2025 03:17:50 +0100 -Subject: [PATCH 35/51] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) - -if you pass -k (keep fptr modules), don't use -r, don't -use -t, you can essentially just use me_cleaner to -extract a ME image without changing it. this is useful -when for example, you just want to set the HAP bit. - -however, me_cleaner still performs a FPTR check. - -on some newer ME versions, it's always invalid according -to me_cleaner, because for example it doesn't handle -ME16 very well yet. - -this patch adds an option to override the FPTR check - -either pass -p or --pass-fptr - -NOTE: we probably won't use this on coreboot's me_cleaner, -which is the corna version. we only need it on the newer -me_cleaner versions for e.g. ME16, on certain setups. -still, it's best to have the patch here too, just in case. - -Signed-off-by: Leah Rowe ---- - util/me_cleaner/me_cleaner.py | 14 ++++++++++---- - 1 file changed, 10 insertions(+), 4 deletions(-) - -diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py -index fae5e56732..228bac899f 100755 ---- a/util/me_cleaner/me_cleaner.py -+++ b/util/me_cleaner/me_cleaner.py -@@ -246,8 +246,10 @@ def check_partition_signature(f, offset): - return "{:#x}".format(decrypted_sig).endswith(sha256.hexdigest()) # FIXME - - --def print_check_partition_signature(f, offset): -- if check_partition_signature(f, offset): -+def print_check_partition_signature(f, offset, pass_fptr): -+ if pass_fptr: -+ print("Skipping FPTR checks because the user told us to") -+ elif check_partition_signature(f, offset): - print("VALID") - else: - print("INVALID!!") -@@ -486,6 +488,8 @@ if __name__ == "__main__": - "--extract-me)", action="store_true") - parser.add_argument("-k", "--keep-modules", help="don't remove the FTPR " - "modules, even when possible", action="store_true") -+ parser.add_argument("-p", "--pass-fptr", help="skip FTPR signature checks" -+ "regardless of other operations", action="store_true") - bw_list.add_argument("-w", "--whitelist", metavar="whitelist", - help="Comma separated list of additional partitions " - "to keep in the final image. This can be used to " -@@ -871,12 +875,14 @@ if __name__ == "__main__": - print("Checking the FTPR RSA signature of the extracted ME " - "image... ", end="") - print_check_partition_signature(mef_copy, -- ftpr_offset + ftpr_mn2_offset) -+ ftpr_offset + ftpr_mn2_offset, -+ args.pass_fptr) - mef_copy.close() - - if not me6_ignition: - print("Checking the FTPR RSA signature... ", end="") -- print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset) -+ print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset, -+ args.pass_fptr) - - f.close() - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch new file mode 100644 index 00000000..4ffaf33c --- /dev/null +++ b/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch @@ -0,0 +1,35 @@ +From 9887eeeb89b29ca8483c9742733fd78ccd7e171b Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 4 Oct 2025 21:57:43 +0100 +Subject: [PATCH 35/51] soc/intel/alderlake: Don't compress FSP-S + +Build systems like lbmk need to reproducibly insert +certain vendor files on release images. + +Compression isn't always reproducible, and making it +so costs a lot more time than simply disabling compression. + +With this change, FSP-S uses slightly more space inside +the flash, but it's not that much. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/alderlake/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index 0f1404ea49..f78729a9c4 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -16,7 +16,7 @@ config SOC_INTEL_ALDERLAKE + select DRAM_SUPPORT_DDR5 + select DRIVERS_USB_ACPI + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 +- select FSP_COMPRESS_FSP_S_LZ4 ++# select FSP_COMPRESS_FSP_S_LZ4 + select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW + select FSP_M_XIP + select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch b/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch new file mode 100644 index 00000000..13a9cd7c --- /dev/null +++ b/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch @@ -0,0 +1,33 @@ +From 1f62cd582614cb3739475dd4439e132b931c5619 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 4 Oct 2025 22:20:11 +0100 +Subject: [PATCH 36/51] alderlake: don't require full fsp repo for fd path + +Signed-off-by: Leah Rowe +--- + src/soc/intel/alderlake/Kconfig | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index f78729a9c4..c05d06289e 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -442,7 +442,14 @@ config FSP_HEADER_PATH + + config FSP_FD_PATH + string +- depends on FSP_USE_REPO ++# dependency removed for lbmk purposes, so that the path is present ++# in the config regardless of whether it's used. this is for ./mk -d ++# on alderlake boards, which is used by lbmk to manually split fsp, ++# even though the result is identical to what coreboot produces, because ++# this enables lbmk to strip the fsp in release archives, and re-insert ++# for compliance reasons (due to technicalities in intel's licensing), ++# and to enable lbmk's advanced checksum verification of vendor files ++# depends on FSP_USE_REPO + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0036-soc-intel-alderlake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0036-soc-intel-alderlake-Don-t-compress-FSP-S.patch deleted file mode 100644 index a5fa5bb5..00000000 --- a/config/coreboot/default/patches/0036-soc-intel-alderlake-Don-t-compress-FSP-S.patch +++ /dev/null @@ -1,35 +0,0 @@ -From f91e6c35aa0ff7111e65a89a4828b773d038a69c Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 4 Oct 2025 21:57:43 +0100 -Subject: [PATCH 36/51] soc/intel/alderlake: Don't compress FSP-S - -Build systems like lbmk need to reproducibly insert -certain vendor files on release images. - -Compression isn't always reproducible, and making it -so costs a lot more time than simply disabling compression. - -With this change, FSP-S uses slightly more space inside -the flash, but it's not that much. - -Signed-off-by: Leah Rowe ---- - src/soc/intel/alderlake/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 0f1404ea49..f78729a9c4 100644 ---- a/src/soc/intel/alderlake/Kconfig -+++ b/src/soc/intel/alderlake/Kconfig -@@ -16,7 +16,7 @@ config SOC_INTEL_ALDERLAKE - select DRAM_SUPPORT_DDR5 - select DRIVERS_USB_ACPI - select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 -- select FSP_COMPRESS_FSP_S_LZ4 -+# select FSP_COMPRESS_FSP_S_LZ4 - select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW - select FSP_M_XIP - select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN --- -2.47.3 - diff --git a/config/coreboot/default/patches/0037-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch b/config/coreboot/default/patches/0037-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch deleted file mode 100644 index 5c9f8fbd..00000000 --- a/config/coreboot/default/patches/0037-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch +++ /dev/null @@ -1,33 +0,0 @@ -From ab4937af6e193b057a8b0212f0667e57eb7ba7d7 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 4 Oct 2025 22:20:11 +0100 -Subject: [PATCH 37/51] alderlake: don't require full fsp repo for fd path - -Signed-off-by: Leah Rowe ---- - src/soc/intel/alderlake/Kconfig | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - -diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index f78729a9c4..c05d06289e 100644 ---- a/src/soc/intel/alderlake/Kconfig -+++ b/src/soc/intel/alderlake/Kconfig -@@ -442,7 +442,14 @@ config FSP_HEADER_PATH - - config FSP_FD_PATH - string -- depends on FSP_USE_REPO -+# dependency removed for lbmk purposes, so that the path is present -+# in the config regardless of whether it's used. this is for ./mk -d -+# on alderlake boards, which is used by lbmk to manually split fsp, -+# even though the result is identical to what coreboot produces, because -+# this enables lbmk to strip the fsp in release archives, and re-insert -+# for compliance reasons (due to technicalities in intel's licensing), -+# and to enable lbmk's advanced checksum verification of vendor files -+# depends on FSP_USE_REPO - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P --- -2.47.3 - diff --git a/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch b/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch new file mode 100644 index 00000000..d491426a --- /dev/null +++ b/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch @@ -0,0 +1,46 @@ +From 0af11ee58ae38a385431253b1f5f0e9dbce98d3d Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 6 Oct 2025 04:47:06 +0100 +Subject: [PATCH 37/51] soc/alderlake: disable stack overflow debug option + +same as on other boards. based on this commit: + +commit 51cc2bacb6b07279b97e9934d079060475481fb6 +Author: Subrata Banik +Author: Subrata Banik +Date: Fri Dec 13 13:07:28 2024 +0530 + + soc/intel/pantherlake: Disable stack overflow debug options + +yeah, i've been replicating this change per platform. + +we do alderlake now in libreboot, so let's set that here too. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/alderlake/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index c05d06289e..acb87275d4 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -343,6 +343,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ + int + default 19200000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch b/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch new file mode 100644 index 00000000..82ad5f07 --- /dev/null +++ b/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch @@ -0,0 +1,92 @@ +From f1369485a721aa4ed239f6a8c0b0ad1b82884c7b Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Sun, 11 May 2025 15:41:22 -0600 +Subject: [PATCH 38/51] ec/dell/mec5035: Add command to disable EC-initiated + thermal shutdown + +If command 0xBF isn't sent, the EC shuts down the system without warning +as soon as the CPU temperature reaches about 87 degrees, without letting +the CPU thermal throttle to try and reduce the temperature. With vendor +firmware, the CPU is able to reach around 100 degrees before thermal +throttling. + +This command was found by collecting EC commands by logging the LPC bus +while running with vendor firmware and then replaying observed commands +from coreboot. By systematically replaying subsets of commands in a +binary search pattern and then stress testing the system, the command to +disable the shutdown was isolated. + +The exact meaning of the parameters for this command are unknown at this +time, but do seem to differ between different generations of these +laptops. Due to this, the commmand should be called by mainboard +specific code which passes the specific parameter value used. + +The Google Wilco EC code, which runs on Latitude Chromebooks and shares +many commands with the standard Latitude ECs, suggests that command 0xBF +tells the EC about the processors CPUID. However, the values observed in +LPC bus logs do not seem to correspond with any CPUID values on the +non-Chromebook systems I tested. + +Observed command parameter values (sent on mailbox registers 2-4): +- E6430 (Ivy Bridge): 0x07, 0x00, 0x00 +- M6800 (Haswell): 0x14, 0x00, 0x00 + +Change-Id: I42f09a3ef681007f64d9c5b1a29248b594737a86 +Signed-off-by: Nicholas Chin +--- + src/ec/dell/mec5035/mec5035.c | 19 +++++++++++++++++++ + src/ec/dell/mec5035/mec5035.h | 2 ++ + 2 files changed, 21 insertions(+) + +diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c +index c5067c16f6..b316fa4989 100644 +--- a/src/ec/dell/mec5035/mec5035.c ++++ b/src/ec/dell/mec5035/mec5035.c +@@ -114,6 +114,25 @@ void mec5035_sleep_enable(void) + ec_command(CMD_SLEEP_ENABLE); + } + ++void mec5035_cmd_bf(u8 i) ++{ ++ /* ++ * If this command isn't sent, the EC shuts down the system as soon as ++ * the CPU temperature reaches about 87 degrees. It is unknown exactly ++ * what the parameters represent. The Google Wilco EC code, which runs ++ * on Latitude Chromebooks and shares some commands with the standard ++ * Latitude EC code, suggests command 0xBF tells the EC the CPUID, but ++ * the values observed in LPC bus logs don't seem to match any CPUID ++ * values of the normal Latitudes this was tested with. ++ * Observed i values: ++ * - E6430 (Ivy Bridge): 0x7 ++ * - M6800 (Haswell): 0x14 ++ */ ++ u8 buf[3] = {i, 0, 0}; ++ write_mailbox_regs(buf, 2, 3); ++ ec_command(CMD_BF); ++} ++ + void mec5035_early_init(void) + { + /* If this isn't sent the EC shuts down the system after about 15 +diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h +index 5cd907bf71..71d1a71075 100644 +--- a/src/ec/dell/mec5035/mec5035.h ++++ b/src/ec/dell/mec5035/mec5035.h +@@ -14,6 +14,7 @@ enum mec5035_cmd { + CMD_POWER_BUTTON_TO_HOST = 0x3e, + CMD_ACPI_WAKEUP_CHANGE = 0x4a, + CMD_SLEEP_ENABLE = 0x64, ++ CMD_BF = 0xbf, + CMD_CPU_OK = 0xc2, + }; + +@@ -65,5 +66,6 @@ void mec5035_change_wake(u8 source, enum ec_wake_change change); + void mec5035_sleep_enable(void); + + void mec5035_smi_sleep(int slp_type); ++void mec5035_cmd_bf(u8 i); + + #endif /* _EC_DELL_MEC5035_H_ */ +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0038-soc-alderlake-disable-stack-overflow-debug-option.patch b/config/coreboot/default/patches/0038-soc-alderlake-disable-stack-overflow-debug-option.patch deleted file mode 100644 index 4a3130ac..00000000 --- a/config/coreboot/default/patches/0038-soc-alderlake-disable-stack-overflow-debug-option.patch +++ /dev/null @@ -1,46 +0,0 @@ -From dec241cc53669870365e103a22d21a9a3111abcc Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 6 Oct 2025 04:47:06 +0100 -Subject: [PATCH 38/51] soc/alderlake: disable stack overflow debug option - -same as on other boards. based on this commit: - -commit 51cc2bacb6b07279b97e9934d079060475481fb6 -Author: Subrata Banik -Author: Subrata Banik -Date: Fri Dec 13 13:07:28 2024 +0530 - - soc/intel/pantherlake: Disable stack overflow debug options - -yeah, i've been replicating this change per platform. - -we do alderlake now in libreboot, so let's set that here too. - -Signed-off-by: Leah Rowe ---- - src/soc/intel/alderlake/Kconfig | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index c05d06289e..acb87275d4 100644 ---- a/src/soc/intel/alderlake/Kconfig -+++ b/src/soc/intel/alderlake/Kconfig -@@ -343,6 +343,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ - int - default 19200000 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ - int - default 133 --- -2.47.3 - diff --git a/config/coreboot/default/patches/0039-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch b/config/coreboot/default/patches/0039-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch deleted file mode 100644 index 6518493e..00000000 --- a/config/coreboot/default/patches/0039-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch +++ /dev/null @@ -1,92 +0,0 @@ -From fa7d21faf931756d8adb84071bc503a0fe8e64c3 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Sun, 11 May 2025 15:41:22 -0600 -Subject: [PATCH 39/51] ec/dell/mec5035: Add command to disable EC-initiated - thermal shutdown - -If command 0xBF isn't sent, the EC shuts down the system without warning -as soon as the CPU temperature reaches about 87 degrees, without letting -the CPU thermal throttle to try and reduce the temperature. With vendor -firmware, the CPU is able to reach around 100 degrees before thermal -throttling. - -This command was found by collecting EC commands by logging the LPC bus -while running with vendor firmware and then replaying observed commands -from coreboot. By systematically replaying subsets of commands in a -binary search pattern and then stress testing the system, the command to -disable the shutdown was isolated. - -The exact meaning of the parameters for this command are unknown at this -time, but do seem to differ between different generations of these -laptops. Due to this, the commmand should be called by mainboard -specific code which passes the specific parameter value used. - -The Google Wilco EC code, which runs on Latitude Chromebooks and shares -many commands with the standard Latitude ECs, suggests that command 0xBF -tells the EC about the processors CPUID. However, the values observed in -LPC bus logs do not seem to correspond with any CPUID values on the -non-Chromebook systems I tested. - -Observed command parameter values (sent on mailbox registers 2-4): -- E6430 (Ivy Bridge): 0x07, 0x00, 0x00 -- M6800 (Haswell): 0x14, 0x00, 0x00 - -Change-Id: I42f09a3ef681007f64d9c5b1a29248b594737a86 -Signed-off-by: Nicholas Chin ---- - src/ec/dell/mec5035/mec5035.c | 19 +++++++++++++++++++ - src/ec/dell/mec5035/mec5035.h | 2 ++ - 2 files changed, 21 insertions(+) - -diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index c5067c16f6..b316fa4989 100644 ---- a/src/ec/dell/mec5035/mec5035.c -+++ b/src/ec/dell/mec5035/mec5035.c -@@ -114,6 +114,25 @@ void mec5035_sleep_enable(void) - ec_command(CMD_SLEEP_ENABLE); - } - -+void mec5035_cmd_bf(u8 i) -+{ -+ /* -+ * If this command isn't sent, the EC shuts down the system as soon as -+ * the CPU temperature reaches about 87 degrees. It is unknown exactly -+ * what the parameters represent. The Google Wilco EC code, which runs -+ * on Latitude Chromebooks and shares some commands with the standard -+ * Latitude EC code, suggests command 0xBF tells the EC the CPUID, but -+ * the values observed in LPC bus logs don't seem to match any CPUID -+ * values of the normal Latitudes this was tested with. -+ * Observed i values: -+ * - E6430 (Ivy Bridge): 0x7 -+ * - M6800 (Haswell): 0x14 -+ */ -+ u8 buf[3] = {i, 0, 0}; -+ write_mailbox_regs(buf, 2, 3); -+ ec_command(CMD_BF); -+} -+ - void mec5035_early_init(void) - { - /* If this isn't sent the EC shuts down the system after about 15 -diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h -index 5cd907bf71..71d1a71075 100644 ---- a/src/ec/dell/mec5035/mec5035.h -+++ b/src/ec/dell/mec5035/mec5035.h -@@ -14,6 +14,7 @@ enum mec5035_cmd { - CMD_POWER_BUTTON_TO_HOST = 0x3e, - CMD_ACPI_WAKEUP_CHANGE = 0x4a, - CMD_SLEEP_ENABLE = 0x64, -+ CMD_BF = 0xbf, - CMD_CPU_OK = 0xc2, - }; - -@@ -65,5 +66,6 @@ void mec5035_change_wake(u8 source, enum ec_wake_change change); - void mec5035_sleep_enable(void); - - void mec5035_smi_sleep(int slp_type); -+void mec5035_cmd_bf(u8 i); - - #endif /* _EC_DELL_MEC5035_H_ */ --- -2.47.3 - diff --git a/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch b/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch new file mode 100644 index 00000000..fe9da83d --- /dev/null +++ b/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch @@ -0,0 +1,36 @@ +From 3e63073e195446ea3adef0e21f5369e7ef27494a Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Sun, 11 May 2025 16:28:23 -0600 +Subject: [PATCH 39/51] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown + at 87 degrees + +If command 0xBF isn't sent, the EC will shut down the system without +warning once the CPU reaches approximately 87 degrees, without the +system thermal throttling first. Call the newly added function from the +MEC5035 code to send this command and disable this behavior. + +Tested on the Latitude E6430. + +Change-Id: I2b2dc1e3ab115e05d05eaac06892343394d37fdf +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/snb_ivb_latitude/early_init.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/src/mainboard/dell/snb_ivb_latitude/early_init.c b/src/mainboard/dell/snb_ivb_latitude/early_init.c +index ff83db095b..ef385a0a70 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/early_init.c ++++ b/src/mainboard/dell/snb_ivb_latitude/early_init.c +@@ -11,4 +11,9 @@ void bootblock_mainboard_early_init(void) + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); ++ ++ /* Observed from LPC logs with vendor firmware. Seems to disable ++ * EC-initiated shutdown when the CPU reaches approximately 87 degrees. ++ * The exact meaning of the parameter is currently unknown. */ ++ mec5035_cmd_bf(0x07); + } +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0040-fix-ifdtool-build.patch b/config/coreboot/default/patches/0040-fix-ifdtool-build.patch new file mode 100644 index 00000000..976d40ef --- /dev/null +++ b/config/coreboot/default/patches/0040-fix-ifdtool-build.patch @@ -0,0 +1,28 @@ +From f05e8514654cddb5041fa65a90ab5260ec55d1e5 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 20 Dec 2025 20:12:48 +0100 +Subject: [PATCH 40/51] fix ifdtool build + +not my mistake. someone messed up. + +Signed-off-by: Leah Rowe +--- + util/ifdtool/ifdtool.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c +index 7f0c10bd0b..2a5365efe7 100644 +--- a/util/ifdtool/ifdtool.c ++++ b/util/ifdtool/ifdtool.c +@@ -2610,7 +2610,7 @@ int main(int argc, char *argv[]) + } + mode_nuke = 1; + break; +- Case 'v': ++ case 'v': + print_version(); + exit(EXIT_SUCCESS); + break; +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0040-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch b/config/coreboot/default/patches/0040-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch deleted file mode 100644 index 0ebfe02a..00000000 --- a/config/coreboot/default/patches/0040-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 0397a0966953d47210a5ae1f7f0cd71a9a10dc68 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Sun, 11 May 2025 16:28:23 -0600 -Subject: [PATCH 40/51] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown - at 87 degrees - -If command 0xBF isn't sent, the EC will shut down the system without -warning once the CPU reaches approximately 87 degrees, without the -system thermal throttling first. Call the newly added function from the -MEC5035 code to send this command and disable this behavior. - -Tested on the Latitude E6430. - -Change-Id: I2b2dc1e3ab115e05d05eaac06892343394d37fdf -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/snb_ivb_latitude/early_init.c | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/src/mainboard/dell/snb_ivb_latitude/early_init.c b/src/mainboard/dell/snb_ivb_latitude/early_init.c -index ff83db095b..ef385a0a70 100644 ---- a/src/mainboard/dell/snb_ivb_latitude/early_init.c -+++ b/src/mainboard/dell/snb_ivb_latitude/early_init.c -@@ -11,4 +11,9 @@ void bootblock_mainboard_early_init(void) - | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN - | COMB_LPC_EN | COMA_LPC_EN); - mec5035_early_init(); -+ -+ /* Observed from LPC logs with vendor firmware. Seems to disable -+ * EC-initiated shutdown when the CPU reaches approximately 87 degrees. -+ * The exact meaning of the parameter is currently unknown. */ -+ mec5035_cmd_bf(0x07); - } --- -2.47.3 - diff --git a/config/coreboot/default/patches/0041-fix-ifdtool-build.patch b/config/coreboot/default/patches/0041-fix-ifdtool-build.patch deleted file mode 100644 index 3124f7c3..00000000 --- a/config/coreboot/default/patches/0041-fix-ifdtool-build.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 42fb6f08310a35587643bdfd75bcdca5318f1022 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 20 Dec 2025 20:12:48 +0100 -Subject: [PATCH 41/51] fix ifdtool build - -not my mistake. someone messed up. - -Signed-off-by: Leah Rowe ---- - util/ifdtool/ifdtool.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index 7f0c10bd0b..2a5365efe7 100644 ---- a/util/ifdtool/ifdtool.c -+++ b/util/ifdtool/ifdtool.c -@@ -2610,7 +2610,7 @@ int main(int argc, char *argv[]) - } - mode_nuke = 1; - break; -- Case 'v': -+ case 'v': - print_version(); - exit(EXIT_SUCCESS); - break; --- -2.47.3 - diff --git a/config/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch b/config/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch new file mode 100644 index 00000000..74c6548f --- /dev/null +++ b/config/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch @@ -0,0 +1,30 @@ +From 76a1f9c12fedcd595b540168efdd9a8439be3bcd Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 20 Dec 2025 22:36:18 +0100 +Subject: [PATCH 41/51] tests/Makefile.mk: use 3rdparty/cmocka by default + +(tests) + +Signed-off-by: Leah Rowe +--- + tests/Makefile.mk | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/tests/Makefile.mk b/tests/Makefile.mk +index 9e3f86a138..a5a518cd35 100644 +--- a/tests/Makefile.mk ++++ b/tests/Makefile.mk +@@ -25,7 +25,9 @@ TEST_LDFLAGS += --coverage + endif + + # Use system cmoka in default, or build from 3rdparty source code if requested +-USE_SYSTEM_CMOCKA ?= 1 ++# PATCH NOTE: lbmk sets it to 0 by default. You can still override it to 1 ++# if you wish; upstream sets this to 1 by default, but we do 0 ++USE_SYSTEM_CMOCKA ?= 0 + ifeq ($(USE_SYSTEM_CMOCKA),1) + ifeq ($(shell $(HOSTPKG_CONFIG) --exists cmocka || echo 1),1) + $(warning No system cmocka, build from 3rdparty instead...) +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch b/config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch new file mode 100644 index 00000000..75d57c94 --- /dev/null +++ b/config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch @@ -0,0 +1,51 @@ +From 942ef84be2203c6a784e5dd80a0e1caeb1d8c98c Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 23 Dec 2025 18:41:27 +0100 +Subject: [PATCH 42/51] mb/dell/optiplex_780: use legacy HDA verb table + +See: + +commit 31fc5b06a6be62b30739d33eeabe6c2727679bb1 +Author: Nicholas Sudsgaard +Date: Thu Aug 7 08:31:24 2025 +0900 + + device: Introduce reworked azalia verb table + +and: + +commit 50a59d4464917503847eeeb2df4320c35cf2f6cc +Author: Nicholas Sudsgaard +Date: Mon Sep 15 16:25:21 2025 +0900 + + device: Add Kconfig to prepare for reworked verb table implementation + +Without this change, lbmk gets the following error +when building for Dell OptiPlex 780: + +i386-elf-ld.bfd: build/ramstage/device/azalia_device.o: in function `azalia_codecs_init': +/path/to/corebootclone/src/device/azalia_device.c:318:(.text.azalia_codecs_init+0xa): undefined reference to `mainboard_azalia_codecs' + +This is a temporary fix. Upstream will require that the code +be fully adapted at a future date. Therefore, one could consider +the current functionality to be "deprecated". + +Signed-off-by: Leah Rowe +--- + src/mainboard/dell/optiplex_780/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig +index fc649e35d5..172bb2fa87 100644 +--- a/src/mainboard/dell/optiplex_780/Kconfig ++++ b/src/mainboard/dell/optiplex_780/Kconfig +@@ -2,6 +2,7 @@ + + config BOARD_DELL_OPTIPLEX_780_COMMON + def_bool n ++ select AZALIA_USE_LEGACY_VERB_TABLE + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_SOCKET_LGA775 + select DRIVERS_I2C_CK505 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0042-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch b/config/coreboot/default/patches/0042-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch deleted file mode 100644 index a8206276..00000000 --- a/config/coreboot/default/patches/0042-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 5bcd048c8ded00a7c12e863a1a9a76c9bba1606a Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 20 Dec 2025 22:36:18 +0100 -Subject: [PATCH 42/51] tests/Makefile.mk: use 3rdparty/cmocka by default - -(tests) - -Signed-off-by: Leah Rowe ---- - tests/Makefile.mk | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/tests/Makefile.mk b/tests/Makefile.mk -index 9e3f86a138..a5a518cd35 100644 ---- a/tests/Makefile.mk -+++ b/tests/Makefile.mk -@@ -25,7 +25,9 @@ TEST_LDFLAGS += --coverage - endif - - # Use system cmoka in default, or build from 3rdparty source code if requested --USE_SYSTEM_CMOCKA ?= 1 -+# PATCH NOTE: lbmk sets it to 0 by default. You can still override it to 1 -+# if you wish; upstream sets this to 1 by default, but we do 0 -+USE_SYSTEM_CMOCKA ?= 0 - ifeq ($(USE_SYSTEM_CMOCKA),1) - ifeq ($(shell $(HOSTPKG_CONFIG) --exists cmocka || echo 1),1) - $(warning No system cmocka, build from 3rdparty instead...) --- -2.47.3 - diff --git a/config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch b/config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch new file mode 100644 index 00000000..d933393d --- /dev/null +++ b/config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch @@ -0,0 +1,30 @@ +From eb141cc6c1372b754fc1cbe9f1dad9aade066e70 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 23 Dec 2025 18:46:45 +0100 +Subject: [PATCH 43/51] hp8300cmt: use legacy verb table + +same as for the 780 optiplex patch + +coreboot is making some changes to the way verbs are +handled. for now, this change is being made to adapt. + +Signed-off-by: Leah Rowe +--- + src/mainboard/hp/compaq_elite_8300_cmt/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig +index d2bfd35dc4..30be7fb3fe 100644 +--- a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig +@@ -2,6 +2,7 @@ if BOARD_HP_COMPAQ_ELITE_8300_CMT + + config BOARD_SPECIFIC_OPTIONS + def_bool y ++ select AZALIA_USE_LEGACY_VERB_TABLE + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0043-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch b/config/coreboot/default/patches/0043-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch deleted file mode 100644 index 1c614c17..00000000 --- a/config/coreboot/default/patches/0043-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch +++ /dev/null @@ -1,51 +0,0 @@ -From ac1c23e215f791c46094377f2f4c7a398e63cc80 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 23 Dec 2025 18:41:27 +0100 -Subject: [PATCH 43/51] mb/dell/optiplex_780: use legacy HDA verb table - -See: - -commit 31fc5b06a6be62b30739d33eeabe6c2727679bb1 -Author: Nicholas Sudsgaard -Date: Thu Aug 7 08:31:24 2025 +0900 - - device: Introduce reworked azalia verb table - -and: - -commit 50a59d4464917503847eeeb2df4320c35cf2f6cc -Author: Nicholas Sudsgaard -Date: Mon Sep 15 16:25:21 2025 +0900 - - device: Add Kconfig to prepare for reworked verb table implementation - -Without this change, lbmk gets the following error -when building for Dell OptiPlex 780: - -i386-elf-ld.bfd: build/ramstage/device/azalia_device.o: in function `azalia_codecs_init': -/path/to/corebootclone/src/device/azalia_device.c:318:(.text.azalia_codecs_init+0xa): undefined reference to `mainboard_azalia_codecs' - -This is a temporary fix. Upstream will require that the code -be fully adapted at a future date. Therefore, one could consider -the current functionality to be "deprecated". - -Signed-off-by: Leah Rowe ---- - src/mainboard/dell/optiplex_780/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig -index fc649e35d5..172bb2fa87 100644 ---- a/src/mainboard/dell/optiplex_780/Kconfig -+++ b/src/mainboard/dell/optiplex_780/Kconfig -@@ -2,6 +2,7 @@ - - config BOARD_DELL_OPTIPLEX_780_COMMON - def_bool n -+ select AZALIA_USE_LEGACY_VERB_TABLE - select BOARD_ROMSIZE_KB_8192 - select CPU_INTEL_SOCKET_LGA775 - select DRIVERS_I2C_CK505 --- -2.47.3 - diff --git a/config/coreboot/default/patches/0044-hp8300cmt-use-legacy-verb-table.patch b/config/coreboot/default/patches/0044-hp8300cmt-use-legacy-verb-table.patch deleted file mode 100644 index b210ce34..00000000 --- a/config/coreboot/default/patches/0044-hp8300cmt-use-legacy-verb-table.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 8802ad95c158e09e89c4bc0c14755d17b5f532bd Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 23 Dec 2025 18:46:45 +0100 -Subject: [PATCH 44/51] hp8300cmt: use legacy verb table - -same as for the 780 optiplex patch - -coreboot is making some changes to the way verbs are -handled. for now, this change is being made to adapt. - -Signed-off-by: Leah Rowe ---- - src/mainboard/hp/compaq_elite_8300_cmt/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig -index d2bfd35dc4..30be7fb3fe 100644 ---- a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig -@@ -2,6 +2,7 @@ if BOARD_HP_COMPAQ_ELITE_8300_CMT - - config BOARD_SPECIFIC_OPTIONS - def_bool y -+ select AZALIA_USE_LEGACY_VERB_TABLE - select BOARD_ROMSIZE_KB_16384 - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES --- -2.47.3 - diff --git a/config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch b/config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch new file mode 100644 index 00000000..e3878515 --- /dev/null +++ b/config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch @@ -0,0 +1,34 @@ +From 58f8869dbd58fb9bbb205b5b3bc37cc4ae58dd5b Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 6 Jan 2026 21:42:21 +0000 +Subject: [PATCH 44/51] topton x2e n150: use old fsp + +i added the old fsp back, so that we didn't have to +mess around with vendor files in lbmk, because coreboot +upstream updated the fsp repo, which modified this +fsp file. + +we know the old fsp worked. there's no point testing +the new one yet, unless someone can tell me about +real bugs that got fixed. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/alderlake/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index acb87275d4..6f1e8b9107 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -463,6 +463,7 @@ config FSP_FD_PATH + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S ++ default "3rdparty/fspcc36ae2b5775fa7400cb3282680afc0f6cb37a3c/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if BOARD_TOPTON_X2E_N150 + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_N + default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch b/config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch new file mode 100644 index 00000000..71fc47c1 --- /dev/null +++ b/config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch @@ -0,0 +1,31 @@ +From c4a5a3f5d01e8947c168cf5cf22755cba3cdf2fa Mon Sep 17 00:00:00 2001 +From: Ron Nazarov +Date: Sat, 14 Feb 2026 20:13:01 +0000 +Subject: [PATCH 45/51] mb/supermicro/x11-lga1151-series: Disable ME HECI in + devicetree + +Since we always use me_cleaner, this speeds up boot time by preventing +coreboot from wasting a few seconds waiting for HECI. + +Change-Id: Ifbb16ba9f09129795dabe7861260ea4d995c0350 +Signed-off-by: Ron Nazarov +--- + src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +index d25288420f..edbb485969 100644 +--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb ++++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +@@ -15,7 +15,7 @@ chip soc/intel/skylake + device ref sa_thermal on end + device ref south_xhci on end + device ref thermal on end +- device ref heci1 on end ++ device ref heci1 off end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0045-topton-x2e-n150-use-old-fsp.patch b/config/coreboot/default/patches/0045-topton-x2e-n150-use-old-fsp.patch deleted file mode 100644 index ef6f94a2..00000000 --- a/config/coreboot/default/patches/0045-topton-x2e-n150-use-old-fsp.patch +++ /dev/null @@ -1,34 +0,0 @@ -From ea848531d1a4ddd9952b8b8d3570770e5ac128cd Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 6 Jan 2026 21:42:21 +0000 -Subject: [PATCH 45/51] topton x2e n150: use old fsp - -i added the old fsp back, so that we didn't have to -mess around with vendor files in lbmk, because coreboot -upstream updated the fsp repo, which modified this -fsp file. - -we know the old fsp worked. there's no point testing -the new one yet, unless someone can tell me about -real bugs that got fixed. - -Signed-off-by: Leah Rowe ---- - src/soc/intel/alderlake/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index acb87275d4..6f1e8b9107 100644 ---- a/src/soc/intel/alderlake/Kconfig -+++ b/src/soc/intel/alderlake/Kconfig -@@ -463,6 +463,7 @@ config FSP_FD_PATH - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S -+ default "3rdparty/fspcc36ae2b5775fa7400cb3282680afc0f6cb37a3c/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if BOARD_TOPTON_X2E_N150 - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_N - default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P - default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S --- -2.47.3 - diff --git a/config/coreboot/default/patches/0046-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch b/config/coreboot/default/patches/0046-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch deleted file mode 100644 index 49318070..00000000 --- a/config/coreboot/default/patches/0046-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 276e29864adfaaa1234d1263a8bf751f7dfd357d Mon Sep 17 00:00:00 2001 -From: Ron Nazarov -Date: Sat, 14 Feb 2026 20:13:01 +0000 -Subject: [PATCH 46/51] mb/supermicro/x11-lga1151-series: Disable ME HECI in - devicetree - -Since we always use me_cleaner, this speeds up boot time by preventing -coreboot from wasting a few seconds waiting for HECI. - -Change-Id: Ifbb16ba9f09129795dabe7861260ea4d995c0350 -Signed-off-by: Ron Nazarov ---- - src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb -index d25288420f..edbb485969 100644 ---- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb -+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb -@@ -15,7 +15,7 @@ chip soc/intel/skylake - device ref sa_thermal on end - device ref south_xhci on end - device ref thermal on end -- device ref heci1 on end -+ device ref heci1 off end - device ref sata on - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ --- -2.47.3 - diff --git a/config/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch b/config/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch new file mode 100644 index 00000000..e99ebdfc --- /dev/null +++ b/config/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch @@ -0,0 +1,68 @@ +From 763c811b82b631ab85e64e150ec70df76b57fd91 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Fri, 20 Feb 2026 01:23:32 +0000 +Subject: [PATCH 46/51] util/ifdtool: option to allow region override + +Signed-off-by: Leah Rowe +--- + util/ifdtool/ifdtool.c | 13 +++++++++++-- + 1 file changed, 11 insertions(+), 2 deletions(-) + +diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c +index 2a5365efe7..c5c3570e6a 100644 +--- a/util/ifdtool/ifdtool.c ++++ b/util/ifdtool/ifdtool.c +@@ -78,6 +78,8 @@ static unsigned int max_regions = 0; + static int selected_chip = 0; + static int platform = -1; + ++static int ignore_region_override = 0; ++ + static const struct region_name region_names[MAX_REGIONS] = { + { "Flash Descriptor", "fd", "flashregion_0_flashdescriptor.bin", "SI_DESC" }, + { "BIOS", "bios", "flashregion_1_bios.bin", "SI_BIOS" }, +@@ -2094,7 +2096,9 @@ static void new_layout(const char *filename, char *image, int size, + } + + for (j = i + 1; j < max_regions; j++) { +- if (regions_collide(&new_regions[i], &new_regions[j])) { ++ if (ignore_region_override) { ++ printf("Ignoring region overlap by user's will.\n"); ++ } else if (regions_collide(&new_regions[i], &new_regions[j])) { + fprintf(stderr, "Regions would overlap:\n"); + + /* See which string is longer and make sure we pad the shorter one */ +@@ -2107,6 +2111,7 @@ static void new_layout(const char *filename, char *image, int size, + new_regions[i].base, new_regions[i].limit); + fprintf(stderr, " %*s : %x-%x\n", padding, region_name(j), + new_regions[j].base, new_regions[j].limit); ++ + exit(EXIT_FAILURE); + } + } +@@ -2363,10 +2368,11 @@ int main(int argc, char *argv[]) + {"newvalue", 1, NULL, 'V'}, + {"topswapsize", 1, NULL, 'T'}, + {"nuke", 1, NULL, 'N'}, ++ {"ignore-region-overlap", 0, NULL, 'I'}, + {0, 0, 0, 0} + }; + +- while ((opt = getopt_long(argc, argv, "S:V:df:F:D:C:M:xi:n:O:s:p:T:elrugEcvth?", ++ while ((opt = getopt_long(argc, argv, "I:S:V:df:F:D:C:M:xi:n:O:s:p:T:elrugEcvth?", + long_options, &option_index)) != EOF) { + switch (opt) { + case 'd': +@@ -2610,6 +2616,9 @@ int main(int argc, char *argv[]) + } + mode_nuke = 1; + break; ++ case 'I': ++ ignore_region_override = 1; ++ break; + case 'v': + print_version(); + exit(EXIT_SUCCESS); +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch b/config/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch new file mode 100644 index 00000000..59eeedee --- /dev/null +++ b/config/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch @@ -0,0 +1,44 @@ +From 3e12bbbac3b15803de4053f8983dc908029832ac Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Fri, 20 Feb 2026 19:31:19 +0000 +Subject: [PATCH 47/51] me_cleaner: don't modify if -k is used + +don't remove *anything*. in libreboot, we only +ever use -k when we werely want to extract the +ME, but otherwise not modify it. this is because +we rely on bruteforce, detecting when me.bin is +found based on mecleaner validation. + +this way, we can much more reliable get the ME +images. + +Signed-off-by: Leah Rowe +--- + util/me_cleaner/me_cleaner.py | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py +index 228bac899f..269aa4ad04 100755 +--- a/util/me_cleaner/me_cleaner.py ++++ b/util/me_cleaner/me_cleaner.py +@@ -677,7 +677,7 @@ if __name__ == "__main__": + # ME 6 Ignition: wipe everything + me6_ignition = False + if not args.check and not args.soft_disable_only and \ +- variant == "ME" and version[0] == 6: ++ variant == "ME" and version[0] == 6 and not args.keep_modules: + mef.seek(ftpr_offset + 0x20) + num_modules = unpack(" -Date: Fri, 20 Feb 2026 01:23:32 +0000 -Subject: [PATCH 47/51] util/ifdtool: option to allow region override - -Signed-off-by: Leah Rowe ---- - util/ifdtool/ifdtool.c | 13 +++++++++++-- - 1 file changed, 11 insertions(+), 2 deletions(-) - -diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index 2a5365efe7..c5c3570e6a 100644 ---- a/util/ifdtool/ifdtool.c -+++ b/util/ifdtool/ifdtool.c -@@ -78,6 +78,8 @@ static unsigned int max_regions = 0; - static int selected_chip = 0; - static int platform = -1; - -+static int ignore_region_override = 0; -+ - static const struct region_name region_names[MAX_REGIONS] = { - { "Flash Descriptor", "fd", "flashregion_0_flashdescriptor.bin", "SI_DESC" }, - { "BIOS", "bios", "flashregion_1_bios.bin", "SI_BIOS" }, -@@ -2094,7 +2096,9 @@ static void new_layout(const char *filename, char *image, int size, - } - - for (j = i + 1; j < max_regions; j++) { -- if (regions_collide(&new_regions[i], &new_regions[j])) { -+ if (ignore_region_override) { -+ printf("Ignoring region overlap by user's will.\n"); -+ } else if (regions_collide(&new_regions[i], &new_regions[j])) { - fprintf(stderr, "Regions would overlap:\n"); - - /* See which string is longer and make sure we pad the shorter one */ -@@ -2107,6 +2111,7 @@ static void new_layout(const char *filename, char *image, int size, - new_regions[i].base, new_regions[i].limit); - fprintf(stderr, " %*s : %x-%x\n", padding, region_name(j), - new_regions[j].base, new_regions[j].limit); -+ - exit(EXIT_FAILURE); - } - } -@@ -2363,10 +2368,11 @@ int main(int argc, char *argv[]) - {"newvalue", 1, NULL, 'V'}, - {"topswapsize", 1, NULL, 'T'}, - {"nuke", 1, NULL, 'N'}, -+ {"ignore-region-overlap", 0, NULL, 'I'}, - {0, 0, 0, 0} - }; - -- while ((opt = getopt_long(argc, argv, "S:V:df:F:D:C:M:xi:n:O:s:p:T:elrugEcvth?", -+ while ((opt = getopt_long(argc, argv, "I:S:V:df:F:D:C:M:xi:n:O:s:p:T:elrugEcvth?", - long_options, &option_index)) != EOF) { - switch (opt) { - case 'd': -@@ -2610,6 +2616,9 @@ int main(int argc, char *argv[]) - } - mode_nuke = 1; - break; -+ case 'I': -+ ignore_region_override = 1; -+ break; - case 'v': - print_version(); - exit(EXIT_SUCCESS); --- -2.47.3 - diff --git a/config/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch b/config/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch new file mode 100644 index 00000000..7703b722 --- /dev/null +++ b/config/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch @@ -0,0 +1,600 @@ +From 6f301fe881df4ed8759bf5b16d59d530798fee30 Mon Sep 17 00:00:00 2001 +From: Kat Inskip +Date: Tue, 17 Feb 2026 16:18:15 -0800 +Subject: [PATCH 48/51] mb/lenovo/sklkbl: Add Lenovo Thinkpad X270 as a variant + +This machine is somewhat dissimilar from the X280 in the PCIe allocations in the overridetree. It also lacks soldered RAM, having a single SODIMM slot. + +This port was based upon the work done by Johann C Rode for the X280 and the VBT and hda verbs were obtained from that work, not obtained separately. GPIO ports and PCI-e allocations have been checked against schematics after editing. + +Functionality has been validated on a ThinkPad X270 with machine type model 20HMS2WU03 with 16GB onboard RAM and i5-7300U CPU. The laptop has been tested running libreboot, booting Guix via GRUB payload. A check of the hardware shows no issues (video, wifi, wired ethernet, reboot, sleep, NVMe). + +An untested variety allowing for a Skylake CPU (for 20K5 and 20K6) has been included. +--- + src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 14 ++ + .../lenovo/sklkbl_thinkpad/Kconfig.name | 3 + + .../sklkbl_thinkpad/variants/x270/data.vbt | Bin 0 -> 6144 bytes + .../variants/x270/gma-mainboard.ads | 19 ++ + .../sklkbl_thinkpad/variants/x270/gpio.c | 200 ++++++++++++++++++ + .../sklkbl_thinkpad/variants/x270/hda_verb.c | 124 +++++++++++ + .../variants/x270/memory_init_params.c | 19 ++ + .../variants/x270/overridetree.cb | 89 ++++++++ + 8 files changed, 468 insertions(+) + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +index 9d4b5f4965..1aaef40a0c 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +@@ -59,6 +59,16 @@ config BOARD_LENOVO_X280 + select SOC_INTEL_KABYLAKE + select HAVE_SPD_IN_CBFS + ++config BOARD_LENOVO_X270_20K6 ++ bool ++ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON ++ select SOC_INTEL_SKYLAKE ++ ++config BOARD_LENOVO_X270_20HM ++ bool ++ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON ++ select SOC_INTEL_KABYLAKE ++ + if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON + + config MAINBOARD_DIR +@@ -70,6 +80,8 @@ config VARIANT_DIR + default "t480s" if BOARD_LENOVO_T480S + default "t580" if BOARD_LENOVO_T580 + default "x280" if BOARD_LENOVO_X280 ++ default "x270" if BOARD_LENOVO_X270_20HM ++ default "x270" if BOARD_LENOVO_X270_20K6 + + config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" +@@ -80,6 +92,8 @@ config MAINBOARD_PART_NUMBER + default "T480s" if BOARD_LENOVO_T480S + default "T580" if BOARD_LENOVO_T580 + default "X280" if BOARD_LENOVO_X280 ++ default "X270" if BOARD_LENOVO_X270_20HM ++ default "X270" if BOARD_LENOVO_X270_20K6 + + config CBFS_SIZE + default 0x900000 +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name +index 1d2888840f..43f9296bc5 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name +@@ -14,3 +14,6 @@ config BOARD_LENOVO_T580 + + config BOARD_LENOVO_X280 + bool "ThinkPad X280" ++ ++config BOARD_LENOVO_X270_20HM ++ bool "ThinkPad X270" +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..bfb312850e0ab4ea834c535df35edb45834ed248 +GIT binary patch +literal 6144 +zcmeHKUu;ul6hF83w!Qs&FT30g8FkDf5a4S-84?3TW@j;APe}bIBew+?D_HG5sZf-7&vkyok@=# +z8c(ONZ(wf#4P2Q8j}K;2xbOJT;q+(=8en9Nz8wwCI}kNrqtD;ir1>5vxw&Phzs2{M +z%))J*^Nkaf-o`vHErAoDN*Y&A{MBB|1XA+35B93JbHvvt;HaeY7Ec#IkF@Xxj@ +zP6k(;H@P#F3nedGs=JfjzpYa!OobkwSsK#P$I2^BlEsV4e37vB4$G)q{*Nk!R-c0tBVQz1gd +z3e(o>A@DI1+dL($vl6C>0P5ZV{-g^pxYUnb>@yes;8K5cv0EIue9 +zGkl+^pEC9(!=IS?2V-_OZgs0qxY=Ge4!PAyH+#j6AGy^p-0ZR&e|4+8#AFGZCACdr +zF$s@L>dO*)UBXW!^=pZJE8*{w>Xz9W8F$NSx6GcD@g-S3E3@;mT(8=*w(DGW^(yn4 +zAdX73_atnRS>NOos_hk9XyacxDE>*#THX@!3ERpD`3eMIq6WR$s^UQVC#{1Gq^xt7 +zU?8;e8r(gGm_M5z*|kA$YW)zZ-l2VHoqv+IZZ{Mr6cJz<1g##<^?;^pBXkQfsMbG8 +zj)o*n*gYj7Okj_PE?l=Ea5?ktR3gF$jT6^lfz{96(n%>cxN^_?5@v=|=~qd!SZp&lSg_nlhO)&rS-Zlsuej$mNrsT3tiG@m({M +zLe6DKG@7OK!rMxtIkS-v>J2YzEOK;RC4{_vs)Sy=U6;SoGqpjBpI>WunFu_%4N1}+ +zr66ea`laMlN~`X%R;)1}c-lG)1mlXaawb#jKo7uXt@_M-9(a%~1Ur_1aKi)nIIh(s +zEo69Ey~xpeG&5 +I4@?IB2821pg#Z8m + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads +new file mode 100644 +index 0000000000..fcfbd75a92 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads +@@ -0,0 +1,19 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (eDP, ++ DP1, ++ DP2, ++ HDMI1, ++ HDMI2, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c +new file mode 100644 +index 0000000000..ec5db9c53c +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c +@@ -0,0 +1,200 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include "../../variant.h" ++ ++static const struct pad_config gpio_table[] = { ++ /* ------- GPIO Community 0 ------- */ ++ ++ /* ------- GPIO Group GPP_A ------- */ ++ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */ ++ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */ ++ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */ ++ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */ ++ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */ ++ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */ ++ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */ ++ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */ ++ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */ ++ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */ ++ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */ ++ PAD_NC(GPP_A11, NONE), ++ PAD_NC(GPP_A12, NONE), /* BM_BUSY#/ISH_GP6 */ ++ PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */ ++ PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */ ++ PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSACK*/ ++ PAD_NC(GPP_A16, NONE), ++ PAD_NC(GPP_A17, NONE), ++ PAD_NC(GPP_A18, NONE), /* ISH_GP0 */ ++ PAD_NC(GPP_A19, NONE), /* ISH_GP1 */ ++ PAD_NC(GPP_A20, NONE), /* ISH_GP2 */ ++ PAD_NC(GPP_A21, NONE), /* ISH_GP3 */ ++ PAD_NC(GPP_A22, NONE), /* ISH_GP4 */ ++ PAD_NC(GPP_A23, NONE), /* ISH_GP5 */ ++ ++ /* ------- GPIO Group GPP_B ------- */ ++ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ ++ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ ++ PAD_NC(GPP_B2, NONE), ++ PAD_NC(GPP_B3, NONE), ++ PAD_NC(GPP_B4, NONE), ++ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (Card Reader / SD) */ ++ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE1 (WLAN) */ ++ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE2 (GBE) */ ++ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (NVMe) */ ++ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), ++ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WWAN) */ ++ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* -EXT_PWR_GATE */ ++ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */ ++ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */ ++ PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */ ++ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */ ++ PAD_NC(GPP_B16, NONE), /* GSPIO0_CLK */ ++ PAD_NC(GPP_B17, NONE), ++ PAD_NC(GPP_B18, NONE), ++ PAD_NC(GPP_B19, NONE), ++ PAD_NC(GPP_B20, NONE), ++ PAD_NC(GPP_B21, NONE), ++ PAD_NC(GPP_B22, NONE), ++ PAD_NC(GPP_B23, NONE), ++ ++ /* ------- GPIO Community 1 ------- */ ++ ++ /* ------- GPIO Group GPP_C ------- */ ++ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ ++ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ ++ PAD_NC(GPP_C2, NONE), /* -SMBALERT */ ++ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */ ++ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ ++ PAD_NC(GPP_C5, NONE), ++ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */ ++ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */ ++ PAD_NC(GPP_C8, NONE), ++ PAD_NC(GPP_C9, NONE), ++ PAD_NC(GPP_C10, NONE), ++ PAD_NC(GPP_C11, NONE), ++ PAD_NC(GPP_C12, NONE), ++ PAD_NC(GPP_C13, NONE), ++ PAD_NC(GPP_C14, NONE), ++ PAD_NC(GPP_C15, NONE), ++ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */ ++ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */ ++ PAD_NC(GPP_C18, NONE), ++ PAD_NC(GPP_C19, NONE), ++ PAD_NC(GPP_C20, NONE), ++ PAD_NC(GPP_C21, NONE), /* X280: TBT_FORCE_PWR X270: INT#_TYPEC_CPU */ ++ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ ++ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ ++ ++ /* ------- GPIO Group GPP_D ------- */ ++ PAD_NC(GPP_D0, NONE), ++ PAD_NC(GPP_D1, NONE), ++ PAD_NC(GPP_D2, NONE), ++ PAD_NC(GPP_D3, NONE), ++ PAD_NC(GPP_D4, NONE), ++ PAD_NC(GPP_D5, NONE), ++ PAD_NC(GPP_D6, NONE), ++ PAD_NC(GPP_D7, NONE), ++ PAD_NC(GPP_D8, NONE), ++ PAD_NC(GPP_D9, UP_20K), ++ PAD_NC(GPP_D10, NONE), ++ PAD_NC(GPP_D11, UP_20K), ++ PAD_NC(GPP_D12, UP_20K), ++ PAD_NC(GPP_D13, NONE), ++ PAD_NC(GPP_D14, NONE), ++ PAD_NC(GPP_D15, NONE), ++ PAD_NC(GPP_D16, NONE), ++ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */ ++ PAD_NC(GPP_D18, NONE), ++ PAD_NC(GPP_D19, NONE), ++ PAD_NC(GPP_D20, NONE), ++ PAD_NC(GPP_D21, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */ ++ PAD_NC(GPP_D23, NONE), ++ ++ /* ------- GPIO Group GPP_E ------- */ ++ PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */ ++ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -SATA1_DTCT */ ++ PAD_NC(GPP_E2, NONE), ++ PAD_NC(GPP_E3, NONE), /* X280: -TBT_PLUG_EVENT X270: ? */ ++ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */ ++ PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1), /* SATA1_DEVSLP */ ++ PAD_NC(GPP_E6, NONE), ++ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* -WWAN_DISABLE */ ++ PAD_NC(GPP_E8, NONE), ++ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */ ++ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */ ++ PAD_NC(GPP_E11, NONE), ++ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */ ++ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */ ++ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */ ++ PAD_NC(GPP_E15, NONE), ++ PAD_NC(GPP_E16, NONE), ++ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ ++ PAD_NC(GPP_E18, NONE), ++ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), ++ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */ ++ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */ ++ PAD_NC(GPP_E22, NONE), ++ PAD_NC(GPP_E23, NONE), ++ ++ /* ------- GPIO Community 2 ------- */ ++ ++ /* -------- GPIO Group GPD -------- */ ++ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */ ++ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */ ++ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */ ++ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */ ++ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */ ++ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */ ++ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */ ++ PAD_NC(GPD7, NONE), ++ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */ ++ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */ ++ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */ ++ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ ++ ++ /* ------- GPIO Community 3 ------- */ ++ ++ /* ------- GPIO Group GPP_F ------- */ ++ PAD_NC(GPP_F0, NONE), /* NFC_ACTIVE */ ++ PAD_NC(GPP_F1, NONE), ++ PAD_NC(GPP_F2, NONE), ++ PAD_NC(GPP_F3, NONE), ++ PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */ ++ PAD_NC(GPP_F5, UP_20K), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, RSMRST, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, RSMRST, OFF, ACPI), /* -INT_MIC_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, RSMRST, OFF, ACPI), /* PLANARID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, RSMRST, OFF, ACPI), /* PLANARID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, RSMRST, OFF, ACPI), /* PLANARID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, RSMRST, OFF, ACPI), /* PLANARID3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID4 */ ++ PAD_NC(GPP_F21, UP_20K), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, RSMRST, OFF, ACPI), /* -TAMPER_SW_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, RSMRST, OFF, ACPI), /* -SC_DTCT */ ++ ++ /* ------- GPIO Group GPP_G ------- */ ++ PAD_NC(GPP_G0, NONE), /* SD_CMD */ ++ PAD_NC(GPP_G1, NONE), /* SD_DATA0 */ ++ PAD_NC(GPP_G2, NONE), /* SD_DATA1 */ ++ PAD_NC(GPP_G3, NONE), /* SD_DATA2 */ ++ PAD_NC(GPP_G4, NONE), /* X280: TBT_RTD3_PWR_EN X270: SD_DATA3 */ ++ PAD_NC(GPP_G5, NONE), /* X280: TBT_FORCE_USB_PWR X270: SD_CD# */ ++ PAD_NC(GPP_G6, NONE), /* X280: -TBT_PERST X270: SD_CLK */ ++ PAD_NC(GPP_G7, NONE), /* X280: -TBT_PCIE_WAKE X270: SD_WP */ ++ ++}; ++ ++void variant_config_gpios(void) ++{ ++ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c +new file mode 100644 +index 0000000000..089e605eaf +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c +@@ -0,0 +1,124 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ 0x10ec0257, // Vendor/Device ID: Realtek ALC257 ++ 0x17aa2256, // Subsystem ID ++ 18, ++ AZALIA_SUBVENDOR(0, 0x17aa2256), ++ ++ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_MIC_IN, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_MIC_IN, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 3, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_HP_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 15 ++ )), ++ ++ //==========Widget node 0x20 - 0 :Hidden register SW reset ++ 0x0205001A, ++ 0x0204C003, ++ 0x0205001A, ++ 0x0204C003, ++ 0x05850000, ++ 0x0584F880, ++ 0x05850000, ++ 0x0584F880, ++ //==========Widget node 0x20 - 1 : ClassD 2W ++ 0x02050038, ++ 0x02048981, ++ 0x0205001B, ++ 0x02040A4B, ++ //==========Widget node 0x20 - 2 ++ 0x0205003C, ++ 0x02043154, ++ 0x0205003C, ++ 0x02043114, ++ //==========Widget node 0x20 - 3 : ++ 0x02050046, ++ 0x02040004, ++ 0x05750003, ++ 0x057409A3, ++ //==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD ++ 0x02050009, ++ 0x02046003, ++ 0x0205000A, ++ 0x02047770, ++ //==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB) ++ 0x02050037, ++ 0x0204FE15, ++ 0x02050030, ++ 0x02049004, ++ ++ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI ++ 0x80860101, // Subsystem ID ++ 4, ++ AZALIA_SUBVENDOR(2, 0x80860101), ++ ++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++}; ++ ++const u32 pc_beep_verbs[] = {}; ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c +new file mode 100644 +index 0000000000..a2317c026d +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c +@@ -0,0 +1,19 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_memory_init_params(FSPM_UPD *mupd) ++{ ++ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; ++ mem_cfg->DqPinsInterleaved = false; /* DDR_DQ probably not in interleave mode */ ++ mem_cfg->CaVrefConfig = 1; /* VREF_CA to CH_A */ ++ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; ++ ++ /* Get SPD for memory slots */ ++ struct spd_block blk = { .addr_map = { 0x50 } }; ++ get_spd_smbus(&blk); ++ dump_spd_info(&blk); ++ ++ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb +new file mode 100644 +index 0000000000..3191cdfac5 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb +@@ -0,0 +1,89 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++chip soc/intel/skylake ++ device domain 0 on ++ device ref south_xhci on ++ register "usb2_ports" = "{ ++ [0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on) ++ [1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A) ++ [2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot) ++ [3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB docking station) ++ [4] = USB2_PORT_MID(OC_SKIP), // JIRCAM (IR camera) ++ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB) ++ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB) ++ [7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam) ++ [8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader) ++ [9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel) ++ }" ++ register "usb3_ports" = "{ ++ [0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on) ++ [1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A) ++ [2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader) ++ [3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSB3 (USB docking station) ++ }" ++ end ++ ++ # PCIe ++ # PCIe Controller 1 - 1x2 + 2x1 ++ # PCIE 1 - RP1 - Media / SD - CLKOUT0 - CLKREQ0 ++ # PCIE 2 - USB3 Port ++ # PCIE 3 - RP3 - WiGig - CLKOUT1 - CLKREQ1 ++ # PCIE 3 - RP3 - WLAN - CLKOUT2 - CLKREQ2 ++ # PCIE 4 - GbE - GbE - CLKOUT3 - CLKREQ3 ++ # PCIe Controller 2 - 1x4 ++ # PCIE 5 - RP5 - NVMe - CLKOUT4 - CLKREQ4 ++ # PCIe Controller 3 - 4x1 ++ # PCIE 7 - RP8 - WWAN - CLKOUT5 - CLKREQ5 ++ # PCIE 8 - Optane ++ ++ # Media / SD - x2 ++ device ref pcie_rp1 on ++ register "PcieRpClkReqSupport[0]" = "true" ++ register "PcieRpClkReqNumber[0]" = "0" ++ register "PcieRpClkSrcNumber[0]" = "0" ++ register "PcieRpAdvancedErrorReporting[0]" = "true" ++ register "PcieRpHotPlug[0]" = "true" ++ end ++ ++ # M.2 WLAN x1 ++ device ref pcie_rp3 on ++ register "PcieRpClkReqSupport[2]" = "true" ++ register "PcieRpClkReqNumber[2]" = "2" ++ register "PcieRpClkSrcNumber[2]" = "2" ++ register "PcieRpAdvancedErrorReporting[2]" = "true" ++ register "PcieRpLtrEnable[2]" = "true" ++ smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X" ++ end ++ ++ # Ethernet (clobbers RP4) ++ device ref gbe on ++ register "LanClkReqSupported" = "true" ++ register "LanClkReqNumber" = "3" ++ register "PcieRpClkReqNumber[3]" = "3" ++ register "PcieRpClkSrcNumber[3]" = "3" ++ register "EnableLanLtr" = "true" ++ register "EnableLanK1Off" = "true" ++ end ++ ++ # M.2 2280 SSD - x4 (RP9) ++ device ref pcie_rp5 on ++ register "PcieRpClkReqSupport[4]" = "true" ++ register "PcieRpClkReqNumber[4]" = "4" ++ register "PcieRpClkSrcNumber[4]" = "4" ++ register "PcieRpAdvancedErrorReporting[4]" = "true" ++ register "PcieRpLtrEnable[4]" = "true" ++ register "PcieRpHotPlug[4]" = "false" ++ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" ++ end ++ ++ # M.2 WWAN x1 ++ device ref pcie_rp8 on ++ register "PcieRpClkReqSupport[7]" = "true" ++ register "PcieRpClkReqNumber[7]" = "5" ++ register "PcieRpClkSrcNumber[7]" = "5" ++ register "PcieRpAdvancedErrorReporting[7]" = "true" ++ register "PcieRpLtrEnable[7]" = "true" ++ smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X" ++ end ++ end ++end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0048-me_cleaner-don-t-modify-if-k-is-used.patch b/config/coreboot/default/patches/0048-me_cleaner-don-t-modify-if-k-is-used.patch deleted file mode 100644 index db705b60..00000000 --- a/config/coreboot/default/patches/0048-me_cleaner-don-t-modify-if-k-is-used.patch +++ /dev/null @@ -1,44 +0,0 @@ -From fb4bc4ed6e1fca747e54a34127ca927cb70318ad Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Fri, 20 Feb 2026 19:31:19 +0000 -Subject: [PATCH 48/51] me_cleaner: don't modify if -k is used - -don't remove *anything*. in libreboot, we only -ever use -k when we werely want to extract the -ME, but otherwise not modify it. this is because -we rely on bruteforce, detecting when me.bin is -found based on mecleaner validation. - -this way, we can much more reliable get the ME -images. - -Signed-off-by: Leah Rowe ---- - util/me_cleaner/me_cleaner.py | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py -index 228bac899f..269aa4ad04 100755 ---- a/util/me_cleaner/me_cleaner.py -+++ b/util/me_cleaner/me_cleaner.py -@@ -677,7 +677,7 @@ if __name__ == "__main__": - # ME 6 Ignition: wipe everything - me6_ignition = False - if not args.check and not args.soft_disable_only and \ -- variant == "ME" and version[0] == 6: -+ variant == "ME" and version[0] == 6 and not args.keep_modules: - mef.seek(ftpr_offset + 0x20) - num_modules = unpack(" -Date: Tue, 17 Feb 2026 16:18:15 -0800 -Subject: [PATCH 49/51] mb/lenovo/sklkbl: Add Lenovo Thinkpad X270 as a variant - -This machine is somewhat dissimilar from the X280 in the PCIe allocations in the overridetree. It also lacks soldered RAM, having a single SODIMM slot. - -This port was based upon the work done by Johann C Rode for the X280 and the VBT and hda verbs were obtained from that work, not obtained separately. GPIO ports and PCI-e allocations have been checked against schematics after editing. - -Functionality has been validated on a ThinkPad X270 with machine type model 20HMS2WU03 with 16GB onboard RAM and i5-7300U CPU. The laptop has been tested running libreboot, booting Guix via GRUB payload. A check of the hardware shows no issues (video, wifi, wired ethernet, reboot, sleep, NVMe). - -An untested variety allowing for a Skylake CPU (for 20K5 and 20K6) has been included. ---- - src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 14 ++ - .../lenovo/sklkbl_thinkpad/Kconfig.name | 3 + - .../sklkbl_thinkpad/variants/x270/data.vbt | Bin 0 -> 6144 bytes - .../variants/x270/gma-mainboard.ads | 19 ++ - .../sklkbl_thinkpad/variants/x270/gpio.c | 200 ++++++++++++++++++ - .../sklkbl_thinkpad/variants/x270/hda_verb.c | 124 +++++++++++ - .../variants/x270/memory_init_params.c | 19 ++ - .../variants/x270/overridetree.cb | 89 ++++++++ - 8 files changed, 468 insertions(+) - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -index 9d4b5f4965..1aaef40a0c 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -@@ -59,6 +59,16 @@ config BOARD_LENOVO_X280 - select SOC_INTEL_KABYLAKE - select HAVE_SPD_IN_CBFS - -+config BOARD_LENOVO_X270_20K6 -+ bool -+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON -+ select SOC_INTEL_SKYLAKE -+ -+config BOARD_LENOVO_X270_20HM -+ bool -+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON -+ select SOC_INTEL_KABYLAKE -+ - if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON - - config MAINBOARD_DIR -@@ -70,6 +80,8 @@ config VARIANT_DIR - default "t480s" if BOARD_LENOVO_T480S - default "t580" if BOARD_LENOVO_T580 - default "x280" if BOARD_LENOVO_X280 -+ default "x270" if BOARD_LENOVO_X270_20HM -+ default "x270" if BOARD_LENOVO_X270_20K6 - - config OVERRIDE_DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -@@ -80,6 +92,8 @@ config MAINBOARD_PART_NUMBER - default "T480s" if BOARD_LENOVO_T480S - default "T580" if BOARD_LENOVO_T580 - default "X280" if BOARD_LENOVO_X280 -+ default "X270" if BOARD_LENOVO_X270_20HM -+ default "X270" if BOARD_LENOVO_X270_20K6 - - config CBFS_SIZE - default 0x900000 -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name -index 1d2888840f..43f9296bc5 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name -@@ -14,3 +14,6 @@ config BOARD_LENOVO_T580 - - config BOARD_LENOVO_X280 - bool "ThinkPad X280" -+ -+config BOARD_LENOVO_X270_20HM -+ bool "ThinkPad X270" -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..bfb312850e0ab4ea834c535df35edb45834ed248 -GIT binary patch -literal 6144 -zcmeHKUu;ul6hF83w!Qs&FT30g8FkDf5a4S-84?3TW@j;APe}bIBew+?D_HG5sZf-7&vkyok@=# -z8c(ONZ(wf#4P2Q8j}K;2xbOJT;q+(=8en9Nz8wwCI}kNrqtD;ir1>5vxw&Phzs2{M -z%))J*^Nkaf-o`vHErAoDN*Y&A{MBB|1XA+35B93JbHvvt;HaeY7Ec#IkF@Xxj@ -zP6k(;H@P#F3nedGs=JfjzpYa!OobkwSsK#P$I2^BlEsV4e37vB4$G)q{*Nk!R-c0tBVQz1gd -z3e(o>A@DI1+dL($vl6C>0P5ZV{-g^pxYUnb>@yes;8K5cv0EIue9 -zGkl+^pEC9(!=IS?2V-_OZgs0qxY=Ge4!PAyH+#j6AGy^p-0ZR&e|4+8#AFGZCACdr -zF$s@L>dO*)UBXW!^=pZJE8*{w>Xz9W8F$NSx6GcD@g-S3E3@;mT(8=*w(DGW^(yn4 -zAdX73_atnRS>NOos_hk9XyacxDE>*#THX@!3ERpD`3eMIq6WR$s^UQVC#{1Gq^xt7 -zU?8;e8r(gGm_M5z*|kA$YW)zZ-l2VHoqv+IZZ{Mr6cJz<1g##<^?;^pBXkQfsMbG8 -zj)o*n*gYj7Okj_PE?l=Ea5?ktR3gF$jT6^lfz{96(n%>cxN^_?5@v=|=~qd!SZp&lSg_nlhO)&rS-Zlsuej$mNrsT3tiG@m({M -zLe6DKG@7OK!rMxtIkS-v>J2YzEOK;RC4{_vs)Sy=U6;SoGqpjBpI>WunFu_%4N1}+ -zr66ea`laMlN~`X%R;)1}c-lG)1mlXaawb#jKo7uXt@_M-9(a%~1Ur_1aKi)nIIh(s -zEo69Ey~xpeG&5 -I4@?IB2821pg#Z8m - -literal 0 -HcmV?d00001 - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads -new file mode 100644 -index 0000000000..fcfbd75a92 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads -@@ -0,0 +1,19 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ (eDP, -+ DP1, -+ DP2, -+ HDMI1, -+ HDMI2, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c -new file mode 100644 -index 0000000000..ec5db9c53c ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c -@@ -0,0 +1,200 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include "../../variant.h" -+ -+static const struct pad_config gpio_table[] = { -+ /* ------- GPIO Community 0 ------- */ -+ -+ /* ------- GPIO Group GPP_A ------- */ -+ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */ -+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */ -+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */ -+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */ -+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */ -+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */ -+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */ -+ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */ -+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */ -+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */ -+ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */ -+ PAD_NC(GPP_A11, NONE), -+ PAD_NC(GPP_A12, NONE), /* BM_BUSY#/ISH_GP6 */ -+ PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */ -+ PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */ -+ PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSACK*/ -+ PAD_NC(GPP_A16, NONE), -+ PAD_NC(GPP_A17, NONE), -+ PAD_NC(GPP_A18, NONE), /* ISH_GP0 */ -+ PAD_NC(GPP_A19, NONE), /* ISH_GP1 */ -+ PAD_NC(GPP_A20, NONE), /* ISH_GP2 */ -+ PAD_NC(GPP_A21, NONE), /* ISH_GP3 */ -+ PAD_NC(GPP_A22, NONE), /* ISH_GP4 */ -+ PAD_NC(GPP_A23, NONE), /* ISH_GP5 */ -+ -+ /* ------- GPIO Group GPP_B ------- */ -+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ -+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ -+ PAD_NC(GPP_B2, NONE), -+ PAD_NC(GPP_B3, NONE), -+ PAD_NC(GPP_B4, NONE), -+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (Card Reader / SD) */ -+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE1 (WLAN) */ -+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE2 (GBE) */ -+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (NVMe) */ -+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WWAN) */ -+ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* -EXT_PWR_GATE */ -+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */ -+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */ -+ PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */ -+ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */ -+ PAD_NC(GPP_B16, NONE), /* GSPIO0_CLK */ -+ PAD_NC(GPP_B17, NONE), -+ PAD_NC(GPP_B18, NONE), -+ PAD_NC(GPP_B19, NONE), -+ PAD_NC(GPP_B20, NONE), -+ PAD_NC(GPP_B21, NONE), -+ PAD_NC(GPP_B22, NONE), -+ PAD_NC(GPP_B23, NONE), -+ -+ /* ------- GPIO Community 1 ------- */ -+ -+ /* ------- GPIO Group GPP_C ------- */ -+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ -+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ -+ PAD_NC(GPP_C2, NONE), /* -SMBALERT */ -+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */ -+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ -+ PAD_NC(GPP_C5, NONE), -+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */ -+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */ -+ PAD_NC(GPP_C8, NONE), -+ PAD_NC(GPP_C9, NONE), -+ PAD_NC(GPP_C10, NONE), -+ PAD_NC(GPP_C11, NONE), -+ PAD_NC(GPP_C12, NONE), -+ PAD_NC(GPP_C13, NONE), -+ PAD_NC(GPP_C14, NONE), -+ PAD_NC(GPP_C15, NONE), -+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */ -+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */ -+ PAD_NC(GPP_C18, NONE), -+ PAD_NC(GPP_C19, NONE), -+ PAD_NC(GPP_C20, NONE), -+ PAD_NC(GPP_C21, NONE), /* X280: TBT_FORCE_PWR X270: INT#_TYPEC_CPU */ -+ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ -+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ -+ -+ /* ------- GPIO Group GPP_D ------- */ -+ PAD_NC(GPP_D0, NONE), -+ PAD_NC(GPP_D1, NONE), -+ PAD_NC(GPP_D2, NONE), -+ PAD_NC(GPP_D3, NONE), -+ PAD_NC(GPP_D4, NONE), -+ PAD_NC(GPP_D5, NONE), -+ PAD_NC(GPP_D6, NONE), -+ PAD_NC(GPP_D7, NONE), -+ PAD_NC(GPP_D8, NONE), -+ PAD_NC(GPP_D9, UP_20K), -+ PAD_NC(GPP_D10, NONE), -+ PAD_NC(GPP_D11, UP_20K), -+ PAD_NC(GPP_D12, UP_20K), -+ PAD_NC(GPP_D13, NONE), -+ PAD_NC(GPP_D14, NONE), -+ PAD_NC(GPP_D15, NONE), -+ PAD_NC(GPP_D16, NONE), -+ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */ -+ PAD_NC(GPP_D18, NONE), -+ PAD_NC(GPP_D19, NONE), -+ PAD_NC(GPP_D20, NONE), -+ PAD_NC(GPP_D21, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */ -+ PAD_NC(GPP_D23, NONE), -+ -+ /* ------- GPIO Group GPP_E ------- */ -+ PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */ -+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -SATA1_DTCT */ -+ PAD_NC(GPP_E2, NONE), -+ PAD_NC(GPP_E3, NONE), /* X280: -TBT_PLUG_EVENT X270: ? */ -+ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */ -+ PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1), /* SATA1_DEVSLP */ -+ PAD_NC(GPP_E6, NONE), -+ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* -WWAN_DISABLE */ -+ PAD_NC(GPP_E8, NONE), -+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */ -+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */ -+ PAD_NC(GPP_E11, NONE), -+ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */ -+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */ -+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */ -+ PAD_NC(GPP_E15, NONE), -+ PAD_NC(GPP_E16, NONE), -+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ -+ PAD_NC(GPP_E18, NONE), -+ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */ -+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */ -+ PAD_NC(GPP_E22, NONE), -+ PAD_NC(GPP_E23, NONE), -+ -+ /* ------- GPIO Community 2 ------- */ -+ -+ /* -------- GPIO Group GPD -------- */ -+ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */ -+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */ -+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */ -+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */ -+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */ -+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */ -+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */ -+ PAD_NC(GPD7, NONE), -+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */ -+ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */ -+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */ -+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ -+ -+ /* ------- GPIO Community 3 ------- */ -+ -+ /* ------- GPIO Group GPP_F ------- */ -+ PAD_NC(GPP_F0, NONE), /* NFC_ACTIVE */ -+ PAD_NC(GPP_F1, NONE), -+ PAD_NC(GPP_F2, NONE), -+ PAD_NC(GPP_F3, NONE), -+ PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */ -+ PAD_NC(GPP_F5, UP_20K), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, RSMRST, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, RSMRST, OFF, ACPI), /* -INT_MIC_DTCT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, RSMRST, OFF, ACPI), /* PLANARID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, RSMRST, OFF, ACPI), /* PLANARID1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, RSMRST, OFF, ACPI), /* PLANARID2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, RSMRST, OFF, ACPI), /* PLANARID3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID4 */ -+ PAD_NC(GPP_F21, UP_20K), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, RSMRST, OFF, ACPI), /* -TAMPER_SW_DTCT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, RSMRST, OFF, ACPI), /* -SC_DTCT */ -+ -+ /* ------- GPIO Group GPP_G ------- */ -+ PAD_NC(GPP_G0, NONE), /* SD_CMD */ -+ PAD_NC(GPP_G1, NONE), /* SD_DATA0 */ -+ PAD_NC(GPP_G2, NONE), /* SD_DATA1 */ -+ PAD_NC(GPP_G3, NONE), /* SD_DATA2 */ -+ PAD_NC(GPP_G4, NONE), /* X280: TBT_RTD3_PWR_EN X270: SD_DATA3 */ -+ PAD_NC(GPP_G5, NONE), /* X280: TBT_FORCE_USB_PWR X270: SD_CD# */ -+ PAD_NC(GPP_G6, NONE), /* X280: -TBT_PERST X270: SD_CLK */ -+ PAD_NC(GPP_G7, NONE), /* X280: -TBT_PCIE_WAKE X270: SD_WP */ -+ -+}; -+ -+void variant_config_gpios(void) -+{ -+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c -new file mode 100644 -index 0000000000..089e605eaf ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c -@@ -0,0 +1,124 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ 0x10ec0257, // Vendor/Device ID: Realtek ALC257 -+ 0x17aa2256, // Subsystem ID -+ 18, -+ AZALIA_SUBVENDOR(0, 0x17aa2256), -+ -+ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( -+ AZALIA_INTEGRATED, -+ AZALIA_INTERNAL, -+ AZALIA_MIC_IN, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_NO_JACK_PRESENCE_DETECT, -+ 2, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( -+ AZALIA_INTEGRATED, -+ AZALIA_INTERNAL, -+ AZALIA_SPEAKER, -+ AZALIA_OTHER_ANALOG, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_NO_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_MIC_IN, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 3, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_HP_OUT, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 15 -+ )), -+ -+ //==========Widget node 0x20 - 0 :Hidden register SW reset -+ 0x0205001A, -+ 0x0204C003, -+ 0x0205001A, -+ 0x0204C003, -+ 0x05850000, -+ 0x0584F880, -+ 0x05850000, -+ 0x0584F880, -+ //==========Widget node 0x20 - 1 : ClassD 2W -+ 0x02050038, -+ 0x02048981, -+ 0x0205001B, -+ 0x02040A4B, -+ //==========Widget node 0x20 - 2 -+ 0x0205003C, -+ 0x02043154, -+ 0x0205003C, -+ 0x02043114, -+ //==========Widget node 0x20 - 3 : -+ 0x02050046, -+ 0x02040004, -+ 0x05750003, -+ 0x057409A3, -+ //==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD -+ 0x02050009, -+ 0x02046003, -+ 0x0205000A, -+ 0x02047770, -+ //==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB) -+ 0x02050037, -+ 0x0204FE15, -+ 0x02050030, -+ 0x02049004, -+ -+ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI -+ 0x80860101, // Subsystem ID -+ 4, -+ AZALIA_SUBVENDOR(2, 0x80860101), -+ -+ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+}; -+ -+const u32 pc_beep_verbs[] = {}; -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c -new file mode 100644 -index 0000000000..a2317c026d ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c -@@ -0,0 +1,19 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+ -+void mainboard_memory_init_params(FSPM_UPD *mupd) -+{ -+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; -+ mem_cfg->DqPinsInterleaved = false; /* DDR_DQ probably not in interleave mode */ -+ mem_cfg->CaVrefConfig = 1; /* VREF_CA to CH_A */ -+ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; -+ -+ /* Get SPD for memory slots */ -+ struct spd_block blk = { .addr_map = { 0x50 } }; -+ get_spd_smbus(&blk); -+ dump_spd_info(&blk); -+ -+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb -new file mode 100644 -index 0000000000..3191cdfac5 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb -@@ -0,0 +1,89 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+chip soc/intel/skylake -+ device domain 0 on -+ device ref south_xhci on -+ register "usb2_ports" = "{ -+ [0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on) -+ [1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A) -+ [2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot) -+ [3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB docking station) -+ [4] = USB2_PORT_MID(OC_SKIP), // JIRCAM (IR camera) -+ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB) -+ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB) -+ [7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam) -+ [8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader) -+ [9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel) -+ }" -+ register "usb3_ports" = "{ -+ [0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on) -+ [1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A) -+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader) -+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSB3 (USB docking station) -+ }" -+ end -+ -+ # PCIe -+ # PCIe Controller 1 - 1x2 + 2x1 -+ # PCIE 1 - RP1 - Media / SD - CLKOUT0 - CLKREQ0 -+ # PCIE 2 - USB3 Port -+ # PCIE 3 - RP3 - WiGig - CLKOUT1 - CLKREQ1 -+ # PCIE 3 - RP3 - WLAN - CLKOUT2 - CLKREQ2 -+ # PCIE 4 - GbE - GbE - CLKOUT3 - CLKREQ3 -+ # PCIe Controller 2 - 1x4 -+ # PCIE 5 - RP5 - NVMe - CLKOUT4 - CLKREQ4 -+ # PCIe Controller 3 - 4x1 -+ # PCIE 7 - RP8 - WWAN - CLKOUT5 - CLKREQ5 -+ # PCIE 8 - Optane -+ -+ # Media / SD - x2 -+ device ref pcie_rp1 on -+ register "PcieRpClkReqSupport[0]" = "true" -+ register "PcieRpClkReqNumber[0]" = "0" -+ register "PcieRpClkSrcNumber[0]" = "0" -+ register "PcieRpAdvancedErrorReporting[0]" = "true" -+ register "PcieRpHotPlug[0]" = "true" -+ end -+ -+ # M.2 WLAN x1 -+ device ref pcie_rp3 on -+ register "PcieRpClkReqSupport[2]" = "true" -+ register "PcieRpClkReqNumber[2]" = "2" -+ register "PcieRpClkSrcNumber[2]" = "2" -+ register "PcieRpAdvancedErrorReporting[2]" = "true" -+ register "PcieRpLtrEnable[2]" = "true" -+ smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X" -+ end -+ -+ # Ethernet (clobbers RP4) -+ device ref gbe on -+ register "LanClkReqSupported" = "true" -+ register "LanClkReqNumber" = "3" -+ register "PcieRpClkReqNumber[3]" = "3" -+ register "PcieRpClkSrcNumber[3]" = "3" -+ register "EnableLanLtr" = "true" -+ register "EnableLanK1Off" = "true" -+ end -+ -+ # M.2 2280 SSD - x4 (RP9) -+ device ref pcie_rp5 on -+ register "PcieRpClkReqSupport[4]" = "true" -+ register "PcieRpClkReqNumber[4]" = "4" -+ register "PcieRpClkSrcNumber[4]" = "4" -+ register "PcieRpAdvancedErrorReporting[4]" = "true" -+ register "PcieRpLtrEnable[4]" = "true" -+ register "PcieRpHotPlug[4]" = "false" -+ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" -+ end -+ -+ # M.2 WWAN x1 -+ device ref pcie_rp8 on -+ register "PcieRpClkReqSupport[7]" = "true" -+ register "PcieRpClkReqNumber[7]" = "5" -+ register "PcieRpClkSrcNumber[7]" = "5" -+ register "PcieRpAdvancedErrorReporting[7]" = "true" -+ register "PcieRpLtrEnable[7]" = "true" -+ smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X" -+ end -+ end -+end --- -2.47.3 - diff --git a/config/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch b/config/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch new file mode 100644 index 00000000..34f21e0a --- /dev/null +++ b/config/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch @@ -0,0 +1,129 @@ +From 4557102ed2f7e1355cc3a331c6452884458b7a5e Mon Sep 17 00:00:00 2001 +From: Kat Inskip +Date: Sat, 21 Feb 2026 19:48:17 +0000 +Subject: [PATCH 49/51] mb/lenovo/x270: Provide correct vbt and hda_verb + +--- + .../sklkbl_thinkpad/variants/x270/data.vbt | Bin 6144 -> 4449 bytes + .../sklkbl_thinkpad/variants/x270/hda_verb.c | 29 +++++++++--------- + 2 files changed, 15 insertions(+), 14 deletions(-) + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt +index bfb312850e0ab4ea834c535df35edb45834ed248..c6561a9c57e4e600bc0adb5f6679f2f5d6b6c640 100644 +GIT binary patch +delta 1043 +zcmcgq-Afcv6hC)nXFtw-?CgzfEwH0LgQ9&f-Qz1ka^prZC-JMFP=YHJZ{oQls$2s?7a?V`MjktC+ +zmIBAkE35L3T{R08;KY{a0fvRBG?I>!>>E2haF{QO$c=4v8Y8%=?LrDlLIKmZ^Gf5CQN1XgElP&$RejtyZ5 +z##fpUKrO{7px=4oVy};I82ZMAiwFT|EMc$(iBg6qn;Wt%1))HsoGWjGZ6rwfW9y;f +z+P1?LzVFv3072#UoFOjAux+UOm(9&6an}i+$f~@7#c_7}8xbIi0I-AuW05M@qt?NB +zRe{Uu7N`$QfgK@eiP+G~9Av)K5N4SlnO~Vdm|74a%B*D8G8>rf%r0h{d4PGCIT}nO +z1kb>tr{s#a!pI3%9?|1Fclp|1QdQ0P@qX6gB^>l)&nqO<`-*_VTP>kxOWk0S0g$)_YB$m-%5#X9 +zknW*;i1-ZYGfEFJqEnMDyL3$JbV`>Ob-boiL6=W;oYCpKE<*;!3~D!IpMe7goi*fD +z18*Djz>w1hzAjgD~h(eazMzGB3(Uim8EziUhBPY#yb{{-gtq*(v} + +delta 808 +zcmX|e2Y=7&(6 +z1vl8CW+z-x@(%LgW907_fIdYjust^(YddwW|77|83Odly8SQ9J9BnF&$EbTJc{NqB +z8Y0(=dhuwr>(#T5HPpr%yse4n(Ztt0#S21;HymyT1(vJ9HuOD)Uv5yoA$IBhCY^G0 +z(d~;~pIj21x?ibNp&{7!_@YPn0@PYX)d4me@cII*iNKvl04c{p;T8;tmbA>dO!%ck**r) +zYT&6wLA@%NymTDqLC|>RKbP37?tsmjG8Gpd7)9xHCH87_(8_ZjHv|kZZECQLbP;tP`&Ou1y@vPq>VYZ132^`jg_97TGF@)_bR(jv;=h#`x%SaO?%yDb{9 +zsC+JqU`~#!PkzxP< + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c +index 089e605eaf..60289355f8 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c +@@ -3,10 +3,10 @@ + #include + + const u32 cim_verb_data[] = { +- 0x10ec0257, // Vendor/Device ID: Realtek ALC257 +- 0x17aa2256, // Subsystem ID +- 18, +- AZALIA_SUBVENDOR(0, 0x17aa2256), ++ 0x10ec0298, // Vendor/Device ID: Realtek ALC298 ++ 0x17aa5062, // Subsystem ID ++ 19, ++ AZALIA_SUBVENDOR(0, 0x17aa5062), + + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, +@@ -15,7 +15,7 @@ const u32 cim_verb_data[] = { + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, +- 2, 0 ++ 4, 0 + )), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( +@@ -27,28 +27,29 @@ const u32 cim_verb_data[] = { + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, 0 + )), +- AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), +- AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( ++ AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( + AZALIA_JACK, +- AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 3, 0 + )), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), +- AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), +- AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1d, 0x40648605), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( + AZALIA_JACK, +- AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, +- 1, 15 ++ 2, 0 + )), + + //==========Widget node 0x20 - 0 :Hidden register SW reset +@@ -107,7 +108,7 @@ const u32 cim_verb_data[] = { + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, +- 1, 0 ++ 2, 0 + )), + AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( + AZALIA_JACK, +@@ -116,7 +117,7 @@ const u32 cim_verb_data[] = { + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, +- 1, 0 ++ 3, 0 + )), + }; + +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch b/config/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch new file mode 100644 index 00000000..7aa2f609 --- /dev/null +++ b/config/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch @@ -0,0 +1,1530 @@ +From 9c21961d34b4c8c410f657f478de82025124dcab Mon Sep 17 00:00:00 2001 +From: Todd Baker +Date: Thu, 12 Mar 2026 13:12:04 -0400 +Subject: [PATCH 50/51] mb/dell: Add OptiPlex 3040 Micro port + (upstream-compatible) + +Based on the OptiPlex 3050 Micro (same Skylake H110 PCH-H platform). +Key differences from 3050: +- DDR3L SODIMMs (256-byte SPD at 0x50/0x52) +- Intel Pentium G4400T-class CPUs (Skylake only, no Kabylake/Coffeelake) +- Realtek ALC3234 HDA (subsystem ID 0x102806bb) +- VBT: DDI E entry removed (phantom port, causes i915 WARN_ON) +- PCIe root ports rp5/rp8/rp21 enabled (PcieRpEnable removed; use device on/off) +- HECI1 set off to prevent stall when HAP bit is set (ME neutralized) + +Signed-off-by: Todd Baker +--- + src/mainboard/dell/optiplex_3040/Kconfig | 37 ++ + src/mainboard/dell/optiplex_3040/Kconfig.name | 4 + + src/mainboard/dell/optiplex_3040/Makefile.mk | 12 + + src/mainboard/dell/optiplex_3040/acpi/ec.asl | 3 + + .../dell/optiplex_3040/acpi/superio.asl | 3 + + .../dell/optiplex_3040/board_info.txt | 7 + + src/mainboard/dell/optiplex_3040/bootblock.c | 107 ++++ + src/mainboard/dell/optiplex_3040/cmos.default | 5 + + src/mainboard/dell/optiplex_3040/cmos.layout | 54 ++ + src/mainboard/dell/optiplex_3040/data.vbt | Bin 0 -> 4300 bytes + .../dell/optiplex_3040/devicetree.cb | 100 ++++ + src/mainboard/dell/optiplex_3040/dsdt.asl | 27 + + .../dell/optiplex_3040/gma-mainboard.ads | 19 + + src/mainboard/dell/optiplex_3040/hda_verb.c | 90 +++ + .../dell/optiplex_3040/include/early_gpio.h | 11 + + .../dell/optiplex_3040/include/gpio.h | 241 +++++++++ + src/mainboard/dell/optiplex_3040/ramstage.c | 512 ++++++++++++++++++ + src/mainboard/dell/optiplex_3040/romstage.c | 22 + + src/mainboard/dell/optiplex_3040/sch5555_ec.c | 54 ++ + src/mainboard/dell/optiplex_3040/sch5555_ec.h | 10 + + 20 files changed, 1318 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_3040/Kconfig + create mode 100644 src/mainboard/dell/optiplex_3040/Kconfig.name + create mode 100644 src/mainboard/dell/optiplex_3040/Makefile.mk + create mode 100644 src/mainboard/dell/optiplex_3040/acpi/ec.asl + create mode 100644 src/mainboard/dell/optiplex_3040/acpi/superio.asl + create mode 100644 src/mainboard/dell/optiplex_3040/board_info.txt + create mode 100644 src/mainboard/dell/optiplex_3040/bootblock.c + create mode 100644 src/mainboard/dell/optiplex_3040/cmos.default + create mode 100644 src/mainboard/dell/optiplex_3040/cmos.layout + create mode 100644 src/mainboard/dell/optiplex_3040/data.vbt + create mode 100644 src/mainboard/dell/optiplex_3040/devicetree.cb + create mode 100644 src/mainboard/dell/optiplex_3040/dsdt.asl + create mode 100644 src/mainboard/dell/optiplex_3040/gma-mainboard.ads + create mode 100644 src/mainboard/dell/optiplex_3040/hda_verb.c + create mode 100644 src/mainboard/dell/optiplex_3040/include/early_gpio.h + create mode 100644 src/mainboard/dell/optiplex_3040/include/gpio.h + create mode 100644 src/mainboard/dell/optiplex_3040/ramstage.c + create mode 100644 src/mainboard/dell/optiplex_3040/romstage.c + create mode 100644 src/mainboard/dell/optiplex_3040/sch5555_ec.c + create mode 100644 src/mainboard/dell/optiplex_3040/sch5555_ec.h + +diff --git a/src/mainboard/dell/optiplex_3040/Kconfig b/src/mainboard/dell/optiplex_3040/Kconfig +new file mode 100644 +index 0000000000..eab8e7d814 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/Kconfig +@@ -0,0 +1,37 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++if BOARD_DELL_OPTIPLEX_3040 ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ select BOARD_ROMSIZE_KB_16384 ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ select INTEL_GMA_ADD_VBT ++ select INTEL_GMA_HAVE_VBT ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_SUPPORTS_SKYLAKE_CPU ++ select SKYLAKE_SOC_PCH_H ++ select AZALIA_USE_LEGACY_VERB_TABLE ++ select SOC_INTEL_COMMON_BLOCK_HDA_VERB ++ select SOC_INTEL_KABYLAKE ++ select SUPERIO_SMSC_SCH555x ++ ++config CBFS_SIZE ++ default 0x900000 ++ ++config MAINBOARD_DIR ++ default "dell/optiplex_3040" ++ ++config MAINBOARD_PART_NUMBER ++ default "OptiPlex 3040 Micro" ++ ++config INTEL_GMA_VBT_FILE ++ default "src/mainboard/$(MAINBOARDDIR)/data.vbt" ++ ++config DIMM_SPD_SIZE ++ default 256 # DDR3L ++ ++endif +diff --git a/src/mainboard/dell/optiplex_3040/Kconfig.name b/src/mainboard/dell/optiplex_3040/Kconfig.name +new file mode 100644 +index 0000000000..e06da5010a +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/Kconfig.name +@@ -0,0 +1,4 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_DELL_OPTIPLEX_3040 ++ bool "Dell OptiPlex 3040 Micro" +diff --git a/src/mainboard/dell/optiplex_3040/Makefile.mk b/src/mainboard/dell/optiplex_3040/Makefile.mk +new file mode 100644 +index 0000000000..0bd72fe691 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/Makefile.mk +@@ -0,0 +1,12 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++bootblock-y += bootblock.c ++bootblock-y += sch5555_ec.c ++ ++romstage-y += romstage.c ++ ++ramstage-y += ramstage.c ++ramstage-y += sch5555_ec.c ++ramstage-y += hda_verb.c ++ ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +diff --git a/src/mainboard/dell/optiplex_3040/acpi/ec.asl b/src/mainboard/dell/optiplex_3040/acpi/ec.asl +new file mode 100644 +index 0000000000..16990d45f4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/acpi/ec.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: CC-PDDC */ ++ ++/* Please update the license if adding licensable material. */ +diff --git a/src/mainboard/dell/optiplex_3040/acpi/superio.asl b/src/mainboard/dell/optiplex_3040/acpi/superio.asl +new file mode 100644 +index 0000000000..16990d45f4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/acpi/superio.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: CC-PDDC */ ++ ++/* Please update the license if adding licensable material. */ +diff --git a/src/mainboard/dell/optiplex_3040/board_info.txt b/src/mainboard/dell/optiplex_3040/board_info.txt +new file mode 100644 +index 0000000000..e43a925ec3 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/board_info.txt +@@ -0,0 +1,7 @@ ++Category: desktop ++Board URL: https://www.dell.com/support/home/en-us/product-support/product/optiplex-3040-micro/overview ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y ++Release year: 2016 +diff --git a/src/mainboard/dell/optiplex_3040/bootblock.c b/src/mainboard/dell/optiplex_3040/bootblock.c +new file mode 100644 +index 0000000000..10689c42a1 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/bootblock.c +@@ -0,0 +1,107 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include "include/early_gpio.h" ++#include "sch5555_ec.h" ++ ++struct ec_init_entry { ++ uint16_t addr; ++ uint8_t val; ++}; ++ ++static void bootblock_ec_init(void) ++{ ++ /* ++ * Early EC init ++ */ ++ ++ static const struct ec_init_entry init_table1[] = { ++ {0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10}, ++ {0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10}, ++ {0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12}, ++ {0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12}, ++ {0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10}, ++ {0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11}, ++ }; ++ ++ for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i) ++ sch5555_mbox_write(2, init_table1[i].addr, init_table1[i].val); ++ ++ static const struct ec_init_entry init_table2[] = { ++ {0x0040, 0x00}, {0x00f8, 0x10}, {0x00f9, 0x00}, {0x00f0, 0x30}, ++ {0x00fa, 0x00}, {0x00fb, 0x00}, {0x00ea, 0x00}, {0x00eb, 0x00}, ++ {0x00ef, 0x7c}, {0x0005, 0x0f}, {0x0014, 0x01}, {0x0018, 0x2f}, ++ {0x0019, 0x2f}, {0x001a, 0x2f}, {0x001b, 0x2f}, {0x01d8, 0x01}, ++ {0x0040, 0x11}, ++ }; ++ ++ for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i) ++ sch5555_mbox_write(1, init_table2[i].addr, init_table2[i].val); ++ ++ sch5555_mbox_write(1, 0x000b, 0x01); ++ sch5555_mbox_write(4, 0x001a, 0x04); ++ sch5555_mbox_write(4, 0x0028, 0x18); ++ sch5555_mbox_write(4, 0x001a, 0x00); ++ sch5555_mbox_write(1, 0x000b, 0x03); ++ ++ /* ++ * Early HWM init ++ */ ++ ++ sch5555_mbox_read(1, 0xcb); ++ sch5555_mbox_read(1, 0xb8); ++ ++ static const struct ec_init_entry hwm_init_table[] = { ++ {0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f}, ++ {0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33}, ++ {0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff}, ++ {0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00}, ++ {0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00}, ++ {0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80}, ++ {0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02}, ++ {0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04}, ++ {0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50}, ++ {0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50}, ++ {0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c}, ++ {0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd}, ++ {0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e}, ++ {0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00}, ++ {0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff}, ++ {0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00}, ++ {0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c}, ++ {0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02}, ++ {0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03}, {0x0015, 0x33}, ++ {0x018b, 0x00}, {0x018c, 0x00}, {0x02f8, 0x5e}, {0x02f9, 0x01}, ++ }; ++ ++ for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i) ++ sch5555_mbox_write(1, hwm_init_table[i].addr, hwm_init_table[i].val); ++} ++ ++ ++#define SCH555x_IOBASE 0x2e ++#define GLOBAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL) ++#define SERIAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1) ++ ++void bootblock_mainboard_early_init(void) ++{ ++ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); ++ ++ // Super I/O early init will map Runtime and EMI registers ++ sch555x_early_init(GLOBAL_DEV); ++ ++ // Changes LED color among a few other things ++ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS); ++ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN); ++ outb(0xf, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); ++ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); ++ ++ // Perform bootblock EC initialization ++ bootblock_ec_init(); ++ ++ // Bootblock EC initialization is required for UART1 to work ++ sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ++} +diff --git a/src/mainboard/dell/optiplex_3040/cmos.default b/src/mainboard/dell/optiplex_3040/cmos.default +new file mode 100644 +index 0000000000..79961f43d8 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/cmos.default +@@ -0,0 +1,5 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Disable +diff --git a/src/mainboard/dell/optiplex_3040/cmos.layout b/src/mainboard/dell/optiplex_3040/cmos.layout +new file mode 100644 +index 0000000000..54a5147b7d +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/cmos.layout +@@ -0,0 +1,54 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++#start-bit length config config-ID name ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++ ++# coreboot config options: southbridge ++409 2 e 7 power_on_after_fail ++ ++# coreboot config options: bootloader ++#Used by ChromeOS: ++416 128 r 0 vbnv ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 415 984 +diff --git a/src/mainboard/dell/optiplex_3040/data.vbt b/src/mainboard/dell/optiplex_3040/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..b503dfc20277775982256a4bdc9108c2ad96f856 +GIT binary patch +literal 4300 +zcmeHJU2GIp6h1SvzjtP~vs09^U_BzjZlPs%m0GmOYuF-@o*+oezEo~tM +ze;7keND#9RYS0kU#1~Uvni!wdNMej6_=85_(Y}}{(ZmFdFTi^4%(PpVU{|7163*n@ +z^D}3@x%b>Ncg~9bjy~Mc^F(j5XA`UD;e#W4o_=Nw +zqp27s48v$n81XpTQ^wTL$Z!iL2M2LGj~T`7#nIx(fnuRWWhw(W4FQh;g5ZTZ3k0~D +zfV>GA6VfIa2rE3W$OFSB6inzd;Q@p(vwA)ni0cH=1F&-b9VCO`B@zKJfty4KAb8-L +zJZM_r&?0VUz7+txAMU3C1SFjZiA^|fN4;W4&0Gio&?_L|M*&4r>?lVetW$OrKoG#k +z@A(Y@`Kui)nFqF%F +zKU^z+*#PBoU<03lNeGk+A?+e{xw6-ml9X}nK9amda;{x22lHem==wKC$wp>pc_BMg +zF5l{!QV(0`OOgWZ6CSYqZJu@zKRK>SFb*tCADK(KVkdgmTyzS25y$Yi&pNB+e|aau +zkAkH?i|70d&iOA3N9+He8qb-wz%`rKuuHS{ZFxHb^E0rl3(g0v63*PE1@gHz +zx%(-qNijeNg97yLhpzeWnbQLxcG2J5339x)D^1T-h+H1~pI>nyLLL7=|AL|ssDsh! +z0Bec}Aodza4>KHK`Y2;BFnpWo?=$u>!ylObJ7a>3t7Lt>%u+J$k@e?f_Oguc%KAq# +z`%K1PWW6l2pn_`^J*luB1@|fX5rrLB@I6KURAFB!_?x2pRTft9K~?Wo*$x#Cs`@dN +zy{_U1s{Vz_E~t1_)$2lRNeDNF^lXSd8B&{cuO-e1RybrgI)M>|&Yqm8*z&TVk@VKB +zqQBhro6>rinl8Rt1*M$0Fv4UVLOiz&qZairoElpXi(uze;m7&H2!$nJCSj$~aJ1Dy +zXlOkw+5H*qxfeVfp`CiB8?VA>f)iOVOk=p-L7+L%gIrg}y^)#_#xWbwOl=;5Q1bo_ +zgm>1C&txMj&D@E~9E6hH^C_lpx`sJ)Z8VKt(+Sf&T|w|U9gx!RttFGY@9Ce)LZi`H +za`%E~vSj}|X)3kk;rW)*WIobp8tCo?Wztik=9MyO`DRqtm0w>CNsF$P>fV%6(#x}?M$}W^}vh###JpoWHsz-Yc_MumA#PYEaC`sjQJM+ +zE@CF+EvV0HT9`j&?}bF?DUs6Knc0~c*jpTYbl}OV + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/optiplex_3040/devicetree.cb b/src/mainboard/dell/optiplex_3040/devicetree.cb +new file mode 100644 +index 0000000000..f1c919fbc7 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/devicetree.cb +@@ -0,0 +1,100 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++chip soc/intel/skylake ++ register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN" ++ ++ # Enable Enhanced Intel SpeedStep ++ register "eist_enable" = "1" ++ ++ device domain 0 on ++ device ref igpu on ++ register "PrimaryDisplay" = "Display_iGFX" ++ end ++ ++ device ref south_xhci on ++ register "usb2_ports" = "{ ++ [0] = USB2_PORT_MID(OC0), // Front panel (blue) ++ [1] = USB2_PORT_MID(OC0), // Front panel (blue) ++ [2] = USB2_PORT_MID(OC3), // Back panel (black) ++ [3] = USB2_PORT_MID(OC2), // Back panel (blue) ++ [4] = USB2_PORT_MID(OC1), // Back panel (blue) ++ [6] = USB2_PORT_MID(OC1), // Back panel (black) ++ [8] = USB2_PORT_MID(OC_SKIP), // WiFi slot ++ }" ++ register "usb3_ports" = "{ ++ [0] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) ++ [1] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) ++ [2] = USB3_PORT_DEFAULT(OC2), // Back panel (blue) ++ [3] = USB3_PORT_DEFAULT(OC1), // Back panel (blue) ++ }" ++ end ++ ++ # ME interface is 'off' to avoid HECI reset delay due to HAP ++ device ref heci1 off end ++ ++ device ref sata on ++ register "SataSalpSupport" = "1" ++ register "SataPortsEnable[0]" = "1" ++ end ++ ++ # M.2 SSD ++ device ref pcie_rp21 on ++ register "PcieRpClkReqSupport[20]" = "1" ++ register "PcieRpClkReqNumber[20]" = "3" ++ register "PcieRpAdvancedErrorReporting[20]" = "1" ++ register "PcieRpLtrEnable[20]" = "true" ++ register "PcieRpClkSrcNumber[20]" = "3" ++ register "PcieRpHotPlug[20]" = "0" ++ end ++ ++ # Realtek LAN ++ device ref pcie_rp5 on ++ register "PcieRpClkReqSupport[4]" = "0" ++ register "PcieRpHotPlug[4]" = "0" ++ end ++ ++ # M.2 WiFi ++ device ref pcie_rp8 on ++ register "PcieRpClkReqSupport[7]" = "0" ++ register "PcieRpHotPlug[7]" = "1" ++ end ++ ++ # UART0 is exposed on test points on the bottom of the board ++ device ref uart0 on ++ register "SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci" ++ end ++ ++ device ref lpc_espi on ++ register "serirq_mode" = "SERIRQ_CONTINUOUS" ++ ++ # I/O decode for EMI/Runtime registers ++ register "gen1_dec" = "0x007c0a01" ++ ++ # SCH5553 ++ chip superio/smsc/sch555x ++ device pnp 2e.0 on # EMI ++ io 0x60 = 0xa00 ++ end ++ device pnp 2e.1 off end # 8042 ++ device pnp 2e.7 on # UART1 ++ io 0x60 = 0x3f8 ++ irq 0x0f = 2 ++ irq 0x70 = 4 ++ end ++ device pnp 2e.8 off end # UART2 ++ device pnp 2e.c on # LPC interface ++ io 0x60 = 0x2e ++ end ++ device pnp 2e.a on # Runtime registers ++ io 0x60 = 0xa40 ++ end ++ device pnp 2e.b off end # Floppy Controller ++ device pnp 2e.11 off end # Parallel Port ++ end ++ end ++ ++ device ref hda on end ++ ++ device ref smbus on end ++ end ++end +diff --git a/src/mainboard/dell/optiplex_3040/dsdt.asl b/src/mainboard/dell/optiplex_3040/dsdt.asl +new file mode 100644 +index 0000000000..9762f6ff74 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/dsdt.asl +@@ -0,0 +1,27 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20110725 ++) ++{ ++ #include ++ #include ++ #include ++ ++ Scope (\_SB) ++ { ++ Device (PCI0) ++ { ++ #include ++ #include ++ } ++ } ++ ++ #include ++} +diff --git a/src/mainboard/dell/optiplex_3040/gma-mainboard.ads b/src/mainboard/dell/optiplex_3040/gma-mainboard.ads +new file mode 100644 +index 0000000000..cb4c22f285 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/gma-mainboard.ads +@@ -0,0 +1,19 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (HDMI1, -- External HDMI ++ DP2, -- External DP (native) ++ HDMI2, -- External DP (DP++) ++ DP3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) ++ HDMI3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/optiplex_3040/hda_verb.c b/src/mainboard/dell/optiplex_3040/hda_verb.c +new file mode 100644 +index 0000000000..5a1db019c7 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/hda_verb.c +@@ -0,0 +1,90 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header, codec 0 */ ++ 0x10ec0255, /* Realtek ALC3234 */ ++ 0x102806bb, /* Subsystem ID */ ++ 11, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ ++ AZALIA_SUBVENDOR(0, 0x102806bb), ++ ++ AZALIA_PIN_CFG(0, 0x12, 0x40000000), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 5, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, ++ AZALIA_LINE_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x1d, 0x4054c029), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, ++ AZALIA_HP_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 5, 15 ++ )), ++ ++ /* coreboot specific header, codec 2 */ ++ 0x80862809, /* Intel Skylake HDMI */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ ++ AZALIA_SUBVENDOR(2, 0x80860101), ++ ++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++}; ++ ++const u32 pc_beep_verbs[] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/optiplex_3040/include/early_gpio.h b/src/mainboard/dell/optiplex_3040/include/early_gpio.h +new file mode 100644 +index 0000000000..fdf1a64c7c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/include/early_gpio.h +@@ -0,0 +1,11 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __OPTIPLEX_3040_EARLY_GPIO_H__ ++#define __OPTIPLEX_3040_EARLY_GPIO_H__ ++ ++static const struct pad_config early_gpio_table[] = { ++ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ ++ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ ++}; ++ ++#endif +diff --git a/src/mainboard/dell/optiplex_3040/include/gpio.h b/src/mainboard/dell/optiplex_3040/include/gpio.h +new file mode 100644 +index 0000000000..29da4b11d4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/include/gpio.h +@@ -0,0 +1,241 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __OPTIPLEX_3040_GPIO_H__ ++#define __OPTIPLEX_3040_GPIO_H__ ++ ++static const struct pad_config gpio_table[] = { ++ ++ /* ------- GPIO Community 0 ------- */ ++ ++ /* ------- GPIO Group GPP_A ------- */ ++ PAD_CFG_NF(GPP_A0, UP_20K, PLTRST, NF1), /* RCIN# */ ++ PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* LAD0 */ ++ PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* LAD1 */ ++ PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* LAD2 */ ++ PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* LAD3 */ ++ PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */ ++ PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKRUN# */ ++ PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), /* CLKOUT_LPC0 */ ++ PAD_CFG_NF(GPP_A10, NONE, PLTRST, NF1), /* CLKOUT_LPC1 */ ++ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), /* PME# */ ++ PAD_CFG_GPO(GPP_A12, 0, PLTRST), /* GPIO */ ++ PAD_CFG_NF(GPP_A13, NONE, PLTRST, NF1), /* SUSWARN#/SUSPWRDNACK */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_A15, UP_20K, PLTRST, NF1), /* SUS_ACK# */ ++ PAD_CFG_GPO(GPP_A16, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_B ------- */ ++ PAD_CFG_GPO(GPP_B0, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B1, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B2, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_B3, 1, RSMRST), /* GPIO (ME_CNTL, B3 -> LOW => HDA_SDO -> HIGH) */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_B5, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B6, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B7, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_B9, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1), /* SLP_S0# */ ++ PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), /* PLTRST# */ ++ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* SPKR */ ++ PAD_CFG_GPO(GPP_B15, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B16, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* GSPIO_MOSI */ ++ PAD_CFG_GPO(GPP_B19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B20, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* GPIO */ ++ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), /* GSPI1_MOSI */ ++ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), /* PCHHOT# */ ++ ++ /* ------- GPIO Community 1 ------- */ ++ ++ /* ------- GPIO Group GPP_C ------- */ ++ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ ++ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_C2, DN_20K, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_C3, NONE, PLTRST, NF1), /* SML0CLK */ ++ PAD_CFG_NF(GPP_C4, NONE, PLTRST, NF1), /* SML0DATA */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK */ ++ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1DATA */ ++ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ ++ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ ++ PAD_CFG_GPO(GPP_C10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C11, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C12, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C13, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C14, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C15, 0, PLTRST), /* GPIO */ ++ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), /* I2C0_SDA */ ++ PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), /* I2C0_SCL */ ++ PAD_CFG_GPO(GPP_C18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C21, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_D ------- */ ++ PAD_CFG_GPO(GPP_D0, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D1, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D2, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D3, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_D6, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_D7, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D8, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D9, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D11, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D13, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D14, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D15, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D16, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D21, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_E ------- */ ++ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATAXPCIE0 */ ++ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SATAXPCIE1 */ ++ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* SATAXPCIE2 */ ++ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* SATA_LED# */ ++ PAD_CFG_NF(GPP_E9, UP_20K, PLTRST, NF1), /* USB_OC0# */ ++ PAD_CFG_NF(GPP_E10, UP_20K, PLTRST, NF1), /* USB_OC1# */ ++ PAD_CFG_NF(GPP_E11, UP_20K, PLTRST, NF1), /* USB_OC2# */ ++ PAD_CFG_NF(GPP_E12, UP_20K, PLTRST, NF1), /* USB_OC3# */ ++ ++ /* ------- GPIO Group GPP_F ------- */ ++ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* SATAXPCIE3 */ ++ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* SATAXPCIE4 */ ++ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* SATAXPCIE5 */ ++ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* SATAXPCIE6 */ ++ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* SATAXPCIE7 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_F6, NONE, RSMRST, NF1), /* SATA_DEVSLP4 */ ++ PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_F9, 0, RSMRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_F13, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), /* USB_OC4# */ ++ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), /* USB_OC5# */ ++ PAD_CFG_NF(GPP_F17, UP_20K, PLTRST, NF1), /* USB_OC6# */ ++ PAD_CFG_TERM_GPO(GPP_F18, 0, UP_20K, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_F19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_F20, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_F21, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_F22, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_F23, 1, RSMRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_G ------- */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_G9, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_G12, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_G14, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G15, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G16, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G17, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_G19, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G20, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_G21, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G22, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_H ------- */ ++ PAD_CFG_GPO(GPP_H0, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H2, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H3, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H4, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H5, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H6, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_H7, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H8, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H9, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H11, 0, PLTRST), /* GPIO */ ++ PAD_CFG_TERM_GPO(GPP_H12, 1, DN_20K, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H15, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H16, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H21, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Community 2 ------- */ ++ ++ /* -------- GPIO Group GPD -------- */ ++ PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* BATLOW# */ ++ PAD_CFG_GPO(GPD1, 0, PWROK), /* GPIO */ ++ PAD_CFG_NF(GPD2, NONE, RSMRST, NF1), /* LAN_WAKE# */ ++ PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), /* PWRBTN# */ ++ PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */ ++ PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */ ++ PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* SLP_A# */ ++ PAD_CFG_GPO(GPD7, 1, RSMRST), /* GPIO */ ++ PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* SUSCLK */ ++ PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */ ++ PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */ ++ PAD_CFG_GPO(GPD11, 1, RSMRST), /* GPIO */ ++ ++ /* ------- GPIO Community 3 ------- */ ++ ++ /* ------- GPIO Group GPP_I ------- */ ++ PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */ ++ PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPC_HPD1 */ ++ PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DDPD_HPD2 */ ++ PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* DDPE_HPD3 */ ++ PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), /* EDP_HPD */ ++ PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* DDPB_CTRLCLK */ ++ PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), /* DDPB_CTRLDATA */ ++ PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* DDPC_CTRLCLK */ ++ PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), /* DDPC_CTRLDATA */ ++ PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */ ++ PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), /* DDPD_CTRLDATA */ ++}; ++ ++#endif +diff --git a/src/mainboard/dell/optiplex_3040/ramstage.c b/src/mainboard/dell/optiplex_3040/ramstage.c +new file mode 100644 +index 0000000000..c391e4ac6d +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/ramstage.c +@@ -0,0 +1,512 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "include/gpio.h" ++#include "sch5555_ec.h" ++ ++void mainboard_silicon_init_params(FSP_SIL_UPD *params) ++{ ++ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); ++} ++ ++#define FORM_FACTOR_MICRO 0 ++#define FORM_FACTOR_SFF 1 ++// Probably DT and MT ++#define FORM_FACTOR_UNK2 2 ++#define FORM_FACTOR_UNK3 3 ++ ++#define HWM_TAB_ADD_TEMP_TARGET 1 ++#define HWM_TAB_PKG_POWER_ANY 0xffff ++ ++struct hwm_tab_entry { ++ uint16_t addr; ++ uint8_t val; ++ uint8_t flags; ++ uint16_t pkg_power; ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MICRO_BASE[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x01b, 0x0f, 0, 0xffff }, ++ { 0x057, 0xff, 0, 0xffff }, ++ { 0x059, 0xff, 0, 0xffff }, ++ { 0x05b, 0xff, 0, 0xffff }, ++ { 0x05d, 0xff, 0, 0xffff }, ++ { 0x05f, 0xff, 0, 0xffff }, ++ { 0x061, 0xff, 0, 0xffff }, ++ { 0x06e, 0x00, 0, 0xffff }, ++ { 0x06f, 0x03, 0, 0xffff }, ++ { 0x070, 0x03, 0, 0xffff }, ++ { 0x071, 0x02, 0, 0xffff }, ++ { 0x072, 0x02, 0, 0xffff }, ++ { 0x073, 0x01, 0, 0xffff }, ++ { 0x074, 0x06, 0, 0xffff }, ++ { 0x075, 0x07, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x80, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xf1, 0, 0xffff }, ++ { 0x086, 0x88, 0, 0xffff }, ++ { 0x087, 0x61, 0, 0xffff }, ++ { 0x088, 0x08, 0, 0xffff }, ++ { 0x089, 0x00, 0, 0xffff }, ++ { 0x08a, 0x73, 0, 0xffff }, ++ { 0x08b, 0x73, 0, 0xffff }, ++ { 0x08c, 0x73, 0, 0xffff }, ++ { 0x090, 0x6d, 0, 0xffff }, ++ { 0x091, 0x7e, 0, 0xffff }, ++ { 0x092, 0x66, 0, 0xffff }, ++ { 0x093, 0xa4, 0, 0xffff }, ++ { 0x094, 0x7c, 0, 0xffff }, ++ { 0x095, 0xa4, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x2e, 0, 0xffff }, ++ { 0x0a1, 0x00, 0, 0xffff }, ++ { 0x0a2, 0x00, 0, 0xffff }, ++ { 0x0ae, 0xa4, 0, 0xffff }, ++ { 0x0af, 0xa4, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0xa4, 0, 0xffff }, ++ { 0x0b3, 0xa4, 0, 0xffff }, ++ { 0x0b6, 0x00, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0d1, 0xff, 0, 0xffff }, ++ { 0x0d6, 0xff, 0, 0xffff }, ++ { 0x0db, 0xff, 0, 0xffff }, ++ { 0x0ea, 0x5c, 0, 0xffff }, ++ { 0x0eb, 0x5c, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x184, 0xff, 0, 0xffff }, ++ { 0x186, 0xff, 0, 0xffff }, ++ { 0x1a1, 0xce, 0, 0xffff }, ++ { 0x1a2, 0x0c, 0, 0xffff }, ++ { 0x1a3, 0x0c, 0, 0xffff }, ++ { 0x1a6, 0x00, 0, 0xffff }, ++ { 0x1a7, 0x00, 0, 0xffff }, ++ { 0x1a8, 0xa4, 0, 0xffff }, ++ { 0x1a9, 0xa4, 0, 0xffff }, ++ { 0x1ab, 0x2d, 0, 0xffff }, ++ { 0x1ac, 0x2d, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1bb, 0x00, 0, 0xffff }, ++ { 0x1bc, 0x00, 0, 0xffff }, ++ { 0x1bd, 0x00, 0, 0xffff }, ++ { 0x1be, 0x01, 0, 0xffff }, ++ { 0x1bf, 0x01, 0, 0xffff }, ++ { 0x1c0, 0x01, 0, 0xffff }, ++ { 0x1c1, 0x01, 0, 0xffff }, ++ { 0x1c2, 0x01, 0, 0xffff }, ++ { 0x280, 0x00, 0, 0xffff }, ++ { 0x281, 0x00, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MICRO_TEMP80[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x01b, 0x0f, 0, 0xffff }, ++ { 0x057, 0xff, 0, 0xffff }, ++ { 0x059, 0xff, 0, 0xffff }, ++ { 0x05b, 0xff, 0, 0xffff }, ++ { 0x05d, 0xff, 0, 0xffff }, ++ { 0x05f, 0xff, 0, 0xffff }, ++ { 0x061, 0xff, 0, 0xffff }, ++ { 0x06e, 0x00, 0, 0xffff }, ++ { 0x06f, 0x03, 0, 0xffff }, ++ { 0x070, 0x03, 0, 0xffff }, ++ { 0x071, 0x02, 0, 0xffff }, ++ { 0x072, 0x02, 0, 0xffff }, ++ { 0x073, 0x01, 0, 0xffff }, ++ { 0x074, 0x06, 0, 0xffff }, ++ { 0x075, 0x07, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x80, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xf6, 0, 0xffff }, ++ { 0x086, 0x88, 0, 0xffff }, ++ { 0x087, 0x61, 0, 0xffff }, ++ { 0x088, 0x08, 0, 0xffff }, ++ { 0x089, 0x00, 0, 0xffff }, ++ { 0x08a, 0x73, 0, 0xffff }, ++ { 0x08b, 0x73, 0, 0xffff }, ++ { 0x08c, 0x73, 0, 0xffff }, ++ { 0x090, 0x6d, 0, 0xffff }, ++ { 0x091, 0x86, 0, 0xffff }, ++ { 0x092, 0x66, 0, 0xffff }, ++ { 0x093, 0xa4, 0, 0xffff }, ++ { 0x094, 0x7c, 0, 0xffff }, ++ { 0x095, 0xa4, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x2e, 0, 0xffff }, ++ { 0x0a1, 0x00, 0, 0xffff }, ++ { 0x0a2, 0x00, 0, 0xffff }, ++ { 0x0ae, 0xa4, 0, 0xffff }, ++ { 0x0af, 0xa4, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0xa4, 0, 0xffff }, ++ { 0x0b3, 0xa4, 0, 0xffff }, ++ { 0x0b6, 0x00, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0d1, 0xff, 0, 0xffff }, ++ { 0x0d6, 0xff, 0, 0xffff }, ++ { 0x0db, 0xff, 0, 0xffff }, ++ { 0x0ea, 0x50, 0, 0xffff }, ++ { 0x0eb, 0x50, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x184, 0xff, 0, 0xffff }, ++ { 0x186, 0xff, 0, 0xffff }, ++ { 0x1a1, 0xce, 0, 0xffff }, ++ { 0x1a2, 0x0c, 0, 0xffff }, ++ { 0x1a3, 0x0c, 0, 0xffff }, ++ { 0x1a6, 0x00, 0, 0xffff }, ++ { 0x1a7, 0x00, 0, 0xffff }, ++ { 0x1a8, 0xa4, 0, 0xffff }, ++ { 0x1a9, 0xa4, 0, 0xffff }, ++ { 0x1ab, 0x2d, 0, 0xffff }, ++ { 0x1ac, 0x2d, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1bb, 0x00, 0, 0xffff }, ++ { 0x1bc, 0x00, 0, 0xffff }, ++ { 0x1bd, 0x00, 0, 0xffff }, ++ { 0x1be, 0x01, 0, 0xffff }, ++ { 0x1bf, 0x01, 0, 0xffff }, ++ { 0x1c0, 0x01, 0, 0xffff }, ++ { 0x1c1, 0x01, 0, 0xffff }, ++ { 0x1c2, 0x01, 0, 0xffff }, ++ { 0x280, 0x00, 0, 0xffff }, ++ { 0x281, 0x00, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MICRO_EARLY_STEPPING[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x01b, 0x0f, 0, 0xffff }, ++ { 0x057, 0xff, 0, 0xffff }, ++ { 0x059, 0xff, 0, 0xffff }, ++ { 0x05b, 0xff, 0, 0xffff }, ++ { 0x05d, 0xff, 0, 0xffff }, ++ { 0x05f, 0xff, 0, 0xffff }, ++ { 0x061, 0xff, 0, 0xffff }, ++ { 0x06e, 0x01, 0, 0xffff }, ++ { 0x06f, 0x03, 0, 0xffff }, ++ { 0x070, 0x03, 0, 0xffff }, ++ { 0x071, 0x02, 0, 0xffff }, ++ { 0x072, 0x02, 0, 0xffff }, ++ { 0x073, 0x01, 0, 0xffff }, ++ { 0x074, 0x06, 0, 0xffff }, ++ { 0x075, 0x07, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x80, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xfd, 0, 0xffff }, ++ { 0x086, 0x60, 0, 0xffff }, ++ { 0x087, 0x50, 0, 0xffff }, ++ { 0x088, 0x08, 0, 0xffff }, ++ { 0x089, 0x00, 0, 0xffff }, ++ { 0x08a, 0x73, 0, 0xffff }, ++ { 0x08b, 0x73, 0, 0xffff }, ++ { 0x08c, 0x73, 0, 0xffff }, ++ { 0x090, 0x6d, 0, 0xffff }, ++ { 0x091, 0x7a, 0, 0xffff }, ++ { 0x092, 0x6b, 0, 0xffff }, ++ { 0x093, 0xa4, 0, 0xffff }, ++ { 0x094, 0x78, 0, 0xffff }, ++ { 0x095, 0xa4, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x2e, 0, 0xffff }, ++ { 0x0a1, 0x00, 0, 0xffff }, ++ { 0x0a2, 0x00, 0, 0xffff }, ++ { 0x0ae, 0xa4, 0, 0xffff }, ++ { 0x0af, 0xa4, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0xa4, 0, 0xffff }, ++ { 0x0b3, 0xa4, 0, 0xffff }, ++ { 0x0b6, 0x00, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0d1, 0xff, 0, 0xffff }, ++ { 0x0d6, 0xff, 0, 0xffff }, ++ { 0x0db, 0xff, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0xffff }, ++ { 0x0eb, 0x64, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x184, 0xff, 0, 0xffff }, ++ { 0x186, 0xff, 0, 0xffff }, ++ { 0x1a1, 0xce, 0, 0xffff }, ++ { 0x1a2, 0x0c, 0, 0xffff }, ++ { 0x1a3, 0x0c, 0, 0xffff }, ++ { 0x1a6, 0x00, 0, 0xffff }, ++ { 0x1a7, 0x00, 0, 0xffff }, ++ { 0x1a8, 0xa4, 0, 0xffff }, ++ { 0x1a9, 0xa4, 0, 0xffff }, ++ { 0x1ab, 0x2d, 0, 0xffff }, ++ { 0x1ac, 0x2d, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1bb, 0x00, 0, 0xffff }, ++ { 0x1bc, 0x00, 0, 0xffff }, ++ { 0x1bd, 0x00, 0, 0xffff }, ++ { 0x1be, 0x01, 0, 0xffff }, ++ { 0x1bf, 0x01, 0, 0xffff }, ++ { 0x1c0, 0x01, 0, 0xffff }, ++ { 0x1c1, 0x01, 0, 0xffff }, ++ { 0x1c2, 0x01, 0, 0xffff }, ++ { 0x280, 0x00, 0, 0xffff }, ++ { 0x281, 0x00, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_SFF[] = { ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++ { 0x072, 0x03, 0, 0xffff }, ++ { 0x075, 0x06, 0, 0xffff }, ++ { 0x07c, 0x00, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x59, 0, 0xffff }, ++ { 0x086, 0x6a, 0, 0xffff }, ++ { 0x087, 0xc0, 0, 0xffff }, ++ { 0x08a, 0x33, 0, 0xffff }, ++ { 0x090, 0x77, 0, 0xffff }, ++ { 0x091, 0x66, 0, 0xffff }, ++ { 0x092, 0x94, 0, 0xffff }, ++ { 0x093, 0x90, 0, 0xffff }, ++ { 0x094, 0x68, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x3e, 0, 0xffff }, ++ { 0x0ae, 0x86, 0, 0xffff }, ++ { 0x0af, 0x86, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0x90, 0, 0xffff }, ++ { 0x0b6, 0x48, 0, 0xffff }, ++ { 0x0b7, 0x48, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x1b1, 0x48, 0, 0xffff }, ++ { 0x1b8, 0x00, 0, 0xffff }, ++ { 0x1be, 0x95, 0, 0xffff }, ++ { 0x1c1, 0x90, 0, 0xffff }, ++ { 0x1c6, 0x00, 0, 0xffff }, ++ { 0x1c9, 0x00, 0, 0xffff }, ++ { 0x280, 0x68, 0, 0xffff }, ++ { 0x281, 0x10, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff} ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MT[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xb9, 0, 0x0010 }, ++ { 0x086, 0xac, 0, 0x0010 }, ++ { 0x087, 0x87, 0, 0x0010 }, ++ { 0x08a, 0x51, 0, 0x0010 }, ++ { 0x08b, 0x39, 0, 0x0010 }, ++ { 0x090, 0x78, 0, 0xffff }, ++ { 0x091, 0x6a, 0, 0xffff }, ++ { 0x092, 0x8f, 0, 0xffff }, ++ { 0x094, 0x68, 0, 0xffff }, ++ { 0x095, 0x5b, 0, 0xffff }, ++ { 0x096, 0x92, 0, 0xffff }, ++ { 0x097, 0x86, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x09a, 0x8b, 0, 0xffff }, ++ { 0x0a0, 0x0a, 0, 0xffff }, ++ { 0x0a1, 0x26, 0, 0xffff }, ++ { 0x0a2, 0xd1, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x7c, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x99, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1a4, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1be, 0x90, 0, 0xffff }, ++ { 0x280, 0xc4, 0, 0xffff }, ++ { 0x281, 0x09, 0, 0xffff }, ++ { 0x282, 0x0a, 0, 0xffff }, ++ { 0x283, 0x14, 0, 0xffff }, ++ { 0x284, 0x01, 0, 0xffff }, ++ { 0x285, 0x01, 0, 0xffff }, ++ { 0x288, 0x94, 0, 0xffff }, ++ { 0x289, 0x11, 0, 0xffff }, ++ { 0x28a, 0x0a, 0, 0xffff }, ++ { 0x28b, 0x14, 0, 0xffff }, ++ { 0x28c, 0x01, 0, 0xffff }, ++ { 0x28d, 0x01, 0, 0xffff }, ++ { 0x294, 0x24, 0, 0xffff }, ++}; ++ ++static uint8_t get_temp_target(void) ++{ ++ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; ++ if (!val) ++ val = 20; ++ return 0x95 - val; ++} ++ ++static uint16_t get_pkg_power(void) ++{ ++ const unsigned int pkg_power = rdmsr(0x614).lo & 0x7fff; ++ const unsigned int power_unit = 1 << (rdmsr(0x606).lo & 0xf); ++ if (pkg_power / power_unit > 65) ++ return 32; ++ else ++ return 16; ++} ++ ++static uint8_t get_core_cnt(void) ++{ ++ // Intel describes this CPUID field as: ++ // > Maximum number of addressable IDs for processor cores in the physical package ++ if (cpuid(0).eax >= 4) ++ return cpuid_ext(4, 0).eax >> 26; ++ return 0; ++} ++ ++static void apply_hwm_tab(const struct hwm_tab_entry *arr, size_t size) ++{ ++ uint8_t temp_target = get_temp_target(); ++ uint16_t pkg_power = get_pkg_power(); ++ ++ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target); ++ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power); ++ ++ for (size_t i = 0; i < size; ++i) { ++ // Skip entry if it doesn't apply for this package power ++ if (arr[i].pkg_power != pkg_power && ++ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY) ++ continue; ++ ++ uint8_t val = arr[i].val; ++ ++ // Add temp target to value if requested (current tables never do) ++ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET) ++ val += temp_target; ++ ++ // Perform write ++ sch5555_mbox_write(1, arr[i].addr, val); ++ } ++} ++ ++static void sch5555_ec_hwm_init(void *arg) ++{ ++ uint8_t form_fac_id, saved_2fc, core_cnt; ++ ++ printk(BIOS_DEBUG, "OptiPlex 3040 late HWM init\n"); ++ ++ form_fac_id = gpio_get(GPP_G2) | gpio_get(GPP_G3) << 1; ++ printk(BIOS_DEBUG, "Form Factor ID = %#x\n", form_fac_id); ++ ++ saved_2fc = sch5555_mbox_read(1, 0x2fc); ++ sch5555_mbox_write(1, 0x2fc, 0xa0); ++ sch5555_mbox_write(1, 0x2fd, 0x32); ++ ++ switch (form_fac_id) { ++ case FORM_FACTOR_MICRO: ++ // CPU stepping <= 3 ++ if ((cpuid(1).eax & 0xf) <= 3) ++ apply_hwm_tab(HWM_TAB_MICRO_EARLY_STEPPING, ARRAY_SIZE(HWM_TAB_MICRO_EARLY_STEPPING)); ++ // Tjunction == 80 ++ else if ((rdmsr(0x1a2).lo >> 16 & 0xff) == 80) ++ apply_hwm_tab(HWM_TAB_MICRO_TEMP80, ARRAY_SIZE(HWM_TAB_MICRO_TEMP80)); ++ else ++ apply_hwm_tab(HWM_TAB_MICRO_BASE, ARRAY_SIZE(HWM_TAB_MICRO_BASE)); ++ break; ++ case FORM_FACTOR_SFF: ++ apply_hwm_tab(HWM_TAB_SFF, ARRAY_SIZE(HWM_TAB_SFF)); ++ break; ++ default: ++ apply_hwm_tab(HWM_TAB_MT, ARRAY_SIZE(HWM_TAB_MT)); ++ break; ++ } ++ ++ core_cnt = get_core_cnt(); ++ printk(BIOS_DEBUG, "CPU Core Count = %#x\n", core_cnt); ++ if (core_cnt > 2) { ++ sch5555_mbox_write(1, 0x9e, 0x30); ++ sch5555_mbox_write(1, 0xeb, sch5555_mbox_read(1, 0xea)); ++ } ++ ++ sch5555_mbox_write(1, 0x2fc, saved_2fc); ++ sch5555_mbox_read(1, 0xb8); ++} ++ ++BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); +diff --git a/src/mainboard/dell/optiplex_3040/romstage.c b/src/mainboard/dell/optiplex_3040/romstage.c +new file mode 100644 +index 0000000000..c2ce2369a4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/romstage.c +@@ -0,0 +1,22 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_memory_init_params(FSPM_UPD *mupd) ++{ ++ /* ++ * OptiPlex 3040 Micro uses DDR3L SO-DIMMs. ++ * SODIMM slots are at I2C addresses 0x50 (slot 0) and 0x52 (slot 1). ++ * SPD size for DDR3L is 256 bytes. ++ */ ++ struct spd_block blk = { .addr_map = { 0x50, 0x52, } }; ++ get_spd_smbus(&blk); ++ dump_spd_info(&blk); ++ ++ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; ++ mem_cfg->DqPinsInterleaved = true; ++ mem_cfg->MemorySpdDataLen = blk.len; ++ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; ++ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; ++} +diff --git a/src/mainboard/dell/optiplex_3040/sch5555_ec.c b/src/mainboard/dell/optiplex_3040/sch5555_ec.c +new file mode 100644 +index 0000000000..1df5026531 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/sch5555_ec.c +@@ -0,0 +1,54 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include "sch5555_ec.h" ++ ++uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t retry = 0; retry < 0xfff; ++retry) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++ ++ // read result ++ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); ++ return inb(SCH555x_EMI_IOBASE + 4); ++} ++ ++void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address and value ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t retry = 0; retry < 0xfff; ++retry) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++} +diff --git a/src/mainboard/dell/optiplex_3040/sch5555_ec.h b/src/mainboard/dell/optiplex_3040/sch5555_ec.h +new file mode 100644 +index 0000000000..9d262d5787 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/sch5555_ec.h +@@ -0,0 +1,10 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __SCH5555_EC_H__ ++#define __SCH5555_EC_H__ ++ ++uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2); ++ ++void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val); ++ ++#endif +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0050-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch b/config/coreboot/default/patches/0050-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch deleted file mode 100644 index b55797ca..00000000 --- a/config/coreboot/default/patches/0050-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch +++ /dev/null @@ -1,129 +0,0 @@ -From 15cfc08cea1e4a091a2dd729bf88fa2a10ef0a3d Mon Sep 17 00:00:00 2001 -From: Kat Inskip -Date: Sat, 21 Feb 2026 19:48:17 +0000 -Subject: [PATCH 50/51] mb/lenovo/x270: Provide correct vbt and hda_verb - ---- - .../sklkbl_thinkpad/variants/x270/data.vbt | Bin 6144 -> 4449 bytes - .../sklkbl_thinkpad/variants/x270/hda_verb.c | 29 +++++++++--------- - 2 files changed, 15 insertions(+), 14 deletions(-) - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt -index bfb312850e0ab4ea834c535df35edb45834ed248..c6561a9c57e4e600bc0adb5f6679f2f5d6b6c640 100644 -GIT binary patch -delta 1043 -zcmcgq-Afcv6hC)nXFtw-?CgzfEwH0LgQ9&f-Qz1ka^prZC-JMFP=YHJZ{oQls$2s?7a?V`MjktC+ -zmIBAkE35L3T{R08;KY{a0fvRBG?I>!>>E2haF{QO$c=4v8Y8%=?LrDlLIKmZ^Gf5CQN1XgElP&$RejtyZ5 -z##fpUKrO{7px=4oVy};I82ZMAiwFT|EMc$(iBg6qn;Wt%1))HsoGWjGZ6rwfW9y;f -z+P1?LzVFv3072#UoFOjAux+UOm(9&6an}i+$f~@7#c_7}8xbIi0I-AuW05M@qt?NB -zRe{Uu7N`$QfgK@eiP+G~9Av)K5N4SlnO~Vdm|74a%B*D8G8>rf%r0h{d4PGCIT}nO -z1kb>tr{s#a!pI3%9?|1Fclp|1QdQ0P@qX6gB^>l)&nqO<`-*_VTP>kxOWk0S0g$)_YB$m-%5#X9 -zknW*;i1-ZYGfEFJqEnMDyL3$JbV`>Ob-boiL6=W;oYCpKE<*;!3~D!IpMe7goi*fD -z18*Djz>w1hzAjgD~h(eazMzGB3(Uim8EziUhBPY#yb{{-gtq*(v} - -delta 808 -zcmX|e2Y=7&(6 -z1vl8CW+z-x@(%LgW907_fIdYjust^(YddwW|77|83Odly8SQ9J9BnF&$EbTJc{NqB -z8Y0(=dhuwr>(#T5HPpr%yse4n(Ztt0#S21;HymyT1(vJ9HuOD)Uv5yoA$IBhCY^G0 -z(d~;~pIj21x?ibNp&{7!_@YPn0@PYX)d4me@cII*iNKvl04c{p;T8;tmbA>dO!%ck**r) -zYT&6wLA@%NymTDqLC|>RKbP37?tsmjG8Gpd7)9xHCH87_(8_ZjHv|kZZECQLbP;tP`&Ou1y@vPq>VYZ132^`jg_97TGF@)_bR(jv;=h#`x%SaO?%yDb{9 -zsC+JqU`~#!PkzxP< - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c -index 089e605eaf..60289355f8 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c -@@ -3,10 +3,10 @@ - #include - - const u32 cim_verb_data[] = { -- 0x10ec0257, // Vendor/Device ID: Realtek ALC257 -- 0x17aa2256, // Subsystem ID -- 18, -- AZALIA_SUBVENDOR(0, 0x17aa2256), -+ 0x10ec0298, // Vendor/Device ID: Realtek ALC298 -+ 0x17aa5062, // Subsystem ID -+ 19, -+ AZALIA_SUBVENDOR(0, 0x17aa5062), - - AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( - AZALIA_INTEGRATED, -@@ -15,7 +15,7 @@ const u32 cim_verb_data[] = { - AZALIA_OTHER_DIGITAL, - AZALIA_COLOR_UNKNOWN, - AZALIA_NO_JACK_PRESENCE_DETECT, -- 2, 0 -+ 4, 0 - )), - AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device - AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( -@@ -27,28 +27,29 @@ const u32 cim_verb_data[] = { - AZALIA_NO_JACK_PRESENCE_DETECT, - 1, 0 - )), -- AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), -- AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( -+ AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( - AZALIA_JACK, -- AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT, - AZALIA_MIC_IN, - AZALIA_STEREO_MONO_1_8, - AZALIA_BLACK, - AZALIA_JACK_PRESENCE_DETECT, - 3, 0 - )), -+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), -- AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), -- AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x1d, 0x40648605), // does not describe a jack or internal device - AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( - AZALIA_JACK, -- AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT, - AZALIA_HP_OUT, - AZALIA_STEREO_MONO_1_8, - AZALIA_BLACK, - AZALIA_JACK_PRESENCE_DETECT, -- 1, 15 -+ 2, 0 - )), - - //==========Widget node 0x20 - 0 :Hidden register SW reset -@@ -107,7 +108,7 @@ const u32 cim_verb_data[] = { - AZALIA_OTHER_DIGITAL, - AZALIA_COLOR_UNKNOWN, - AZALIA_JACK_PRESENCE_DETECT, -- 1, 0 -+ 2, 0 - )), - AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( - AZALIA_JACK, -@@ -116,7 +117,7 @@ const u32 cim_verb_data[] = { - AZALIA_OTHER_DIGITAL, - AZALIA_COLOR_UNKNOWN, - AZALIA_JACK_PRESENCE_DETECT, -- 1, 0 -+ 3, 0 - )), - }; - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0051-disable-Werror-in-the-coreboot-build-system.patch b/config/coreboot/default/patches/0051-disable-Werror-in-the-coreboot-build-system.patch new file mode 100644 index 00000000..73d73284 --- /dev/null +++ b/config/coreboot/default/patches/0051-disable-Werror-in-the-coreboot-build-system.patch @@ -0,0 +1,411 @@ +From 31f8f8de88963b1329aeac1b5c09de53165e7ce8 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Thu, 23 Apr 2026 20:27:35 +0100 +Subject: [PATCH 51/51] disable -Werror in the coreboot build system + +we don't want it in libreboot, a coreboot distro. + +you have NO IDEA how many times users have complained +in the past that libreboot doesn't build, and it was +code that was actually fine in practice, but the compiler +was just being overly pedantic. i often sit there and +fix each one. no more. + +just remove Werror. this shall be libreboot policy from now +on. it makes sense for coreboot to enable this, because that +is for developers. coreboot-distro is for coreboot users. + +Signed-off-by: Leah Rowe +--- + Makefile.mk | 2 -- + payloads/libpayload/Makefile.mk | 2 +- + payloads/libpayload/Makefile.payload | 2 +- + payloads/libpayload/sample/Makefile | 2 +- + payloads/libpayload/sample/arch_mock/Makefile | 2 +- + payloads/libpayload/tests/Makefile.mk | 2 +- + payloads/linuxcheck/Makefile | 2 +- + src/lib/gnat/Makefile.mk | 1 - + tests/Makefile.common | 2 +- + util/amdfwtool/Makefile.mk | 3 ++- + util/archive/Makefile | 3 ++- + util/bincfg/Makefile | 3 ++- + util/bucts/Makefile | 3 ++- + util/cbfstool/Makefile.mk | 2 +- + util/cbfstool/lz4/Makefile | 8 ++++---- + util/cbmem/Makefile | 3 ++- + util/ectool/Makefile | 2 +- + util/futility/Makefile.mk | 2 +- + util/ifdtool/Makefile.mk | 2 +- + util/intelvbttool/Makefile | 2 +- + util/msrtool/configure | 2 +- + util/pmh7tool/Makefile | 2 +- + util/superiotool/Makefile | 6 +++--- + util/uio_usbdebug/Makefile | 2 +- + util/xcompile/xcompile | 2 +- + 25 files changed, 33 insertions(+), 31 deletions(-) + +diff --git a/Makefile.mk b/Makefile.mk +index 8f541ad187..ff9ed89e00 100644 +--- a/Makefile.mk ++++ b/Makefile.mk +@@ -555,7 +555,6 @@ CFLAGS_common += -ffunction-sections + CFLAGS_common += -fdata-sections + CFLAGS_common += -fno-pie + CFLAGS_common += -Wstring-compare +-CFLAGS_common += -Werror + ifeq ($(CONFIG_COMPILER_GCC),y) + CFLAGS_common += -Wold-style-declaration + CFLAGS_common += -Wcast-function-type +@@ -581,7 +580,6 @@ endif + ADAFLAGS_common += -gnatp + ADAFLAGS_common += -Wuninitialized + ADAFLAGS_common += -Wall +-ADAFLAGS_common += -Werror + ADAFLAGS_common += -pipe + ADAFLAGS_common += -g + ADAFLAGS_common += -nostdinc +diff --git a/payloads/libpayload/Makefile.mk b/payloads/libpayload/Makefile.mk +index 0f5d1a0e11..45c2c5ad74 100644 +--- a/payloads/libpayload/Makefile.mk ++++ b/payloads/libpayload/Makefile.mk +@@ -80,7 +80,7 @@ CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer + CFLAGS += -ffunction-sections -fdata-sections + CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wvla + CFLAGS += -Wwrite-strings -Wredundant-decls -Wimplicit-fallthrough +-CFLAGS += -Wstrict-aliasing -Wshadow -Wno-address-of-packed-member -Werror ++CFLAGS += -Wstrict-aliasing -Wshadow -Wno-address-of-packed-member + + ifeq ($(CONFIG_LP_LTO),y) + CFLAGS += -flto +diff --git a/payloads/libpayload/Makefile.payload b/payloads/libpayload/Makefile.payload +index 2eafd4bec3..c74704c58d 100644 +--- a/payloads/libpayload/Makefile.payload ++++ b/payloads/libpayload/Makefile.payload +@@ -84,7 +84,7 @@ endif + + CFLAGS = $(CFLAGS_$(ARCH)) + CFLAGS += -Os -ffreestanding +-CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla -Werror ++CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla + ifeq ($(CONFIG_LP_LTO),y) + CFLAGS += -flto + endif +diff --git a/payloads/libpayload/sample/Makefile b/payloads/libpayload/sample/Makefile +index 1249e9a017..269511d7df 100644 +--- a/payloads/libpayload/sample/Makefile ++++ b/payloads/libpayload/sample/Makefile +@@ -44,7 +44,7 @@ AS := $(AS_$(ARCH-y)) + LIBPAYLOAD_DIR := ../install/libpayload + XCC := CC="$(CC)" $(LIBPAYLOAD_DIR)/bin/lpgcc + XAS := AS="$(AS)" $(LIBPAYLOAD_DIR)/bin/lpas +-CFLAGS := -fno-builtin -Wall -Werror -Os ++CFLAGS := -fno-builtin -Wall -Os + TARGET := hello + OBJS := $(TARGET).o + +diff --git a/payloads/libpayload/sample/arch_mock/Makefile b/payloads/libpayload/sample/arch_mock/Makefile +index a1e748111e..a146c2b3be 100644 +--- a/payloads/libpayload/sample/arch_mock/Makefile ++++ b/payloads/libpayload/sample/arch_mock/Makefile +@@ -12,7 +12,7 @@ CC := gcc + AS := as + OBJCOPY := objcopy + LIBPAYLOAD_DIR := ../../install/libpayload +-CFLAGS := -fno-builtin -Wall -Werror -Os \ ++CFLAGS := -fno-builtin -Wall -Os \ + -include $(LIBPAYLOAD_DIR)/include/kconfig.h \ + -include $(LIBPAYLOAD_DIR)/include/compiler.h \ + -I $(LIBPAYLOAD_DIR)/include \ +diff --git a/payloads/libpayload/tests/Makefile.mk b/payloads/libpayload/tests/Makefile.mk +index 6b6c78d835..b2e7433b65 100644 +--- a/payloads/libpayload/tests/Makefile.mk ++++ b/payloads/libpayload/tests/Makefile.mk +@@ -45,7 +45,7 @@ TEST_CFLAGS += -I$(cmockasrc)/include + # Minimal subset of warnings and errors. Tests can be less strict than actual build. + TEST_CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wvla + TEST_CFLAGS += -Wwrite-strings -Wno-address-of-packed-member -Wimplicit-fallthrough +-TEST_CFLAGS += -Wstrict-aliasing -Wshadow -Werror ++TEST_CFLAGS += -Wstrict-aliasing -Wshadow + TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type + + TEST_CFLAGS += -std=gnu11 -ffunction-sections -fdata-sections -fno-builtin +diff --git a/payloads/linuxcheck/Makefile b/payloads/linuxcheck/Makefile +index 838c90df0c..a9d016db36 100644 +--- a/payloads/linuxcheck/Makefile ++++ b/payloads/linuxcheck/Makefile +@@ -3,7 +3,7 @@ XCOMPILE=$(LIBPAYLOAD_DIR)/libpayload.xcompile + # build libpayload and put .config file in $(CURDIR) instead of ../libpayload + # to avoid pollute the libpayload source directory and possible conflicts + LPOPTS=obj="$(CURDIR)/build" DESTDIR="$(CURDIR)" DOTCONFIG="$(CURDIR)/.config" +-CFLAGS += -Wall -Wvla -Werror -Os -ffreestanding -nostdinc -nostdlib ++CFLAGS += -Wall -Wvla -Os -ffreestanding -nostdinc -nostdlib + ifeq ($(CONFIG_ARCH_X86),y) + TARGETARCH = i386 + endif +diff --git a/src/lib/gnat/Makefile.mk b/src/lib/gnat/Makefile.mk +index 150a715067..9d9591bc00 100644 +--- a/src/lib/gnat/Makefile.mk ++++ b/src/lib/gnat/Makefile.mk +@@ -12,7 +12,6 @@ ADAFLAGS_libgnat-$(1) := \ + -gnatpg \ + -I$$(src)/lib/gnat/ \ + $$(GCC_ADAFLAGS_$(1)) \ +- -Werror \ + -fno-pie \ + + libgnat-$(1)-y += a-unccon.ads +diff --git a/tests/Makefile.common b/tests/Makefile.common +index 085e4cffc4..831867cf5c 100644 +--- a/tests/Makefile.common ++++ b/tests/Makefile.common +@@ -46,7 +46,7 @@ TEST_INCLUDES += -I$(dir $(TEST_KCONFIG_AUTOHEADER)) + # -Wmissing-prototypes just make working with the test framework cumbersome. + # Only put conservative warnings here that really detect code that's obviously + # unintentional. +-TEST_CFLAGS += -Wall -Werror -Wundef -Wstrict-prototypes -Wno-inline-asm ++TEST_CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wno-inline-asm + TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type + TEST_CFLAGS += -Wno-array-compare -Wno-trigraphs + TEST_CFLAGS += -Wno-unused-but-set-variables +diff --git a/util/amdfwtool/Makefile.mk b/util/amdfwtool/Makefile.mk +index 0b9cc1b644..271afce4a7 100644 +--- a/util/amdfwtool/Makefile.mk ++++ b/util/amdfwtool/Makefile.mk +@@ -6,7 +6,8 @@ amdfwtoolobj = amdfwtool.o data_parse.o signed_psp.o handle_file.o opts.o + amdfwreadobj = amdfwread.o + amdfwheader = amdfwtool.h + +-WERROR ?= -Werror ++# no werror for you ++WERROR ?= + AMDFWTOOLCFLAGS :=-O2 -Wall -Wextra -Wshadow $(WERROR) + AMDFWTOOLCFLAGS += -I $(top)/src/commonlib/bsd/include + AMDFWTOOLCFLAGS += -D_GNU_SOURCE # memmem() from string.h +diff --git a/util/archive/Makefile b/util/archive/Makefile +index 2de6a6294a..70820aeba2 100644 +--- a/util/archive/Makefile ++++ b/util/archive/Makefile +@@ -1,7 +1,8 @@ + ## SPDX-License-Identifier: GPL-2.0-only + PROGRAM = archive + HOSTCC ?= gcc +-WERROR=-Werror ++# no werror for u ++WERROR= + CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR} + + SRCS = $(PROGRAM).c +diff --git a/util/bincfg/Makefile b/util/bincfg/Makefile +index dbcbc7711c..debef6c597 100644 +--- a/util/bincfg/Makefile ++++ b/util/bincfg/Makefile +@@ -3,7 +3,8 @@ CC = gcc + YACC = bison + LEX = flex + TARGET=bincfg +-WERROR=-Werror ++# no werror for u ++WERROR= + CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR} + CFLAGS+=-Wno-unused-function + LDFLAGS= -lfl +diff --git a/util/bucts/Makefile b/util/bucts/Makefile +index d32258d1ec..a81aa5e1ae 100644 +--- a/util/bucts/Makefile ++++ b/util/bucts/Makefile +@@ -3,7 +3,8 @@ CC:=gcc + OBJ:=bucts.o + TARGET=bucts + VERSION:=$(shell git describe) +-WERROR=-Werror ++# no werror for u ++WERROR= + CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR} + + ifeq ($(shell uname), FreeBSD) +diff --git a/util/cbfstool/Makefile.mk b/util/cbfstool/Makefile.mk +index d3f07f9777..e34f69c1f1 100644 +--- a/util/cbfstool/Makefile.mk ++++ b/util/cbfstool/Makefile.mk +@@ -140,7 +140,7 @@ cse_serger_obj += common.o + cse_serger_obj += cse_helpers.o + cse_serger_obj += $(foreach var, $(bpdt_formats_obj), $(var)) + +-TOOLCFLAGS ?= -Werror -Wall -Wextra -Wshadow ++TOOLCFLAGS ?= -Wall -Wextra -Wshadow + TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow + TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings + TOOLCFLAGS += -O2 +diff --git a/util/cbfstool/lz4/Makefile b/util/cbfstool/lz4/Makefile +index d624e84703..be484c805f 100644 +--- a/util/cbfstool/lz4/Makefile ++++ b/util/cbfstool/lz4/Makefile +@@ -72,10 +72,10 @@ cmake: + @cd cmake_unofficial; cmake CMakeLists.txt; $(MAKE) + + gpptest: clean +- $(MAKE) all CC=g++ CFLAGS="-O3 -I../lib -Wall -Wextra -Wundef -Wshadow -Wcast-align -Werror" ++ $(MAKE) all CC=g++ CFLAGS="-O3 -I../lib -Wall -Wextra -Wundef -Wshadow -Wcast-align" + + clangtest: clean +- CFLAGS="-O3 -Werror -Wconversion -Wno-sign-conversion" $(MAKE) all CC=clang ++ CFLAGS="-O3 -Wconversion -Wno-sign-conversion" $(MAKE) all CC=clang + + sanitize: clean + CFLAGS="-O3 -g -fsanitize=undefined" $(MAKE) test CC=clang FUZZER_TIME="-T1mn" NB_LOOPS=-i1 +@@ -84,8 +84,8 @@ staticAnalyze: clean + CFLAGS=-g clang-tidy $(CLANG_TIDY_CHECKS) $(CLANG_TIDY_ARGS) $(SRCS) + + armtest: clean +- CFLAGS="-O3 -Werror" $(MAKE) -C $(LZ4DIR) all CC=arm-linux-gnueabi-gcc +- CFLAGS="-O3 -Werror" $(MAKE) -C $(PRGDIR) bins CC=arm-linux-gnueabi-gcc ++ CFLAGS="-O3" $(MAKE) -C $(LZ4DIR) all CC=arm-linux-gnueabi-gcc ++ CFLAGS="-O3" $(MAKE) -C $(PRGDIR) bins CC=arm-linux-gnueabi-gcc + + versionsTest: clean + $(MAKE) -C versionsTest +diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile +index e265ea6693..3aaaeac794 100644 +--- a/util/cbmem/Makefile ++++ b/util/cbmem/Makefile +@@ -9,7 +9,8 @@ CC ?= $(CROSS_COMPILE)gcc + INSTALL ?= /usr/bin/env install + PREFIX ?= /usr/local + CFLAGS ?= -O2 +-WERROR=-Werror ++# no werror for you! ++WERROR= + CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wshadow $(WERROR) + CPPFLAGS += -I . -I $(ROOT)/commonlib/include -I $(ROOT)/commonlib/bsd/include + CPPFLAGS += -include $(ROOT)/commonlib/bsd/include/commonlib/bsd/compiler.h +diff --git a/util/ectool/Makefile b/util/ectool/Makefile +index a90773e5c6..5724ac6009 100644 +--- a/util/ectool/Makefile ++++ b/util/ectool/Makefile +@@ -1,7 +1,7 @@ + ## SPDX-License-Identifier: GPL-2.0-only + + CC ?= gcc +-WERROR=-Werror ++WERROR= + CFLAGS = -O2 -Wall -Wextra -Wshadow $(WERROR) + PROGRAM = ectool + INSTALL ?= /usr/bin/env install +diff --git a/util/futility/Makefile.mk b/util/futility/Makefile.mk +index a7bcee50d3..cb5363b93e 100644 +--- a/util/futility/Makefile.mk ++++ b/util/futility/Makefile.mk +@@ -10,7 +10,7 @@ $(VBOOT_FUTILITY): | check-openssl-presence + unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \ + BUILD=$(VBOOT_HOST_BUILD) \ + CC="$(HOSTCC)" \ +- WERROR="-Werror -Wno-deprecated-declarations" \ ++ WERROR="-Wno-deprecated-declarations" \ + PKG_CONFIG="$(HOSTPKGCONFIG)" \ + V=$(V) \ + USE_FLASHROM=0 \ +diff --git a/util/ifdtool/Makefile.mk b/util/ifdtool/Makefile.mk +index 2b97bf51c8..47953aedb1 100644 +--- a/util/ifdtool/Makefile.mk ++++ b/util/ifdtool/Makefile.mk +@@ -2,7 +2,7 @@ + + ifdtoolobj = ifdtool.o fmap.o kv_pair.o valstr.o + +-IFDTOOLCFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror ++IFDTOOLCFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes + IFDTOOLCFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include + IFDTOOLCFLAGS += -I$(top)/util/cbfstool/flashmap + IFDTOOLCFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h +diff --git a/util/intelvbttool/Makefile b/util/intelvbttool/Makefile +index 5c770dec9e..8963263354 100644 +--- a/util/intelvbttool/Makefile ++++ b/util/intelvbttool/Makefile +@@ -6,7 +6,7 @@ CC ?= gcc + INSTALL ?= /usr/bin/env install + PREFIX ?= /usr/local + CFLAGS ?= -O2 -g +-CFLAGS += -Wall -Werror ++CFLAGS += -Wall + CFLAGS += -I../../src/commonlib/include -I ../../src/commonlib/bsd/include + + all: $(PROGRAM) +diff --git a/util/msrtool/configure b/util/msrtool/configure +index 659cbcd66b..731e24f550 100755 +--- a/util/msrtool/configure ++++ b/util/msrtool/configure +@@ -133,7 +133,7 @@ CC=`findprog "compiler" "${CC}" clang gcc cc icc` || exit + INSTALL=`findprog "install" "${INSTALL}" install ginstall` || exit + + test -n "$DEBUG" && myCFLAGS="-O2 -g" || myCFLAGS="-Os" +-CFLAGS="${CFLAGS} ${myCFLAGS} -Wall -Werror" ++CFLAGS="${CFLAGS} ${myCFLAGS} -Wall" + + cat > .config.c << EOF + #include +diff --git a/util/pmh7tool/Makefile b/util/pmh7tool/Makefile +index 0a2ebbe147..c04d7e9bf9 100644 +--- a/util/pmh7tool/Makefile ++++ b/util/pmh7tool/Makefile +@@ -1,7 +1,7 @@ + ## SPDX-License-Identifier: GPL-2.0-only + + CC = gcc +-CFLAGS = -O2 -Wall -Wextra -Werror ++CFLAGS = -O2 -Wall -Wextra + PROGRAM = pmh7tool + INSTALL = /usr/bin/env install + PREFIX = /usr/local +diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile +index 39839d9aa6..06aa7b6571 100644 +--- a/util/superiotool/Makefile ++++ b/util/superiotool/Makefile +@@ -12,7 +12,7 @@ PREFIX ?= /usr/local + VERSION := -D'SUPERIOTOOL_VERSION="$(shell git describe 2>/dev/null)"' + + CFLAGS += -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \ +- -Werror-implicit-function-declaration -std=c11 -pedantic $(VERSION) \ ++ -std=c11 -pedantic $(VERSION) \ + -Wno-variadic-macros -I $(TOP)/src/commonlib/bsd/include + LDFLAGS += -lz + +@@ -24,8 +24,8 @@ ifeq ($(OS_ARCH), Darwin) + LIBS = -framework IOKit -framework DirectHW -lpci -lz + endif + ifeq ($(OS_ARCH), FreeBSD) +-CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \ +- -Werror-implicit-function-declaration -std=c11 $(VERSION) \ ++CFLAGS = -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \ ++ -std=c11 $(VERSION) \ + -I/usr/local/include + LDFLAGS += -L/usr/local/lib + LIBS = -lz +diff --git a/util/uio_usbdebug/Makefile b/util/uio_usbdebug/Makefile +index af1cc8e1ec..2ceb28cd53 100644 +--- a/util/uio_usbdebug/Makefile ++++ b/util/uio_usbdebug/Makefile +@@ -30,7 +30,7 @@ KCONFIG_H := ../../src/include/kconfig.h + + CFLAGS += \ + -m32 -g \ +- -Wall -Wextra -Werror \ ++ -Wall -Wextra \ + -Wno-unused-parameter -Wno-error=sign-compare + CPPFLAGS += \ + -Iinclude/ \ +diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile +index f88da69306..ef43e28683 100755 +--- a/util/xcompile/xcompile ++++ b/util/xcompile/xcompile +@@ -124,7 +124,7 @@ testcc() { + local tmp_o="$TMPFILE.o" + rm -f "$tmp_c" "$tmp_o" + echo "void _start(void) {}" >"$tmp_c" +- "$cc" -nostdlib -Werror $cflags -c "$tmp_c" -o "$tmp_o" >/dev/null 2>&1 ++ "$cc" -nostdlib $cflags -c "$tmp_c" -o "$tmp_o" >/dev/null 2>&1 + } + + testld() { +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0051-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch b/config/coreboot/default/patches/0051-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch deleted file mode 100644 index b6473d8e..00000000 --- a/config/coreboot/default/patches/0051-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch +++ /dev/null @@ -1,1530 +0,0 @@ -From 24cb7949962e910c22ccb3e388699709591f2834 Mon Sep 17 00:00:00 2001 -From: Todd Baker -Date: Thu, 12 Mar 2026 13:12:04 -0400 -Subject: [PATCH 51/51] mb/dell: Add OptiPlex 3040 Micro port - (upstream-compatible) - -Based on the OptiPlex 3050 Micro (same Skylake H110 PCH-H platform). -Key differences from 3050: -- DDR3L SODIMMs (256-byte SPD at 0x50/0x52) -- Intel Pentium G4400T-class CPUs (Skylake only, no Kabylake/Coffeelake) -- Realtek ALC3234 HDA (subsystem ID 0x102806bb) -- VBT: DDI E entry removed (phantom port, causes i915 WARN_ON) -- PCIe root ports rp5/rp8/rp21 enabled (PcieRpEnable removed; use device on/off) -- HECI1 set off to prevent stall when HAP bit is set (ME neutralized) - -Signed-off-by: Todd Baker ---- - src/mainboard/dell/optiplex_3040/Kconfig | 37 ++ - src/mainboard/dell/optiplex_3040/Kconfig.name | 4 + - src/mainboard/dell/optiplex_3040/Makefile.mk | 12 + - src/mainboard/dell/optiplex_3040/acpi/ec.asl | 3 + - .../dell/optiplex_3040/acpi/superio.asl | 3 + - .../dell/optiplex_3040/board_info.txt | 7 + - src/mainboard/dell/optiplex_3040/bootblock.c | 107 ++++ - src/mainboard/dell/optiplex_3040/cmos.default | 5 + - src/mainboard/dell/optiplex_3040/cmos.layout | 54 ++ - src/mainboard/dell/optiplex_3040/data.vbt | Bin 0 -> 4300 bytes - .../dell/optiplex_3040/devicetree.cb | 100 ++++ - src/mainboard/dell/optiplex_3040/dsdt.asl | 27 + - .../dell/optiplex_3040/gma-mainboard.ads | 19 + - src/mainboard/dell/optiplex_3040/hda_verb.c | 90 +++ - .../dell/optiplex_3040/include/early_gpio.h | 11 + - .../dell/optiplex_3040/include/gpio.h | 241 +++++++++ - src/mainboard/dell/optiplex_3040/ramstage.c | 512 ++++++++++++++++++ - src/mainboard/dell/optiplex_3040/romstage.c | 22 + - src/mainboard/dell/optiplex_3040/sch5555_ec.c | 54 ++ - src/mainboard/dell/optiplex_3040/sch5555_ec.h | 10 + - 20 files changed, 1318 insertions(+) - create mode 100644 src/mainboard/dell/optiplex_3040/Kconfig - create mode 100644 src/mainboard/dell/optiplex_3040/Kconfig.name - create mode 100644 src/mainboard/dell/optiplex_3040/Makefile.mk - create mode 100644 src/mainboard/dell/optiplex_3040/acpi/ec.asl - create mode 100644 src/mainboard/dell/optiplex_3040/acpi/superio.asl - create mode 100644 src/mainboard/dell/optiplex_3040/board_info.txt - create mode 100644 src/mainboard/dell/optiplex_3040/bootblock.c - create mode 100644 src/mainboard/dell/optiplex_3040/cmos.default - create mode 100644 src/mainboard/dell/optiplex_3040/cmos.layout - create mode 100644 src/mainboard/dell/optiplex_3040/data.vbt - create mode 100644 src/mainboard/dell/optiplex_3040/devicetree.cb - create mode 100644 src/mainboard/dell/optiplex_3040/dsdt.asl - create mode 100644 src/mainboard/dell/optiplex_3040/gma-mainboard.ads - create mode 100644 src/mainboard/dell/optiplex_3040/hda_verb.c - create mode 100644 src/mainboard/dell/optiplex_3040/include/early_gpio.h - create mode 100644 src/mainboard/dell/optiplex_3040/include/gpio.h - create mode 100644 src/mainboard/dell/optiplex_3040/ramstage.c - create mode 100644 src/mainboard/dell/optiplex_3040/romstage.c - create mode 100644 src/mainboard/dell/optiplex_3040/sch5555_ec.c - create mode 100644 src/mainboard/dell/optiplex_3040/sch5555_ec.h - -diff --git a/src/mainboard/dell/optiplex_3040/Kconfig b/src/mainboard/dell/optiplex_3040/Kconfig -new file mode 100644 -index 0000000000..eab8e7d814 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/Kconfig -@@ -0,0 +1,37 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+if BOARD_DELL_OPTIPLEX_3040 -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ select BOARD_ROMSIZE_KB_16384 -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ select INTEL_GMA_ADD_VBT -+ select INTEL_GMA_HAVE_VBT -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_SUPPORTS_SKYLAKE_CPU -+ select SKYLAKE_SOC_PCH_H -+ select AZALIA_USE_LEGACY_VERB_TABLE -+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB -+ select SOC_INTEL_KABYLAKE -+ select SUPERIO_SMSC_SCH555x -+ -+config CBFS_SIZE -+ default 0x900000 -+ -+config MAINBOARD_DIR -+ default "dell/optiplex_3040" -+ -+config MAINBOARD_PART_NUMBER -+ default "OptiPlex 3040 Micro" -+ -+config INTEL_GMA_VBT_FILE -+ default "src/mainboard/$(MAINBOARDDIR)/data.vbt" -+ -+config DIMM_SPD_SIZE -+ default 256 # DDR3L -+ -+endif -diff --git a/src/mainboard/dell/optiplex_3040/Kconfig.name b/src/mainboard/dell/optiplex_3040/Kconfig.name -new file mode 100644 -index 0000000000..e06da5010a ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/Kconfig.name -@@ -0,0 +1,4 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_DELL_OPTIPLEX_3040 -+ bool "Dell OptiPlex 3040 Micro" -diff --git a/src/mainboard/dell/optiplex_3040/Makefile.mk b/src/mainboard/dell/optiplex_3040/Makefile.mk -new file mode 100644 -index 0000000000..0bd72fe691 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/Makefile.mk -@@ -0,0 +1,12 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+bootblock-y += bootblock.c -+bootblock-y += sch5555_ec.c -+ -+romstage-y += romstage.c -+ -+ramstage-y += ramstage.c -+ramstage-y += sch5555_ec.c -+ramstage-y += hda_verb.c -+ -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -diff --git a/src/mainboard/dell/optiplex_3040/acpi/ec.asl b/src/mainboard/dell/optiplex_3040/acpi/ec.asl -new file mode 100644 -index 0000000000..16990d45f4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/acpi/ec.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: CC-PDDC */ -+ -+/* Please update the license if adding licensable material. */ -diff --git a/src/mainboard/dell/optiplex_3040/acpi/superio.asl b/src/mainboard/dell/optiplex_3040/acpi/superio.asl -new file mode 100644 -index 0000000000..16990d45f4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/acpi/superio.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: CC-PDDC */ -+ -+/* Please update the license if adding licensable material. */ -diff --git a/src/mainboard/dell/optiplex_3040/board_info.txt b/src/mainboard/dell/optiplex_3040/board_info.txt -new file mode 100644 -index 0000000000..e43a925ec3 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/board_info.txt -@@ -0,0 +1,7 @@ -+Category: desktop -+Board URL: https://www.dell.com/support/home/en-us/product-support/product/optiplex-3040-micro/overview -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2016 -diff --git a/src/mainboard/dell/optiplex_3040/bootblock.c b/src/mainboard/dell/optiplex_3040/bootblock.c -new file mode 100644 -index 0000000000..10689c42a1 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/bootblock.c -@@ -0,0 +1,107 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include -+#include "include/early_gpio.h" -+#include "sch5555_ec.h" -+ -+struct ec_init_entry { -+ uint16_t addr; -+ uint8_t val; -+}; -+ -+static void bootblock_ec_init(void) -+{ -+ /* -+ * Early EC init -+ */ -+ -+ static const struct ec_init_entry init_table1[] = { -+ {0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10}, -+ {0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10}, -+ {0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12}, -+ {0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12}, -+ {0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10}, -+ {0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11}, -+ }; -+ -+ for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i) -+ sch5555_mbox_write(2, init_table1[i].addr, init_table1[i].val); -+ -+ static const struct ec_init_entry init_table2[] = { -+ {0x0040, 0x00}, {0x00f8, 0x10}, {0x00f9, 0x00}, {0x00f0, 0x30}, -+ {0x00fa, 0x00}, {0x00fb, 0x00}, {0x00ea, 0x00}, {0x00eb, 0x00}, -+ {0x00ef, 0x7c}, {0x0005, 0x0f}, {0x0014, 0x01}, {0x0018, 0x2f}, -+ {0x0019, 0x2f}, {0x001a, 0x2f}, {0x001b, 0x2f}, {0x01d8, 0x01}, -+ {0x0040, 0x11}, -+ }; -+ -+ for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i) -+ sch5555_mbox_write(1, init_table2[i].addr, init_table2[i].val); -+ -+ sch5555_mbox_write(1, 0x000b, 0x01); -+ sch5555_mbox_write(4, 0x001a, 0x04); -+ sch5555_mbox_write(4, 0x0028, 0x18); -+ sch5555_mbox_write(4, 0x001a, 0x00); -+ sch5555_mbox_write(1, 0x000b, 0x03); -+ -+ /* -+ * Early HWM init -+ */ -+ -+ sch5555_mbox_read(1, 0xcb); -+ sch5555_mbox_read(1, 0xb8); -+ -+ static const struct ec_init_entry hwm_init_table[] = { -+ {0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f}, -+ {0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33}, -+ {0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff}, -+ {0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00}, -+ {0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00}, -+ {0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80}, -+ {0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02}, -+ {0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04}, -+ {0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50}, -+ {0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50}, -+ {0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c}, -+ {0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd}, -+ {0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e}, -+ {0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00}, -+ {0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff}, -+ {0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00}, -+ {0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c}, -+ {0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02}, -+ {0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03}, {0x0015, 0x33}, -+ {0x018b, 0x00}, {0x018c, 0x00}, {0x02f8, 0x5e}, {0x02f9, 0x01}, -+ }; -+ -+ for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i) -+ sch5555_mbox_write(1, hwm_init_table[i].addr, hwm_init_table[i].val); -+} -+ -+ -+#define SCH555x_IOBASE 0x2e -+#define GLOBAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL) -+#define SERIAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1) -+ -+void bootblock_mainboard_early_init(void) -+{ -+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -+ -+ // Super I/O early init will map Runtime and EMI registers -+ sch555x_early_init(GLOBAL_DEV); -+ -+ // Changes LED color among a few other things -+ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS); -+ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN); -+ outb(0xf, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); -+ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); -+ -+ // Perform bootblock EC initialization -+ bootblock_ec_init(); -+ -+ // Bootblock EC initialization is required for UART1 to work -+ sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -+} -diff --git a/src/mainboard/dell/optiplex_3040/cmos.default b/src/mainboard/dell/optiplex_3040/cmos.default -new file mode 100644 -index 0000000000..79961f43d8 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/cmos.default -@@ -0,0 +1,5 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -diff --git a/src/mainboard/dell/optiplex_3040/cmos.layout b/src/mainboard/dell/optiplex_3040/cmos.layout -new file mode 100644 -index 0000000000..54a5147b7d ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/cmos.layout -@@ -0,0 +1,54 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+#start-bit length config config-ID name -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+# coreboot config options: southbridge -+409 2 e 7 power_on_after_fail -+ -+# coreboot config options: bootloader -+#Used by ChromeOS: -+416 128 r 0 vbnv -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 415 984 -diff --git a/src/mainboard/dell/optiplex_3040/data.vbt b/src/mainboard/dell/optiplex_3040/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..b503dfc20277775982256a4bdc9108c2ad96f856 -GIT binary patch -literal 4300 -zcmeHJU2GIp6h1SvzjtP~vs09^U_BzjZlPs%m0GmOYuF-@o*+oezEo~tM -ze;7keND#9RYS0kU#1~Uvni!wdNMej6_=85_(Y}}{(ZmFdFTi^4%(PpVU{|7163*n@ -z^D}3@x%b>Ncg~9bjy~Mc^F(j5XA`UD;e#W4o_=Nw -zqp27s48v$n81XpTQ^wTL$Z!iL2M2LGj~T`7#nIx(fnuRWWhw(W4FQh;g5ZTZ3k0~D -zfV>GA6VfIa2rE3W$OFSB6inzd;Q@p(vwA)ni0cH=1F&-b9VCO`B@zKJfty4KAb8-L -zJZM_r&?0VUz7+txAMU3C1SFjZiA^|fN4;W4&0Gio&?_L|M*&4r>?lVetW$OrKoG#k -z@A(Y@`Kui)nFqF%F -zKU^z+*#PBoU<03lNeGk+A?+e{xw6-ml9X}nK9amda;{x22lHem==wKC$wp>pc_BMg -zF5l{!QV(0`OOgWZ6CSYqZJu@zKRK>SFb*tCADK(KVkdgmTyzS25y$Yi&pNB+e|aau -zkAkH?i|70d&iOA3N9+He8qb-wz%`rKuuHS{ZFxHb^E0rl3(g0v63*PE1@gHz -zx%(-qNijeNg97yLhpzeWnbQLxcG2J5339x)D^1T-h+H1~pI>nyLLL7=|AL|ssDsh! -z0Bec}Aodza4>KHK`Y2;BFnpWo?=$u>!ylObJ7a>3t7Lt>%u+J$k@e?f_Oguc%KAq# -z`%K1PWW6l2pn_`^J*luB1@|fX5rrLB@I6KURAFB!_?x2pRTft9K~?Wo*$x#Cs`@dN -zy{_U1s{Vz_E~t1_)$2lRNeDNF^lXSd8B&{cuO-e1RybrgI)M>|&Yqm8*z&TVk@VKB -zqQBhro6>rinl8Rt1*M$0Fv4UVLOiz&qZairoElpXi(uze;m7&H2!$nJCSj$~aJ1Dy -zXlOkw+5H*qxfeVfp`CiB8?VA>f)iOVOk=p-L7+L%gIrg}y^)#_#xWbwOl=;5Q1bo_ -zgm>1C&txMj&D@E~9E6hH^C_lpx`sJ)Z8VKt(+Sf&T|w|U9gx!RttFGY@9Ce)LZi`H -za`%E~vSj}|X)3kk;rW)*WIobp8tCo?Wztik=9MyO`DRqtm0w>CNsF$P>fV%6(#x}?M$}W^}vh###JpoWHsz-Yc_MumA#PYEaC`sjQJM+ -zE@CF+EvV0HT9`j&?}bF?DUs6Knc0~c*jpTYbl}OV - -literal 0 -HcmV?d00001 - -diff --git a/src/mainboard/dell/optiplex_3040/devicetree.cb b/src/mainboard/dell/optiplex_3040/devicetree.cb -new file mode 100644 -index 0000000000..f1c919fbc7 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/devicetree.cb -@@ -0,0 +1,100 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+chip soc/intel/skylake -+ register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN" -+ -+ # Enable Enhanced Intel SpeedStep -+ register "eist_enable" = "1" -+ -+ device domain 0 on -+ device ref igpu on -+ register "PrimaryDisplay" = "Display_iGFX" -+ end -+ -+ device ref south_xhci on -+ register "usb2_ports" = "{ -+ [0] = USB2_PORT_MID(OC0), // Front panel (blue) -+ [1] = USB2_PORT_MID(OC0), // Front panel (blue) -+ [2] = USB2_PORT_MID(OC3), // Back panel (black) -+ [3] = USB2_PORT_MID(OC2), // Back panel (blue) -+ [4] = USB2_PORT_MID(OC1), // Back panel (blue) -+ [6] = USB2_PORT_MID(OC1), // Back panel (black) -+ [8] = USB2_PORT_MID(OC_SKIP), // WiFi slot -+ }" -+ register "usb3_ports" = "{ -+ [0] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) -+ [1] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) -+ [2] = USB3_PORT_DEFAULT(OC2), // Back panel (blue) -+ [3] = USB3_PORT_DEFAULT(OC1), // Back panel (blue) -+ }" -+ end -+ -+ # ME interface is 'off' to avoid HECI reset delay due to HAP -+ device ref heci1 off end -+ -+ device ref sata on -+ register "SataSalpSupport" = "1" -+ register "SataPortsEnable[0]" = "1" -+ end -+ -+ # M.2 SSD -+ device ref pcie_rp21 on -+ register "PcieRpClkReqSupport[20]" = "1" -+ register "PcieRpClkReqNumber[20]" = "3" -+ register "PcieRpAdvancedErrorReporting[20]" = "1" -+ register "PcieRpLtrEnable[20]" = "true" -+ register "PcieRpClkSrcNumber[20]" = "3" -+ register "PcieRpHotPlug[20]" = "0" -+ end -+ -+ # Realtek LAN -+ device ref pcie_rp5 on -+ register "PcieRpClkReqSupport[4]" = "0" -+ register "PcieRpHotPlug[4]" = "0" -+ end -+ -+ # M.2 WiFi -+ device ref pcie_rp8 on -+ register "PcieRpClkReqSupport[7]" = "0" -+ register "PcieRpHotPlug[7]" = "1" -+ end -+ -+ # UART0 is exposed on test points on the bottom of the board -+ device ref uart0 on -+ register "SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci" -+ end -+ -+ device ref lpc_espi on -+ register "serirq_mode" = "SERIRQ_CONTINUOUS" -+ -+ # I/O decode for EMI/Runtime registers -+ register "gen1_dec" = "0x007c0a01" -+ -+ # SCH5553 -+ chip superio/smsc/sch555x -+ device pnp 2e.0 on # EMI -+ io 0x60 = 0xa00 -+ end -+ device pnp 2e.1 off end # 8042 -+ device pnp 2e.7 on # UART1 -+ io 0x60 = 0x3f8 -+ irq 0x0f = 2 -+ irq 0x70 = 4 -+ end -+ device pnp 2e.8 off end # UART2 -+ device pnp 2e.c on # LPC interface -+ io 0x60 = 0x2e -+ end -+ device pnp 2e.a on # Runtime registers -+ io 0x60 = 0xa40 -+ end -+ device pnp 2e.b off end # Floppy Controller -+ device pnp 2e.11 off end # Parallel Port -+ end -+ end -+ -+ device ref hda on end -+ -+ device ref smbus on end -+ end -+end -diff --git a/src/mainboard/dell/optiplex_3040/dsdt.asl b/src/mainboard/dell/optiplex_3040/dsdt.asl -new file mode 100644 -index 0000000000..9762f6ff74 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/dsdt.asl -@@ -0,0 +1,27 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20110725 -+) -+{ -+ #include -+ #include -+ #include -+ -+ Scope (\_SB) -+ { -+ Device (PCI0) -+ { -+ #include -+ #include -+ } -+ } -+ -+ #include -+} -diff --git a/src/mainboard/dell/optiplex_3040/gma-mainboard.ads b/src/mainboard/dell/optiplex_3040/gma-mainboard.ads -new file mode 100644 -index 0000000000..cb4c22f285 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/gma-mainboard.ads -@@ -0,0 +1,19 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ (HDMI1, -- External HDMI -+ DP2, -- External DP (native) -+ HDMI2, -- External DP (DP++) -+ DP3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) -+ HDMI3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/optiplex_3040/hda_verb.c b/src/mainboard/dell/optiplex_3040/hda_verb.c -new file mode 100644 -index 0000000000..5a1db019c7 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/hda_verb.c -@@ -0,0 +1,90 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ /* coreboot specific header, codec 0 */ -+ 0x10ec0255, /* Realtek ALC3234 */ -+ 0x102806bb, /* Subsystem ID */ -+ 11, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ -+ AZALIA_SUBVENDOR(0, 0x102806bb), -+ -+ AZALIA_PIN_CFG(0, 0x12, 0x40000000), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( -+ AZALIA_INTEGRATED, -+ AZALIA_INTERNAL, -+ AZALIA_SPEAKER, -+ AZALIA_OTHER_ANALOG, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_NO_JACK_PRESENCE_DETECT, -+ 5, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, -+ AZALIA_LINE_OUT, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 2, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x1d, 0x4054c029), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, -+ AZALIA_HP_OUT, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 5, 15 -+ )), -+ -+ /* coreboot specific header, codec 2 */ -+ 0x80862809, /* Intel Skylake HDMI */ -+ 0x80860101, /* Subsystem ID */ -+ 4, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ -+ AZALIA_SUBVENDOR(2, 0x80860101), -+ -+ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+}; -+ -+const u32 pc_beep_verbs[] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/optiplex_3040/include/early_gpio.h b/src/mainboard/dell/optiplex_3040/include/early_gpio.h -new file mode 100644 -index 0000000000..fdf1a64c7c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/include/early_gpio.h -@@ -0,0 +1,11 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __OPTIPLEX_3040_EARLY_GPIO_H__ -+#define __OPTIPLEX_3040_EARLY_GPIO_H__ -+ -+static const struct pad_config early_gpio_table[] = { -+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ -+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ -+}; -+ -+#endif -diff --git a/src/mainboard/dell/optiplex_3040/include/gpio.h b/src/mainboard/dell/optiplex_3040/include/gpio.h -new file mode 100644 -index 0000000000..29da4b11d4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/include/gpio.h -@@ -0,0 +1,241 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __OPTIPLEX_3040_GPIO_H__ -+#define __OPTIPLEX_3040_GPIO_H__ -+ -+static const struct pad_config gpio_table[] = { -+ -+ /* ------- GPIO Community 0 ------- */ -+ -+ /* ------- GPIO Group GPP_A ------- */ -+ PAD_CFG_NF(GPP_A0, UP_20K, PLTRST, NF1), /* RCIN# */ -+ PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* LAD0 */ -+ PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* LAD1 */ -+ PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* LAD2 */ -+ PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* LAD3 */ -+ PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */ -+ PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKRUN# */ -+ PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), /* CLKOUT_LPC0 */ -+ PAD_CFG_NF(GPP_A10, NONE, PLTRST, NF1), /* CLKOUT_LPC1 */ -+ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), /* PME# */ -+ PAD_CFG_GPO(GPP_A12, 0, PLTRST), /* GPIO */ -+ PAD_CFG_NF(GPP_A13, NONE, PLTRST, NF1), /* SUSWARN#/SUSPWRDNACK */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_A15, UP_20K, PLTRST, NF1), /* SUS_ACK# */ -+ PAD_CFG_GPO(GPP_A16, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_B ------- */ -+ PAD_CFG_GPO(GPP_B0, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B1, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B2, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_B3, 1, RSMRST), /* GPIO (ME_CNTL, B3 -> LOW => HDA_SDO -> HIGH) */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_B5, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B6, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B7, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_B9, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1), /* SLP_S0# */ -+ PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), /* PLTRST# */ -+ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* SPKR */ -+ PAD_CFG_GPO(GPP_B15, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B16, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* GSPIO_MOSI */ -+ PAD_CFG_GPO(GPP_B19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B20, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* GPIO */ -+ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), /* GSPI1_MOSI */ -+ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), /* PCHHOT# */ -+ -+ /* ------- GPIO Community 1 ------- */ -+ -+ /* ------- GPIO Group GPP_C ------- */ -+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ -+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_C2, DN_20K, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_C3, NONE, PLTRST, NF1), /* SML0CLK */ -+ PAD_CFG_NF(GPP_C4, NONE, PLTRST, NF1), /* SML0DATA */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK */ -+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1DATA */ -+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ -+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ -+ PAD_CFG_GPO(GPP_C10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C11, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C12, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C13, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C14, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C15, 0, PLTRST), /* GPIO */ -+ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), /* I2C0_SDA */ -+ PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), /* I2C0_SCL */ -+ PAD_CFG_GPO(GPP_C18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C21, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_D ------- */ -+ PAD_CFG_GPO(GPP_D0, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D1, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D2, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D3, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_D6, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_D7, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D8, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D9, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D11, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D13, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D14, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D15, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D16, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D21, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_E ------- */ -+ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATAXPCIE0 */ -+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SATAXPCIE1 */ -+ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* SATAXPCIE2 */ -+ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* SATA_LED# */ -+ PAD_CFG_NF(GPP_E9, UP_20K, PLTRST, NF1), /* USB_OC0# */ -+ PAD_CFG_NF(GPP_E10, UP_20K, PLTRST, NF1), /* USB_OC1# */ -+ PAD_CFG_NF(GPP_E11, UP_20K, PLTRST, NF1), /* USB_OC2# */ -+ PAD_CFG_NF(GPP_E12, UP_20K, PLTRST, NF1), /* USB_OC3# */ -+ -+ /* ------- GPIO Group GPP_F ------- */ -+ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* SATAXPCIE3 */ -+ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* SATAXPCIE4 */ -+ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* SATAXPCIE5 */ -+ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* SATAXPCIE6 */ -+ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* SATAXPCIE7 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_F6, NONE, RSMRST, NF1), /* SATA_DEVSLP4 */ -+ PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_F9, 0, RSMRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_F13, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), /* USB_OC4# */ -+ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), /* USB_OC5# */ -+ PAD_CFG_NF(GPP_F17, UP_20K, PLTRST, NF1), /* USB_OC6# */ -+ PAD_CFG_TERM_GPO(GPP_F18, 0, UP_20K, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_F19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_F20, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_F21, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_F22, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_F23, 1, RSMRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_G ------- */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_G9, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_G12, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_G14, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G15, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G16, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G17, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_G19, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G20, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_G21, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G22, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_H ------- */ -+ PAD_CFG_GPO(GPP_H0, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H2, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H3, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H4, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H5, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H6, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_H7, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H8, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H9, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H11, 0, PLTRST), /* GPIO */ -+ PAD_CFG_TERM_GPO(GPP_H12, 1, DN_20K, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H15, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H16, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H21, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Community 2 ------- */ -+ -+ /* -------- GPIO Group GPD -------- */ -+ PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* BATLOW# */ -+ PAD_CFG_GPO(GPD1, 0, PWROK), /* GPIO */ -+ PAD_CFG_NF(GPD2, NONE, RSMRST, NF1), /* LAN_WAKE# */ -+ PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), /* PWRBTN# */ -+ PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */ -+ PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */ -+ PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* SLP_A# */ -+ PAD_CFG_GPO(GPD7, 1, RSMRST), /* GPIO */ -+ PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* SUSCLK */ -+ PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */ -+ PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */ -+ PAD_CFG_GPO(GPD11, 1, RSMRST), /* GPIO */ -+ -+ /* ------- GPIO Community 3 ------- */ -+ -+ /* ------- GPIO Group GPP_I ------- */ -+ PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */ -+ PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPC_HPD1 */ -+ PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DDPD_HPD2 */ -+ PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* DDPE_HPD3 */ -+ PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), /* EDP_HPD */ -+ PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* DDPB_CTRLCLK */ -+ PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), /* DDPB_CTRLDATA */ -+ PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* DDPC_CTRLCLK */ -+ PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), /* DDPC_CTRLDATA */ -+ PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */ -+ PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), /* DDPD_CTRLDATA */ -+}; -+ -+#endif -diff --git a/src/mainboard/dell/optiplex_3040/ramstage.c b/src/mainboard/dell/optiplex_3040/ramstage.c -new file mode 100644 -index 0000000000..c391e4ac6d ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/ramstage.c -@@ -0,0 +1,512 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "include/gpio.h" -+#include "sch5555_ec.h" -+ -+void mainboard_silicon_init_params(FSP_SIL_UPD *params) -+{ -+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -+} -+ -+#define FORM_FACTOR_MICRO 0 -+#define FORM_FACTOR_SFF 1 -+// Probably DT and MT -+#define FORM_FACTOR_UNK2 2 -+#define FORM_FACTOR_UNK3 3 -+ -+#define HWM_TAB_ADD_TEMP_TARGET 1 -+#define HWM_TAB_PKG_POWER_ANY 0xffff -+ -+struct hwm_tab_entry { -+ uint16_t addr; -+ uint8_t val; -+ uint8_t flags; -+ uint16_t pkg_power; -+}; -+ -+static const struct hwm_tab_entry HWM_TAB_MICRO_BASE[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x01b, 0x0f, 0, 0xffff }, -+ { 0x057, 0xff, 0, 0xffff }, -+ { 0x059, 0xff, 0, 0xffff }, -+ { 0x05b, 0xff, 0, 0xffff }, -+ { 0x05d, 0xff, 0, 0xffff }, -+ { 0x05f, 0xff, 0, 0xffff }, -+ { 0x061, 0xff, 0, 0xffff }, -+ { 0x06e, 0x00, 0, 0xffff }, -+ { 0x06f, 0x03, 0, 0xffff }, -+ { 0x070, 0x03, 0, 0xffff }, -+ { 0x071, 0x02, 0, 0xffff }, -+ { 0x072, 0x02, 0, 0xffff }, -+ { 0x073, 0x01, 0, 0xffff }, -+ { 0x074, 0x06, 0, 0xffff }, -+ { 0x075, 0x07, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x80, 0, 0xffff }, -+ { 0x082, 0x80, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0xf1, 0, 0xffff }, -+ { 0x086, 0x88, 0, 0xffff }, -+ { 0x087, 0x61, 0, 0xffff }, -+ { 0x088, 0x08, 0, 0xffff }, -+ { 0x089, 0x00, 0, 0xffff }, -+ { 0x08a, 0x73, 0, 0xffff }, -+ { 0x08b, 0x73, 0, 0xffff }, -+ { 0x08c, 0x73, 0, 0xffff }, -+ { 0x090, 0x6d, 0, 0xffff }, -+ { 0x091, 0x7e, 0, 0xffff }, -+ { 0x092, 0x66, 0, 0xffff }, -+ { 0x093, 0xa4, 0, 0xffff }, -+ { 0x094, 0x7c, 0, 0xffff }, -+ { 0x095, 0xa4, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x099, 0xa4, 0, 0xffff }, -+ { 0x09a, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x2e, 0, 0xffff }, -+ { 0x0a1, 0x00, 0, 0xffff }, -+ { 0x0a2, 0x00, 0, 0xffff }, -+ { 0x0ae, 0xa4, 0, 0xffff }, -+ { 0x0af, 0xa4, 0, 0xffff }, -+ { 0x0b0, 0xa4, 0, 0xffff }, -+ { 0x0b1, 0xa4, 0, 0xffff }, -+ { 0x0b2, 0xa4, 0, 0xffff }, -+ { 0x0b3, 0xa4, 0, 0xffff }, -+ { 0x0b6, 0x00, 0, 0xffff }, -+ { 0x0b7, 0x00, 0, 0xffff }, -+ { 0x0d1, 0xff, 0, 0xffff }, -+ { 0x0d6, 0xff, 0, 0xffff }, -+ { 0x0db, 0xff, 0, 0xffff }, -+ { 0x0ea, 0x5c, 0, 0xffff }, -+ { 0x0eb, 0x5c, 0, 0xffff }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x184, 0xff, 0, 0xffff }, -+ { 0x186, 0xff, 0, 0xffff }, -+ { 0x1a1, 0xce, 0, 0xffff }, -+ { 0x1a2, 0x0c, 0, 0xffff }, -+ { 0x1a3, 0x0c, 0, 0xffff }, -+ { 0x1a6, 0x00, 0, 0xffff }, -+ { 0x1a7, 0x00, 0, 0xffff }, -+ { 0x1a8, 0xa4, 0, 0xffff }, -+ { 0x1a9, 0xa4, 0, 0xffff }, -+ { 0x1ab, 0x2d, 0, 0xffff }, -+ { 0x1ac, 0x2d, 0, 0xffff }, -+ { 0x1b1, 0x00, 0, 0xffff }, -+ { 0x1bb, 0x00, 0, 0xffff }, -+ { 0x1bc, 0x00, 0, 0xffff }, -+ { 0x1bd, 0x00, 0, 0xffff }, -+ { 0x1be, 0x01, 0, 0xffff }, -+ { 0x1bf, 0x01, 0, 0xffff }, -+ { 0x1c0, 0x01, 0, 0xffff }, -+ { 0x1c1, 0x01, 0, 0xffff }, -+ { 0x1c2, 0x01, 0, 0xffff }, -+ { 0x280, 0x00, 0, 0xffff }, -+ { 0x281, 0x00, 0, 0xffff }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x040, 0x01, 0, 0xffff }, -+}; -+ -+static const struct hwm_tab_entry HWM_TAB_MICRO_TEMP80[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x01b, 0x0f, 0, 0xffff }, -+ { 0x057, 0xff, 0, 0xffff }, -+ { 0x059, 0xff, 0, 0xffff }, -+ { 0x05b, 0xff, 0, 0xffff }, -+ { 0x05d, 0xff, 0, 0xffff }, -+ { 0x05f, 0xff, 0, 0xffff }, -+ { 0x061, 0xff, 0, 0xffff }, -+ { 0x06e, 0x00, 0, 0xffff }, -+ { 0x06f, 0x03, 0, 0xffff }, -+ { 0x070, 0x03, 0, 0xffff }, -+ { 0x071, 0x02, 0, 0xffff }, -+ { 0x072, 0x02, 0, 0xffff }, -+ { 0x073, 0x01, 0, 0xffff }, -+ { 0x074, 0x06, 0, 0xffff }, -+ { 0x075, 0x07, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x80, 0, 0xffff }, -+ { 0x082, 0x80, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0xf6, 0, 0xffff }, -+ { 0x086, 0x88, 0, 0xffff }, -+ { 0x087, 0x61, 0, 0xffff }, -+ { 0x088, 0x08, 0, 0xffff }, -+ { 0x089, 0x00, 0, 0xffff }, -+ { 0x08a, 0x73, 0, 0xffff }, -+ { 0x08b, 0x73, 0, 0xffff }, -+ { 0x08c, 0x73, 0, 0xffff }, -+ { 0x090, 0x6d, 0, 0xffff }, -+ { 0x091, 0x86, 0, 0xffff }, -+ { 0x092, 0x66, 0, 0xffff }, -+ { 0x093, 0xa4, 0, 0xffff }, -+ { 0x094, 0x7c, 0, 0xffff }, -+ { 0x095, 0xa4, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x099, 0xa4, 0, 0xffff }, -+ { 0x09a, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x2e, 0, 0xffff }, -+ { 0x0a1, 0x00, 0, 0xffff }, -+ { 0x0a2, 0x00, 0, 0xffff }, -+ { 0x0ae, 0xa4, 0, 0xffff }, -+ { 0x0af, 0xa4, 0, 0xffff }, -+ { 0x0b0, 0xa4, 0, 0xffff }, -+ { 0x0b1, 0xa4, 0, 0xffff }, -+ { 0x0b2, 0xa4, 0, 0xffff }, -+ { 0x0b3, 0xa4, 0, 0xffff }, -+ { 0x0b6, 0x00, 0, 0xffff }, -+ { 0x0b7, 0x00, 0, 0xffff }, -+ { 0x0d1, 0xff, 0, 0xffff }, -+ { 0x0d6, 0xff, 0, 0xffff }, -+ { 0x0db, 0xff, 0, 0xffff }, -+ { 0x0ea, 0x50, 0, 0xffff }, -+ { 0x0eb, 0x50, 0, 0xffff }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x184, 0xff, 0, 0xffff }, -+ { 0x186, 0xff, 0, 0xffff }, -+ { 0x1a1, 0xce, 0, 0xffff }, -+ { 0x1a2, 0x0c, 0, 0xffff }, -+ { 0x1a3, 0x0c, 0, 0xffff }, -+ { 0x1a6, 0x00, 0, 0xffff }, -+ { 0x1a7, 0x00, 0, 0xffff }, -+ { 0x1a8, 0xa4, 0, 0xffff }, -+ { 0x1a9, 0xa4, 0, 0xffff }, -+ { 0x1ab, 0x2d, 0, 0xffff }, -+ { 0x1ac, 0x2d, 0, 0xffff }, -+ { 0x1b1, 0x00, 0, 0xffff }, -+ { 0x1bb, 0x00, 0, 0xffff }, -+ { 0x1bc, 0x00, 0, 0xffff }, -+ { 0x1bd, 0x00, 0, 0xffff }, -+ { 0x1be, 0x01, 0, 0xffff }, -+ { 0x1bf, 0x01, 0, 0xffff }, -+ { 0x1c0, 0x01, 0, 0xffff }, -+ { 0x1c1, 0x01, 0, 0xffff }, -+ { 0x1c2, 0x01, 0, 0xffff }, -+ { 0x280, 0x00, 0, 0xffff }, -+ { 0x281, 0x00, 0, 0xffff }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x040, 0x01, 0, 0xffff }, -+}; -+ -+static const struct hwm_tab_entry HWM_TAB_MICRO_EARLY_STEPPING[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x01b, 0x0f, 0, 0xffff }, -+ { 0x057, 0xff, 0, 0xffff }, -+ { 0x059, 0xff, 0, 0xffff }, -+ { 0x05b, 0xff, 0, 0xffff }, -+ { 0x05d, 0xff, 0, 0xffff }, -+ { 0x05f, 0xff, 0, 0xffff }, -+ { 0x061, 0xff, 0, 0xffff }, -+ { 0x06e, 0x01, 0, 0xffff }, -+ { 0x06f, 0x03, 0, 0xffff }, -+ { 0x070, 0x03, 0, 0xffff }, -+ { 0x071, 0x02, 0, 0xffff }, -+ { 0x072, 0x02, 0, 0xffff }, -+ { 0x073, 0x01, 0, 0xffff }, -+ { 0x074, 0x06, 0, 0xffff }, -+ { 0x075, 0x07, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x80, 0, 0xffff }, -+ { 0x082, 0x80, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0xfd, 0, 0xffff }, -+ { 0x086, 0x60, 0, 0xffff }, -+ { 0x087, 0x50, 0, 0xffff }, -+ { 0x088, 0x08, 0, 0xffff }, -+ { 0x089, 0x00, 0, 0xffff }, -+ { 0x08a, 0x73, 0, 0xffff }, -+ { 0x08b, 0x73, 0, 0xffff }, -+ { 0x08c, 0x73, 0, 0xffff }, -+ { 0x090, 0x6d, 0, 0xffff }, -+ { 0x091, 0x7a, 0, 0xffff }, -+ { 0x092, 0x6b, 0, 0xffff }, -+ { 0x093, 0xa4, 0, 0xffff }, -+ { 0x094, 0x78, 0, 0xffff }, -+ { 0x095, 0xa4, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x099, 0xa4, 0, 0xffff }, -+ { 0x09a, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x2e, 0, 0xffff }, -+ { 0x0a1, 0x00, 0, 0xffff }, -+ { 0x0a2, 0x00, 0, 0xffff }, -+ { 0x0ae, 0xa4, 0, 0xffff }, -+ { 0x0af, 0xa4, 0, 0xffff }, -+ { 0x0b0, 0xa4, 0, 0xffff }, -+ { 0x0b1, 0xa4, 0, 0xffff }, -+ { 0x0b2, 0xa4, 0, 0xffff }, -+ { 0x0b3, 0xa4, 0, 0xffff }, -+ { 0x0b6, 0x00, 0, 0xffff }, -+ { 0x0b7, 0x00, 0, 0xffff }, -+ { 0x0d1, 0xff, 0, 0xffff }, -+ { 0x0d6, 0xff, 0, 0xffff }, -+ { 0x0db, 0xff, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0xffff }, -+ { 0x0eb, 0x64, 0, 0xffff }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x184, 0xff, 0, 0xffff }, -+ { 0x186, 0xff, 0, 0xffff }, -+ { 0x1a1, 0xce, 0, 0xffff }, -+ { 0x1a2, 0x0c, 0, 0xffff }, -+ { 0x1a3, 0x0c, 0, 0xffff }, -+ { 0x1a6, 0x00, 0, 0xffff }, -+ { 0x1a7, 0x00, 0, 0xffff }, -+ { 0x1a8, 0xa4, 0, 0xffff }, -+ { 0x1a9, 0xa4, 0, 0xffff }, -+ { 0x1ab, 0x2d, 0, 0xffff }, -+ { 0x1ac, 0x2d, 0, 0xffff }, -+ { 0x1b1, 0x00, 0, 0xffff }, -+ { 0x1bb, 0x00, 0, 0xffff }, -+ { 0x1bc, 0x00, 0, 0xffff }, -+ { 0x1bd, 0x00, 0, 0xffff }, -+ { 0x1be, 0x01, 0, 0xffff }, -+ { 0x1bf, 0x01, 0, 0xffff }, -+ { 0x1c0, 0x01, 0, 0xffff }, -+ { 0x1c1, 0x01, 0, 0xffff }, -+ { 0x1c2, 0x01, 0, 0xffff }, -+ { 0x280, 0x00, 0, 0xffff }, -+ { 0x281, 0x00, 0, 0xffff }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x040, 0x01, 0, 0xffff }, -+}; -+ -+static const struct hwm_tab_entry HWM_TAB_SFF[] = { -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x040, 0x01, 0, 0xffff }, -+ { 0x072, 0x03, 0, 0xffff }, -+ { 0x075, 0x06, 0, 0xffff }, -+ { 0x07c, 0x00, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x00, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0x59, 0, 0xffff }, -+ { 0x086, 0x6a, 0, 0xffff }, -+ { 0x087, 0xc0, 0, 0xffff }, -+ { 0x08a, 0x33, 0, 0xffff }, -+ { 0x090, 0x77, 0, 0xffff }, -+ { 0x091, 0x66, 0, 0xffff }, -+ { 0x092, 0x94, 0, 0xffff }, -+ { 0x093, 0x90, 0, 0xffff }, -+ { 0x094, 0x68, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x099, 0xa4, 0, 0xffff }, -+ { 0x09a, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x3e, 0, 0xffff }, -+ { 0x0ae, 0x86, 0, 0xffff }, -+ { 0x0af, 0x86, 0, 0xffff }, -+ { 0x0b0, 0xa4, 0, 0xffff }, -+ { 0x0b1, 0xa4, 0, 0xffff }, -+ { 0x0b2, 0x90, 0, 0xffff }, -+ { 0x0b6, 0x48, 0, 0xffff }, -+ { 0x0b7, 0x48, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x1b1, 0x48, 0, 0xffff }, -+ { 0x1b8, 0x00, 0, 0xffff }, -+ { 0x1be, 0x95, 0, 0xffff }, -+ { 0x1c1, 0x90, 0, 0xffff }, -+ { 0x1c6, 0x00, 0, 0xffff }, -+ { 0x1c9, 0x00, 0, 0xffff }, -+ { 0x280, 0x68, 0, 0xffff }, -+ { 0x281, 0x10, 0, 0xffff }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff} -+}; -+ -+static const struct hwm_tab_entry HWM_TAB_MT[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x00, 0, 0xffff }, -+ { 0x082, 0x80, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0xb9, 0, 0x0010 }, -+ { 0x086, 0xac, 0, 0x0010 }, -+ { 0x087, 0x87, 0, 0x0010 }, -+ { 0x08a, 0x51, 0, 0x0010 }, -+ { 0x08b, 0x39, 0, 0x0010 }, -+ { 0x090, 0x78, 0, 0xffff }, -+ { 0x091, 0x6a, 0, 0xffff }, -+ { 0x092, 0x8f, 0, 0xffff }, -+ { 0x094, 0x68, 0, 0xffff }, -+ { 0x095, 0x5b, 0, 0xffff }, -+ { 0x096, 0x92, 0, 0xffff }, -+ { 0x097, 0x86, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x09a, 0x8b, 0, 0xffff }, -+ { 0x0a0, 0x0a, 0, 0xffff }, -+ { 0x0a1, 0x26, 0, 0xffff }, -+ { 0x0a2, 0xd1, 0, 0xffff }, -+ { 0x0ae, 0x7c, 0, 0xffff }, -+ { 0x0af, 0x7c, 0, 0xffff }, -+ { 0x0b0, 0x9a, 0, 0xffff }, -+ { 0x0b3, 0x7c, 0, 0xffff }, -+ { 0x0b6, 0x08, 0, 0xffff }, -+ { 0x0b7, 0x00, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0xffff }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x0fd, 0x01, 0, 0xffff }, -+ { 0x1a1, 0x99, 0, 0xffff }, -+ { 0x1a2, 0x00, 0, 0xffff }, -+ { 0x1a4, 0x00, 0, 0xffff }, -+ { 0x1b1, 0x00, 0, 0xffff }, -+ { 0x1be, 0x90, 0, 0xffff }, -+ { 0x280, 0xc4, 0, 0xffff }, -+ { 0x281, 0x09, 0, 0xffff }, -+ { 0x282, 0x0a, 0, 0xffff }, -+ { 0x283, 0x14, 0, 0xffff }, -+ { 0x284, 0x01, 0, 0xffff }, -+ { 0x285, 0x01, 0, 0xffff }, -+ { 0x288, 0x94, 0, 0xffff }, -+ { 0x289, 0x11, 0, 0xffff }, -+ { 0x28a, 0x0a, 0, 0xffff }, -+ { 0x28b, 0x14, 0, 0xffff }, -+ { 0x28c, 0x01, 0, 0xffff }, -+ { 0x28d, 0x01, 0, 0xffff }, -+ { 0x294, 0x24, 0, 0xffff }, -+}; -+ -+static uint8_t get_temp_target(void) -+{ -+ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; -+ if (!val) -+ val = 20; -+ return 0x95 - val; -+} -+ -+static uint16_t get_pkg_power(void) -+{ -+ const unsigned int pkg_power = rdmsr(0x614).lo & 0x7fff; -+ const unsigned int power_unit = 1 << (rdmsr(0x606).lo & 0xf); -+ if (pkg_power / power_unit > 65) -+ return 32; -+ else -+ return 16; -+} -+ -+static uint8_t get_core_cnt(void) -+{ -+ // Intel describes this CPUID field as: -+ // > Maximum number of addressable IDs for processor cores in the physical package -+ if (cpuid(0).eax >= 4) -+ return cpuid_ext(4, 0).eax >> 26; -+ return 0; -+} -+ -+static void apply_hwm_tab(const struct hwm_tab_entry *arr, size_t size) -+{ -+ uint8_t temp_target = get_temp_target(); -+ uint16_t pkg_power = get_pkg_power(); -+ -+ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target); -+ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power); -+ -+ for (size_t i = 0; i < size; ++i) { -+ // Skip entry if it doesn't apply for this package power -+ if (arr[i].pkg_power != pkg_power && -+ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY) -+ continue; -+ -+ uint8_t val = arr[i].val; -+ -+ // Add temp target to value if requested (current tables never do) -+ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET) -+ val += temp_target; -+ -+ // Perform write -+ sch5555_mbox_write(1, arr[i].addr, val); -+ } -+} -+ -+static void sch5555_ec_hwm_init(void *arg) -+{ -+ uint8_t form_fac_id, saved_2fc, core_cnt; -+ -+ printk(BIOS_DEBUG, "OptiPlex 3040 late HWM init\n"); -+ -+ form_fac_id = gpio_get(GPP_G2) | gpio_get(GPP_G3) << 1; -+ printk(BIOS_DEBUG, "Form Factor ID = %#x\n", form_fac_id); -+ -+ saved_2fc = sch5555_mbox_read(1, 0x2fc); -+ sch5555_mbox_write(1, 0x2fc, 0xa0); -+ sch5555_mbox_write(1, 0x2fd, 0x32); -+ -+ switch (form_fac_id) { -+ case FORM_FACTOR_MICRO: -+ // CPU stepping <= 3 -+ if ((cpuid(1).eax & 0xf) <= 3) -+ apply_hwm_tab(HWM_TAB_MICRO_EARLY_STEPPING, ARRAY_SIZE(HWM_TAB_MICRO_EARLY_STEPPING)); -+ // Tjunction == 80 -+ else if ((rdmsr(0x1a2).lo >> 16 & 0xff) == 80) -+ apply_hwm_tab(HWM_TAB_MICRO_TEMP80, ARRAY_SIZE(HWM_TAB_MICRO_TEMP80)); -+ else -+ apply_hwm_tab(HWM_TAB_MICRO_BASE, ARRAY_SIZE(HWM_TAB_MICRO_BASE)); -+ break; -+ case FORM_FACTOR_SFF: -+ apply_hwm_tab(HWM_TAB_SFF, ARRAY_SIZE(HWM_TAB_SFF)); -+ break; -+ default: -+ apply_hwm_tab(HWM_TAB_MT, ARRAY_SIZE(HWM_TAB_MT)); -+ break; -+ } -+ -+ core_cnt = get_core_cnt(); -+ printk(BIOS_DEBUG, "CPU Core Count = %#x\n", core_cnt); -+ if (core_cnt > 2) { -+ sch5555_mbox_write(1, 0x9e, 0x30); -+ sch5555_mbox_write(1, 0xeb, sch5555_mbox_read(1, 0xea)); -+ } -+ -+ sch5555_mbox_write(1, 0x2fc, saved_2fc); -+ sch5555_mbox_read(1, 0xb8); -+} -+ -+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); -diff --git a/src/mainboard/dell/optiplex_3040/romstage.c b/src/mainboard/dell/optiplex_3040/romstage.c -new file mode 100644 -index 0000000000..c2ce2369a4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/romstage.c -@@ -0,0 +1,22 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+ -+void mainboard_memory_init_params(FSPM_UPD *mupd) -+{ -+ /* -+ * OptiPlex 3040 Micro uses DDR3L SO-DIMMs. -+ * SODIMM slots are at I2C addresses 0x50 (slot 0) and 0x52 (slot 1). -+ * SPD size for DDR3L is 256 bytes. -+ */ -+ struct spd_block blk = { .addr_map = { 0x50, 0x52, } }; -+ get_spd_smbus(&blk); -+ dump_spd_info(&blk); -+ -+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; -+ mem_cfg->DqPinsInterleaved = true; -+ mem_cfg->MemorySpdDataLen = blk.len; -+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; -+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; -+} -diff --git a/src/mainboard/dell/optiplex_3040/sch5555_ec.c b/src/mainboard/dell/optiplex_3040/sch5555_ec.c -new file mode 100644 -index 0000000000..1df5026531 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/sch5555_ec.c -@@ -0,0 +1,54 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include "sch5555_ec.h" -+ -+uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2) -+{ -+ // clear ec-to-host mailbox -+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); -+ outb(tmp, SCH555x_EMI_IOBASE + 1); -+ -+ // send address -+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); -+ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); -+ -+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); -+ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); -+ -+ // send message to ec -+ outb(1, SCH555x_EMI_IOBASE); -+ -+ // wait for ack -+ for (size_t retry = 0; retry < 0xfff; ++retry) -+ if (inb(SCH555x_EMI_IOBASE + 1) & 1) -+ break; -+ -+ // read result -+ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); -+ return inb(SCH555x_EMI_IOBASE + 4); -+} -+ -+void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val) -+{ -+ // clear ec-to-host mailbox -+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); -+ outb(tmp, SCH555x_EMI_IOBASE + 1); -+ -+ // send address and value -+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); -+ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); -+ -+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); -+ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); -+ -+ // send message to ec -+ outb(1, SCH555x_EMI_IOBASE); -+ -+ // wait for ack -+ for (size_t retry = 0; retry < 0xfff; ++retry) -+ if (inb(SCH555x_EMI_IOBASE + 1) & 1) -+ break; -+} -diff --git a/src/mainboard/dell/optiplex_3040/sch5555_ec.h b/src/mainboard/dell/optiplex_3040/sch5555_ec.h -new file mode 100644 -index 0000000000..9d262d5787 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3040/sch5555_ec.h -@@ -0,0 +1,10 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __SCH5555_EC_H__ -+#define __SCH5555_EC_H__ -+ -+uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2); -+ -+void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val); -+ -+#endif --- -2.47.3 - diff --git a/config/coreboot/default/patches/0052-disable-Werror-in-the-coreboot-build-system.patch b/config/coreboot/default/patches/0052-disable-Werror-in-the-coreboot-build-system.patch deleted file mode 100644 index 84f2a6fa..00000000 --- a/config/coreboot/default/patches/0052-disable-Werror-in-the-coreboot-build-system.patch +++ /dev/null @@ -1,411 +0,0 @@ -From 841b591f7294c95de5de4cb97e15398c8c5020a0 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Thu, 23 Apr 2026 20:27:35 +0100 -Subject: [PATCH 1/1] disable -Werror in the coreboot build system - -we don't want it in libreboot, a coreboot distro. - -you have NO IDEA how many times users have complained -in the past that libreboot doesn't build, and it was -code that was actually fine in practice, but the compiler -was just being overly pedantic. i often sit there and -fix each one. no more. - -just remove Werror. this shall be libreboot policy from now -on. it makes sense for coreboot to enable this, because that -is for developers. coreboot-distro is for coreboot users. - -Signed-off-by: Leah Rowe ---- - Makefile.mk | 2 -- - payloads/libpayload/Makefile.mk | 2 +- - payloads/libpayload/Makefile.payload | 2 +- - payloads/libpayload/sample/Makefile | 2 +- - payloads/libpayload/sample/arch_mock/Makefile | 2 +- - payloads/libpayload/tests/Makefile.mk | 2 +- - payloads/linuxcheck/Makefile | 2 +- - src/lib/gnat/Makefile.mk | 1 - - tests/Makefile.common | 2 +- - util/amdfwtool/Makefile.mk | 3 ++- - util/archive/Makefile | 3 ++- - util/bincfg/Makefile | 3 ++- - util/bucts/Makefile | 3 ++- - util/cbfstool/Makefile.mk | 2 +- - util/cbfstool/lz4/Makefile | 8 ++++---- - util/cbmem/Makefile | 3 ++- - util/ectool/Makefile | 2 +- - util/futility/Makefile.mk | 2 +- - util/ifdtool/Makefile.mk | 2 +- - util/intelvbttool/Makefile | 2 +- - util/msrtool/configure | 2 +- - util/pmh7tool/Makefile | 2 +- - util/superiotool/Makefile | 6 +++--- - util/uio_usbdebug/Makefile | 2 +- - util/xcompile/xcompile | 2 +- - 25 files changed, 33 insertions(+), 31 deletions(-) - -diff --git a/Makefile.mk b/Makefile.mk -index 8f541ad187..ff9ed89e00 100644 ---- a/Makefile.mk -+++ b/Makefile.mk -@@ -555,7 +555,6 @@ CFLAGS_common += -ffunction-sections - CFLAGS_common += -fdata-sections - CFLAGS_common += -fno-pie - CFLAGS_common += -Wstring-compare --CFLAGS_common += -Werror - ifeq ($(CONFIG_COMPILER_GCC),y) - CFLAGS_common += -Wold-style-declaration - CFLAGS_common += -Wcast-function-type -@@ -581,7 +580,6 @@ endif - ADAFLAGS_common += -gnatp - ADAFLAGS_common += -Wuninitialized - ADAFLAGS_common += -Wall --ADAFLAGS_common += -Werror - ADAFLAGS_common += -pipe - ADAFLAGS_common += -g - ADAFLAGS_common += -nostdinc -diff --git a/payloads/libpayload/Makefile.mk b/payloads/libpayload/Makefile.mk -index 0f5d1a0e11..45c2c5ad74 100644 ---- a/payloads/libpayload/Makefile.mk -+++ b/payloads/libpayload/Makefile.mk -@@ -80,7 +80,7 @@ CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer - CFLAGS += -ffunction-sections -fdata-sections - CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wvla - CFLAGS += -Wwrite-strings -Wredundant-decls -Wimplicit-fallthrough --CFLAGS += -Wstrict-aliasing -Wshadow -Wno-address-of-packed-member -Werror -+CFLAGS += -Wstrict-aliasing -Wshadow -Wno-address-of-packed-member - - ifeq ($(CONFIG_LP_LTO),y) - CFLAGS += -flto -diff --git a/payloads/libpayload/Makefile.payload b/payloads/libpayload/Makefile.payload -index 2eafd4bec3..c74704c58d 100644 ---- a/payloads/libpayload/Makefile.payload -+++ b/payloads/libpayload/Makefile.payload -@@ -84,7 +84,7 @@ endif - - CFLAGS = $(CFLAGS_$(ARCH)) - CFLAGS += -Os -ffreestanding --CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla -Werror -+CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla - ifeq ($(CONFIG_LP_LTO),y) - CFLAGS += -flto - endif -diff --git a/payloads/libpayload/sample/Makefile b/payloads/libpayload/sample/Makefile -index 1249e9a017..269511d7df 100644 ---- a/payloads/libpayload/sample/Makefile -+++ b/payloads/libpayload/sample/Makefile -@@ -44,7 +44,7 @@ AS := $(AS_$(ARCH-y)) - LIBPAYLOAD_DIR := ../install/libpayload - XCC := CC="$(CC)" $(LIBPAYLOAD_DIR)/bin/lpgcc - XAS := AS="$(AS)" $(LIBPAYLOAD_DIR)/bin/lpas --CFLAGS := -fno-builtin -Wall -Werror -Os -+CFLAGS := -fno-builtin -Wall -Os - TARGET := hello - OBJS := $(TARGET).o - -diff --git a/payloads/libpayload/sample/arch_mock/Makefile b/payloads/libpayload/sample/arch_mock/Makefile -index a1e748111e..a146c2b3be 100644 ---- a/payloads/libpayload/sample/arch_mock/Makefile -+++ b/payloads/libpayload/sample/arch_mock/Makefile -@@ -12,7 +12,7 @@ CC := gcc - AS := as - OBJCOPY := objcopy - LIBPAYLOAD_DIR := ../../install/libpayload --CFLAGS := -fno-builtin -Wall -Werror -Os \ -+CFLAGS := -fno-builtin -Wall -Os \ - -include $(LIBPAYLOAD_DIR)/include/kconfig.h \ - -include $(LIBPAYLOAD_DIR)/include/compiler.h \ - -I $(LIBPAYLOAD_DIR)/include \ -diff --git a/payloads/libpayload/tests/Makefile.mk b/payloads/libpayload/tests/Makefile.mk -index 6b6c78d835..b2e7433b65 100644 ---- a/payloads/libpayload/tests/Makefile.mk -+++ b/payloads/libpayload/tests/Makefile.mk -@@ -45,7 +45,7 @@ TEST_CFLAGS += -I$(cmockasrc)/include - # Minimal subset of warnings and errors. Tests can be less strict than actual build. - TEST_CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wvla - TEST_CFLAGS += -Wwrite-strings -Wno-address-of-packed-member -Wimplicit-fallthrough --TEST_CFLAGS += -Wstrict-aliasing -Wshadow -Werror -+TEST_CFLAGS += -Wstrict-aliasing -Wshadow - TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type - - TEST_CFLAGS += -std=gnu11 -ffunction-sections -fdata-sections -fno-builtin -diff --git a/payloads/linuxcheck/Makefile b/payloads/linuxcheck/Makefile -index 838c90df0c..a9d016db36 100644 ---- a/payloads/linuxcheck/Makefile -+++ b/payloads/linuxcheck/Makefile -@@ -3,7 +3,7 @@ XCOMPILE=$(LIBPAYLOAD_DIR)/libpayload.xcompile - # build libpayload and put .config file in $(CURDIR) instead of ../libpayload - # to avoid pollute the libpayload source directory and possible conflicts - LPOPTS=obj="$(CURDIR)/build" DESTDIR="$(CURDIR)" DOTCONFIG="$(CURDIR)/.config" --CFLAGS += -Wall -Wvla -Werror -Os -ffreestanding -nostdinc -nostdlib -+CFLAGS += -Wall -Wvla -Os -ffreestanding -nostdinc -nostdlib - ifeq ($(CONFIG_ARCH_X86),y) - TARGETARCH = i386 - endif -diff --git a/src/lib/gnat/Makefile.mk b/src/lib/gnat/Makefile.mk -index 150a715067..9d9591bc00 100644 ---- a/src/lib/gnat/Makefile.mk -+++ b/src/lib/gnat/Makefile.mk -@@ -12,7 +12,6 @@ ADAFLAGS_libgnat-$(1) := \ - -gnatpg \ - -I$$(src)/lib/gnat/ \ - $$(GCC_ADAFLAGS_$(1)) \ -- -Werror \ - -fno-pie \ - - libgnat-$(1)-y += a-unccon.ads -diff --git a/tests/Makefile.common b/tests/Makefile.common -index 085e4cffc4..831867cf5c 100644 ---- a/tests/Makefile.common -+++ b/tests/Makefile.common -@@ -46,7 +46,7 @@ TEST_INCLUDES += -I$(dir $(TEST_KCONFIG_AUTOHEADER)) - # -Wmissing-prototypes just make working with the test framework cumbersome. - # Only put conservative warnings here that really detect code that's obviously - # unintentional. --TEST_CFLAGS += -Wall -Werror -Wundef -Wstrict-prototypes -Wno-inline-asm -+TEST_CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wno-inline-asm - TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type - TEST_CFLAGS += -Wno-array-compare -Wno-trigraphs - TEST_CFLAGS += -Wno-unused-but-set-variables -diff --git a/util/amdfwtool/Makefile.mk b/util/amdfwtool/Makefile.mk -index 0b9cc1b644..271afce4a7 100644 ---- a/util/amdfwtool/Makefile.mk -+++ b/util/amdfwtool/Makefile.mk -@@ -6,7 +6,8 @@ amdfwtoolobj = amdfwtool.o data_parse.o signed_psp.o handle_file.o opts.o - amdfwreadobj = amdfwread.o - amdfwheader = amdfwtool.h - --WERROR ?= -Werror -+# no werror for you -+WERROR ?= - AMDFWTOOLCFLAGS :=-O2 -Wall -Wextra -Wshadow $(WERROR) - AMDFWTOOLCFLAGS += -I $(top)/src/commonlib/bsd/include - AMDFWTOOLCFLAGS += -D_GNU_SOURCE # memmem() from string.h -diff --git a/util/archive/Makefile b/util/archive/Makefile -index 2de6a6294a..70820aeba2 100644 ---- a/util/archive/Makefile -+++ b/util/archive/Makefile -@@ -1,7 +1,8 @@ - ## SPDX-License-Identifier: GPL-2.0-only - PROGRAM = archive - HOSTCC ?= gcc --WERROR=-Werror -+# no werror for u -+WERROR= - CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR} - - SRCS = $(PROGRAM).c -diff --git a/util/bincfg/Makefile b/util/bincfg/Makefile -index dbcbc7711c..debef6c597 100644 ---- a/util/bincfg/Makefile -+++ b/util/bincfg/Makefile -@@ -3,7 +3,8 @@ CC = gcc - YACC = bison - LEX = flex - TARGET=bincfg --WERROR=-Werror -+# no werror for u -+WERROR= - CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR} - CFLAGS+=-Wno-unused-function - LDFLAGS= -lfl -diff --git a/util/bucts/Makefile b/util/bucts/Makefile -index d32258d1ec..a81aa5e1ae 100644 ---- a/util/bucts/Makefile -+++ b/util/bucts/Makefile -@@ -3,7 +3,8 @@ CC:=gcc - OBJ:=bucts.o - TARGET=bucts - VERSION:=$(shell git describe) --WERROR=-Werror -+# no werror for u -+WERROR= - CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR} - - ifeq ($(shell uname), FreeBSD) -diff --git a/util/cbfstool/Makefile.mk b/util/cbfstool/Makefile.mk -index d3f07f9777..e34f69c1f1 100644 ---- a/util/cbfstool/Makefile.mk -+++ b/util/cbfstool/Makefile.mk -@@ -140,7 +140,7 @@ cse_serger_obj += common.o - cse_serger_obj += cse_helpers.o - cse_serger_obj += $(foreach var, $(bpdt_formats_obj), $(var)) - --TOOLCFLAGS ?= -Werror -Wall -Wextra -Wshadow -+TOOLCFLAGS ?= -Wall -Wextra -Wshadow - TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow - TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings - TOOLCFLAGS += -O2 -diff --git a/util/cbfstool/lz4/Makefile b/util/cbfstool/lz4/Makefile -index d624e84703..be484c805f 100644 ---- a/util/cbfstool/lz4/Makefile -+++ b/util/cbfstool/lz4/Makefile -@@ -72,10 +72,10 @@ cmake: - @cd cmake_unofficial; cmake CMakeLists.txt; $(MAKE) - - gpptest: clean -- $(MAKE) all CC=g++ CFLAGS="-O3 -I../lib -Wall -Wextra -Wundef -Wshadow -Wcast-align -Werror" -+ $(MAKE) all CC=g++ CFLAGS="-O3 -I../lib -Wall -Wextra -Wundef -Wshadow -Wcast-align" - - clangtest: clean -- CFLAGS="-O3 -Werror -Wconversion -Wno-sign-conversion" $(MAKE) all CC=clang -+ CFLAGS="-O3 -Wconversion -Wno-sign-conversion" $(MAKE) all CC=clang - - sanitize: clean - CFLAGS="-O3 -g -fsanitize=undefined" $(MAKE) test CC=clang FUZZER_TIME="-T1mn" NB_LOOPS=-i1 -@@ -84,8 +84,8 @@ staticAnalyze: clean - CFLAGS=-g clang-tidy $(CLANG_TIDY_CHECKS) $(CLANG_TIDY_ARGS) $(SRCS) - - armtest: clean -- CFLAGS="-O3 -Werror" $(MAKE) -C $(LZ4DIR) all CC=arm-linux-gnueabi-gcc -- CFLAGS="-O3 -Werror" $(MAKE) -C $(PRGDIR) bins CC=arm-linux-gnueabi-gcc -+ CFLAGS="-O3" $(MAKE) -C $(LZ4DIR) all CC=arm-linux-gnueabi-gcc -+ CFLAGS="-O3" $(MAKE) -C $(PRGDIR) bins CC=arm-linux-gnueabi-gcc - - versionsTest: clean - $(MAKE) -C versionsTest -diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile -index e265ea6693..3aaaeac794 100644 ---- a/util/cbmem/Makefile -+++ b/util/cbmem/Makefile -@@ -9,7 +9,8 @@ CC ?= $(CROSS_COMPILE)gcc - INSTALL ?= /usr/bin/env install - PREFIX ?= /usr/local - CFLAGS ?= -O2 --WERROR=-Werror -+# no werror for you! -+WERROR= - CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wshadow $(WERROR) - CPPFLAGS += -I . -I $(ROOT)/commonlib/include -I $(ROOT)/commonlib/bsd/include - CPPFLAGS += -include $(ROOT)/commonlib/bsd/include/commonlib/bsd/compiler.h -diff --git a/util/ectool/Makefile b/util/ectool/Makefile -index a90773e5c6..5724ac6009 100644 ---- a/util/ectool/Makefile -+++ b/util/ectool/Makefile -@@ -1,7 +1,7 @@ - ## SPDX-License-Identifier: GPL-2.0-only - - CC ?= gcc --WERROR=-Werror -+WERROR= - CFLAGS = -O2 -Wall -Wextra -Wshadow $(WERROR) - PROGRAM = ectool - INSTALL ?= /usr/bin/env install -diff --git a/util/futility/Makefile.mk b/util/futility/Makefile.mk -index a7bcee50d3..cb5363b93e 100644 ---- a/util/futility/Makefile.mk -+++ b/util/futility/Makefile.mk -@@ -10,7 +10,7 @@ $(VBOOT_FUTILITY): | check-openssl-presence - unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \ - BUILD=$(VBOOT_HOST_BUILD) \ - CC="$(HOSTCC)" \ -- WERROR="-Werror -Wno-deprecated-declarations" \ -+ WERROR="-Wno-deprecated-declarations" \ - PKG_CONFIG="$(HOSTPKGCONFIG)" \ - V=$(V) \ - USE_FLASHROM=0 \ -diff --git a/util/ifdtool/Makefile.mk b/util/ifdtool/Makefile.mk -index 2b97bf51c8..47953aedb1 100644 ---- a/util/ifdtool/Makefile.mk -+++ b/util/ifdtool/Makefile.mk -@@ -2,7 +2,7 @@ - - ifdtoolobj = ifdtool.o fmap.o kv_pair.o valstr.o - --IFDTOOLCFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror -+IFDTOOLCFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes - IFDTOOLCFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include - IFDTOOLCFLAGS += -I$(top)/util/cbfstool/flashmap - IFDTOOLCFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h -diff --git a/util/intelvbttool/Makefile b/util/intelvbttool/Makefile -index 5c770dec9e..8963263354 100644 ---- a/util/intelvbttool/Makefile -+++ b/util/intelvbttool/Makefile -@@ -6,7 +6,7 @@ CC ?= gcc - INSTALL ?= /usr/bin/env install - PREFIX ?= /usr/local - CFLAGS ?= -O2 -g --CFLAGS += -Wall -Werror -+CFLAGS += -Wall - CFLAGS += -I../../src/commonlib/include -I ../../src/commonlib/bsd/include - - all: $(PROGRAM) -diff --git a/util/msrtool/configure b/util/msrtool/configure -index 659cbcd66b..731e24f550 100755 ---- a/util/msrtool/configure -+++ b/util/msrtool/configure -@@ -133,7 +133,7 @@ CC=`findprog "compiler" "${CC}" clang gcc cc icc` || exit - INSTALL=`findprog "install" "${INSTALL}" install ginstall` || exit - - test -n "$DEBUG" && myCFLAGS="-O2 -g" || myCFLAGS="-Os" --CFLAGS="${CFLAGS} ${myCFLAGS} -Wall -Werror" -+CFLAGS="${CFLAGS} ${myCFLAGS} -Wall" - - cat > .config.c << EOF - #include -diff --git a/util/pmh7tool/Makefile b/util/pmh7tool/Makefile -index 0a2ebbe147..c04d7e9bf9 100644 ---- a/util/pmh7tool/Makefile -+++ b/util/pmh7tool/Makefile -@@ -1,7 +1,7 @@ - ## SPDX-License-Identifier: GPL-2.0-only - - CC = gcc --CFLAGS = -O2 -Wall -Wextra -Werror -+CFLAGS = -O2 -Wall -Wextra - PROGRAM = pmh7tool - INSTALL = /usr/bin/env install - PREFIX = /usr/local -diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile -index 39839d9aa6..06aa7b6571 100644 ---- a/util/superiotool/Makefile -+++ b/util/superiotool/Makefile -@@ -12,7 +12,7 @@ PREFIX ?= /usr/local - VERSION := -D'SUPERIOTOOL_VERSION="$(shell git describe 2>/dev/null)"' - - CFLAGS += -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \ -- -Werror-implicit-function-declaration -std=c11 -pedantic $(VERSION) \ -+ -std=c11 -pedantic $(VERSION) \ - -Wno-variadic-macros -I $(TOP)/src/commonlib/bsd/include - LDFLAGS += -lz - -@@ -24,8 +24,8 @@ ifeq ($(OS_ARCH), Darwin) - LIBS = -framework IOKit -framework DirectHW -lpci -lz - endif - ifeq ($(OS_ARCH), FreeBSD) --CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \ -- -Werror-implicit-function-declaration -std=c11 $(VERSION) \ -+CFLAGS = -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \ -+ -std=c11 $(VERSION) \ - -I/usr/local/include - LDFLAGS += -L/usr/local/lib - LIBS = -lz -diff --git a/util/uio_usbdebug/Makefile b/util/uio_usbdebug/Makefile -index af1cc8e1ec..2ceb28cd53 100644 ---- a/util/uio_usbdebug/Makefile -+++ b/util/uio_usbdebug/Makefile -@@ -30,7 +30,7 @@ KCONFIG_H := ../../src/include/kconfig.h - - CFLAGS += \ - -m32 -g \ -- -Wall -Wextra -Werror \ -+ -Wall -Wextra \ - -Wno-unused-parameter -Wno-error=sign-compare - CPPFLAGS += \ - -Iinclude/ \ -diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile -index f88da69306..ef43e28683 100755 ---- a/util/xcompile/xcompile -+++ b/util/xcompile/xcompile -@@ -124,7 +124,7 @@ testcc() { - local tmp_o="$TMPFILE.o" - rm -f "$tmp_c" "$tmp_o" - echo "void _start(void) {}" >"$tmp_c" -- "$cc" -nostdlib -Werror $cflags -c "$tmp_c" -o "$tmp_o" >/dev/null 2>&1 -+ "$cc" -nostdlib $cflags -c "$tmp_c" -o "$tmp_o" >/dev/null 2>&1 - } - - testld() { --- -2.47.3 - -- cgit v1.2.1