From d8ac9d53b66a3a940962945c4102f1fcd644cde1 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 27 Oct 2024 01:12:56 +0100 Subject: Switch Dell 3050 Micro to newer coreboot revision Specifically, use the same revision that Mate used in patchset 15. This will ensure that any issues are *not* caused by the coreboot revision; this is being done, because the old coreboot revision was from July, but patchset 15 from Mate is based on a September revision of coreboot. I've been eliminating as many variables as possible, trying to fix SeaBIOS payload on this machine, because it hangs in Libreboot, but not when building from gerrit directly, which means the coreboot revision may be a factor (since I'm using his patches on an older revision so upstream might have made some changes since then that the port relies on). For this, a new coreboot tree is used, called "dell7", referring to the fact that Kabylake is Intel's 7th generation. Signed-off-by: Leah Rowe --- .../0061-WIP-OptiPlex-3050-Micro-port.patch | 1421 -------------------- .../0064-dell-optiplex_3050-add-hda_verb.c.patch | 140 -- .../0065-dell-optiplex_3050-Add-data.vbt.patch | 74 - .../config/libgfxinit_corebootfb | 40 +- .../config/libgfxinit_txtmode | 36 +- config/coreboot/dell3050micro_fsp_16mb/target.cfg | 4 +- .../0001-WIP-OptiPlex-3050-Micro-port.patch | 1421 ++++++++++++++++++++ .../0002-dell-optiplex_3050-add-hda_verb.c.patch | 140 ++ .../0003-dell-optiplex_3050-Add-data.vbt.patch | 74 + ...ing-for-coreboot-images-built-without-a-p.patch | 39 + config/coreboot/dell7/target.cfg | 2 + .../dell7010sff_12mb/config/libgfxinit_txtmode | 1 - .../config/libgfxinit_corebootfb | 1 - .../dell9020mt_nri_12mb/config/libgfxinit_txtmode | 1 - .../config/libgfxinit_corebootfb | 1 - .../dell9020sff_nri_12mb/config/libgfxinit_txtmode | 1 - .../e4300_4mb/config/libgfxinit_corebootfb | 1 - .../coreboot/e4300_4mb/config/libgfxinit_txtmode | 1 - .../e5420_6mb/config/libgfxinit_corebootfb | 1 - .../coreboot/e5420_6mb/config/libgfxinit_txtmode | 1 - .../e5520_6mb/config/libgfxinit_corebootfb | 1 - .../coreboot/e5520_6mb/config/libgfxinit_txtmode | 1 - .../e5530_12mb/config/libgfxinit_corebootfb | 1 - .../coreboot/e5530_12mb/config/libgfxinit_txtmode | 1 - .../e6220_10mb/config/libgfxinit_corebootfb | 1 - .../coreboot/e6220_10mb/config/libgfxinit_txtmode | 1 - .../e6230_12mb/config/libgfxinit_corebootfb | 1 - .../coreboot/e6230_12mb/config/libgfxinit_txtmode | 1 - .../e6320_10mb/config/libgfxinit_corebootfb | 1 - .../coreboot/e6320_10mb/config/libgfxinit_txtmode | 1 - .../e6330_12mb/config/libgfxinit_corebootfb | 1 - .../coreboot/e6330_12mb/config/libgfxinit_txtmode | 1 - .../e6400_4mb/config/libgfxinit_corebootfb | 1 - .../coreboot/e6400_4mb/config/libgfxinit_txtmode | 1 - config/coreboot/e6400nvidia_4mb/config/normal | 1 - .../e6420_10mb/config/libgfxinit_corebootfb | 1 - .../coreboot/e6420_10mb/config/libgfxinit_txtmode | 1 - .../e6430_12mb/config/libgfxinit_corebootfb | 1 - .../coreboot/e6430_12mb/config/libgfxinit_txtmode | 1 - .../e6520_10mb/config/libgfxinit_corebootfb | 1 - .../coreboot/e6520_10mb/config/libgfxinit_txtmode | 1 - .../e6530_12mb/config/libgfxinit_corebootfb | 1 - .../coreboot/e6530_12mb/config/libgfxinit_txtmode | 1 - .../coreboot/t1650_12mb/config/libgfxinit_txtmode | 1 - .../dell7/acpica-unix-20230628.tar.gz/module.cfg | 3 + .../dell7/binutils-2.43.1.tar.xz/module.cfg | 3 + config/submodule/coreboot/dell7/fsp/module.cfg | 3 + .../coreboot/dell7/gcc-14.2.0.tar.xz/module.cfg | 3 + .../coreboot/dell7/gmp-6.3.0.tar.xz/module.cfg | 3 + .../coreboot/dell7/intel-microcode/module.cfg | 3 + .../submodule/coreboot/dell7/libgfxinit/module.cfg | 3 + ...gma-plls.adb-Make-reference-clock-frequen.patch | 42 + .../submodule/coreboot/dell7/libhwbase/module.cfg | 3 + config/submodule/coreboot/dell7/module.list | 12 + .../coreboot/dell7/mpc-1.3.1.tar.gz/module.cfg | 3 + .../coreboot/dell7/mpfr-4.2.1.tar.xz/module.cfg | 3 + .../coreboot/dell7/nasm-2.16.03.tar.bz2/module.cfg | 3 + config/submodule/coreboot/dell7/vboot/module.cfg | 3 + ...inuz.c-Fix-the-bounds-check-on-vmlinuz_he.patch | 178 +++ 59 files changed, 1998 insertions(+), 1694 deletions(-) delete mode 100644 config/coreboot/default/patches/0061-WIP-OptiPlex-3050-Micro-port.patch delete mode 100644 config/coreboot/default/patches/0064-dell-optiplex_3050-add-hda_verb.c.patch delete mode 100644 config/coreboot/default/patches/0065-dell-optiplex_3050-Add-data.vbt.patch create mode 100644 config/coreboot/dell7/patches/0001-WIP-OptiPlex-3050-Micro-port.patch create mode 100644 config/coreboot/dell7/patches/0002-dell-optiplex_3050-add-hda_verb.c.patch create mode 100644 config/coreboot/dell7/patches/0003-dell-optiplex_3050-Add-data.vbt.patch create mode 100644 config/coreboot/dell7/patches/0004-Remove-warning-for-coreboot-images-built-without-a-p.patch create mode 100644 config/coreboot/dell7/target.cfg create mode 100644 config/submodule/coreboot/dell7/acpica-unix-20230628.tar.gz/module.cfg create mode 100644 config/submodule/coreboot/dell7/binutils-2.43.1.tar.xz/module.cfg create mode 100644 config/submodule/coreboot/dell7/fsp/module.cfg create mode 100644 config/submodule/coreboot/dell7/gcc-14.2.0.tar.xz/module.cfg create mode 100644 config/submodule/coreboot/dell7/gmp-6.3.0.tar.xz/module.cfg create mode 100644 config/submodule/coreboot/dell7/intel-microcode/module.cfg create mode 100644 config/submodule/coreboot/dell7/libgfxinit/module.cfg create mode 100644 config/submodule/coreboot/dell7/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch create mode 100644 config/submodule/coreboot/dell7/libhwbase/module.cfg create mode 100644 config/submodule/coreboot/dell7/module.list create mode 100644 config/submodule/coreboot/dell7/mpc-1.3.1.tar.gz/module.cfg create mode 100644 config/submodule/coreboot/dell7/mpfr-4.2.1.tar.xz/module.cfg create mode 100644 config/submodule/coreboot/dell7/nasm-2.16.03.tar.bz2/module.cfg create mode 100644 config/submodule/coreboot/dell7/vboot/module.cfg create mode 100644 config/submodule/coreboot/dell7/vboot/patches/0001-extract_vmlinuz.c-Fix-the-bounds-check-on-vmlinuz_he.patch diff --git a/config/coreboot/default/patches/0061-WIP-OptiPlex-3050-Micro-port.patch b/config/coreboot/default/patches/0061-WIP-OptiPlex-3050-Micro-port.patch deleted file mode 100644 index a808fb3f..00000000 --- a/config/coreboot/default/patches/0061-WIP-OptiPlex-3050-Micro-port.patch +++ /dev/null @@ -1,1421 +0,0 @@ -From 66896f156eaade2c01636ac445cfd47afa6a32cc Mon Sep 17 00:00:00 2001 -From: Mate Kukri -Date: Thu, 24 Oct 2024 18:05:19 +0100 -Subject: [PATCH 61/65] [WIP] OptiPlex 3050 Micro port - -- Boots Linux -- SMSC SCH5553 SIO/EC - + Serial port works - + PWM fan control works -- Realtek Gigabit LAN works -- WiFi slot works -- NVMe SSD slot works -- Extra: LPSS UART0 - + Stock FW sets undocumented power gating bit, RTC battery needs to - be pulled for it to work. - + Signals exposed on test points on the back of the board. - FIXME: add documentation about this -- Needs 'deguard' to bypass BootGuard - + See https://review.coreboot.org/plugins/gitiles/deguard -- TODO: HDA verbs -- TODO: USB ports -- TODO: Add VBT -- Currently limited to the Micro form factor, but others are very - similar - -Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 -Signed-off-by: Mate Kukri ---- - src/mainboard/dell/optiplex_3050/Kconfig | 32 ++ - src/mainboard/dell/optiplex_3050/Kconfig.name | 4 + - src/mainboard/dell/optiplex_3050/Makefile.mk | 9 + - src/mainboard/dell/optiplex_3050/acpi/ec.asl | 3 + - .../dell/optiplex_3050/acpi/superio.asl | 3 + - .../dell/optiplex_3050/board_info.txt | 7 + - src/mainboard/dell/optiplex_3050/bootblock.c | 107 ++++ - src/mainboard/dell/optiplex_3050/cmos.default | 5 + - src/mainboard/dell/optiplex_3050/cmos.layout | 54 ++ - .../dell/optiplex_3050/devicetree.cb | 119 ++++ - src/mainboard/dell/optiplex_3050/dsdt.asl | 27 + - .../dell/optiplex_3050/gma-mainboard.ads | 19 + - .../dell/optiplex_3050/include/early_gpio.h | 11 + - .../dell/optiplex_3050/include/gpio.h | 241 ++++++++ - src/mainboard/dell/optiplex_3050/ramstage.c | 513 ++++++++++++++++++ - src/mainboard/dell/optiplex_3050/romstage.c | 26 + - src/mainboard/dell/optiplex_3050/sch5555_ec.c | 54 ++ - src/mainboard/dell/optiplex_3050/sch5555_ec.h | 10 + - 18 files changed, 1244 insertions(+) - create mode 100644 src/mainboard/dell/optiplex_3050/Kconfig - create mode 100644 src/mainboard/dell/optiplex_3050/Kconfig.name - create mode 100644 src/mainboard/dell/optiplex_3050/Makefile.mk - create mode 100644 src/mainboard/dell/optiplex_3050/acpi/ec.asl - create mode 100644 src/mainboard/dell/optiplex_3050/acpi/superio.asl - create mode 100644 src/mainboard/dell/optiplex_3050/board_info.txt - create mode 100644 src/mainboard/dell/optiplex_3050/bootblock.c - create mode 100644 src/mainboard/dell/optiplex_3050/cmos.default - create mode 100644 src/mainboard/dell/optiplex_3050/cmos.layout - create mode 100644 src/mainboard/dell/optiplex_3050/devicetree.cb - create mode 100644 src/mainboard/dell/optiplex_3050/dsdt.asl - create mode 100644 src/mainboard/dell/optiplex_3050/gma-mainboard.ads - create mode 100644 src/mainboard/dell/optiplex_3050/include/early_gpio.h - create mode 100644 src/mainboard/dell/optiplex_3050/include/gpio.h - create mode 100644 src/mainboard/dell/optiplex_3050/ramstage.c - create mode 100644 src/mainboard/dell/optiplex_3050/romstage.c - create mode 100644 src/mainboard/dell/optiplex_3050/sch5555_ec.c - create mode 100644 src/mainboard/dell/optiplex_3050/sch5555_ec.h - -diff --git a/src/mainboard/dell/optiplex_3050/Kconfig b/src/mainboard/dell/optiplex_3050/Kconfig -new file mode 100644 -index 0000000000..2f0dccb98d ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/Kconfig -@@ -0,0 +1,32 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+if BOARD_DELL_OPTIPLEX_3050 -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ select BOARD_ROMSIZE_KB_16384 -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ # select INTEL_GMA_HAVE_VBT -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_SUPPORTS_KABYLAKE_CPU -+ select MAINBOARD_SUPPORTS_SKYLAKE_CPU -+ select SKYLAKE_SOC_PCH_H -+ select SOC_INTEL_KABYLAKE -+ select SUPERIO_SMSC_SCH555x -+ -+config CBFS_SIZE -+ default 0x900000 -+ -+config MAINBOARD_DIR -+ default "dell/optiplex_3050" -+ -+config MAINBOARD_PART_NUMBER -+ default "OptiPlex 3050 Micro" -+ -+config DIMM_SPD_SIZE -+ default 512 # DDR4 -+ -+endif -diff --git a/src/mainboard/dell/optiplex_3050/Kconfig.name b/src/mainboard/dell/optiplex_3050/Kconfig.name -new file mode 100644 -index 0000000000..14eab7f52c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/Kconfig.name -@@ -0,0 +1,4 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_DELL_OPTIPLEX_3050 -+ bool "OptiPlex 3050 Micro" -diff --git a/src/mainboard/dell/optiplex_3050/Makefile.mk b/src/mainboard/dell/optiplex_3050/Makefile.mk -new file mode 100644 -index 0000000000..d50ea40879 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/Makefile.mk -@@ -0,0 +1,9 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+bootblock-y += bootblock.c -+bootblock-y += sch5555_ec.c -+ -+romstage-y += romstage.c -+ -+ramstage-y += ramstage.c sch5555_ec.c -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -diff --git a/src/mainboard/dell/optiplex_3050/acpi/ec.asl b/src/mainboard/dell/optiplex_3050/acpi/ec.asl -new file mode 100644 -index 0000000000..16990d45f4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/acpi/ec.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: CC-PDDC */ -+ -+/* Please update the license if adding licensable material. */ -diff --git a/src/mainboard/dell/optiplex_3050/acpi/superio.asl b/src/mainboard/dell/optiplex_3050/acpi/superio.asl -new file mode 100644 -index 0000000000..16990d45f4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/acpi/superio.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: CC-PDDC */ -+ -+/* Please update the license if adding licensable material. */ -diff --git a/src/mainboard/dell/optiplex_3050/board_info.txt b/src/mainboard/dell/optiplex_3050/board_info.txt -new file mode 100644 -index 0000000000..47a4a3a4f3 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/board_info.txt -@@ -0,0 +1,7 @@ -+Category: desktop -+Board URL: https://www.dell.com/support/kbdoc/en-uk/000124265/dell-optiplex-3050-system-guide -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2017 -diff --git a/src/mainboard/dell/optiplex_3050/bootblock.c b/src/mainboard/dell/optiplex_3050/bootblock.c -new file mode 100644 -index 0000000000..10689c42a1 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/bootblock.c -@@ -0,0 +1,107 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include -+#include "include/early_gpio.h" -+#include "sch5555_ec.h" -+ -+struct ec_init_entry { -+ uint16_t addr; -+ uint8_t val; -+}; -+ -+static void bootblock_ec_init(void) -+{ -+ /* -+ * Early EC init -+ */ -+ -+ static const struct ec_init_entry init_table1[] = { -+ {0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10}, -+ {0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10}, -+ {0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12}, -+ {0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12}, -+ {0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10}, -+ {0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11}, -+ }; -+ -+ for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i) -+ sch5555_mbox_write(2, init_table1[i].addr, init_table1[i].val); -+ -+ static const struct ec_init_entry init_table2[] = { -+ {0x0040, 0x00}, {0x00f8, 0x10}, {0x00f9, 0x00}, {0x00f0, 0x30}, -+ {0x00fa, 0x00}, {0x00fb, 0x00}, {0x00ea, 0x00}, {0x00eb, 0x00}, -+ {0x00ef, 0x7c}, {0x0005, 0x0f}, {0x0014, 0x01}, {0x0018, 0x2f}, -+ {0x0019, 0x2f}, {0x001a, 0x2f}, {0x001b, 0x2f}, {0x01d8, 0x01}, -+ {0x0040, 0x11}, -+ }; -+ -+ for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i) -+ sch5555_mbox_write(1, init_table2[i].addr, init_table2[i].val); -+ -+ sch5555_mbox_write(1, 0x000b, 0x01); -+ sch5555_mbox_write(4, 0x001a, 0x04); -+ sch5555_mbox_write(4, 0x0028, 0x18); -+ sch5555_mbox_write(4, 0x001a, 0x00); -+ sch5555_mbox_write(1, 0x000b, 0x03); -+ -+ /* -+ * Early HWM init -+ */ -+ -+ sch5555_mbox_read(1, 0xcb); -+ sch5555_mbox_read(1, 0xb8); -+ -+ static const struct ec_init_entry hwm_init_table[] = { -+ {0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f}, -+ {0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33}, -+ {0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff}, -+ {0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00}, -+ {0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00}, -+ {0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80}, -+ {0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02}, -+ {0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04}, -+ {0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50}, -+ {0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50}, -+ {0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c}, -+ {0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd}, -+ {0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e}, -+ {0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00}, -+ {0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff}, -+ {0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00}, -+ {0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c}, -+ {0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02}, -+ {0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03}, {0x0015, 0x33}, -+ {0x018b, 0x00}, {0x018c, 0x00}, {0x02f8, 0x5e}, {0x02f9, 0x01}, -+ }; -+ -+ for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i) -+ sch5555_mbox_write(1, hwm_init_table[i].addr, hwm_init_table[i].val); -+} -+ -+ -+#define SCH555x_IOBASE 0x2e -+#define GLOBAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL) -+#define SERIAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1) -+ -+void bootblock_mainboard_early_init(void) -+{ -+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -+ -+ // Super I/O early init will map Runtime and EMI registers -+ sch555x_early_init(GLOBAL_DEV); -+ -+ // Changes LED color among a few other things -+ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS); -+ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN); -+ outb(0xf, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); -+ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); -+ -+ // Perform bootblock EC initialization -+ bootblock_ec_init(); -+ -+ // Bootblock EC initialization is required for UART1 to work -+ sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -+} -diff --git a/src/mainboard/dell/optiplex_3050/cmos.default b/src/mainboard/dell/optiplex_3050/cmos.default -new file mode 100644 -index 0000000000..79961f43d8 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/cmos.default -@@ -0,0 +1,5 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -diff --git a/src/mainboard/dell/optiplex_3050/cmos.layout b/src/mainboard/dell/optiplex_3050/cmos.layout -new file mode 100644 -index 0000000000..54a5147b7d ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/cmos.layout -@@ -0,0 +1,54 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+#start-bit length config config-ID name -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+# coreboot config options: southbridge -+409 2 e 7 power_on_after_fail -+ -+# coreboot config options: bootloader -+#Used by ChromeOS: -+416 128 r 0 vbnv -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 415 984 -diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb -new file mode 100644 -index 0000000000..eb731fe48f ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/devicetree.cb -@@ -0,0 +1,119 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+chip soc/intel/skylake -+ register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN" -+ -+ # Enable Enhanced Intel SpeedStep -+ register "eist_enable" = "1" -+ -+ device cpu_cluster 0 on end -+ -+ device domain 0 on -+ device ref igpu on -+ register "PrimaryDisplay" = "Display_iGFX" -+ end -+ -+ device ref south_xhci on -+ register "usb2_ports" = "{ -+ [0] = USB2_PORT_MID(OC0), -+ [1] = USB2_PORT_MID(OC0), -+ [2] = USB2_PORT_MID(OC4), -+ [3] = USB2_PORT_MID(OC4), -+ [4] = USB2_PORT_MID(OC2), -+ [5] = USB2_PORT_MID(OC2), -+ [6] = USB2_PORT_MID(OC0), -+ [7] = USB2_PORT_MID(OC0), -+ [8] = USB2_PORT_MID(OC0), -+ [9] = USB2_PORT_MID(OC0), -+ [10] = USB2_PORT_MID(OC1), -+ [11] = USB2_PORT_MID(OC1), -+ [12] = USB2_PORT_MID(OC_SKIP), -+ [13] = USB2_PORT_MID(OC_SKIP), -+ }" -+ register "usb3_ports" = "{ -+ [0] = USB3_PORT_DEFAULT(OC0), -+ [1] = USB3_PORT_DEFAULT(OC0), -+ [2] = USB3_PORT_DEFAULT(OC3), -+ [3] = USB3_PORT_DEFAULT(OC3), -+ [4] = USB3_PORT_DEFAULT(OC1), -+ [5] = USB3_PORT_DEFAULT(OC1), -+ [6] = USB3_PORT_DEFAULT(OC_SKIP), -+ [7] = USB3_PORT_DEFAULT(OC_SKIP), -+ [8] = USB3_PORT_DEFAULT(OC_SKIP), -+ [9] = USB3_PORT_DEFAULT(OC_SKIP), -+ }" -+ end -+ -+ # ME interface is 'off' to avoid HECI reset delay due to HAP -+ device ref heci1 off end -+ -+ device ref sata on -+ register "SataSalpSupport" = "1" -+ register "SataPortsEnable[0]" = "1" -+ end -+ -+ device ref pcie_rp21 on -+ register "PcieRpEnable[20]" = "1" -+ register "PcieRpClkReqSupport[20]" = "1" -+ register "PcieRpClkReqNumber[20]" = "3" -+ register "PcieRpAdvancedErrorReporting[20]" = "1" -+ register "PcieRpLtrEnable[20]" = "1" -+ register "PcieRpClkSrcNumber[20]" = "3" -+ register "PcieRpHotPlug[20]" = "1" -+ end -+ -+ # Realtek LAN -+ device ref pcie_rp5 on -+ register "PcieRpEnable[4]" = "1" -+ register "PcieRpClkReqSupport[4]" = "0" -+ register "PcieRpHotPlug[4]" = "0" -+ end -+ -+ # M.2 WiFi -+ device ref pcie_rp8 on -+ register "PcieRpEnable[7]" = "1" -+ register "PcieRpClkReqSupport[7]" = "0" -+ register "PcieRpHotPlug[7]" = "1" -+ end -+ -+ # UART0 is exposed on test points on the bottom of the board -+ device ref uart0 on -+ register "SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci" -+ end -+ -+ device ref lpc_espi on -+ register "serirq_mode" = "SERIRQ_CONTINUOUS" -+ -+ # I/O decode for EMI/Runtime registers -+ register "gen1_dec" = "0x007c0a01" -+ -+ # SCH5553 -+ chip superio/smsc/sch555x -+ device pnp 2e.0 on # EMI -+ io 0x60 = 0xa00 -+ end -+ device pnp 2e.1 off end # 8042 -+ device pnp 2e.7 on # UART1 -+ io 0x60 = 0x3f8 -+ irq 0x0f = 2 -+ irq 0x70 = 4 -+ end -+ device pnp 2e.8 off end # UART2 -+ device pnp 2e.c on # LPC interface -+ io 0x60 = 0x2e -+ end -+ device pnp 2e.a on # Runtime registers -+ io 0x60 = 0xa40 -+ end -+ device pnp 2e.b off end # Floppy Controller -+ device pnp 2e.11 off end # Parallel Port -+ end -+ end -+ -+ device ref hda on -+ register "PchHdaVcType" = "Vc1" -+ end -+ -+ device ref smbus on end -+ end -+end -diff --git a/src/mainboard/dell/optiplex_3050/dsdt.asl b/src/mainboard/dell/optiplex_3050/dsdt.asl -new file mode 100644 -index 0000000000..9762f6ff74 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/dsdt.asl -@@ -0,0 +1,27 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20110725 -+) -+{ -+ #include -+ #include -+ #include -+ -+ Scope (\_SB) -+ { -+ Device (PCI0) -+ { -+ #include -+ #include -+ } -+ } -+ -+ #include -+} -diff --git a/src/mainboard/dell/optiplex_3050/gma-mainboard.ads b/src/mainboard/dell/optiplex_3050/gma-mainboard.ads -new file mode 100644 -index 0000000000..cb4c22f285 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/gma-mainboard.ads -@@ -0,0 +1,19 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ (HDMI1, -- External HDMI -+ DP2, -- External DP (native) -+ HDMI2, -- External DP (DP++) -+ DP3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) -+ HDMI3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/optiplex_3050/include/early_gpio.h b/src/mainboard/dell/optiplex_3050/include/early_gpio.h -new file mode 100644 -index 0000000000..17a16371e3 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/include/early_gpio.h -@@ -0,0 +1,11 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __OPTIPLEX_3050_EARLY_GPIO_H__ -+#define __OPTIPLEX_3050_EARLY_GPIO_H__ -+ -+static const struct pad_config early_gpio_table[] = { -+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ -+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ -+}; -+ -+#endif -diff --git a/src/mainboard/dell/optiplex_3050/include/gpio.h b/src/mainboard/dell/optiplex_3050/include/gpio.h -new file mode 100644 -index 0000000000..83293c32a9 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/include/gpio.h -@@ -0,0 +1,241 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __OPTIPLEX_3050_GPIO_H__ -+#define __OPTIPLEX_3050_GPIO_H__ -+ -+static const struct pad_config gpio_table[] = { -+ -+ /* ------- GPIO Community 0 ------- */ -+ -+ /* ------- GPIO Group GPP_A ------- */ -+ PAD_CFG_NF(GPP_A0, UP_20K, PLTRST, NF1), /* RCIN# */ -+ PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* LAD0 */ -+ PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* LAD1 */ -+ PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* LAD2 */ -+ PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* LAD3 */ -+ PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */ -+ PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKRUN# */ -+ PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), /* CLKOUT_LPC0 */ -+ PAD_CFG_NF(GPP_A10, NONE, PLTRST, NF1), /* CLKOUT_LPC1 */ -+ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), /* PME# */ -+ PAD_CFG_GPO(GPP_A12, 0, PLTRST), /* GPIO */ -+ PAD_CFG_NF(GPP_A13, NONE, PLTRST, NF1), /* SUSWARN#/SUSPWRDNACK */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_A15, UP_20K, PLTRST, NF1), /* SUS_ACK# */ -+ PAD_CFG_GPO(GPP_A16, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_B ------- */ -+ PAD_CFG_GPO(GPP_B0, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B1, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B2, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_B3, 1, RSMRST), /* GPIO (ME_CNTL, B3 -> LOW => HDA_SDO -> HIGH) */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_B5, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B6, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B7, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_B9, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1), /* SLP_S0# */ -+ PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), /* PLTRST# */ -+ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* SPKR */ -+ PAD_CFG_GPO(GPP_B15, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B16, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* GSPIO_MOSI */ -+ PAD_CFG_GPO(GPP_B19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B20, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* GPIO */ -+ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), /* GSPI1_MOSI */ -+ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), /* PCHHOT# */ -+ -+ /* ------- GPIO Community 1 ------- */ -+ -+ /* ------- GPIO Group GPP_C ------- */ -+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ -+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_C2, DN_20K, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_C3, NONE, PLTRST, NF1), /* SML0CLK */ -+ PAD_CFG_NF(GPP_C4, NONE, PLTRST, NF1), /* SML0DATA */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK */ -+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1DATA */ -+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ -+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ -+ PAD_CFG_GPO(GPP_C10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C11, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C12, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C13, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C14, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C15, 0, PLTRST), /* GPIO */ -+ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), /* I2C0_SDA */ -+ PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), /* I2C0_SCL */ -+ PAD_CFG_GPO(GPP_C18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C21, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_D ------- */ -+ PAD_CFG_GPO(GPP_D0, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D1, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D2, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D3, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_D6, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_D7, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D8, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D9, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D11, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D13, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D14, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D15, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D16, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D21, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_E ------- */ -+ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATAXPCIE0 */ -+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SATAXPCIE1 */ -+ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* SATAXPCIE2 */ -+ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* SATA_LED# */ -+ PAD_CFG_NF(GPP_E9, UP_20K, PLTRST, NF1), /* USB_OC0# */ -+ PAD_CFG_NF(GPP_E10, UP_20K, PLTRST, NF1), /* USB_OC1# */ -+ PAD_CFG_NF(GPP_E11, UP_20K, PLTRST, NF1), /* USB_OC2# */ -+ PAD_CFG_NF(GPP_E12, UP_20K, PLTRST, NF1), /* USB_OC3# */ -+ -+ /* ------- GPIO Group GPP_F ------- */ -+ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* SATAXPCIE3 */ -+ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* SATAXPCIE4 */ -+ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* SATAXPCIE5 */ -+ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* SATAXPCIE6 */ -+ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* SATAXPCIE7 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_F6, NONE, RSMRST, NF1), /* SATA_DEVSLP4 */ -+ PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_F9, 0, RSMRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_F13, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), /* USB_OC4# */ -+ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), /* USB_OC5# */ -+ PAD_CFG_NF(GPP_F17, UP_20K, PLTRST, NF1), /* USB_OC6# */ -+ PAD_CFG_TERM_GPO(GPP_F18, 0, UP_20K, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_F19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_F20, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_F21, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_F22, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_F23, 1, RSMRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_G ------- */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_G9, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_G12, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_G14, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G15, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G16, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G17, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_G19, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G20, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_G21, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G22, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_H ------- */ -+ PAD_CFG_GPO(GPP_H0, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H2, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H3, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H4, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H5, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H6, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_H7, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H8, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H9, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H11, 0, PLTRST), /* GPIO */ -+ PAD_CFG_TERM_GPO(GPP_H12, 1, DN_20K, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H15, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H16, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H21, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Community 2 ------- */ -+ -+ /* -------- GPIO Group GPD -------- */ -+ PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* BATLOW# */ -+ PAD_CFG_GPO(GPD1, 0, PWROK), /* GPIO */ -+ PAD_CFG_NF(GPD2, NONE, RSMRST, NF1), /* LAN_WAKE# */ -+ PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), /* PWRBTN# */ -+ PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */ -+ PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */ -+ PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* SLP_A# */ -+ PAD_CFG_GPO(GPD7, 1, RSMRST), /* GPIO */ -+ PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* SUSCLK */ -+ PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */ -+ PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */ -+ PAD_CFG_GPO(GPD11, 1, RSMRST), /* GPIO */ -+ -+ /* ------- GPIO Community 3 ------- */ -+ -+ /* ------- GPIO Group GPP_I ------- */ -+ PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */ -+ PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPC_HPD1 */ -+ PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DDPD_HPD2 */ -+ PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* DDPE_HPD3 */ -+ PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), /* EDP_HPD */ -+ PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* DDPB_CTRLCLK */ -+ PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), /* DDPB_CTRLDATA */ -+ PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* DDPC_CTRLCLK */ -+ PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), /* DDPC_CTRLDATA */ -+ PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */ -+ PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), /* DDPD_CTRLDATA */ -+}; -+ -+#endif -diff --git a/src/mainboard/dell/optiplex_3050/ramstage.c b/src/mainboard/dell/optiplex_3050/ramstage.c -new file mode 100644 -index 0000000000..5cf2c81e50 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/ramstage.c -@@ -0,0 +1,513 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "include/gpio.h" -+#include "sch5555_ec.h" -+ -+void mainboard_silicon_init_params(FSP_SIL_UPD *params) -+{ -+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -+} -+ -+#define FORM_FACTOR_MICRO 0 -+#define FORM_FACTOR_SFF 1 -+// NOTE: one of these is MT, but 2 and 3 both get the same table anyways -+#define FORM_FACTOR_UNK2 2 -+#define FORM_FACTOR_UNK3 3 -+ -+#define HWM_TAB_ADD_TEMP_TARGET 1 -+#define HWM_TAB_PKG_POWER_ANY 0xffff -+ -+struct hwm_tab_entry { -+ uint16_t addr; -+ uint8_t val; -+ uint8_t flags; -+ uint16_t pkg_power; -+}; -+ -+static const struct hwm_tab_entry HWM_TAB_MICRO_BASE[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x01b, 0x0f, 0, 0xffff }, -+ { 0x057, 0xff, 0, 0xffff }, -+ { 0x059, 0xff, 0, 0xffff }, -+ { 0x05b, 0xff, 0, 0xffff }, -+ { 0x05d, 0xff, 0, 0xffff }, -+ { 0x05f, 0xff, 0, 0xffff }, -+ { 0x061, 0xff, 0, 0xffff }, -+ { 0x06e, 0x00, 0, 0xffff }, -+ { 0x06f, 0x03, 0, 0xffff }, -+ { 0x070, 0x03, 0, 0xffff }, -+ { 0x071, 0x02, 0, 0xffff }, -+ { 0x072, 0x02, 0, 0xffff }, -+ { 0x073, 0x01, 0, 0xffff }, -+ { 0x074, 0x06, 0, 0xffff }, -+ { 0x075, 0x07, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x80, 0, 0xffff }, -+ { 0x082, 0x80, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0xf1, 0, 0xffff }, -+ { 0x086, 0x88, 0, 0xffff }, -+ { 0x087, 0x61, 0, 0xffff }, -+ { 0x088, 0x08, 0, 0xffff }, -+ { 0x089, 0x00, 0, 0xffff }, -+ { 0x08a, 0x73, 0, 0xffff }, -+ { 0x08b, 0x73, 0, 0xffff }, -+ { 0x08c, 0x73, 0, 0xffff }, -+ { 0x090, 0x6d, 0, 0xffff }, -+ { 0x091, 0x7e, 0, 0xffff }, -+ { 0x092, 0x66, 0, 0xffff }, -+ { 0x093, 0xa4, 0, 0xffff }, -+ { 0x094, 0x7c, 0, 0xffff }, -+ { 0x095, 0xa4, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x099, 0xa4, 0, 0xffff }, -+ { 0x09a, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x2e, 0, 0xffff }, -+ { 0x0a1, 0x00, 0, 0xffff }, -+ { 0x0a2, 0x00, 0, 0xffff }, -+ { 0x0ae, 0xa4, 0, 0xffff }, -+ { 0x0af, 0xa4, 0, 0xffff }, -+ { 0x0b0, 0xa4, 0, 0xffff }, -+ { 0x0b1, 0xa4, 0, 0xffff }, -+ { 0x0b2, 0xa4, 0, 0xffff }, -+ { 0x0b3, 0xa4, 0, 0xffff }, -+ { 0x0b6, 0x00, 0, 0xffff }, -+ { 0x0b7, 0x00, 0, 0xffff }, -+ { 0x0d1, 0xff, 0, 0xffff }, -+ { 0x0d6, 0xff, 0, 0xffff }, -+ { 0x0db, 0xff, 0, 0xffff }, -+ { 0x0ea, 0x5c, 0, 0xffff }, -+ { 0x0eb, 0x5c, 0, 0xffff }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x184, 0xff, 0, 0xffff }, -+ { 0x186, 0xff, 0, 0xffff }, -+ { 0x1a1, 0xce, 0, 0xffff }, -+ { 0x1a2, 0x0c, 0, 0xffff }, -+ { 0x1a3, 0x0c, 0, 0xffff }, -+ { 0x1a6, 0x00, 0, 0xffff }, -+ { 0x1a7, 0x00, 0, 0xffff }, -+ { 0x1a8, 0xa4, 0, 0xffff }, -+ { 0x1a9, 0xa4, 0, 0xffff }, -+ { 0x1ab, 0x2d, 0, 0xffff }, -+ { 0x1ac, 0x2d, 0, 0xffff }, -+ { 0x1b1, 0x00, 0, 0xffff }, -+ { 0x1bb, 0x00, 0, 0xffff }, -+ { 0x1bc, 0x00, 0, 0xffff }, -+ { 0x1bd, 0x00, 0, 0xffff }, -+ { 0x1be, 0x01, 0, 0xffff }, -+ { 0x1bf, 0x01, 0, 0xffff }, -+ { 0x1c0, 0x01, 0, 0xffff }, -+ { 0x1c1, 0x01, 0, 0xffff }, -+ { 0x1c2, 0x01, 0, 0xffff }, -+ { 0x280, 0x00, 0, 0xffff }, -+ { 0x281, 0x00, 0, 0xffff }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x040, 0x01, 0, 0xffff }, -+}; -+ -+static const struct hwm_tab_entry HWM_TAB_MICRO_TEMP80[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x01b, 0x0f, 0, 0xffff }, -+ { 0x057, 0xff, 0, 0xffff }, -+ { 0x059, 0xff, 0, 0xffff }, -+ { 0x05b, 0xff, 0, 0xffff }, -+ { 0x05d, 0xff, 0, 0xffff }, -+ { 0x05f, 0xff, 0, 0xffff }, -+ { 0x061, 0xff, 0, 0xffff }, -+ { 0x06e, 0x00, 0, 0xffff }, -+ { 0x06f, 0x03, 0, 0xffff }, -+ { 0x070, 0x03, 0, 0xffff }, -+ { 0x071, 0x02, 0, 0xffff }, -+ { 0x072, 0x02, 0, 0xffff }, -+ { 0x073, 0x01, 0, 0xffff }, -+ { 0x074, 0x06, 0, 0xffff }, -+ { 0x075, 0x07, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x80, 0, 0xffff }, -+ { 0x082, 0x80, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0xf6, 0, 0xffff }, -+ { 0x086, 0x88, 0, 0xffff }, -+ { 0x087, 0x61, 0, 0xffff }, -+ { 0x088, 0x08, 0, 0xffff }, -+ { 0x089, 0x00, 0, 0xffff }, -+ { 0x08a, 0x73, 0, 0xffff }, -+ { 0x08b, 0x73, 0, 0xffff }, -+ { 0x08c, 0x73, 0, 0xffff }, -+ { 0x090, 0x6d, 0, 0xffff }, -+ { 0x091, 0x86, 0, 0xffff }, -+ { 0x092, 0x66, 0, 0xffff }, -+ { 0x093, 0xa4, 0, 0xffff }, -+ { 0x094, 0x7c, 0, 0xffff }, -+ { 0x095, 0xa4, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x099, 0xa4, 0, 0xffff }, -+ { 0x09a, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x2e, 0, 0xffff }, -+ { 0x0a1, 0x00, 0, 0xffff }, -+ { 0x0a2, 0x00, 0, 0xffff }, -+ { 0x0ae, 0xa4, 0, 0xffff }, -+ { 0x0af, 0xa4, 0, 0xffff }, -+ { 0x0b0, 0xa4, 0, 0xffff }, -+ { 0x0b1, 0xa4, 0, 0xffff }, -+ { 0x0b2, 0xa4, 0, 0xffff }, -+ { 0x0b3, 0xa4, 0, 0xffff }, -+ { 0x0b6, 0x00, 0, 0xffff }, -+ { 0x0b7, 0x00, 0, 0xffff }, -+ { 0x0d1, 0xff, 0, 0xffff }, -+ { 0x0d6, 0xff, 0, 0xffff }, -+ { 0x0db, 0xff, 0, 0xffff }, -+ { 0x0ea, 0x50, 0, 0xffff }, -+ { 0x0eb, 0x50, 0, 0xffff }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x184, 0xff, 0, 0xffff }, -+ { 0x186, 0xff, 0, 0xffff }, -+ { 0x1a1, 0xce, 0, 0xffff }, -+ { 0x1a2, 0x0c, 0, 0xffff }, -+ { 0x1a3, 0x0c, 0, 0xffff }, -+ { 0x1a6, 0x00, 0, 0xffff }, -+ { 0x1a7, 0x00, 0, 0xffff }, -+ { 0x1a8, 0xa4, 0, 0xffff }, -+ { 0x1a9, 0xa4, 0, 0xffff }, -+ { 0x1ab, 0x2d, 0, 0xffff }, -+ { 0x1ac, 0x2d, 0, 0xffff }, -+ { 0x1b1, 0x00, 0, 0xffff }, -+ { 0x1bb, 0x00, 0, 0xffff }, -+ { 0x1bc, 0x00, 0, 0xffff }, -+ { 0x1bd, 0x00, 0, 0xffff }, -+ { 0x1be, 0x01, 0, 0xffff }, -+ { 0x1bf, 0x01, 0, 0xffff }, -+ { 0x1c0, 0x01, 0, 0xffff }, -+ { 0x1c1, 0x01, 0, 0xffff }, -+ { 0x1c2, 0x01, 0, 0xffff }, -+ { 0x280, 0x00, 0, 0xffff }, -+ { 0x281, 0x00, 0, 0xffff }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x040, 0x01, 0, 0xffff }, -+}; -+ -+static const struct hwm_tab_entry HWM_TAB_MICRO_EARLY_STEPPING[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x01b, 0x0f, 0, 0xffff }, -+ { 0x057, 0xff, 0, 0xffff }, -+ { 0x059, 0xff, 0, 0xffff }, -+ { 0x05b, 0xff, 0, 0xffff }, -+ { 0x05d, 0xff, 0, 0xffff }, -+ { 0x05f, 0xff, 0, 0xffff }, -+ { 0x061, 0xff, 0, 0xffff }, -+ { 0x06e, 0x01, 0, 0xffff }, -+ { 0x06f, 0x03, 0, 0xffff }, -+ { 0x070, 0x03, 0, 0xffff }, -+ { 0x071, 0x02, 0, 0xffff }, -+ { 0x072, 0x02, 0, 0xffff }, -+ { 0x073, 0x01, 0, 0xffff }, -+ { 0x074, 0x06, 0, 0xffff }, -+ { 0x075, 0x07, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x80, 0, 0xffff }, -+ { 0x082, 0x80, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0xfd, 0, 0xffff }, -+ { 0x086, 0x60, 0, 0xffff }, -+ { 0x087, 0x50, 0, 0xffff }, -+ { 0x088, 0x08, 0, 0xffff }, -+ { 0x089, 0x00, 0, 0xffff }, -+ { 0x08a, 0x73, 0, 0xffff }, -+ { 0x08b, 0x73, 0, 0xffff }, -+ { 0x08c, 0x73, 0, 0xffff }, -+ { 0x090, 0x6d, 0, 0xffff }, -+ { 0x091, 0x7a, 0, 0xffff }, -+ { 0x092, 0x6b, 0, 0xffff }, -+ { 0x093, 0xa4, 0, 0xffff }, -+ { 0x094, 0x78, 0, 0xffff }, -+ { 0x095, 0xa4, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x099, 0xa4, 0, 0xffff }, -+ { 0x09a, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x2e, 0, 0xffff }, -+ { 0x0a1, 0x00, 0, 0xffff }, -+ { 0x0a2, 0x00, 0, 0xffff }, -+ { 0x0ae, 0xa4, 0, 0xffff }, -+ { 0x0af, 0xa4, 0, 0xffff }, -+ { 0x0b0, 0xa4, 0, 0xffff }, -+ { 0x0b1, 0xa4, 0, 0xffff }, -+ { 0x0b2, 0xa4, 0, 0xffff }, -+ { 0x0b3, 0xa4, 0, 0xffff }, -+ { 0x0b6, 0x00, 0, 0xffff }, -+ { 0x0b7, 0x00, 0, 0xffff }, -+ { 0x0d1, 0xff, 0, 0xffff }, -+ { 0x0d6, 0xff, 0, 0xffff }, -+ { 0x0db, 0xff, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0xffff }, -+ { 0x0eb, 0x64, 0, 0xffff }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x184, 0xff, 0, 0xffff }, -+ { 0x186, 0xff, 0, 0xffff }, -+ { 0x1a1, 0xce, 0, 0xffff }, -+ { 0x1a2, 0x0c, 0, 0xffff }, -+ { 0x1a3, 0x0c, 0, 0xffff }, -+ { 0x1a6, 0x00, 0, 0xffff }, -+ { 0x1a7, 0x00, 0, 0xffff }, -+ { 0x1a8, 0xa4, 0, 0xffff }, -+ { 0x1a9, 0xa4, 0, 0xffff }, -+ { 0x1ab, 0x2d, 0, 0xffff }, -+ { 0x1ac, 0x2d, 0, 0xffff }, -+ { 0x1b1, 0x00, 0, 0xffff }, -+ { 0x1bb, 0x00, 0, 0xffff }, -+ { 0x1bc, 0x00, 0, 0xffff }, -+ { 0x1bd, 0x00, 0, 0xffff }, -+ { 0x1be, 0x01, 0, 0xffff }, -+ { 0x1bf, 0x01, 0, 0xffff }, -+ { 0x1c0, 0x01, 0, 0xffff }, -+ { 0x1c1, 0x01, 0, 0xffff }, -+ { 0x1c2, 0x01, 0, 0xffff }, -+ { 0x280, 0x00, 0, 0xffff }, -+ { 0x281, 0x00, 0, 0xffff }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x040, 0x01, 0, 0xffff }, -+}; -+ -+static const struct hwm_tab_entry HWM_TAB_SFF[] = { -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x040, 0x01, 0, 0xffff }, -+ { 0x072, 0x03, 0, 0xffff }, -+ { 0x075, 0x06, 0, 0xffff }, -+ { 0x07c, 0x00, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x00, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0x59, 0, 0xffff }, -+ { 0x086, 0x6a, 0, 0xffff }, -+ { 0x087, 0xc0, 0, 0xffff }, -+ { 0x08a, 0x33, 0, 0xffff }, -+ { 0x090, 0x77, 0, 0xffff }, -+ { 0x091, 0x66, 0, 0xffff }, -+ { 0x092, 0x94, 0, 0xffff }, -+ { 0x093, 0x90, 0, 0xffff }, -+ { 0x094, 0x68, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x099, 0xa4, 0, 0xffff }, -+ { 0x09a, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x3e, 0, 0xffff }, -+ { 0x0ae, 0x86, 0, 0xffff }, -+ { 0x0af, 0x86, 0, 0xffff }, -+ { 0x0b0, 0xa4, 0, 0xffff }, -+ { 0x0b1, 0xa4, 0, 0xffff }, -+ { 0x0b2, 0x90, 0, 0xffff }, -+ { 0x0b6, 0x48, 0, 0xffff }, -+ { 0x0b7, 0x48, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x1b1, 0x48, 0, 0xffff }, -+ { 0x1b8, 0x00, 0, 0xffff }, -+ { 0x1be, 0x95, 0, 0xffff }, -+ { 0x1c1, 0x90, 0, 0xffff }, -+ { 0x1c6, 0x00, 0, 0xffff }, -+ { 0x1c9, 0x00, 0, 0xffff }, -+ { 0x280, 0x68, 0, 0xffff }, -+ { 0x281, 0x10, 0, 0xffff }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff} -+}; -+ -+static const struct hwm_tab_entry HWM_TAB_MT[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x00, 0, 0xffff }, -+ { 0x082, 0x80, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0xb9, 0, 0x0010 }, -+ { 0x086, 0xac, 0, 0x0010 }, -+ { 0x087, 0x87, 0, 0x0010 }, -+ { 0x08a, 0x51, 0, 0x0010 }, -+ { 0x08b, 0x39, 0, 0x0010 }, -+ { 0x090, 0x78, 0, 0xffff }, -+ { 0x091, 0x6a, 0, 0xffff }, -+ { 0x092, 0x8f, 0, 0xffff }, -+ { 0x094, 0x68, 0, 0xffff }, -+ { 0x095, 0x5b, 0, 0xffff }, -+ { 0x096, 0x92, 0, 0xffff }, -+ { 0x097, 0x86, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x09a, 0x8b, 0, 0xffff }, -+ { 0x0a0, 0x0a, 0, 0xffff }, -+ { 0x0a1, 0x26, 0, 0xffff }, -+ { 0x0a2, 0xd1, 0, 0xffff }, -+ { 0x0ae, 0x7c, 0, 0xffff }, -+ { 0x0af, 0x7c, 0, 0xffff }, -+ { 0x0b0, 0x9a, 0, 0xffff }, -+ { 0x0b3, 0x7c, 0, 0xffff }, -+ { 0x0b6, 0x08, 0, 0xffff }, -+ { 0x0b7, 0x00, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0xffff }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x0fd, 0x01, 0, 0xffff }, -+ { 0x1a1, 0x99, 0, 0xffff }, -+ { 0x1a2, 0x00, 0, 0xffff }, -+ { 0x1a4, 0x00, 0, 0xffff }, -+ { 0x1b1, 0x00, 0, 0xffff }, -+ { 0x1be, 0x90, 0, 0xffff }, -+ { 0x280, 0xc4, 0, 0xffff }, -+ { 0x281, 0x09, 0, 0xffff }, -+ { 0x282, 0x0a, 0, 0xffff }, -+ { 0x283, 0x14, 0, 0xffff }, -+ { 0x284, 0x01, 0, 0xffff }, -+ { 0x285, 0x01, 0, 0xffff }, -+ { 0x288, 0x94, 0, 0xffff }, -+ { 0x289, 0x11, 0, 0xffff }, -+ { 0x28a, 0x0a, 0, 0xffff }, -+ { 0x28b, 0x14, 0, 0xffff }, -+ { 0x28c, 0x01, 0, 0xffff }, -+ { 0x28d, 0x01, 0, 0xffff }, -+ { 0x294, 0x24, 0, 0xffff }, -+}; -+ -+static uint8_t get_temp_target(void) -+{ -+ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; -+ if (!val) -+ val = 20; -+ return 0x95 - val; -+} -+ -+static uint16_t get_pkg_power(void) -+{ -+ const unsigned int pkg_power = rdmsr(0x614).lo & 0x7fff; -+ const unsigned int power_unit = 1 << (rdmsr(0x606).lo & 0xf); -+ if (pkg_power / power_unit > 65) -+ return 32; -+ else -+ return 16; -+} -+ -+static uint8_t get_core_cnt(void) -+{ -+ // Intel describes this CPUID field as: -+ // > Maximum number of addressable IDs for processor cores in the physical package -+ if (cpuid(0).eax >= 4) -+ return cpuid_ext(4, 0).eax >> 26; -+ return 0; -+} -+ -+static void apply_hwm_tab(const struct hwm_tab_entry *arr, size_t size) -+{ -+ uint8_t temp_target = get_temp_target(); -+ uint16_t pkg_power = get_pkg_power(); -+ -+ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target); -+ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power); -+ -+ for (size_t i = 0; i < size; ++i) { -+ // Skip entry if it doesn't apply for this package power -+ if (arr[i].pkg_power != pkg_power && -+ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY) -+ continue; -+ -+ uint8_t val = arr[i].val; -+ -+ // Add temp target to value if requested (current tables never do) -+ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET) -+ val += temp_target; -+ -+ // Perform write -+ sch5555_mbox_write(1, arr[i].addr, val); -+ -+ } -+} -+ -+static void sch5555_ec_hwm_init(void *arg) -+{ -+ uint8_t form_fac_id, saved_2fc, core_cnt; -+ -+ printk(BIOS_DEBUG, "OptiPlex 3050 late HWM init\n"); -+ -+ form_fac_id = gpio_get(GPP_G2) | gpio_get(GPP_G3) << 1; -+ printk(BIOS_DEBUG, "Form Factor ID = %#x\n", form_fac_id); -+ -+ saved_2fc = sch5555_mbox_read(1, 0x2fc); -+ sch5555_mbox_write(1, 0x2fc, 0xa0); -+ sch5555_mbox_write(1, 0x2fd, 0x32); -+ -+ switch (form_fac_id) { -+ case FORM_FACTOR_MICRO: -+ // CPU stepping <= 3 -+ if ((cpuid(1).eax & 0xf) <= 3) -+ apply_hwm_tab(HWM_TAB_MICRO_EARLY_STEPPING, ARRAY_SIZE(HWM_TAB_MICRO_EARLY_STEPPING)); -+ // Tjunction == 80 -+ else if ((rdmsr(0x1a2).lo >> 16 & 0xff) == 80) -+ apply_hwm_tab(HWM_TAB_MICRO_TEMP80, ARRAY_SIZE(HWM_TAB_MICRO_TEMP80)); -+ else -+ apply_hwm_tab(HWM_TAB_MICRO_BASE, ARRAY_SIZE(HWM_TAB_MICRO_BASE)); -+ break; -+ case FORM_FACTOR_SFF: -+ apply_hwm_tab(HWM_TAB_SFF, ARRAY_SIZE(HWM_TAB_SFF)); -+ break; -+ default: -+ apply_hwm_tab(HWM_TAB_MT, ARRAY_SIZE(HWM_TAB_MT)); -+ break; -+ } -+ -+ core_cnt = get_core_cnt(); -+ printk(BIOS_DEBUG, "CPU Core Count = %#x\n", core_cnt); -+ if (get_core_cnt() > 2) { -+ sch5555_mbox_write(1, 0x9e, 0x30); -+ sch5555_mbox_write(1, 0xeb, sch5555_mbox_read(1, 0xea)); -+ } -+ -+ sch5555_mbox_write(1, 0x2fc, saved_2fc); -+ sch5555_mbox_read(1, 0xb8); -+} -+ -+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); -diff --git a/src/mainboard/dell/optiplex_3050/romstage.c b/src/mainboard/dell/optiplex_3050/romstage.c -new file mode 100644 -index 0000000000..a4734e5d61 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/romstage.c -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+void mainboard_memory_init_params(FSPM_UPD *mupd) -+{ -+ struct spd_block blk = { .addr_map = { 0x50, 0x52, } }; -+ get_spd_smbus(&blk); -+ dump_spd_info(&blk); -+ -+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; -+ mem_cfg->DqPinsInterleaved = true; -+ mem_cfg->CaVrefConfig = 2; -+ mem_cfg->MemorySpdDataLen = blk.len; -+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; -+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; -+ -+ /* use virtual channel 1 for the dmi interface of the PCH -+ * FIXME: do we need this? */ -+ mupd->FspmTestConfig.DmiVc1 = 1; -+} -diff --git a/src/mainboard/dell/optiplex_3050/sch5555_ec.c b/src/mainboard/dell/optiplex_3050/sch5555_ec.c -new file mode 100644 -index 0000000000..1df5026531 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/sch5555_ec.c -@@ -0,0 +1,54 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include "sch5555_ec.h" -+ -+uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2) -+{ -+ // clear ec-to-host mailbox -+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); -+ outb(tmp, SCH555x_EMI_IOBASE + 1); -+ -+ // send address -+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); -+ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); -+ -+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); -+ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); -+ -+ // send message to ec -+ outb(1, SCH555x_EMI_IOBASE); -+ -+ // wait for ack -+ for (size_t retry = 0; retry < 0xfff; ++retry) -+ if (inb(SCH555x_EMI_IOBASE + 1) & 1) -+ break; -+ -+ // read result -+ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); -+ return inb(SCH555x_EMI_IOBASE + 4); -+} -+ -+void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val) -+{ -+ // clear ec-to-host mailbox -+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); -+ outb(tmp, SCH555x_EMI_IOBASE + 1); -+ -+ // send address and value -+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); -+ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); -+ -+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); -+ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); -+ -+ // send message to ec -+ outb(1, SCH555x_EMI_IOBASE); -+ -+ // wait for ack -+ for (size_t retry = 0; retry < 0xfff; ++retry) -+ if (inb(SCH555x_EMI_IOBASE + 1) & 1) -+ break; -+} -diff --git a/src/mainboard/dell/optiplex_3050/sch5555_ec.h b/src/mainboard/dell/optiplex_3050/sch5555_ec.h -new file mode 100644 -index 0000000000..9d262d5787 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/sch5555_ec.h -@@ -0,0 +1,10 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __SCH5555_EC_H__ -+#define __SCH5555_EC_H__ -+ -+uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2); -+ -+void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val); -+ -+#endif --- -2.39.5 - diff --git a/config/coreboot/default/patches/0064-dell-optiplex_3050-add-hda_verb.c.patch b/config/coreboot/default/patches/0064-dell-optiplex_3050-add-hda_verb.c.patch deleted file mode 100644 index df9accf8..00000000 --- a/config/coreboot/default/patches/0064-dell-optiplex_3050-add-hda_verb.c.patch +++ /dev/null @@ -1,140 +0,0 @@ -From 782562bca3d9904e1e34f2cc6089876412b276cd Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sun, 6 Oct 2024 17:25:27 +0100 -Subject: [PATCH 64/65] dell/optiplex_3050: add hda_verb.c - -Configured for the line jack at the front of the machine. - -Based on dumps from the vendor BIOS. - -Signed-off-by: Leah Rowe ---- - src/mainboard/dell/optiplex_3050/Kconfig | 1 + - src/mainboard/dell/optiplex_3050/Makefile.mk | 3 +- - src/mainboard/dell/optiplex_3050/hda_verb.c | 90 ++++++++++++++++++++ - 3 files changed, 93 insertions(+), 1 deletion(-) - create mode 100644 src/mainboard/dell/optiplex_3050/hda_verb.c - -diff --git a/src/mainboard/dell/optiplex_3050/Kconfig b/src/mainboard/dell/optiplex_3050/Kconfig -index 2f0dccb98d..eab6034158 100644 ---- a/src/mainboard/dell/optiplex_3050/Kconfig -+++ b/src/mainboard/dell/optiplex_3050/Kconfig -@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS - select SKYLAKE_SOC_PCH_H - select SOC_INTEL_KABYLAKE - select SUPERIO_SMSC_SCH555x -+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB - - config CBFS_SIZE - default 0x900000 -diff --git a/src/mainboard/dell/optiplex_3050/Makefile.mk b/src/mainboard/dell/optiplex_3050/Makefile.mk -index d50ea40879..90b3cc4c48 100644 ---- a/src/mainboard/dell/optiplex_3050/Makefile.mk -+++ b/src/mainboard/dell/optiplex_3050/Makefile.mk -@@ -5,5 +5,6 @@ bootblock-y += sch5555_ec.c - - romstage-y += romstage.c - --ramstage-y += ramstage.c sch5555_ec.c -+ramstage-y += ramstage.c sch5555_ec.c hda_verb.c -+ - ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -diff --git a/src/mainboard/dell/optiplex_3050/hda_verb.c b/src/mainboard/dell/optiplex_3050/hda_verb.c -new file mode 100644 -index 0000000000..621e4f7a52 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/hda_verb.c -@@ -0,0 +1,90 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ /* coreboot specific header, codec 0 */ -+ 0x10ec0255, /* Realtek ALC3234 */ -+ 0x102807a3, /* Subsystem ID */ -+ 11, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ -+ AZALIA_SUBVENDOR(0, 0x102807a3), -+ -+ AZALIA_PIN_CFG(0, 0x12, 0x40000000), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( -+ AZALIA_INTEGRATED, -+ AZALIA_INTERNAL, -+ AZALIA_SPEAKER, -+ AZALIA_OTHER_ANALOG, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_NO_JACK_PRESENCE_DETECT, -+ 5, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, -+ AZALIA_LINE_OUT, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 2, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x1d, 0x4054c029), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, -+ AZALIA_HP_OUT, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 5, 15 -+ )), -+ -+ /* coreboot specific header, codec 2 */ -+ 0x80862809, /* Intel Skylake HDMI */ -+ 0x80860101, /* Subsystem ID */ -+ 4, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ -+ AZALIA_SUBVENDOR(2, 0x80860101), -+ -+ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+}; -+ -+const u32 pc_beep_verbs[] = {}; -+ -+AZALIA_ARRAY_SIZES; --- -2.39.5 - diff --git a/config/coreboot/default/patches/0065-dell-optiplex_3050-Add-data.vbt.patch b/config/coreboot/default/patches/0065-dell-optiplex_3050-Add-data.vbt.patch deleted file mode 100644 index 7c4fa56b..00000000 --- a/config/coreboot/default/patches/0065-dell-optiplex_3050-Add-data.vbt.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 60de0b27075ef9cc8339896e769e4231a43ceeea Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sun, 6 Oct 2024 23:48:05 +0100 -Subject: [PATCH 65/65] dell/optiplex_3050: Add data.vbt - -Signed-off-by: Leah Rowe ---- - src/mainboard/dell/optiplex_3050/Kconfig | 5 +++++ - src/mainboard/dell/optiplex_3050/data.vbt | Bin 0 -> 4300 bytes - 2 files changed, 5 insertions(+) - create mode 100644 src/mainboard/dell/optiplex_3050/data.vbt - -diff --git a/src/mainboard/dell/optiplex_3050/Kconfig b/src/mainboard/dell/optiplex_3050/Kconfig -index eab6034158..523a160ae3 100644 ---- a/src/mainboard/dell/optiplex_3050/Kconfig -+++ b/src/mainboard/dell/optiplex_3050/Kconfig -@@ -17,6 +17,8 @@ config BOARD_SPECIFIC_OPTIONS - select SOC_INTEL_KABYLAKE - select SUPERIO_SMSC_SCH555x - select SOC_INTEL_COMMON_BLOCK_HDA_VERB -+ select INTEL_GMA_HAVE_VBT -+ select INTEL_GMA_ADD_VBT - - config CBFS_SIZE - default 0x900000 -@@ -27,6 +29,9 @@ config MAINBOARD_DIR - config MAINBOARD_PART_NUMBER - default "OptiPlex 3050 Micro" - -+config INTEL_GMA_VBT_FILE -+ default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" -+ - config DIMM_SPD_SIZE - default 512 # DDR4 - -diff --git a/src/mainboard/dell/optiplex_3050/data.vbt b/src/mainboard/dell/optiplex_3050/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..6dc40cd99563bcd957ec2a9c4567e3b21e5d1d1f -GIT binary patch -literal 4300 -zcmeHJZ)_A*5TD(>zi)T1ds~!pU>yX`jfBW9Nd2eS$e@7qg=y|L+*|P~Ybk24rH<}xJ9eg%eaW32z1vbf_%+-P -zC$uXU01ASzM2Q>g;@$hkii6SZG3@E+#eVw*w9N;N1g6_?YiB3s;_)?@>DbVf-r9}P -zO`Vx|jP%robSBQ#gsrAYO>p&IQpqWSxVK|yXmkvV`v!Im77N$TZXru*X!y{`-Y55r -zVKf!Pgkc!X2_qgyK4nY|jSRP7a&Qp0+diYXy*OGNIan;Ts7z%5ry$@FKoGo8XMq5h -z6OcC{V?x>l17U>+7I|RUgn|iuCftWGW>(Kf196=odH`0=A3;(GULp|y6Ks_T0R#_x -zlLt);9A0GWnQsLE?*|8{0RgE`gv2JC<6bXwubJ}!0Qv+3{3xJE9q#3H25 -z>@mL~p#5nF3*pl}^hKCxt9(*`c-X6 -zFkpAE5jIOv7?VVJPHKbYp3@KrBCHN-@DOp9_>7mqcf{Wl|3v&7@nvGak3pDtDe*nT -zYl+trr--)_KT146>^lIL%Ay5+{&h=mW!RCRdEk{8SSMWj3D+L{)!qr(URTPlwf|yGUKG?B!CDGOpf7(oT__tC!2cJgEtK{*6}R$n1=r -z$PSguH+xU1hb?rHq(J+G2P}V^ryazPkEs%j0}In3b4gctpl8)ZC&3qS6o31yv0DC@ -zBN6*5So*Vg*3aOq|DtfT{{PvtW2P75FZ$;1Eo6%!)V*$4D5C>nt} -z7_D}&ricJyuY&X-!vUs`GWIOPx0wDOV;?d6f$4uRCdjx-*4N7{CF5RMe_CcQ%J`0~ -ze<-uhWc)?e%Q6cpxK`1V3hPmDzoNgOuwx3otLUF7>?;L-S9HJ1!Ybac>fI{aq2eJ` -ze@SJpsrbICf1$GTDqdFgx)56u!i^z48)A=#)F$0)i8F!~4)H=KFrv`ilM@v#FA5q- -zZ`~^T%U!!Etw*TnvRA91loJ<5n5;vH=aymAq8i4g#?~Vu@R%z0b-pk{VF{Q?SZOpI -zZFLYDT8~J)KBGPNg2zT^r<&>dt1z12coq!P7_N5^Xb$wE-B-rFk(v<3F&oiLZ61P9 -z^8O8kx7Uu(WFsrh-0{jBgc7g$6w^0d!yLLcn#Qi_glV3tAo!dLNa^?163N|n^-pD? -z(daC>dtpbi#Q&W%m0IHPOiO7pA89lVboYWH=_yh1N|ChuwX7oAZcPqP-%SWj_FFt3 -zyd_?zD3jia8uH=I*yP#l#Bw9^#^N~y33zEtk*o#5XfjXdCkjSG)~N^WoRlb;h;B3| -zIfCjSc(I06T!_GA1{WKOk*chsMCXx5vW@41o#fZgYViT9VSih*nQN}>g+zCejX>9! -zZ{c$hGa+w5eO}YT_FH@}B)U(Dl-|zF&dk8R;^4yrPZe)YrI^k%j}0~VZ%*1PT98&h -z556thD#%T3IZc)NKi{(4RJn@8Dq3?JywFKA?WW585y(IR)(Ee|k5bDtz|lFnDY}0G -Ds8qe3 - -literal 0 -HcmV?d00001 - --- -2.39.5 - diff --git a/config/coreboot/dell3050micro_fsp_16mb/config/libgfxinit_corebootfb b/config/coreboot/dell3050micro_fsp_16mb/config/libgfxinit_corebootfb index a6d11f3f..1a04eaf7 100644 --- a/config/coreboot/dell3050micro_fsp_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell3050micro_fsp_16mb/config/libgfxinit_corebootfb @@ -10,9 +10,9 @@ CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set -CONFIG_ARCH_SUPPORTS_CLANG=y # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set +# CONFIG_LTO is not set # CONFIG_IWYU is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set @@ -57,6 +57,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_AOOSTAR is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARM is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set @@ -68,6 +69,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_CWWK is not set CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ERYING is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set @@ -75,12 +77,14 @@ CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HARDKERNEL is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set # CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set # CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LATTEPANDA is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set # CONFIG_VENDOR_MSI is not set @@ -124,14 +128,18 @@ CONFIG_MAX_CPUS=8 CONFIG_POST_DEVICE=y CONFIG_POST_IO=y CONFIG_UART_FOR_CONSOLE=0 +CONFIG_OVERRIDE_DEVICETREE="" CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set -CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_PCIEXP_CLK_PM=y CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=256 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +# CONFIG_FATAL_ASSERTS is not set CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" # CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 @@ -141,9 +149,8 @@ CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_USE_PM_ACPI_TIMER=y -# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set -# CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set CONFIG_BOARD_DELL_OPTIPLEX_3050=y # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set @@ -161,15 +168,14 @@ CONFIG_BOARD_DELL_OPTIPLEX_3050=y # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set # CONFIG_BOARD_DELL_PRECISION_T1650 is not set # CONFIG_BOARD_DELL_XPS_8300 is not set -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=256 -CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfef00000 CONFIG_DCACHE_RAM_SIZE=0x40000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro" +# CONFIG_USE_LEGACY_8254_TIMER is not set CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 CONFIG_DRIVERS_INTEL_WIFI=y CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd" @@ -179,9 +185,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y -# CONFIG_USE_LEGACY_8254_TIMER is not set # CONFIG_DEBUG_SMI is not set -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro" # CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set CONFIG_HAVE_IFD_BIN=y CONFIG_PS2K_EISAID="PNP0303" @@ -260,10 +264,13 @@ CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30 CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35 CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/" CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" +CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_FSP_PUBLISH_MBP_HOB=y +CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003 CONFIG_MAX_HECI_DEVICES=5 CONFIG_BOOTBLOCK_IN_CBFS=y CONFIG_HAVE_PAM0_REGISTER=y @@ -372,6 +379,8 @@ CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y CONFIG_SA_ENABLE_DPR=y +CONFIG_HAVE_CAPID_A_REGISTER=y +CONFIG_HAVE_BDSM_BGSM_REGISTER=y CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y @@ -498,6 +507,9 @@ CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y # CONFIG_DUMP_SMBIOS_TYPE17 is not set CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 +CONFIG_DEFAULT_EBDA_LOWMEM=0x100000 +CONFIG_DEFAULT_EBDA_SEGMENT=0xF600 +CONFIG_DEFAULT_EBDA_SIZE=0x400 # end of Chipset # @@ -520,6 +532,11 @@ CONFIG_NO_EARLY_GFX_INIT=y CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y CONFIG_LINEAR_FRAMEBUFFER=y # CONFIG_BOOTSPLASH is not set +CONFIG_DEFAULT_SCREEN_ROTATION_NONE=y +# CONFIG_DEFAULT_SCREEN_ROTATION_90 is not set +# CONFIG_DEFAULT_SCREEN_ROTATION_180 is not set +# CONFIG_DEFAULT_SCREEN_ROTATION_270 is not set +CONFIG_DEFAULT_SCREEN_ROTATION_INT=0 # end of Display CONFIG_PCI=y @@ -548,6 +565,7 @@ CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y # CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 # CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set +# CONFIG_DRIVERS_EFI_FW_INFO is not set # CONFIG_ELOG is not set CONFIG_CACHE_MRC_SETTINGS=y CONFIG_MRC_SETTINGS_PROTECT=y @@ -582,13 +600,12 @@ CONFIG_FSP_T_RESERVED_SIZE=0x0 CONFIG_FSP_M_XIP=y CONFIG_HAVE_FSP_LOGO_SUPPORT=y CONFIG_FSP_COMPRESS_FSP_S_LZ4=y -CONFIG_FSP_STATUS_GLOBAL_RESET_REQUIRED_3=y -CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003 CONFIG_SOC_INTEL_COMMON_FSP_RESET=y CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y # CONFIG_DISPLAY_FSP_TIMESTAMPS is not set +# CONFIG_BUILDING_WITH_DEBUG_FSP is not set CONFIG_INTEL_GMA_ACPI=y CONFIG_VBT_CBFS_COMPRESSION_LZMA=y # CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set @@ -763,7 +780,6 @@ CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y # General Debug Settings # # CONFIG_GDB_STUB is not set -# CONFIG_FATAL_ASSERTS is not set CONFIG_HAVE_DEBUG_GPIO=y # CONFIG_DEBUG_GPIO is not set # CONFIG_DEBUG_CBFS is not set diff --git a/config/coreboot/dell3050micro_fsp_16mb/config/libgfxinit_txtmode b/config/coreboot/dell3050micro_fsp_16mb/config/libgfxinit_txtmode index 7e1bc8d6..529cdd56 100644 --- a/config/coreboot/dell3050micro_fsp_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell3050micro_fsp_16mb/config/libgfxinit_txtmode @@ -10,9 +10,9 @@ CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set -CONFIG_ARCH_SUPPORTS_CLANG=y # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set +# CONFIG_LTO is not set # CONFIG_IWYU is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set @@ -57,6 +57,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_AOOSTAR is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARM is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set @@ -68,6 +69,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_CWWK is not set CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ERYING is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set @@ -75,12 +77,14 @@ CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HARDKERNEL is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set # CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set # CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LATTEPANDA is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set # CONFIG_VENDOR_MSI is not set @@ -122,14 +126,18 @@ CONFIG_MAX_CPUS=8 CONFIG_POST_DEVICE=y CONFIG_POST_IO=y CONFIG_UART_FOR_CONSOLE=0 +CONFIG_OVERRIDE_DEVICETREE="" CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set -CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_PCIEXP_CLK_PM=y CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=256 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +# CONFIG_FATAL_ASSERTS is not set CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" # CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 @@ -139,9 +147,8 @@ CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_USE_PM_ACPI_TIMER=y -# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set -# CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set CONFIG_BOARD_DELL_OPTIPLEX_3050=y # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set @@ -159,15 +166,14 @@ CONFIG_BOARD_DELL_OPTIPLEX_3050=y # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set # CONFIG_BOARD_DELL_PRECISION_T1650 is not set # CONFIG_BOARD_DELL_XPS_8300 is not set -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=256 -CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfef00000 CONFIG_DCACHE_RAM_SIZE=0x40000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro" +# CONFIG_USE_LEGACY_8254_TIMER is not set CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 CONFIG_DRIVERS_INTEL_WIFI=y CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd" @@ -177,9 +183,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y -# CONFIG_USE_LEGACY_8254_TIMER is not set # CONFIG_DEBUG_SMI is not set -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro" # CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set CONFIG_HAVE_IFD_BIN=y CONFIG_PS2K_EISAID="PNP0303" @@ -258,10 +262,13 @@ CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30 CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35 CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/" CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" +CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_FSP_PUBLISH_MBP_HOB=y +CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003 CONFIG_MAX_HECI_DEVICES=5 CONFIG_BOOTBLOCK_IN_CBFS=y CONFIG_HAVE_PAM0_REGISTER=y @@ -370,6 +377,8 @@ CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y CONFIG_SA_ENABLE_DPR=y +CONFIG_HAVE_CAPID_A_REGISTER=y +CONFIG_HAVE_BDSM_BGSM_REGISTER=y CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y @@ -496,6 +505,9 @@ CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y # CONFIG_DUMP_SMBIOS_TYPE17 is not set CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 +CONFIG_DEFAULT_EBDA_LOWMEM=0x100000 +CONFIG_DEFAULT_EBDA_SEGMENT=0xF600 +CONFIG_DEFAULT_EBDA_SIZE=0x400 # end of Chipset # @@ -516,6 +528,7 @@ CONFIG_NO_EARLY_GFX_INIT=y # CONFIG_VGA_TEXT_FRAMEBUFFER=y # CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +CONFIG_DEFAULT_SCREEN_ROTATION_INT=0 # end of Display CONFIG_PCI=y @@ -544,6 +557,7 @@ CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y # CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 # CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set +# CONFIG_DRIVERS_EFI_FW_INFO is not set # CONFIG_ELOG is not set CONFIG_CACHE_MRC_SETTINGS=y CONFIG_MRC_SETTINGS_PROTECT=y @@ -578,13 +592,12 @@ CONFIG_FSP_T_RESERVED_SIZE=0x0 CONFIG_FSP_M_XIP=y CONFIG_HAVE_FSP_LOGO_SUPPORT=y CONFIG_FSP_COMPRESS_FSP_S_LZ4=y -CONFIG_FSP_STATUS_GLOBAL_RESET_REQUIRED_3=y -CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003 CONFIG_SOC_INTEL_COMMON_FSP_RESET=y CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y # CONFIG_DISPLAY_FSP_TIMESTAMPS is not set +# CONFIG_BUILDING_WITH_DEBUG_FSP is not set CONFIG_INTEL_GMA_ACPI=y CONFIG_VBT_CBFS_COMPRESSION_LZMA=y # CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set @@ -760,7 +773,6 @@ CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y # General Debug Settings # # CONFIG_GDB_STUB is not set -# CONFIG_FATAL_ASSERTS is not set CONFIG_HAVE_DEBUG_GPIO=y # CONFIG_DEBUG_GPIO is not set # CONFIG_DEBUG_CBFS is not set diff --git a/config/coreboot/dell3050micro_fsp_16mb/target.cfg b/config/coreboot/dell3050micro_fsp_16mb/target.cfg index 12448aa7..b45300e9 100644 --- a/config/coreboot/dell3050micro_fsp_16mb/target.cfg +++ b/config/coreboot/dell3050micro_fsp_16mb/target.cfg @@ -1,4 +1,4 @@ -tree="default" +tree="dell7" xarch="i386-elf" payload_seabios="y" payload_grub="y" @@ -9,4 +9,4 @@ vcfg="3050micro" build_depend="seabios/default grub/xhci memtest86plus" IFD_platform="sklkbl" grubname="fallback/payload" # make GRUB the primary payload on this board -seabiosname="seabios.elf" # this actually disables the seabios payload +seabiosname="seabios.elf" diff --git a/config/coreboot/dell7/patches/0001-WIP-OptiPlex-3050-Micro-port.patch b/config/coreboot/dell7/patches/0001-WIP-OptiPlex-3050-Micro-port.patch new file mode 100644 index 00000000..e8a6bcc0 --- /dev/null +++ b/config/coreboot/dell7/patches/0001-WIP-OptiPlex-3050-Micro-port.patch @@ -0,0 +1,1421 @@ +From 2d266c50e2062dc202209494e9c1532ce8debd29 Mon Sep 17 00:00:00 2001 +From: Mate Kukri +Date: Thu, 24 Oct 2024 18:05:19 +0100 +Subject: [PATCH 1/4] [WIP] OptiPlex 3050 Micro port + +- Boots Linux +- SMSC SCH5553 SIO/EC + + Serial port works + + PWM fan control works +- Realtek Gigabit LAN works +- WiFi slot works +- NVMe SSD slot works +- Extra: LPSS UART0 + + Stock FW sets undocumented power gating bit, RTC battery needs to + be pulled for it to work. + + Signals exposed on test points on the back of the board. + FIXME: add documentation about this +- Needs 'deguard' to bypass BootGuard + + See https://review.coreboot.org/plugins/gitiles/deguard +- TODO: HDA verbs +- TODO: USB ports +- TODO: Add VBT +- Currently limited to the Micro form factor, but others are very + similar + +Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 +Signed-off-by: Mate Kukri +--- + src/mainboard/dell/optiplex_3050/Kconfig | 32 ++ + src/mainboard/dell/optiplex_3050/Kconfig.name | 4 + + src/mainboard/dell/optiplex_3050/Makefile.mk | 9 + + src/mainboard/dell/optiplex_3050/acpi/ec.asl | 3 + + .../dell/optiplex_3050/acpi/superio.asl | 3 + + .../dell/optiplex_3050/board_info.txt | 7 + + src/mainboard/dell/optiplex_3050/bootblock.c | 107 ++++ + src/mainboard/dell/optiplex_3050/cmos.default | 5 + + src/mainboard/dell/optiplex_3050/cmos.layout | 54 ++ + .../dell/optiplex_3050/devicetree.cb | 119 ++++ + src/mainboard/dell/optiplex_3050/dsdt.asl | 27 + + .../dell/optiplex_3050/gma-mainboard.ads | 19 + + .../dell/optiplex_3050/include/early_gpio.h | 11 + + .../dell/optiplex_3050/include/gpio.h | 241 ++++++++ + src/mainboard/dell/optiplex_3050/ramstage.c | 513 ++++++++++++++++++ + src/mainboard/dell/optiplex_3050/romstage.c | 26 + + src/mainboard/dell/optiplex_3050/sch5555_ec.c | 54 ++ + src/mainboard/dell/optiplex_3050/sch5555_ec.h | 10 + + 18 files changed, 1244 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_3050/Kconfig + create mode 100644 src/mainboard/dell/optiplex_3050/Kconfig.name + create mode 100644 src/mainboard/dell/optiplex_3050/Makefile.mk + create mode 100644 src/mainboard/dell/optiplex_3050/acpi/ec.asl + create mode 100644 src/mainboard/dell/optiplex_3050/acpi/superio.asl + create mode 100644 src/mainboard/dell/optiplex_3050/board_info.txt + create mode 100644 src/mainboard/dell/optiplex_3050/bootblock.c + create mode 100644 src/mainboard/dell/optiplex_3050/cmos.default + create mode 100644 src/mainboard/dell/optiplex_3050/cmos.layout + create mode 100644 src/mainboard/dell/optiplex_3050/devicetree.cb + create mode 100644 src/mainboard/dell/optiplex_3050/dsdt.asl + create mode 100644 src/mainboard/dell/optiplex_3050/gma-mainboard.ads + create mode 100644 src/mainboard/dell/optiplex_3050/include/early_gpio.h + create mode 100644 src/mainboard/dell/optiplex_3050/include/gpio.h + create mode 100644 src/mainboard/dell/optiplex_3050/ramstage.c + create mode 100644 src/mainboard/dell/optiplex_3050/romstage.c + create mode 100644 src/mainboard/dell/optiplex_3050/sch5555_ec.c + create mode 100644 src/mainboard/dell/optiplex_3050/sch5555_ec.h + +diff --git a/src/mainboard/dell/optiplex_3050/Kconfig b/src/mainboard/dell/optiplex_3050/Kconfig +new file mode 100644 +index 0000000000..2f0dccb98d +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/Kconfig +@@ -0,0 +1,32 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++if BOARD_DELL_OPTIPLEX_3050 ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ select BOARD_ROMSIZE_KB_16384 ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ # select INTEL_GMA_HAVE_VBT ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_SUPPORTS_KABYLAKE_CPU ++ select MAINBOARD_SUPPORTS_SKYLAKE_CPU ++ select SKYLAKE_SOC_PCH_H ++ select SOC_INTEL_KABYLAKE ++ select SUPERIO_SMSC_SCH555x ++ ++config CBFS_SIZE ++ default 0x900000 ++ ++config MAINBOARD_DIR ++ default "dell/optiplex_3050" ++ ++config MAINBOARD_PART_NUMBER ++ default "OptiPlex 3050 Micro" ++ ++config DIMM_SPD_SIZE ++ default 512 # DDR4 ++ ++endif +diff --git a/src/mainboard/dell/optiplex_3050/Kconfig.name b/src/mainboard/dell/optiplex_3050/Kconfig.name +new file mode 100644 +index 0000000000..14eab7f52c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/Kconfig.name +@@ -0,0 +1,4 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_DELL_OPTIPLEX_3050 ++ bool "OptiPlex 3050 Micro" +diff --git a/src/mainboard/dell/optiplex_3050/Makefile.mk b/src/mainboard/dell/optiplex_3050/Makefile.mk +new file mode 100644 +index 0000000000..d50ea40879 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/Makefile.mk +@@ -0,0 +1,9 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++bootblock-y += bootblock.c ++bootblock-y += sch5555_ec.c ++ ++romstage-y += romstage.c ++ ++ramstage-y += ramstage.c sch5555_ec.c ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +diff --git a/src/mainboard/dell/optiplex_3050/acpi/ec.asl b/src/mainboard/dell/optiplex_3050/acpi/ec.asl +new file mode 100644 +index 0000000000..16990d45f4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/acpi/ec.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: CC-PDDC */ ++ ++/* Please update the license if adding licensable material. */ +diff --git a/src/mainboard/dell/optiplex_3050/acpi/superio.asl b/src/mainboard/dell/optiplex_3050/acpi/superio.asl +new file mode 100644 +index 0000000000..16990d45f4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/acpi/superio.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: CC-PDDC */ ++ ++/* Please update the license if adding licensable material. */ +diff --git a/src/mainboard/dell/optiplex_3050/board_info.txt b/src/mainboard/dell/optiplex_3050/board_info.txt +new file mode 100644 +index 0000000000..47a4a3a4f3 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/board_info.txt +@@ -0,0 +1,7 @@ ++Category: desktop ++Board URL: https://www.dell.com/support/kbdoc/en-uk/000124265/dell-optiplex-3050-system-guide ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y ++Release year: 2017 +diff --git a/src/mainboard/dell/optiplex_3050/bootblock.c b/src/mainboard/dell/optiplex_3050/bootblock.c +new file mode 100644 +index 0000000000..10689c42a1 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/bootblock.c +@@ -0,0 +1,107 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include "include/early_gpio.h" ++#include "sch5555_ec.h" ++ ++struct ec_init_entry { ++ uint16_t addr; ++ uint8_t val; ++}; ++ ++static void bootblock_ec_init(void) ++{ ++ /* ++ * Early EC init ++ */ ++ ++ static const struct ec_init_entry init_table1[] = { ++ {0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10}, ++ {0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10}, ++ {0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12}, ++ {0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12}, ++ {0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10}, ++ {0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11}, ++ }; ++ ++ for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i) ++ sch5555_mbox_write(2, init_table1[i].addr, init_table1[i].val); ++ ++ static const struct ec_init_entry init_table2[] = { ++ {0x0040, 0x00}, {0x00f8, 0x10}, {0x00f9, 0x00}, {0x00f0, 0x30}, ++ {0x00fa, 0x00}, {0x00fb, 0x00}, {0x00ea, 0x00}, {0x00eb, 0x00}, ++ {0x00ef, 0x7c}, {0x0005, 0x0f}, {0x0014, 0x01}, {0x0018, 0x2f}, ++ {0x0019, 0x2f}, {0x001a, 0x2f}, {0x001b, 0x2f}, {0x01d8, 0x01}, ++ {0x0040, 0x11}, ++ }; ++ ++ for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i) ++ sch5555_mbox_write(1, init_table2[i].addr, init_table2[i].val); ++ ++ sch5555_mbox_write(1, 0x000b, 0x01); ++ sch5555_mbox_write(4, 0x001a, 0x04); ++ sch5555_mbox_write(4, 0x0028, 0x18); ++ sch5555_mbox_write(4, 0x001a, 0x00); ++ sch5555_mbox_write(1, 0x000b, 0x03); ++ ++ /* ++ * Early HWM init ++ */ ++ ++ sch5555_mbox_read(1, 0xcb); ++ sch5555_mbox_read(1, 0xb8); ++ ++ static const struct ec_init_entry hwm_init_table[] = { ++ {0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f}, ++ {0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33}, ++ {0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff}, ++ {0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00}, ++ {0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00}, ++ {0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80}, ++ {0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02}, ++ {0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04}, ++ {0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50}, ++ {0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50}, ++ {0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c}, ++ {0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd}, ++ {0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e}, ++ {0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00}, ++ {0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff}, ++ {0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00}, ++ {0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c}, ++ {0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02}, ++ {0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03}, {0x0015, 0x33}, ++ {0x018b, 0x00}, {0x018c, 0x00}, {0x02f8, 0x5e}, {0x02f9, 0x01}, ++ }; ++ ++ for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i) ++ sch5555_mbox_write(1, hwm_init_table[i].addr, hwm_init_table[i].val); ++} ++ ++ ++#define SCH555x_IOBASE 0x2e ++#define GLOBAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL) ++#define SERIAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1) ++ ++void bootblock_mainboard_early_init(void) ++{ ++ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); ++ ++ // Super I/O early init will map Runtime and EMI registers ++ sch555x_early_init(GLOBAL_DEV); ++ ++ // Changes LED color among a few other things ++ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS); ++ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN); ++ outb(0xf, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); ++ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); ++ ++ // Perform bootblock EC initialization ++ bootblock_ec_init(); ++ ++ // Bootblock EC initialization is required for UART1 to work ++ sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ++} +diff --git a/src/mainboard/dell/optiplex_3050/cmos.default b/src/mainboard/dell/optiplex_3050/cmos.default +new file mode 100644 +index 0000000000..79961f43d8 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/cmos.default +@@ -0,0 +1,5 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Disable +diff --git a/src/mainboard/dell/optiplex_3050/cmos.layout b/src/mainboard/dell/optiplex_3050/cmos.layout +new file mode 100644 +index 0000000000..54a5147b7d +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/cmos.layout +@@ -0,0 +1,54 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++#start-bit length config config-ID name ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++ ++# coreboot config options: southbridge ++409 2 e 7 power_on_after_fail ++ ++# coreboot config options: bootloader ++#Used by ChromeOS: ++416 128 r 0 vbnv ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 415 984 +diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb +new file mode 100644 +index 0000000000..eb731fe48f +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/devicetree.cb +@@ -0,0 +1,119 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++chip soc/intel/skylake ++ register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN" ++ ++ # Enable Enhanced Intel SpeedStep ++ register "eist_enable" = "1" ++ ++ device cpu_cluster 0 on end ++ ++ device domain 0 on ++ device ref igpu on ++ register "PrimaryDisplay" = "Display_iGFX" ++ end ++ ++ device ref south_xhci on ++ register "usb2_ports" = "{ ++ [0] = USB2_PORT_MID(OC0), ++ [1] = USB2_PORT_MID(OC0), ++ [2] = USB2_PORT_MID(OC4), ++ [3] = USB2_PORT_MID(OC4), ++ [4] = USB2_PORT_MID(OC2), ++ [5] = USB2_PORT_MID(OC2), ++ [6] = USB2_PORT_MID(OC0), ++ [7] = USB2_PORT_MID(OC0), ++ [8] = USB2_PORT_MID(OC0), ++ [9] = USB2_PORT_MID(OC0), ++ [10] = USB2_PORT_MID(OC1), ++ [11] = USB2_PORT_MID(OC1), ++ [12] = USB2_PORT_MID(OC_SKIP), ++ [13] = USB2_PORT_MID(OC_SKIP), ++ }" ++ register "usb3_ports" = "{ ++ [0] = USB3_PORT_DEFAULT(OC0), ++ [1] = USB3_PORT_DEFAULT(OC0), ++ [2] = USB3_PORT_DEFAULT(OC3), ++ [3] = USB3_PORT_DEFAULT(OC3), ++ [4] = USB3_PORT_DEFAULT(OC1), ++ [5] = USB3_PORT_DEFAULT(OC1), ++ [6] = USB3_PORT_DEFAULT(OC_SKIP), ++ [7] = USB3_PORT_DEFAULT(OC_SKIP), ++ [8] = USB3_PORT_DEFAULT(OC_SKIP), ++ [9] = USB3_PORT_DEFAULT(OC_SKIP), ++ }" ++ end ++ ++ # ME interface is 'off' to avoid HECI reset delay due to HAP ++ device ref heci1 off end ++ ++ device ref sata on ++ register "SataSalpSupport" = "1" ++ register "SataPortsEnable[0]" = "1" ++ end ++ ++ device ref pcie_rp21 on ++ register "PcieRpEnable[20]" = "1" ++ register "PcieRpClkReqSupport[20]" = "1" ++ register "PcieRpClkReqNumber[20]" = "3" ++ register "PcieRpAdvancedErrorReporting[20]" = "1" ++ register "PcieRpLtrEnable[20]" = "1" ++ register "PcieRpClkSrcNumber[20]" = "3" ++ register "PcieRpHotPlug[20]" = "1" ++ end ++ ++ # Realtek LAN ++ device ref pcie_rp5 on ++ register "PcieRpEnable[4]" = "1" ++ register "PcieRpClkReqSupport[4]" = "0" ++ register "PcieRpHotPlug[4]" = "0" ++ end ++ ++ # M.2 WiFi ++ device ref pcie_rp8 on ++ register "PcieRpEnable[7]" = "1" ++ register "PcieRpClkReqSupport[7]" = "0" ++ register "PcieRpHotPlug[7]" = "1" ++ end ++ ++ # UART0 is exposed on test points on the bottom of the board ++ device ref uart0 on ++ register "SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci" ++ end ++ ++ device ref lpc_espi on ++ register "serirq_mode" = "SERIRQ_CONTINUOUS" ++ ++ # I/O decode for EMI/Runtime registers ++ register "gen1_dec" = "0x007c0a01" ++ ++ # SCH5553 ++ chip superio/smsc/sch555x ++ device pnp 2e.0 on # EMI ++ io 0x60 = 0xa00 ++ end ++ device pnp 2e.1 off end # 8042 ++ device pnp 2e.7 on # UART1 ++ io 0x60 = 0x3f8 ++ irq 0x0f = 2 ++ irq 0x70 = 4 ++ end ++ device pnp 2e.8 off end # UART2 ++ device pnp 2e.c on # LPC interface ++ io 0x60 = 0x2e ++ end ++ device pnp 2e.a on # Runtime registers ++ io 0x60 = 0xa40 ++ end ++ device pnp 2e.b off end # Floppy Controller ++ device pnp 2e.11 off end # Parallel Port ++ end ++ end ++ ++ device ref hda on ++ register "PchHdaVcType" = "Vc1" ++ end ++ ++ device ref smbus on end ++ end ++end +diff --git a/src/mainboard/dell/optiplex_3050/dsdt.asl b/src/mainboard/dell/optiplex_3050/dsdt.asl +new file mode 100644 +index 0000000000..9762f6ff74 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/dsdt.asl +@@ -0,0 +1,27 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20110725 ++) ++{ ++ #include ++ #include ++ #include ++ ++ Scope (\_SB) ++ { ++ Device (PCI0) ++ { ++ #include ++ #include ++ } ++ } ++ ++ #include ++} +diff --git a/src/mainboard/dell/optiplex_3050/gma-mainboard.ads b/src/mainboard/dell/optiplex_3050/gma-mainboard.ads +new file mode 100644 +index 0000000000..cb4c22f285 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/gma-mainboard.ads +@@ -0,0 +1,19 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (HDMI1, -- External HDMI ++ DP2, -- External DP (native) ++ HDMI2, -- External DP (DP++) ++ DP3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) ++ HDMI3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/optiplex_3050/include/early_gpio.h b/src/mainboard/dell/optiplex_3050/include/early_gpio.h +new file mode 100644 +index 0000000000..17a16371e3 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/include/early_gpio.h +@@ -0,0 +1,11 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __OPTIPLEX_3050_EARLY_GPIO_H__ ++#define __OPTIPLEX_3050_EARLY_GPIO_H__ ++ ++static const struct pad_config early_gpio_table[] = { ++ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ ++ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ ++}; ++ ++#endif +diff --git a/src/mainboard/dell/optiplex_3050/include/gpio.h b/src/mainboard/dell/optiplex_3050/include/gpio.h +new file mode 100644 +index 0000000000..83293c32a9 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/include/gpio.h +@@ -0,0 +1,241 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __OPTIPLEX_3050_GPIO_H__ ++#define __OPTIPLEX_3050_GPIO_H__ ++ ++static const struct pad_config gpio_table[] = { ++ ++ /* ------- GPIO Community 0 ------- */ ++ ++ /* ------- GPIO Group GPP_A ------- */ ++ PAD_CFG_NF(GPP_A0, UP_20K, PLTRST, NF1), /* RCIN# */ ++ PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* LAD0 */ ++ PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* LAD1 */ ++ PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* LAD2 */ ++ PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* LAD3 */ ++ PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */ ++ PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKRUN# */ ++ PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), /* CLKOUT_LPC0 */ ++ PAD_CFG_NF(GPP_A10, NONE, PLTRST, NF1), /* CLKOUT_LPC1 */ ++ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), /* PME# */ ++ PAD_CFG_GPO(GPP_A12, 0, PLTRST), /* GPIO */ ++ PAD_CFG_NF(GPP_A13, NONE, PLTRST, NF1), /* SUSWARN#/SUSPWRDNACK */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_A15, UP_20K, PLTRST, NF1), /* SUS_ACK# */ ++ PAD_CFG_GPO(GPP_A16, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_B ------- */ ++ PAD_CFG_GPO(GPP_B0, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B1, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B2, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_B3, 1, RSMRST), /* GPIO (ME_CNTL, B3 -> LOW => HDA_SDO -> HIGH) */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_B5, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B6, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B7, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_B9, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1), /* SLP_S0# */ ++ PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), /* PLTRST# */ ++ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* SPKR */ ++ PAD_CFG_GPO(GPP_B15, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B16, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* GSPIO_MOSI */ ++ PAD_CFG_GPO(GPP_B19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B20, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* GPIO */ ++ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), /* GSPI1_MOSI */ ++ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), /* PCHHOT# */ ++ ++ /* ------- GPIO Community 1 ------- */ ++ ++ /* ------- GPIO Group GPP_C ------- */ ++ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ ++ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_C2, DN_20K, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_C3, NONE, PLTRST, NF1), /* SML0CLK */ ++ PAD_CFG_NF(GPP_C4, NONE, PLTRST, NF1), /* SML0DATA */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK */ ++ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1DATA */ ++ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ ++ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ ++ PAD_CFG_GPO(GPP_C10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C11, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C12, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C13, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C14, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C15, 0, PLTRST), /* GPIO */ ++ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), /* I2C0_SDA */ ++ PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), /* I2C0_SCL */ ++ PAD_CFG_GPO(GPP_C18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C21, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_D ------- */ ++ PAD_CFG_GPO(GPP_D0, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D1, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D2, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D3, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_D6, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_D7, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D8, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D9, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D11, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D13, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D14, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D15, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D16, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D21, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_E ------- */ ++ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATAXPCIE0 */ ++ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SATAXPCIE1 */ ++ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* SATAXPCIE2 */ ++ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* SATA_LED# */ ++ PAD_CFG_NF(GPP_E9, UP_20K, PLTRST, NF1), /* USB_OC0# */ ++ PAD_CFG_NF(GPP_E10, UP_20K, PLTRST, NF1), /* USB_OC1# */ ++ PAD_CFG_NF(GPP_E11, UP_20K, PLTRST, NF1), /* USB_OC2# */ ++ PAD_CFG_NF(GPP_E12, UP_20K, PLTRST, NF1), /* USB_OC3# */ ++ ++ /* ------- GPIO Group GPP_F ------- */ ++ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* SATAXPCIE3 */ ++ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* SATAXPCIE4 */ ++ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* SATAXPCIE5 */ ++ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* SATAXPCIE6 */ ++ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* SATAXPCIE7 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_F6, NONE, RSMRST, NF1), /* SATA_DEVSLP4 */ ++ PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_F9, 0, RSMRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_F13, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), /* USB_OC4# */ ++ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), /* USB_OC5# */ ++ PAD_CFG_NF(GPP_F17, UP_20K, PLTRST, NF1), /* USB_OC6# */ ++ PAD_CFG_TERM_GPO(GPP_F18, 0, UP_20K, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_F19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_F20, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_F21, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_F22, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_F23, 1, RSMRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_G ------- */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_G9, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_G12, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_G14, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G15, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G16, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G17, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_G19, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G20, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_G21, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G22, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_H ------- */ ++ PAD_CFG_GPO(GPP_H0, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H2, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H3, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H4, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H5, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H6, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_H7, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H8, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H9, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H11, 0, PLTRST), /* GPIO */ ++ PAD_CFG_TERM_GPO(GPP_H12, 1, DN_20K, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H15, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H16, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H21, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Community 2 ------- */ ++ ++ /* -------- GPIO Group GPD -------- */ ++ PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* BATLOW# */ ++ PAD_CFG_GPO(GPD1, 0, PWROK), /* GPIO */ ++ PAD_CFG_NF(GPD2, NONE, RSMRST, NF1), /* LAN_WAKE# */ ++ PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), /* PWRBTN# */ ++ PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */ ++ PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */ ++ PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* SLP_A# */ ++ PAD_CFG_GPO(GPD7, 1, RSMRST), /* GPIO */ ++ PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* SUSCLK */ ++ PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */ ++ PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */ ++ PAD_CFG_GPO(GPD11, 1, RSMRST), /* GPIO */ ++ ++ /* ------- GPIO Community 3 ------- */ ++ ++ /* ------- GPIO Group GPP_I ------- */ ++ PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */ ++ PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPC_HPD1 */ ++ PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DDPD_HPD2 */ ++ PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* DDPE_HPD3 */ ++ PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), /* EDP_HPD */ ++ PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* DDPB_CTRLCLK */ ++ PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), /* DDPB_CTRLDATA */ ++ PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* DDPC_CTRLCLK */ ++ PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), /* DDPC_CTRLDATA */ ++ PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */ ++ PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), /* DDPD_CTRLDATA */ ++}; ++ ++#endif +diff --git a/src/mainboard/dell/optiplex_3050/ramstage.c b/src/mainboard/dell/optiplex_3050/ramstage.c +new file mode 100644 +index 0000000000..5cf2c81e50 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/ramstage.c +@@ -0,0 +1,513 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "include/gpio.h" ++#include "sch5555_ec.h" ++ ++void mainboard_silicon_init_params(FSP_SIL_UPD *params) ++{ ++ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); ++} ++ ++#define FORM_FACTOR_MICRO 0 ++#define FORM_FACTOR_SFF 1 ++// NOTE: one of these is MT, but 2 and 3 both get the same table anyways ++#define FORM_FACTOR_UNK2 2 ++#define FORM_FACTOR_UNK3 3 ++ ++#define HWM_TAB_ADD_TEMP_TARGET 1 ++#define HWM_TAB_PKG_POWER_ANY 0xffff ++ ++struct hwm_tab_entry { ++ uint16_t addr; ++ uint8_t val; ++ uint8_t flags; ++ uint16_t pkg_power; ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MICRO_BASE[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x01b, 0x0f, 0, 0xffff }, ++ { 0x057, 0xff, 0, 0xffff }, ++ { 0x059, 0xff, 0, 0xffff }, ++ { 0x05b, 0xff, 0, 0xffff }, ++ { 0x05d, 0xff, 0, 0xffff }, ++ { 0x05f, 0xff, 0, 0xffff }, ++ { 0x061, 0xff, 0, 0xffff }, ++ { 0x06e, 0x00, 0, 0xffff }, ++ { 0x06f, 0x03, 0, 0xffff }, ++ { 0x070, 0x03, 0, 0xffff }, ++ { 0x071, 0x02, 0, 0xffff }, ++ { 0x072, 0x02, 0, 0xffff }, ++ { 0x073, 0x01, 0, 0xffff }, ++ { 0x074, 0x06, 0, 0xffff }, ++ { 0x075, 0x07, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x80, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xf1, 0, 0xffff }, ++ { 0x086, 0x88, 0, 0xffff }, ++ { 0x087, 0x61, 0, 0xffff }, ++ { 0x088, 0x08, 0, 0xffff }, ++ { 0x089, 0x00, 0, 0xffff }, ++ { 0x08a, 0x73, 0, 0xffff }, ++ { 0x08b, 0x73, 0, 0xffff }, ++ { 0x08c, 0x73, 0, 0xffff }, ++ { 0x090, 0x6d, 0, 0xffff }, ++ { 0x091, 0x7e, 0, 0xffff }, ++ { 0x092, 0x66, 0, 0xffff }, ++ { 0x093, 0xa4, 0, 0xffff }, ++ { 0x094, 0x7c, 0, 0xffff }, ++ { 0x095, 0xa4, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x2e, 0, 0xffff }, ++ { 0x0a1, 0x00, 0, 0xffff }, ++ { 0x0a2, 0x00, 0, 0xffff }, ++ { 0x0ae, 0xa4, 0, 0xffff }, ++ { 0x0af, 0xa4, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0xa4, 0, 0xffff }, ++ { 0x0b3, 0xa4, 0, 0xffff }, ++ { 0x0b6, 0x00, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0d1, 0xff, 0, 0xffff }, ++ { 0x0d6, 0xff, 0, 0xffff }, ++ { 0x0db, 0xff, 0, 0xffff }, ++ { 0x0ea, 0x5c, 0, 0xffff }, ++ { 0x0eb, 0x5c, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x184, 0xff, 0, 0xffff }, ++ { 0x186, 0xff, 0, 0xffff }, ++ { 0x1a1, 0xce, 0, 0xffff }, ++ { 0x1a2, 0x0c, 0, 0xffff }, ++ { 0x1a3, 0x0c, 0, 0xffff }, ++ { 0x1a6, 0x00, 0, 0xffff }, ++ { 0x1a7, 0x00, 0, 0xffff }, ++ { 0x1a8, 0xa4, 0, 0xffff }, ++ { 0x1a9, 0xa4, 0, 0xffff }, ++ { 0x1ab, 0x2d, 0, 0xffff }, ++ { 0x1ac, 0x2d, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1bb, 0x00, 0, 0xffff }, ++ { 0x1bc, 0x00, 0, 0xffff }, ++ { 0x1bd, 0x00, 0, 0xffff }, ++ { 0x1be, 0x01, 0, 0xffff }, ++ { 0x1bf, 0x01, 0, 0xffff }, ++ { 0x1c0, 0x01, 0, 0xffff }, ++ { 0x1c1, 0x01, 0, 0xffff }, ++ { 0x1c2, 0x01, 0, 0xffff }, ++ { 0x280, 0x00, 0, 0xffff }, ++ { 0x281, 0x00, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MICRO_TEMP80[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x01b, 0x0f, 0, 0xffff }, ++ { 0x057, 0xff, 0, 0xffff }, ++ { 0x059, 0xff, 0, 0xffff }, ++ { 0x05b, 0xff, 0, 0xffff }, ++ { 0x05d, 0xff, 0, 0xffff }, ++ { 0x05f, 0xff, 0, 0xffff }, ++ { 0x061, 0xff, 0, 0xffff }, ++ { 0x06e, 0x00, 0, 0xffff }, ++ { 0x06f, 0x03, 0, 0xffff }, ++ { 0x070, 0x03, 0, 0xffff }, ++ { 0x071, 0x02, 0, 0xffff }, ++ { 0x072, 0x02, 0, 0xffff }, ++ { 0x073, 0x01, 0, 0xffff }, ++ { 0x074, 0x06, 0, 0xffff }, ++ { 0x075, 0x07, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x80, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xf6, 0, 0xffff }, ++ { 0x086, 0x88, 0, 0xffff }, ++ { 0x087, 0x61, 0, 0xffff }, ++ { 0x088, 0x08, 0, 0xffff }, ++ { 0x089, 0x00, 0, 0xffff }, ++ { 0x08a, 0x73, 0, 0xffff }, ++ { 0x08b, 0x73, 0, 0xffff }, ++ { 0x08c, 0x73, 0, 0xffff }, ++ { 0x090, 0x6d, 0, 0xffff }, ++ { 0x091, 0x86, 0, 0xffff }, ++ { 0x092, 0x66, 0, 0xffff }, ++ { 0x093, 0xa4, 0, 0xffff }, ++ { 0x094, 0x7c, 0, 0xffff }, ++ { 0x095, 0xa4, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x2e, 0, 0xffff }, ++ { 0x0a1, 0x00, 0, 0xffff }, ++ { 0x0a2, 0x00, 0, 0xffff }, ++ { 0x0ae, 0xa4, 0, 0xffff }, ++ { 0x0af, 0xa4, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0xa4, 0, 0xffff }, ++ { 0x0b3, 0xa4, 0, 0xffff }, ++ { 0x0b6, 0x00, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0d1, 0xff, 0, 0xffff }, ++ { 0x0d6, 0xff, 0, 0xffff }, ++ { 0x0db, 0xff, 0, 0xffff }, ++ { 0x0ea, 0x50, 0, 0xffff }, ++ { 0x0eb, 0x50, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x184, 0xff, 0, 0xffff }, ++ { 0x186, 0xff, 0, 0xffff }, ++ { 0x1a1, 0xce, 0, 0xffff }, ++ { 0x1a2, 0x0c, 0, 0xffff }, ++ { 0x1a3, 0x0c, 0, 0xffff }, ++ { 0x1a6, 0x00, 0, 0xffff }, ++ { 0x1a7, 0x00, 0, 0xffff }, ++ { 0x1a8, 0xa4, 0, 0xffff }, ++ { 0x1a9, 0xa4, 0, 0xffff }, ++ { 0x1ab, 0x2d, 0, 0xffff }, ++ { 0x1ac, 0x2d, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1bb, 0x00, 0, 0xffff }, ++ { 0x1bc, 0x00, 0, 0xffff }, ++ { 0x1bd, 0x00, 0, 0xffff }, ++ { 0x1be, 0x01, 0, 0xffff }, ++ { 0x1bf, 0x01, 0, 0xffff }, ++ { 0x1c0, 0x01, 0, 0xffff }, ++ { 0x1c1, 0x01, 0, 0xffff }, ++ { 0x1c2, 0x01, 0, 0xffff }, ++ { 0x280, 0x00, 0, 0xffff }, ++ { 0x281, 0x00, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MICRO_EARLY_STEPPING[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x01b, 0x0f, 0, 0xffff }, ++ { 0x057, 0xff, 0, 0xffff }, ++ { 0x059, 0xff, 0, 0xffff }, ++ { 0x05b, 0xff, 0, 0xffff }, ++ { 0x05d, 0xff, 0, 0xffff }, ++ { 0x05f, 0xff, 0, 0xffff }, ++ { 0x061, 0xff, 0, 0xffff }, ++ { 0x06e, 0x01, 0, 0xffff }, ++ { 0x06f, 0x03, 0, 0xffff }, ++ { 0x070, 0x03, 0, 0xffff }, ++ { 0x071, 0x02, 0, 0xffff }, ++ { 0x072, 0x02, 0, 0xffff }, ++ { 0x073, 0x01, 0, 0xffff }, ++ { 0x074, 0x06, 0, 0xffff }, ++ { 0x075, 0x07, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x80, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xfd, 0, 0xffff }, ++ { 0x086, 0x60, 0, 0xffff }, ++ { 0x087, 0x50, 0, 0xffff }, ++ { 0x088, 0x08, 0, 0xffff }, ++ { 0x089, 0x00, 0, 0xffff }, ++ { 0x08a, 0x73, 0, 0xffff }, ++ { 0x08b, 0x73, 0, 0xffff }, ++ { 0x08c, 0x73, 0, 0xffff }, ++ { 0x090, 0x6d, 0, 0xffff }, ++ { 0x091, 0x7a, 0, 0xffff }, ++ { 0x092, 0x6b, 0, 0xffff }, ++ { 0x093, 0xa4, 0, 0xffff }, ++ { 0x094, 0x78, 0, 0xffff }, ++ { 0x095, 0xa4, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x2e, 0, 0xffff }, ++ { 0x0a1, 0x00, 0, 0xffff }, ++ { 0x0a2, 0x00, 0, 0xffff }, ++ { 0x0ae, 0xa4, 0, 0xffff }, ++ { 0x0af, 0xa4, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0xa4, 0, 0xffff }, ++ { 0x0b3, 0xa4, 0, 0xffff }, ++ { 0x0b6, 0x00, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0d1, 0xff, 0, 0xffff }, ++ { 0x0d6, 0xff, 0, 0xffff }, ++ { 0x0db, 0xff, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0xffff }, ++ { 0x0eb, 0x64, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x184, 0xff, 0, 0xffff }, ++ { 0x186, 0xff, 0, 0xffff }, ++ { 0x1a1, 0xce, 0, 0xffff }, ++ { 0x1a2, 0x0c, 0, 0xffff }, ++ { 0x1a3, 0x0c, 0, 0xffff }, ++ { 0x1a6, 0x00, 0, 0xffff }, ++ { 0x1a7, 0x00, 0, 0xffff }, ++ { 0x1a8, 0xa4, 0, 0xffff }, ++ { 0x1a9, 0xa4, 0, 0xffff }, ++ { 0x1ab, 0x2d, 0, 0xffff }, ++ { 0x1ac, 0x2d, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1bb, 0x00, 0, 0xffff }, ++ { 0x1bc, 0x00, 0, 0xffff }, ++ { 0x1bd, 0x00, 0, 0xffff }, ++ { 0x1be, 0x01, 0, 0xffff }, ++ { 0x1bf, 0x01, 0, 0xffff }, ++ { 0x1c0, 0x01, 0, 0xffff }, ++ { 0x1c1, 0x01, 0, 0xffff }, ++ { 0x1c2, 0x01, 0, 0xffff }, ++ { 0x280, 0x00, 0, 0xffff }, ++ { 0x281, 0x00, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_SFF[] = { ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++ { 0x072, 0x03, 0, 0xffff }, ++ { 0x075, 0x06, 0, 0xffff }, ++ { 0x07c, 0x00, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x59, 0, 0xffff }, ++ { 0x086, 0x6a, 0, 0xffff }, ++ { 0x087, 0xc0, 0, 0xffff }, ++ { 0x08a, 0x33, 0, 0xffff }, ++ { 0x090, 0x77, 0, 0xffff }, ++ { 0x091, 0x66, 0, 0xffff }, ++ { 0x092, 0x94, 0, 0xffff }, ++ { 0x093, 0x90, 0, 0xffff }, ++ { 0x094, 0x68, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x3e, 0, 0xffff }, ++ { 0x0ae, 0x86, 0, 0xffff }, ++ { 0x0af, 0x86, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0x90, 0, 0xffff }, ++ { 0x0b6, 0x48, 0, 0xffff }, ++ { 0x0b7, 0x48, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x1b1, 0x48, 0, 0xffff }, ++ { 0x1b8, 0x00, 0, 0xffff }, ++ { 0x1be, 0x95, 0, 0xffff }, ++ { 0x1c1, 0x90, 0, 0xffff }, ++ { 0x1c6, 0x00, 0, 0xffff }, ++ { 0x1c9, 0x00, 0, 0xffff }, ++ { 0x280, 0x68, 0, 0xffff }, ++ { 0x281, 0x10, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff} ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MT[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xb9, 0, 0x0010 }, ++ { 0x086, 0xac, 0, 0x0010 }, ++ { 0x087, 0x87, 0, 0x0010 }, ++ { 0x08a, 0x51, 0, 0x0010 }, ++ { 0x08b, 0x39, 0, 0x0010 }, ++ { 0x090, 0x78, 0, 0xffff }, ++ { 0x091, 0x6a, 0, 0xffff }, ++ { 0x092, 0x8f, 0, 0xffff }, ++ { 0x094, 0x68, 0, 0xffff }, ++ { 0x095, 0x5b, 0, 0xffff }, ++ { 0x096, 0x92, 0, 0xffff }, ++ { 0x097, 0x86, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x09a, 0x8b, 0, 0xffff }, ++ { 0x0a0, 0x0a, 0, 0xffff }, ++ { 0x0a1, 0x26, 0, 0xffff }, ++ { 0x0a2, 0xd1, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x7c, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x99, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1a4, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1be, 0x90, 0, 0xffff }, ++ { 0x280, 0xc4, 0, 0xffff }, ++ { 0x281, 0x09, 0, 0xffff }, ++ { 0x282, 0x0a, 0, 0xffff }, ++ { 0x283, 0x14, 0, 0xffff }, ++ { 0x284, 0x01, 0, 0xffff }, ++ { 0x285, 0x01, 0, 0xffff }, ++ { 0x288, 0x94, 0, 0xffff }, ++ { 0x289, 0x11, 0, 0xffff }, ++ { 0x28a, 0x0a, 0, 0xffff }, ++ { 0x28b, 0x14, 0, 0xffff }, ++ { 0x28c, 0x01, 0, 0xffff }, ++ { 0x28d, 0x01, 0, 0xffff }, ++ { 0x294, 0x24, 0, 0xffff }, ++}; ++ ++static uint8_t get_temp_target(void) ++{ ++ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; ++ if (!val) ++ val = 20; ++ return 0x95 - val; ++} ++ ++static uint16_t get_pkg_power(void) ++{ ++ const unsigned int pkg_power = rdmsr(0x614).lo & 0x7fff; ++ const unsigned int power_unit = 1 << (rdmsr(0x606).lo & 0xf); ++ if (pkg_power / power_unit > 65) ++ return 32; ++ else ++ return 16; ++} ++ ++static uint8_t get_core_cnt(void) ++{ ++ // Intel describes this CPUID field as: ++ // > Maximum number of addressable IDs for processor cores in the physical package ++ if (cpuid(0).eax >= 4) ++ return cpuid_ext(4, 0).eax >> 26; ++ return 0; ++} ++ ++static void apply_hwm_tab(const struct hwm_tab_entry *arr, size_t size) ++{ ++ uint8_t temp_target = get_temp_target(); ++ uint16_t pkg_power = get_pkg_power(); ++ ++ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target); ++ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power); ++ ++ for (size_t i = 0; i < size; ++i) { ++ // Skip entry if it doesn't apply for this package power ++ if (arr[i].pkg_power != pkg_power && ++ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY) ++ continue; ++ ++ uint8_t val = arr[i].val; ++ ++ // Add temp target to value if requested (current tables never do) ++ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET) ++ val += temp_target; ++ ++ // Perform write ++ sch5555_mbox_write(1, arr[i].addr, val); ++ ++ } ++} ++ ++static void sch5555_ec_hwm_init(void *arg) ++{ ++ uint8_t form_fac_id, saved_2fc, core_cnt; ++ ++ printk(BIOS_DEBUG, "OptiPlex 3050 late HWM init\n"); ++ ++ form_fac_id = gpio_get(GPP_G2) | gpio_get(GPP_G3) << 1; ++ printk(BIOS_DEBUG, "Form Factor ID = %#x\n", form_fac_id); ++ ++ saved_2fc = sch5555_mbox_read(1, 0x2fc); ++ sch5555_mbox_write(1, 0x2fc, 0xa0); ++ sch5555_mbox_write(1, 0x2fd, 0x32); ++ ++ switch (form_fac_id) { ++ case FORM_FACTOR_MICRO: ++ // CPU stepping <= 3 ++ if ((cpuid(1).eax & 0xf) <= 3) ++ apply_hwm_tab(HWM_TAB_MICRO_EARLY_STEPPING, ARRAY_SIZE(HWM_TAB_MICRO_EARLY_STEPPING)); ++ // Tjunction == 80 ++ else if ((rdmsr(0x1a2).lo >> 16 & 0xff) == 80) ++ apply_hwm_tab(HWM_TAB_MICRO_TEMP80, ARRAY_SIZE(HWM_TAB_MICRO_TEMP80)); ++ else ++ apply_hwm_tab(HWM_TAB_MICRO_BASE, ARRAY_SIZE(HWM_TAB_MICRO_BASE)); ++ break; ++ case FORM_FACTOR_SFF: ++ apply_hwm_tab(HWM_TAB_SFF, ARRAY_SIZE(HWM_TAB_SFF)); ++ break; ++ default: ++ apply_hwm_tab(HWM_TAB_MT, ARRAY_SIZE(HWM_TAB_MT)); ++ break; ++ } ++ ++ core_cnt = get_core_cnt(); ++ printk(BIOS_DEBUG, "CPU Core Count = %#x\n", core_cnt); ++ if (get_core_cnt() > 2) { ++ sch5555_mbox_write(1, 0x9e, 0x30); ++ sch5555_mbox_write(1, 0xeb, sch5555_mbox_read(1, 0xea)); ++ } ++ ++ sch5555_mbox_write(1, 0x2fc, saved_2fc); ++ sch5555_mbox_read(1, 0xb8); ++} ++ ++BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); +diff --git a/src/mainboard/dell/optiplex_3050/romstage.c b/src/mainboard/dell/optiplex_3050/romstage.c +new file mode 100644 +index 0000000000..a4734e5d61 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/romstage.c +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++void mainboard_memory_init_params(FSPM_UPD *mupd) ++{ ++ struct spd_block blk = { .addr_map = { 0x50, 0x52, } }; ++ get_spd_smbus(&blk); ++ dump_spd_info(&blk); ++ ++ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; ++ mem_cfg->DqPinsInterleaved = true; ++ mem_cfg->CaVrefConfig = 2; ++ mem_cfg->MemorySpdDataLen = blk.len; ++ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; ++ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; ++ ++ /* use virtual channel 1 for the dmi interface of the PCH ++ * FIXME: do we need this? */ ++ mupd->FspmTestConfig.DmiVc1 = 1; ++} +diff --git a/src/mainboard/dell/optiplex_3050/sch5555_ec.c b/src/mainboard/dell/optiplex_3050/sch5555_ec.c +new file mode 100644 +index 0000000000..1df5026531 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/sch5555_ec.c +@@ -0,0 +1,54 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include "sch5555_ec.h" ++ ++uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t retry = 0; retry < 0xfff; ++retry) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++ ++ // read result ++ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); ++ return inb(SCH555x_EMI_IOBASE + 4); ++} ++ ++void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address and value ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t retry = 0; retry < 0xfff; ++retry) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++} +diff --git a/src/mainboard/dell/optiplex_3050/sch5555_ec.h b/src/mainboard/dell/optiplex_3050/sch5555_ec.h +new file mode 100644 +index 0000000000..9d262d5787 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/sch5555_ec.h +@@ -0,0 +1,10 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __SCH5555_EC_H__ ++#define __SCH5555_EC_H__ ++ ++uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2); ++ ++void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val); ++ ++#endif +-- +2.39.5 + diff --git a/config/coreboot/dell7/patches/0002-dell-optiplex_3050-add-hda_verb.c.patch b/config/coreboot/dell7/patches/0002-dell-optiplex_3050-add-hda_verb.c.patch new file mode 100644 index 00000000..376a8761 --- /dev/null +++ b/config/coreboot/dell7/patches/0002-dell-optiplex_3050-add-hda_verb.c.patch @@ -0,0 +1,140 @@ +From 6140f780837726a24d6c473ac50a62fdd5ee8f2d Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sun, 6 Oct 2024 17:25:27 +0100 +Subject: [PATCH 2/4] dell/optiplex_3050: add hda_verb.c + +Configured for the line jack at the front of the machine. + +Based on dumps from the vendor BIOS. + +Signed-off-by: Leah Rowe +--- + src/mainboard/dell/optiplex_3050/Kconfig | 1 + + src/mainboard/dell/optiplex_3050/Makefile.mk | 3 +- + src/mainboard/dell/optiplex_3050/hda_verb.c | 90 ++++++++++++++++++++ + 3 files changed, 93 insertions(+), 1 deletion(-) + create mode 100644 src/mainboard/dell/optiplex_3050/hda_verb.c + +diff --git a/src/mainboard/dell/optiplex_3050/Kconfig b/src/mainboard/dell/optiplex_3050/Kconfig +index 2f0dccb98d..eab6034158 100644 +--- a/src/mainboard/dell/optiplex_3050/Kconfig ++++ b/src/mainboard/dell/optiplex_3050/Kconfig +@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS + select SKYLAKE_SOC_PCH_H + select SOC_INTEL_KABYLAKE + select SUPERIO_SMSC_SCH555x ++ select SOC_INTEL_COMMON_BLOCK_HDA_VERB + + config CBFS_SIZE + default 0x900000 +diff --git a/src/mainboard/dell/optiplex_3050/Makefile.mk b/src/mainboard/dell/optiplex_3050/Makefile.mk +index d50ea40879..90b3cc4c48 100644 +--- a/src/mainboard/dell/optiplex_3050/Makefile.mk ++++ b/src/mainboard/dell/optiplex_3050/Makefile.mk +@@ -5,5 +5,6 @@ bootblock-y += sch5555_ec.c + + romstage-y += romstage.c + +-ramstage-y += ramstage.c sch5555_ec.c ++ramstage-y += ramstage.c sch5555_ec.c hda_verb.c ++ + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +diff --git a/src/mainboard/dell/optiplex_3050/hda_verb.c b/src/mainboard/dell/optiplex_3050/hda_verb.c +new file mode 100644 +index 0000000000..621e4f7a52 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3050/hda_verb.c +@@ -0,0 +1,90 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header, codec 0 */ ++ 0x10ec0255, /* Realtek ALC3234 */ ++ 0x102807a3, /* Subsystem ID */ ++ 11, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ ++ AZALIA_SUBVENDOR(0, 0x102807a3), ++ ++ AZALIA_PIN_CFG(0, 0x12, 0x40000000), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 5, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, ++ AZALIA_LINE_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x1d, 0x4054c029), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, ++ AZALIA_HP_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 5, 15 ++ )), ++ ++ /* coreboot specific header, codec 2 */ ++ 0x80862809, /* Intel Skylake HDMI */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ ++ AZALIA_SUBVENDOR(2, 0x80860101), ++ ++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++}; ++ ++const u32 pc_beep_verbs[] = {}; ++ ++AZALIA_ARRAY_SIZES; +-- +2.39.5 + diff --git a/config/coreboot/dell7/patches/0003-dell-optiplex_3050-Add-data.vbt.patch b/config/coreboot/dell7/patches/0003-dell-optiplex_3050-Add-data.vbt.patch new file mode 100644 index 00000000..5ec93c6f --- /dev/null +++ b/config/coreboot/dell7/patches/0003-dell-optiplex_3050-Add-data.vbt.patch @@ -0,0 +1,74 @@ +From e8c7028be21084ef2f89140cccb393ca7a0ff327 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sun, 6 Oct 2024 23:48:05 +0100 +Subject: [PATCH 3/4] dell/optiplex_3050: Add data.vbt + +Signed-off-by: Leah Rowe +--- + src/mainboard/dell/optiplex_3050/Kconfig | 5 +++++ + src/mainboard/dell/optiplex_3050/data.vbt | Bin 0 -> 4300 bytes + 2 files changed, 5 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_3050/data.vbt + +diff --git a/src/mainboard/dell/optiplex_3050/Kconfig b/src/mainboard/dell/optiplex_3050/Kconfig +index eab6034158..523a160ae3 100644 +--- a/src/mainboard/dell/optiplex_3050/Kconfig ++++ b/src/mainboard/dell/optiplex_3050/Kconfig +@@ -17,6 +17,8 @@ config BOARD_SPECIFIC_OPTIONS + select SOC_INTEL_KABYLAKE + select SUPERIO_SMSC_SCH555x + select SOC_INTEL_COMMON_BLOCK_HDA_VERB ++ select INTEL_GMA_HAVE_VBT ++ select INTEL_GMA_ADD_VBT + + config CBFS_SIZE + default 0x900000 +@@ -27,6 +29,9 @@ config MAINBOARD_DIR + config MAINBOARD_PART_NUMBER + default "OptiPlex 3050 Micro" + ++config INTEL_GMA_VBT_FILE ++ default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" ++ + config DIMM_SPD_SIZE + default 512 # DDR4 + +diff --git a/src/mainboard/dell/optiplex_3050/data.vbt b/src/mainboard/dell/optiplex_3050/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..6dc40cd99563bcd957ec2a9c4567e3b21e5d1d1f +GIT binary patch +literal 4300 +zcmeHJZ)_A*5TD(>zi)T1ds~!pU>yX`jfBW9Nd2eS$e@7qg=y|L+*|P~Ybk24rH<}xJ9eg%eaW32z1vbf_%+-P +zC$uXU01ASzM2Q>g;@$hkii6SZG3@E+#eVw*w9N;N1g6_?YiB3s;_)?@>DbVf-r9}P +zO`Vx|jP%robSBQ#gsrAYO>p&IQpqWSxVK|yXmkvV`v!Im77N$TZXru*X!y{`-Y55r +zVKf!Pgkc!X2_qgyK4nY|jSRP7a&Qp0+diYXy*OGNIan;Ts7z%5ry$@FKoGo8XMq5h +z6OcC{V?x>l17U>+7I|RUgn|iuCftWGW>(Kf196=odH`0=A3;(GULp|y6Ks_T0R#_x +zlLt);9A0GWnQsLE?*|8{0RgE`gv2JC<6bXwubJ}!0Qv+3{3xJE9q#3H25 +z>@mL~p#5nF3*pl}^hKCxt9(*`c-X6 +zFkpAE5jIOv7?VVJPHKbYp3@KrBCHN-@DOp9_>7mqcf{Wl|3v&7@nvGak3pDtDe*nT +zYl+trr--)_KT146>^lIL%Ay5+{&h=mW!RCRdEk{8SSMWj3D+L{)!qr(URTPlwf|yGUKG?B!CDGOpf7(oT__tC!2cJgEtK{*6}R$n1=r +z$PSguH+xU1hb?rHq(J+G2P}V^ryazPkEs%j0}In3b4gctpl8)ZC&3qS6o31yv0DC@ +zBN6*5So*Vg*3aOq|DtfT{{PvtW2P75FZ$;1Eo6%!)V*$4D5C>nt} +z7_D}&ricJyuY&X-!vUs`GWIOPx0wDOV;?d6f$4uRCdjx-*4N7{CF5RMe_CcQ%J`0~ +ze<-uhWc)?e%Q6cpxK`1V3hPmDzoNgOuwx3otLUF7>?;L-S9HJ1!Ybac>fI{aq2eJ` +ze@SJpsrbICf1$GTDqdFgx)56u!i^z48)A=#)F$0)i8F!~4)H=KFrv`ilM@v#FA5q- +zZ`~^T%U!!Etw*TnvRA91loJ<5n5;vH=aymAq8i4g#?~Vu@R%z0b-pk{VF{Q?SZOpI +zZFLYDT8~J)KBGPNg2zT^r<&>dt1z12coq!P7_N5^Xb$wE-B-rFk(v<3F&oiLZ61P9 +z^8O8kx7Uu(WFsrh-0{jBgc7g$6w^0d!yLLcn#Qi_glV3tAo!dLNa^?163N|n^-pD? +z(daC>dtpbi#Q&W%m0IHPOiO7pA89lVboYWH=_yh1N|ChuwX7oAZcPqP-%SWj_FFt3 +zyd_?zD3jia8uH=I*yP#l#Bw9^#^N~y33zEtk*o#5XfjXdCkjSG)~N^WoRlb;h;B3| +zIfCjSc(I06T!_GA1{WKOk*chsMCXx5vW@41o#fZgYViT9VSih*nQN}>g+zCejX>9! +zZ{c$hGa+w5eO}YT_FH@}B)U(Dl-|zF&dk8R;^4yrPZe)YrI^k%j}0~VZ%*1PT98&h +z556thD#%T3IZc)NKi{(4RJn@8Dq3?JywFKA?WW585y(IR)(Ee|k5bDtz|lFnDY}0G +Ds8qe3 + +literal 0 +HcmV?d00001 + +-- +2.39.5 + diff --git a/config/coreboot/dell7/patches/0004-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/dell7/patches/0004-Remove-warning-for-coreboot-images-built-without-a-p.patch new file mode 100644 index 00000000..ece00c26 --- /dev/null +++ b/config/coreboot/dell7/patches/0004-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -0,0 +1,39 @@ +From d7f20d6adf94e6c4736c55e88fcd1c8bde88994a Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Fri, 12 May 2023 19:55:15 -0600 +Subject: [PATCH 4/4] Remove warning for coreboot images built without a + payload + +I added this in upstream to prevent people from accidentally flashing +roms without a payload resulting in a no boot situation, but in +libreboot lbmk handles the payload and thus this warning always comes +up. This has caused confusion and concern so just patch it out. +--- + payloads/Makefile.mk | 13 +------------ + 1 file changed, 1 insertion(+), 12 deletions(-) + +diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk +index 5f988dac1b..516133880f 100644 +--- a/payloads/Makefile.mk ++++ b/payloads/Makefile.mk +@@ -50,16 +50,5 @@ distclean-payloads: + print-repo-info-payloads: + -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) + +-ifeq ($(CONFIG_PAYLOAD_NONE),y) +-show_notices:: warn_no_payload +-endif +- +-warn_no_payload: +- printf "\n\t** WARNING **\n" +- printf "coreboot has been built without a payload. Writing\n" +- printf "a coreboot image without a payload to your board's\n" +- printf "flash chip will result in a non-booting system. You\n" +- printf "can use cbfstool to add a payload to the image.\n\n" +- + .PHONY: force-payload coreinfo nvramcui +-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload ++.PHONY: clean-payloads distclean-payloads print-repo-info-payloads +-- +2.39.5 + diff --git a/config/coreboot/dell7/target.cfg b/config/coreboot/dell7/target.cfg new file mode 100644 index 00000000..366f8eff --- /dev/null +++ b/config/coreboot/dell7/target.cfg @@ -0,0 +1,2 @@ +tree="dell7" +rev="e81fdd74a930b0bf8105816ea115ceaeb99bae1d" diff --git a/config/coreboot/dell7010sff_12mb/config/libgfxinit_txtmode b/config/coreboot/dell7010sff_12mb/config/libgfxinit_txtmode index 3e4ee022..05151e1f 100644 --- a/config/coreboot/dell7010sff_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell7010sff_12mb/config/libgfxinit_txtmode @@ -143,7 +143,6 @@ CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_corebootfb index 7db6d89e..8d8c5c20 100644 --- a/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_corebootfb @@ -144,7 +144,6 @@ CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_txtmode index 831b4b29..231d6e94 100644 --- a/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_txtmode @@ -142,7 +142,6 @@ CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_corebootfb index 2c460c4b..8d5ecd79 100644 --- a/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_corebootfb @@ -144,7 +144,6 @@ CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_txtmode index 3563bf2c..272c35d5 100644 --- a/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_txtmode @@ -142,7 +142,6 @@ CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e4300_4mb/config/libgfxinit_corebootfb b/config/coreboot/e4300_4mb/config/libgfxinit_corebootfb index 43b5e1f5..67021be8 100644 --- a/config/coreboot/e4300_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e4300_4mb/config/libgfxinit_corebootfb @@ -141,7 +141,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set CONFIG_BOARD_DELL_E4300=y # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e4300_4mb/config/libgfxinit_txtmode b/config/coreboot/e4300_4mb/config/libgfxinit_txtmode index 28caa370..e6309b47 100644 --- a/config/coreboot/e4300_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/e4300_4mb/config/libgfxinit_txtmode @@ -139,7 +139,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set CONFIG_BOARD_DELL_E4300=y # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e5420_6mb/config/libgfxinit_corebootfb b/config/coreboot/e5420_6mb/config/libgfxinit_corebootfb index af5b8906..3367bc2b 100644 --- a/config/coreboot/e5420_6mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e5420_6mb/config/libgfxinit_corebootfb @@ -142,7 +142,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set CONFIG_BOARD_DELL_LATITUDE_E5420=y diff --git a/config/coreboot/e5420_6mb/config/libgfxinit_txtmode b/config/coreboot/e5420_6mb/config/libgfxinit_txtmode index 72ebebc1..331dda80 100644 --- a/config/coreboot/e5420_6mb/config/libgfxinit_txtmode +++ b/config/coreboot/e5420_6mb/config/libgfxinit_txtmode @@ -140,7 +140,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set CONFIG_BOARD_DELL_LATITUDE_E5420=y diff --git a/config/coreboot/e5520_6mb/config/libgfxinit_corebootfb b/config/coreboot/e5520_6mb/config/libgfxinit_corebootfb index 911c6b65..f6113581 100644 --- a/config/coreboot/e5520_6mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e5520_6mb/config/libgfxinit_corebootfb @@ -142,7 +142,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e5520_6mb/config/libgfxinit_txtmode b/config/coreboot/e5520_6mb/config/libgfxinit_txtmode index eecdfd6c..96bd21fc 100644 --- a/config/coreboot/e5520_6mb/config/libgfxinit_txtmode +++ b/config/coreboot/e5520_6mb/config/libgfxinit_txtmode @@ -140,7 +140,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e5530_12mb/config/libgfxinit_corebootfb b/config/coreboot/e5530_12mb/config/libgfxinit_corebootfb index de00bd3b..7702f7bd 100644 --- a/config/coreboot/e5530_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e5530_12mb/config/libgfxinit_corebootfb @@ -142,7 +142,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e5530_12mb/config/libgfxinit_txtmode b/config/coreboot/e5530_12mb/config/libgfxinit_txtmode index 5bacbb59..fa950439 100644 --- a/config/coreboot/e5530_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/e5530_12mb/config/libgfxinit_txtmode @@ -140,7 +140,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6220_10mb/config/libgfxinit_corebootfb b/config/coreboot/e6220_10mb/config/libgfxinit_corebootfb index 67995fc1..25c27fdb 100644 --- a/config/coreboot/e6220_10mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6220_10mb/config/libgfxinit_corebootfb @@ -142,7 +142,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6220_10mb/config/libgfxinit_txtmode b/config/coreboot/e6220_10mb/config/libgfxinit_txtmode index 8a51ce95..3a79e7e3 100644 --- a/config/coreboot/e6220_10mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6220_10mb/config/libgfxinit_txtmode @@ -140,7 +140,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6230_12mb/config/libgfxinit_corebootfb b/config/coreboot/e6230_12mb/config/libgfxinit_corebootfb index c15da3a1..7bc76f82 100644 --- a/config/coreboot/e6230_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6230_12mb/config/libgfxinit_corebootfb @@ -142,7 +142,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6230_12mb/config/libgfxinit_txtmode b/config/coreboot/e6230_12mb/config/libgfxinit_txtmode index db76355a..2d578a57 100644 --- a/config/coreboot/e6230_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6230_12mb/config/libgfxinit_txtmode @@ -140,7 +140,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6320_10mb/config/libgfxinit_corebootfb b/config/coreboot/e6320_10mb/config/libgfxinit_corebootfb index 75af1da9..e6867cd1 100644 --- a/config/coreboot/e6320_10mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6320_10mb/config/libgfxinit_corebootfb @@ -142,7 +142,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6320_10mb/config/libgfxinit_txtmode b/config/coreboot/e6320_10mb/config/libgfxinit_txtmode index bba8ac91..ca030f32 100644 --- a/config/coreboot/e6320_10mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6320_10mb/config/libgfxinit_txtmode @@ -140,7 +140,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6330_12mb/config/libgfxinit_corebootfb b/config/coreboot/e6330_12mb/config/libgfxinit_corebootfb index 6b00fa47..bd93e3bf 100644 --- a/config/coreboot/e6330_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6330_12mb/config/libgfxinit_corebootfb @@ -142,7 +142,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6330_12mb/config/libgfxinit_txtmode b/config/coreboot/e6330_12mb/config/libgfxinit_txtmode index b7dedfce..ee4686da 100644 --- a/config/coreboot/e6330_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6330_12mb/config/libgfxinit_txtmode @@ -140,7 +140,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb b/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb index 4267793a..84809847 100644 --- a/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb @@ -141,7 +141,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set CONFIG_BOARD_DELL_E6400=y -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6400_4mb/config/libgfxinit_txtmode b/config/coreboot/e6400_4mb/config/libgfxinit_txtmode index efd7fcef..4b53f9a9 100644 --- a/config/coreboot/e6400_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6400_4mb/config/libgfxinit_txtmode @@ -139,7 +139,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set CONFIG_BOARD_DELL_E6400=y -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6400nvidia_4mb/config/normal b/config/coreboot/e6400nvidia_4mb/config/normal index 455bb78f..79c3790a 100644 --- a/config/coreboot/e6400nvidia_4mb/config/normal +++ b/config/coreboot/e6400nvidia_4mb/config/normal @@ -138,7 +138,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set CONFIG_BOARD_DELL_E6400=y -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6420_10mb/config/libgfxinit_corebootfb b/config/coreboot/e6420_10mb/config/libgfxinit_corebootfb index b2cb70fe..f558eefd 100644 --- a/config/coreboot/e6420_10mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6420_10mb/config/libgfxinit_corebootfb @@ -142,7 +142,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6420_10mb/config/libgfxinit_txtmode b/config/coreboot/e6420_10mb/config/libgfxinit_txtmode index 2ed613a2..2158736b 100644 --- a/config/coreboot/e6420_10mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6420_10mb/config/libgfxinit_txtmode @@ -140,7 +140,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb b/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb index 1f99865c..593d294c 100644 --- a/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb @@ -142,7 +142,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6430_12mb/config/libgfxinit_txtmode b/config/coreboot/e6430_12mb/config/libgfxinit_txtmode index 54d89ef4..e9211864 100644 --- a/config/coreboot/e6430_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6430_12mb/config/libgfxinit_txtmode @@ -140,7 +140,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6520_10mb/config/libgfxinit_corebootfb b/config/coreboot/e6520_10mb/config/libgfxinit_corebootfb index 1eea8822..381b7207 100644 --- a/config/coreboot/e6520_10mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6520_10mb/config/libgfxinit_corebootfb @@ -142,7 +142,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6520_10mb/config/libgfxinit_txtmode b/config/coreboot/e6520_10mb/config/libgfxinit_txtmode index 3a8fc91c..92d54b1b 100644 --- a/config/coreboot/e6520_10mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6520_10mb/config/libgfxinit_txtmode @@ -140,7 +140,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb b/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb index 6cfb5add..4345d838 100644 --- a/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb @@ -142,7 +142,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/e6530_12mb/config/libgfxinit_txtmode b/config/coreboot/e6530_12mb/config/libgfxinit_txtmode index ed32a935..d5a2b25b 100644 --- a/config/coreboot/e6530_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6530_12mb/config/libgfxinit_txtmode @@ -140,7 +140,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/coreboot/t1650_12mb/config/libgfxinit_txtmode b/config/coreboot/t1650_12mb/config/libgfxinit_txtmode index 9761efd6..e7358991 100644 --- a/config/coreboot/t1650_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t1650_12mb/config/libgfxinit_txtmode @@ -143,7 +143,6 @@ CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_E4300 is not set # CONFIG_BOARD_DELL_E6400 is not set -# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set diff --git a/config/submodule/coreboot/dell7/acpica-unix-20230628.tar.gz/module.cfg b/config/submodule/coreboot/dell7/acpica-unix-20230628.tar.gz/module.cfg new file mode 100644 index 00000000..6dde459a --- /dev/null +++ b/config/submodule/coreboot/dell7/acpica-unix-20230628.tar.gz/module.cfg @@ -0,0 +1,3 @@ +subfile="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix-20230628.tar.gz" +subfile_bkup="https://mirror.math.princeton.edu/pub/libreboot/misc/acpica/acpica-unix-20230628.tar.gz" +subhash="d726e69ebd8b8110690e3aff8d1919b43b0a2185efdeb9131ea8d89d321ca3a318a89c721ea740ae366f31ed3d1c11c2906f8807ee8a190e6f67fe5b2023cea4" diff --git a/config/submodule/coreboot/dell7/binutils-2.43.1.tar.xz/module.cfg b/config/submodule/coreboot/dell7/binutils-2.43.1.tar.xz/module.cfg new file mode 100644 index 00000000..f3e372a4 --- /dev/null +++ b/config/submodule/coreboot/dell7/binutils-2.43.1.tar.xz/module.cfg @@ -0,0 +1,3 @@ +subfile="https://ftp.nluug.nl/pub/gnu/binutils/binutils-2.43.1.tar.xz" +subfile_bkup="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils/binutils-2.43.1.tar.xz" +subhash="20977ad17729141a2c26d358628f44a0944b84dcfefdec2ba029c2d02f40dfc41cc91c0631044560d2bd6f9a51e1f15846b4b311befbe14f1239f14ff7d57824" diff --git a/config/submodule/coreboot/dell7/fsp/module.cfg b/config/submodule/coreboot/dell7/fsp/module.cfg new file mode 100644 index 00000000..8042a059 --- /dev/null +++ b/config/submodule/coreboot/dell7/fsp/module.cfg @@ -0,0 +1,3 @@ +subrepo="https://review.coreboot.org/fsp.git" +subrepo_bkup="https://github.com/coreboot/fsp" +subhash="68328e297e195a6cfb1949b60d971c032a172ba3" diff --git a/config/submodule/coreboot/dell7/gcc-14.2.0.tar.xz/module.cfg b/config/submodule/coreboot/dell7/gcc-14.2.0.tar.xz/module.cfg new file mode 100644 index 00000000..9a4892f5 --- /dev/null +++ b/config/submodule/coreboot/dell7/gcc-14.2.0.tar.xz/module.cfg @@ -0,0 +1,3 @@ +subfile="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-14.2.0/gcc-14.2.0.tar.xz" +subfile_bkup="https://ftp.nluug.nl/pub/gnu/gcc/gcc-14.2.0/gcc-14.2.0.tar.xz" +subhash="932bdef0cda94bacedf452ab17f103c0cb511ff2cec55e9112fc0328cbf1d803b42595728ea7b200e0a057c03e85626f937012e49a7515bc5dd256b2bf4bc396" diff --git a/config/submodule/coreboot/dell7/gmp-6.3.0.tar.xz/module.cfg b/config/submodule/coreboot/dell7/gmp-6.3.0.tar.xz/module.cfg new file mode 100644 index 00000000..fe274faf --- /dev/null +++ b/config/submodule/coreboot/dell7/gmp-6.3.0.tar.xz/module.cfg @@ -0,0 +1,3 @@ +subfile="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz" +subfile_bkup="https://ftp.nluug.nl/pub/gnu/gmp/gmp-6.3.0.tar.xz" +subhash="e85a0dab5195889948a3462189f0e0598d331d3457612e2d3350799dba2e244316d256f8161df5219538eb003e4b5343f989aaa00f96321559063ed8c8f29fd2" diff --git a/config/submodule/coreboot/dell7/intel-microcode/module.cfg b/config/submodule/coreboot/dell7/intel-microcode/module.cfg new file mode 100644 index 00000000..cb6c6d46 --- /dev/null +++ b/config/submodule/coreboot/dell7/intel-microcode/module.cfg @@ -0,0 +1,3 @@ +subrepo="https://review.coreboot.org/intel-microcode.git" +subrepo_bkup="https://github.com/coreboot/intel-microcode" +subhash="fbfe741896c55b36fcbf0560a68be96286103556" diff --git a/config/submodule/coreboot/dell7/libgfxinit/module.cfg b/config/submodule/coreboot/dell7/libgfxinit/module.cfg new file mode 100644 index 00000000..1ba41724 --- /dev/null +++ b/config/submodule/coreboot/dell7/libgfxinit/module.cfg @@ -0,0 +1,3 @@ +subrepo="https://review.coreboot.org/libgfxinit.git" +subrepo_bkup="https://github.com/coreboot/libgfxinit" +subhash="17cfc92f402493979783585b6581efbd98c0cf07" diff --git a/config/submodule/coreboot/dell7/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch b/config/submodule/coreboot/dell7/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch new file mode 100644 index 00000000..2d248941 --- /dev/null +++ b/config/submodule/coreboot/dell7/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch @@ -0,0 +1,42 @@ +From ba078864500de99c26b6ea7e3fdcef19bca582a7 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Mon, 20 May 2024 10:10:03 -0600 +Subject: [PATCH 1/1] g45/hw-gfx-gma-plls.adb: Make reference clock frequency + configurable + +Instead of assuming a 96 MHz reference clock frequency, use the value +specified by the new INTEL_GMA_DPLL_REF_FREQ Kconfig. This defaults to +96 MHz to preserve the existing behavior. An example of where this is +needed is the DPLL_REF_SSCLK input, which will typically be 100 MHz +to support LVDS spread spectrum clocking. + +Signed-off-by: Nicholas Chin +--- + common/g45/hw-gfx-gma-plls.adb | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/common/g45/hw-gfx-gma-plls.adb b/common/g45/hw-gfx-gma-plls.adb +index 67242f2..5e970d7 100644 +--- a/common/g45/hw-gfx-gma-plls.adb ++++ b/common/g45/hw-gfx-gma-plls.adb +@@ -12,6 +12,8 @@ + -- GNU General Public License for more details. + -- + ++with CB.Config; ++ + with HW.Time; + with HW.GFX.GMA.Config; + with HW.GFX.GMA.Registers; +@@ -460,7 +462,7 @@ is + (Display => Port_Cfg.Display, + Target_Dotclock => Target_Clock, + -- should be, but doesn't has to be always the same: +- Reference_Clock => 96_000_000, ++ Reference_Clock => CB.Config.INTEL_GMA_DPLL_REF_FREQ, + Best_Clock => Clk, + Valid => Success); + else +-- +2.39.2 + diff --git a/config/submodule/coreboot/dell7/libhwbase/module.cfg b/config/submodule/coreboot/dell7/libhwbase/module.cfg new file mode 100644 index 00000000..2937b8b7 --- /dev/null +++ b/config/submodule/coreboot/dell7/libhwbase/module.cfg @@ -0,0 +1,3 @@ +subrepo="https://review.coreboot.org/libhwbase.git" +subrepo_bkup="https://github.com/coreboot/libhwbase" +subhash="584629b9f4771b7618951cec57df2ca3af9c6981" diff --git a/config/submodule/coreboot/dell7/module.list b/config/submodule/coreboot/dell7/module.list new file mode 100644 index 00000000..1cc88fd6 --- /dev/null +++ b/config/submodule/coreboot/dell7/module.list @@ -0,0 +1,12 @@ +3rdparty/fsp +3rdparty/intel-microcode +3rdparty/libgfxinit +3rdparty/libhwbase +3rdparty/vboot +util/crossgcc/tarballs/binutils-2.43.1.tar.xz +util/crossgcc/tarballs/gcc-14.2.0.tar.xz +util/crossgcc/tarballs/gmp-6.3.0.tar.xz +util/crossgcc/tarballs/mpc-1.3.1.tar.gz +util/crossgcc/tarballs/mpfr-4.2.1.tar.xz +util/crossgcc/tarballs/nasm-2.16.03.tar.bz2 +util/crossgcc/tarballs/acpica-unix-20230628.tar.gz diff --git a/config/submodule/coreboot/dell7/mpc-1.3.1.tar.gz/module.cfg b/config/submodule/coreboot/dell7/mpc-1.3.1.tar.gz/module.cfg new file mode 100644 index 00000000..f98b6444 --- /dev/null +++ b/config/submodule/coreboot/dell7/mpc-1.3.1.tar.gz/module.cfg @@ -0,0 +1,3 @@ +subfile="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc/mpc-1.3.1.tar.gz" +subfile_bkup="https://ftp.nluug.nl/pub/gnu/mpc/mpc-1.3.1.tar.gz" +subhash="4bab4ef6076f8c5dfdc99d810b51108ced61ea2942ba0c1c932d624360a5473df20d32b300fc76f2ba4aa2a97e1f275c9fd494a1ba9f07c4cb2ad7ceaeb1ae97" diff --git a/config/submodule/coreboot/dell7/mpfr-4.2.1.tar.xz/module.cfg b/config/submodule/coreboot/dell7/mpfr-4.2.1.tar.xz/module.cfg new file mode 100644 index 00000000..3419bc30 --- /dev/null +++ b/config/submodule/coreboot/dell7/mpfr-4.2.1.tar.xz/module.cfg @@ -0,0 +1,3 @@ +subfile="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr/mpfr-4.2.1.tar.xz" +subfile_bkup="https://ftp.nluug.nl/pub/gnu/mpfr/mpfr-4.2.1.tar.xz" +subhash="bc68c0d755d5446403644833ecbb07e37360beca45f474297b5d5c40926df1efc3e2067eecffdf253f946288bcca39ca89b0613f545d46a9e767d1d4cf358475" diff --git a/config/submodule/coreboot/dell7/nasm-2.16.03.tar.bz2/module.cfg b/config/submodule/coreboot/dell7/nasm-2.16.03.tar.bz2/module.cfg new file mode 100644 index 00000000..c98cc71f --- /dev/null +++ b/config/submodule/coreboot/dell7/nasm-2.16.03.tar.bz2/module.cfg @@ -0,0 +1,3 @@ +subfile="https://www.nasm.us/pub/nasm/releasebuilds/2.16.03/nasm-2.16.03.tar.bz2" +subfile_bkup="https://www.mirrorservice.org/sites/distfiles.macports.org/nasm/nasm-2.16.03.tar.bz2" +subhash="f28445d368debdf44219cc57df33800a8c0e49186cd60836d4adfec7700d53b801d34aa9fc9bfda74169843f33a1e8b465e11292582eb968bb9c3a26f54dd172" diff --git a/config/submodule/coreboot/dell7/vboot/module.cfg b/config/submodule/coreboot/dell7/vboot/module.cfg new file mode 100644 index 00000000..917d23fa --- /dev/null +++ b/config/submodule/coreboot/dell7/vboot/module.cfg @@ -0,0 +1,3 @@ +subrepo="https://review.coreboot.org/vboot.git" +subrepo_bkup="https://github.com/coreboot/vboot" +subhash="f1f70f46dc5482bb7c654e53ed58d4001e386df2" diff --git a/config/submodule/coreboot/dell7/vboot/patches/0001-extract_vmlinuz.c-Fix-the-bounds-check-on-vmlinuz_he.patch b/config/submodule/coreboot/dell7/vboot/patches/0001-extract_vmlinuz.c-Fix-the-bounds-check-on-vmlinuz_he.patch new file mode 100644 index 00000000..1ac41de6 --- /dev/null +++ b/config/submodule/coreboot/dell7/vboot/patches/0001-extract_vmlinuz.c-Fix-the-bounds-check-on-vmlinuz_he.patch @@ -0,0 +1,178 @@ +From 195f61375aeec9eec16604ec59f6eda2e6058cc1 Mon Sep 17 00:00:00 2001 +From: "Luke T. Shumaker" +Date: Thu, 30 May 2024 14:08:33 -0600 +Subject: [PATCH 1/1] extract_vmlinuz.c: Fix the bounds check on + vmlinuz_header_{offset,size} + +The check on vmlinuz_header_offset and vmlinuz_header_size is obviously +wrong: + + if (!vmlinuz_header_size || + kpart_data + vmlinuz_header_offset + vmlinuz_header_size > + kpart_data) { + return 1; + } + +`kpart_data + some_unsigned_values` can obviously never be `> kpart_data`, +unless something has overflowed! And `vmlinuz_header_offset` hasn't even +been set yet (besides being initialized to zero)! + +GCC will deduce that if the check didn't cause the function to bail, then +vmlinuz_header_size (a uint32_t) must be "negative"; that is: in the range +[2GiB,4GiB). + +On platforms where size_t is 32-bits, this is *especially* broken. +memcpy's size argument must be in the range [0,2GiB). Because GCC has +proved that vmlinuz_header_size is higher than that, it will fail to +compile: + + host/lib/extract_vmlinuz.c:67:9: error: 'memcpy' specified bound between 2147483648 and 4294967295 exceeds maximum object size 2147483647 [-Werror=stringop-overflow=] + +So, fix the check. + +I can now say that what I suspect the original author meant to write would +be the following patch, if `vmlinuz_header_offset` were already set: + + -kpart_data + vmlinuz_header_offset + vmlinuz_header_size > kpart_data + +now + vmlinuz_header_offset + vmlinuz_header_size > kpart_size + +This hypothesis is supported by `now` not getting incremented by +`kblob_size` the way it is for the keyblock and preamble sizes. + +However, we can also see that even this "corrected" bounds check is +insufficient: it does not detect the vmlinuz_header overflowing into +kblob_data. + +OK, so let's describe the fix: + +Have a `*vmlinuz_header` pointer instead of a +`uint64_t vmlinuz_header_offset`, to be more similar to all the other +regions. With this change, the correct check becomes a simple + + vmlinuz_header + vmlinuz_header_size > kblob_data + +While we're at it, make some changes that could have helped avoid this in +the first place: + + - Add comments. + - Calculate the vmlinuz_header offset right away, instead of waiting. + - Go ahead and increment `now` by `kblob_size`, to increase regularity. + +Change-Id: I5c03e49070b6dd2e04459566ef7dd129d27736e4 +--- + host/lib/extract_vmlinuz.c | 72 +++++++++++++++++++++++++++----------- + 1 file changed, 51 insertions(+), 21 deletions(-) + +diff --git a/host/lib/extract_vmlinuz.c b/host/lib/extract_vmlinuz.c +index 4ccfcf33..d2c09443 100644 +--- a/host/lib/extract_vmlinuz.c ++++ b/host/lib/extract_vmlinuz.c +@@ -15,16 +15,44 @@ + + int ExtractVmlinuz(void *kpart_data, size_t kpart_size, + void **vmlinuz_out, size_t *vmlinuz_size) { ++ // We're going to be extracting `vmlinuz_header` and ++ // `kblob_data`, and returning the concatenation of them. ++ // ++ // kpart_data = +-[kpart_size]------------------------------------+ ++ // | | ++ // keyblock = | +-[keyblock->keyblock_size]-------------------+ | ++ // | | struct vb2_keyblock keyblock | | ++ // | | char [] ...data... | | ++ // | +---------------------------------------------+ | ++ // | | ++ // preamble = | +-[preamble->preamble_size]-------------------+ | ++ // | | struct vb2_kernel_preamble preamble | | ++ // | | char [] ...data... | | ++ // | | char [] vmlinuz_header | | ++ // | | char [] ...data... | | ++ // | +---------------------------------------------+ | ++ // | | ++ // kblob_data= | +-[preamble->body_signature.data_size]--------+ | ++ // | | char [] ...data... | | ++ // | +---------------------------------------------+ | ++ // | | ++ // +-------------------------------------------------+ ++ + size_t now = 0; ++ // The 3 sections of kpart_data. ++ struct vb2_keyblock *keyblock = NULL; + struct vb2_kernel_preamble *preamble = NULL; + uint8_t *kblob_data = NULL; + uint32_t kblob_size = 0; ++ // vmlinuz_header ++ uint8_t *vmlinuz_header = NULL; + uint32_t vmlinuz_header_size = 0; +- uint64_t vmlinuz_header_address = 0; +- uint64_t vmlinuz_header_offset = 0; ++ // The concatenated result. + void *vmlinuz = NULL; + +- struct vb2_keyblock *keyblock = (struct vb2_keyblock *)kpart_data; ++ // Isolate the 3 sections of kpart_data. ++ ++ keyblock = (struct vb2_keyblock *)kpart_data; + now += keyblock->keyblock_size; + if (now > kpart_size) + return 1; +@@ -36,37 +64,39 @@ int ExtractVmlinuz(void *kpart_data, size_t kpart_size, + + kblob_data = kpart_data + now; + kblob_size = preamble->body_signature.data_size; +- +- if (!kblob_data || (now + kblob_size) > kpart_size) ++ now += kblob_size; ++ if (now > kpart_size) + return 1; + ++ // Find `vmlinuz_header` within `preamble`. ++ + if (preamble->header_version_minor > 0) { +- vmlinuz_header_address = preamble->vmlinuz_header_address; ++ // calculate the vmlinuz_header offset from ++ // the beginning of the kpart_data. The kblob doesn't ++ // include the body_load_offset, but does include ++ // the keyblock and preamble sections. ++ size_t vmlinuz_header_offset = ++ preamble->vmlinuz_header_address - ++ preamble->body_load_address + ++ keyblock->keyblock_size + ++ preamble->preamble_size; ++ ++ vmlinuz_header = kpart_data + vmlinuz_header_offset; + vmlinuz_header_size = preamble->vmlinuz_header_size; + } + +- if (!vmlinuz_header_size || +- kpart_data + vmlinuz_header_offset + vmlinuz_header_size > +- kpart_data) { ++ if (!vmlinuz_header || ++ !vmlinuz_header_size || ++ vmlinuz_header + vmlinuz_header_size > kblob_data) { + return 1; + } + +- // calculate the vmlinuz_header offset from +- // the beginning of the kpart_data. The kblob doesn't +- // include the body_load_offset, but does include +- // the keyblock and preamble sections. +- vmlinuz_header_offset = vmlinuz_header_address - +- preamble->body_load_address + +- keyblock->keyblock_size + +- preamble->preamble_size; ++ // Concatenate and return. + + vmlinuz = malloc(vmlinuz_header_size + kblob_size); + if (vmlinuz == NULL) + return 1; +- +- memcpy(vmlinuz, kpart_data + vmlinuz_header_offset, +- vmlinuz_header_size); +- ++ memcpy(vmlinuz, vmlinuz_header, vmlinuz_header_size); + memcpy(vmlinuz + vmlinuz_header_size, kblob_data, kblob_size); + + *vmlinuz_out = vmlinuz; +-- +2.45.1 + -- cgit v1.2.1