From cc2f08e7bbf9fc32bdd37079ee93b477ef4e8d09 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 14 Jul 2025 11:18:42 +0100 Subject: Revert "coreboot: rev 8b52167a9f 13 July 2025, rebase t480" This reverts commit 32dfdfbb01b84bb9c058e9b84305f15a14d4e231. The update caused an issue on T480: Backlight comes on, then off, then on, then off, repeatedly, and never gets to the payload. Will have to investigate further. Signed-off-by: Leah Rowe --- ...01-add-c3-and-clockgen-to-apple-macbook21.patch | 4 +- .../0002-lenovo-t400-Enable-all-SATA-ports.patch | 4 +- ...230-set-me_state-Disabled-in-cmos.default.patch | 4 +- ..._state-Disabled-on-all-cmos.default-files.patch | 4 +- ...-ifdtool-add-nuke-flag-all-0xFF-on-region.patch | 4 +- ...00-Enable-01.0-device-in-devicetree-for-d.patch | 4 +- ...ing-for-coreboot-images-built-without-a-p.patch | 4 +- ...CK-Disable-coreboot-related-BL31-features.patch | 4 +- ...-dell-e6430-use-ME-Soft-Temporary-Disable.patch | 4 +- ...0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch | 4 +- ...intel-haswell-make-IOMMU-a-runtime-option.patch | 4 +- ...ll-optiplex_9020-Disable-IOMMU-by-default.patch | 4 +- ...well-Fully-disable-iGPU-when-dGPU-is-used.patch | 4 +- ...c-dell-mec5035-Add-S3-suspend-SMI-handler.patch | 4 +- ...ell-lock-policy-regs-when-disabling-IOMMU.patch | 4 +- ...0016-nb-intel-gm45-Make-DDR2-raminit-work.patch | 4 +- ...Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch | 4 +- ...00-Use-100-MHz-reference-clock-for-displa.patch | 4 +- ...019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch | 4 +- ...0020-mb-dell-Convert-E6400-into-a-variant.patch | 4 +- ...-mb-dell-gm45_latitudes-Add-E4300-variant.patch | 4 +- ...ell-Add-S3-SMI-handler-for-Dell-Latitudes.patch | 4 +- ...-mec5035-Route-power-button-event-to-host.patch | 4 +- ...-Disable-compression-on-refcode-insertion.patch | 4 +- ...ntel-Disable-stack-overflow-debug-options.patch | 4 +- ...026-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch | 708 ------- ...0026-soc-intel-skylake-configure-usb-acpi.patch | 94 + ...027-mb-dell-optiplex_780-Add-USFF-variant.patch | 326 --- ...kylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch | 30 + ...novo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch | 2232 ++++++++++++++++++++ ...rc-intel-x4x-Disable-stack-overflow-debug.patch | 33 - ...p-8300cmt-remove-xhci_overcurrent_mapping.patch | 42 - ...029-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch | 708 +++++++ .../0030-dell-3050micro-disable-nvme-hotplug.patch | 49 - ...030-mb-dell-optiplex_780-Add-USFF-variant.patch | 326 +++ .../0031-dell-3050micro-disable-nvme-hotplug.patch | 49 + ...0031-soc-intel-skylake-configure-usb-acpi.patch | 94 - ...Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch | 78 + ...kylake-Disable-stack-overflow-debug-optio.patch | 61 - ...33-soc-intel-skylake-Don-t-compress-FSP-S.patch | 6 +- ...l-pmc-Hardcoded-poweroff-after-power-fail.patch | 4 +- ...o-h8-Add-CFR-objects-for-existing-options.patch | 182 -- ...kylake-Disable-stack-overflow-debug-optio.patch | 61 + ...pmh7-Add-CFR-objects-for-existing-options.patch | 62 - ...rc-intel-x4x-Disable-stack-overflow-debug.patch | 33 + ...7-Conditional-TBFW-setting-for-T480-T480S.patch | 37 + ...8-Replace-chip-regs-for-BT-WWAN-detect-wi.patch | 512 ----- ...k-building-other-thinkpads-with-the-hacks.patch | 153 ++ ...8-Add-Kconfig-to-select-use-of-Thermal-Zo.patch | 137 -- ...o-h8-Rework-invalid-temperature-reporting.patch | 488 ----- ...p-8300cmt-remove-xhci_overcurrent_mapping.patch | 42 + ...0040-ec-lenovo-Add-support-for-MEC1653-EC.patch | 371 ---- ...0-lenovo-t480-Drop-redundant-PcieRpEnable.patch | 113 + ...novo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch | 1859 ---------------- ...Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch | 78 - ...3-Conditional-TBFW-setting-for-T480-T480S.patch | 37 - config/coreboot/default/target.cfg | 2 +- .../hp2170p_16mb/config/libgfxinit_corebootfb | 1 - .../hp2170p_16mb/config/libgfxinit_txtmode | 1 - .../hp2560p_8mb/config/libgfxinit_corebootfb | 1 - .../coreboot/hp2560p_8mb/config/libgfxinit_txtmode | 1 - .../hp2570p_16mb/config/libgfxinit_corebootfb | 1 - .../hp2570p_16mb/config/libgfxinit_txtmode | 1 - .../hp8200sff_4mb/config/libgfxinit_corebootfb | 1 - .../hp8200sff_4mb/config/libgfxinit_txtmode | 1 - .../hp8200sff_8mb/config/libgfxinit_corebootfb | 1 - .../hp8200sff_8mb/config/libgfxinit_txtmode | 1 - .../hp820g2_12mb/config/libgfxinit_corebootfb | 1 - .../hp820g2_12mb/config/libgfxinit_txtmode | 1 - .../hp8300cmt_16mb/config/libgfxinit_corebootfb | 1 - .../hp8300cmt_16mb/config/libgfxinit_txtmode | 1 - .../hp8300usdt_16mb/config/libgfxinit_corebootfb | 1 - .../hp8300usdt_16mb/config/libgfxinit_txtmode | 1 - .../hp8460pintel_8mb/config/libgfxinit_corebootfb | 1 - .../hp8460pintel_8mb/config/libgfxinit_txtmode | 1 - .../hp8470pintel_16mb/config/libgfxinit_corebootfb | 1 - .../hp8470pintel_16mb/config/libgfxinit_txtmode | 1 - config/coreboot/hp8560w_8mb/config/normal | 1 - .../hp9470m_16mb/config/libgfxinit_corebootfb | 1 - .../hp9470m_16mb/config/libgfxinit_txtmode | 1 - .../config/libgfxinit_corebootfb | 1 - .../hppro3500series_8mb/config/libgfxinit_txtmode | 1 - .../r400_16mb/config/libgfxinit_corebootfb | 2 - .../coreboot/r400_16mb/config/libgfxinit_txtmode | 2 - .../coreboot/r400_4mb/config/libgfxinit_corebootfb | 2 - config/coreboot/r400_4mb/config/libgfxinit_txtmode | 2 - .../coreboot/r400_8mb/config/libgfxinit_corebootfb | 2 - config/coreboot/r400_8mb/config/libgfxinit_txtmode | 2 - .../coreboot/r500_4mb/config/libgfxinit_corebootfb | 1 - config/coreboot/r500_4mb/config/libgfxinit_txtmode | 1 - .../t400_16mb/config/libgfxinit_corebootfb | 2 - .../coreboot/t400_16mb/config/libgfxinit_txtmode | 2 - .../coreboot/t400_4mb/config/libgfxinit_corebootfb | 2 - config/coreboot/t400_4mb/config/libgfxinit_txtmode | 2 - .../coreboot/t400_8mb/config/libgfxinit_corebootfb | 2 - config/coreboot/t400_8mb/config/libgfxinit_txtmode | 2 - .../coreboot/t420_8mb/config/libgfxinit_corebootfb | 1 - config/coreboot/t420_8mb/config/libgfxinit_txtmode | 1 - .../t420s_8mb/config/libgfxinit_corebootfb | 1 - .../coreboot/t420s_8mb/config/libgfxinit_txtmode | 1 - .../t430_12mb/config/libgfxinit_corebootfb | 2 - .../coreboot/t430_12mb/config/libgfxinit_txtmode | 2 - .../t480_vfsp_16mb/config/libgfxinit_corebootfb | 13 +- .../t480_vfsp_16mb/config/libgfxinit_txtmode | 13 +- .../t480s_vfsp_16mb/config/libgfxinit_corebootfb | 12 +- .../t480s_vfsp_16mb/config/libgfxinit_txtmode | 12 +- .../t500_16mb/config/libgfxinit_corebootfb | 2 - .../coreboot/t500_16mb/config/libgfxinit_txtmode | 2 - .../coreboot/t500_4mb/config/libgfxinit_corebootfb | 2 - config/coreboot/t500_4mb/config/libgfxinit_txtmode | 2 - .../coreboot/t500_8mb/config/libgfxinit_corebootfb | 2 - config/coreboot/t500_8mb/config/libgfxinit_txtmode | 2 - .../coreboot/t520_8mb/config/libgfxinit_corebootfb | 2 - config/coreboot/t520_8mb/config/libgfxinit_txtmode | 2 - .../t530_12mb/config/libgfxinit_corebootfb | 2 - .../coreboot/t530_12mb/config/libgfxinit_txtmode | 2 - .../t60_16mb_intelgpu/config/libgfxinit_corebootfb | 2 - .../t60_16mb_intelgpu/config/libgfxinit_txtmode | 2 - .../t60_intelgpu/config/libgfxinit_corebootfb | 2 - .../t60_intelgpu/config/libgfxinit_txtmode | 2 - .../w500_16mb/config/libgfxinit_corebootfb | 2 - .../coreboot/w500_16mb/config/libgfxinit_txtmode | 2 - .../coreboot/w500_4mb/config/libgfxinit_corebootfb | 2 - config/coreboot/w500_4mb/config/libgfxinit_txtmode | 2 - .../coreboot/w500_8mb/config/libgfxinit_corebootfb | 2 - config/coreboot/w500_8mb/config/libgfxinit_txtmode | 2 - .../w530_12mb/config/libgfxinit_corebootfb | 2 - .../coreboot/w530_12mb/config/libgfxinit_txtmode | 2 - .../x200_16mb/config/libgfxinit_corebootfb | 2 - .../coreboot/x200_16mb/config/libgfxinit_txtmode | 2 - .../coreboot/x200_4mb/config/libgfxinit_corebootfb | 2 - config/coreboot/x200_4mb/config/libgfxinit_txtmode | 2 - .../coreboot/x200_8mb/config/libgfxinit_corebootfb | 2 - config/coreboot/x200_8mb/config/libgfxinit_txtmode | 2 - .../coreboot/x220_8mb/config/libgfxinit_corebootfb | 1 - config/coreboot/x220_8mb/config/libgfxinit_txtmode | 1 - .../x230_12mb/config/libgfxinit_corebootfb | 1 - .../coreboot/x230_12mb/config/libgfxinit_txtmode | 1 - .../x230_16mb/config/libgfxinit_corebootfb | 1 - .../coreboot/x230_16mb/config/libgfxinit_txtmode | 1 - .../x230t_12mb/config/libgfxinit_corebootfb | 1 - .../coreboot/x230t_12mb/config/libgfxinit_txtmode | 1 - .../x230t_16mb/config/libgfxinit_corebootfb | 1 - .../coreboot/x230t_16mb/config/libgfxinit_txtmode | 1 - config/coreboot/x60/config/libgfxinit_corebootfb | 2 - config/coreboot/x60/config/libgfxinit_txtmode | 2 - .../coreboot/x60_16mb/config/libgfxinit_corebootfb | 2 - config/coreboot/x60_16mb/config/libgfxinit_txtmode | 2 - 148 files changed, 4032 insertions(+), 5258 deletions(-) delete mode 100644 config/coreboot/default/patches/0026-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch create mode 100644 config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch delete mode 100644 config/coreboot/default/patches/0027-mb-dell-optiplex_780-Add-USFF-variant.patch create mode 100644 config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch create mode 100644 config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch delete mode 100644 config/coreboot/default/patches/0028-src-intel-x4x-Disable-stack-overflow-debug.patch delete mode 100644 config/coreboot/default/patches/0029-hp-8300cmt-remove-xhci_overcurrent_mapping.patch create mode 100644 config/coreboot/default/patches/0029-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch delete mode 100644 config/coreboot/default/patches/0030-dell-3050micro-disable-nvme-hotplug.patch create mode 100644 config/coreboot/default/patches/0030-mb-dell-optiplex_780-Add-USFF-variant.patch create mode 100644 config/coreboot/default/patches/0031-dell-3050micro-disable-nvme-hotplug.patch delete mode 100644 config/coreboot/default/patches/0031-soc-intel-skylake-configure-usb-acpi.patch create mode 100644 config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch delete mode 100644 config/coreboot/default/patches/0032-src-intel-skylake-Disable-stack-overflow-debug-optio.patch delete mode 100644 config/coreboot/default/patches/0035-ec-lenovo-h8-Add-CFR-objects-for-existing-options.patch create mode 100644 config/coreboot/default/patches/0035-src-intel-skylake-Disable-stack-overflow-debug-optio.patch delete mode 100644 config/coreboot/default/patches/0036-ec-lenovo-pmh7-Add-CFR-objects-for-existing-options.patch create mode 100644 config/coreboot/default/patches/0036-src-intel-x4x-Disable-stack-overflow-debug.patch create mode 100644 config/coreboot/default/patches/0037-Conditional-TBFW-setting-for-T480-T480S.patch delete mode 100644 config/coreboot/default/patches/0037-ec-lenovo-h8-Replace-chip-regs-for-BT-WWAN-detect-wi.patch create mode 100644 config/coreboot/default/patches/0038-do-not-break-building-other-thinkpads-with-the-hacks.patch delete mode 100644 config/coreboot/default/patches/0038-ec-lenovo-h8-Add-Kconfig-to-select-use-of-Thermal-Zo.patch delete mode 100644 config/coreboot/default/patches/0039-ec-lenovo-h8-Rework-invalid-temperature-reporting.patch create mode 100644 config/coreboot/default/patches/0039-hp-8300cmt-remove-xhci_overcurrent_mapping.patch delete mode 100644 config/coreboot/default/patches/0040-ec-lenovo-Add-support-for-MEC1653-EC.patch create mode 100644 config/coreboot/default/patches/0040-lenovo-t480-Drop-redundant-PcieRpEnable.patch delete mode 100644 config/coreboot/default/patches/0041-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch delete mode 100644 config/coreboot/default/patches/0042-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch delete mode 100644 config/coreboot/default/patches/0043-Conditional-TBFW-setting-for-T480-T480S.patch diff --git a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch index 60d8080d..d5a356e4 100644 --- a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch +++ b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch @@ -1,7 +1,7 @@ -From 7e5ec10bd8a3d95a1d2e12a66e79f180858806c3 Mon Sep 17 00:00:00 2001 +From 2a1f4af15aa785776498c17abd5d790e1507bd02 Mon Sep 17 00:00:00 2001 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> Date: Wed, 27 Oct 2021 13:36:01 +0200 -Subject: [PATCH 01/43] add c3 and clockgen to apple/macbook21 +Subject: [PATCH 01/41] add c3 and clockgen to apple/macbook21 --- src/mainboard/apple/macbook21/Kconfig | 1 + diff --git a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch index 3a62e972..95cf7cd9 100644 --- a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch +++ b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch @@ -1,7 +1,7 @@ -From ded01a8b8f88729c14ddda81c6aa3ceb027cf137 Mon Sep 17 00:00:00 2001 +From 089da6f216a8f6c9deec3e6c8d9feb5bf2ff907b Mon Sep 17 00:00:00 2001 From: persmule Date: Sun, 31 Oct 2021 23:33:26 +0000 -Subject: [PATCH 02/43] lenovo/t400: Enable all SATA ports +Subject: [PATCH 02/41] lenovo/t400: Enable all SATA ports There are 2 SATA ports on the chassis of t400(s), but at least one dock for t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its diff --git a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch index ff89ae4a..98bd1ebe 100644 --- a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch +++ b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -1,7 +1,7 @@ -From 2d0fa52a3fccb6e178726db2ae2d0d19cb14f92a Mon Sep 17 00:00:00 2001 +From ce328f1fa7e7cd90f31728eb1c1215bcb062acd6 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 3 Jan 2022 19:06:22 +0000 -Subject: [PATCH 03/43] lenovo/x230: set me_state=Disabled in cmos.default +Subject: [PATCH 03/41] lenovo/x230: set me_state=Disabled in cmos.default I only recently found out about this. It's possible to use me_cleaner to do the same thing, but some people might just flash coreboot and not do diff --git a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch index 5997b08a..4595d767 100644 --- a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch +++ b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -1,7 +1,7 @@ -From cb0364d9f5814e8bbc853e250eb541b7b040bb08 Mon Sep 17 00:00:00 2001 +From a7aaa58404cb19e6d89a9c9c5a137f9629d6e140 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 2 Mar 2022 21:50:01 +0000 -Subject: [PATCH 04/43] set me_state=Disabled on all cmos.default files! +Subject: [PATCH 04/41] set me_state=Disabled on all cmos.default files! yeah. why the hell isn't this the default diff --git a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch index 75c947a5..5c193b84 100644 --- a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -1,7 +1,7 @@ -From 9a1c993ce23a0c08ed660293143607a8343729b2 Mon Sep 17 00:00:00 2001 +From 5a226a91554c70c1c5d56a3184abdea48ea43fbb Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 05/43] util/ifdtool: add --nuke flag (all 0xFF on region) +Subject: [PATCH 05/41] util/ifdtool: add --nuke flag (all 0xFF on region) When this option is used, the region's contents are overwritten with all ones (0xFF). diff --git a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch index 9c085c55..0929787d 100644 --- a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -1,7 +1,7 @@ -From bc9eb4f1d9e39f87498e08880606731775991a4a Mon Sep 17 00:00:00 2001 +From 0994cde09852b152039f478937875ada3b3933d8 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 06/43] mb/dell/e6400: Enable 01.0 device in devicetree for +Subject: [PATCH 06/41] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU models Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed diff --git a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch index b121ddd2..8e38a793 100644 --- a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,7 +1,7 @@ -From 9707d3d8c7e55e2244663983e97b79368565e007 Mon Sep 17 00:00:00 2001 +From b8f173c3ef36873314d4718cf8a8cbe472c0a62b Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 07/43] Remove warning for coreboot images built without a +Subject: [PATCH 07/41] Remove warning for coreboot images built without a payload I added this in upstream to prevent people from accidentally flashing diff --git a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch index aa29df40..7a66ec5c 100644 --- a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch +++ b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch @@ -1,7 +1,7 @@ -From 0fb47aa25ac0eca68991b16e31c106c48f29df23 Mon Sep 17 00:00:00 2001 +From f9ac80501381f464f20b0dfb8b921cfd32267728 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Thu, 22 Jun 2023 16:44:27 +0300 -Subject: [PATCH 08/43] HACK: Disable coreboot related BL31 features +Subject: [PATCH 08/41] HACK: Disable coreboot related BL31 features I don't know why, but removing this BL31 make argument lets gru-kevin power off properly when shut down from Linux. Needs investigation. diff --git a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch index 33bcaefc..2fbd7b3d 100644 --- a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch +++ b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch @@ -1,7 +1,7 @@ -From 7180330d306c3e66f1868ff38d6c8f34975ce833 Mon Sep 17 00:00:00 2001 +From 8833d84c55c8fc1c49cf320c1825e89984555900 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 5 Nov 2023 11:41:41 +0000 -Subject: [PATCH 09/43] dell/e6430: use ME Soft Temporary Disable +Subject: [PATCH 09/41] dell/e6430: use ME Soft Temporary Disable i overlooked this. it's set on other boards. diff --git a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch index d27aca56..dd8c94a4 100644 --- a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch +++ b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch @@ -1,7 +1,7 @@ -From c5ee5befc6ca5a7bbedfb7b5a594897d66d4fb83 Mon Sep 17 00:00:00 2001 +From 40b9ffdb09eb40581ae2ea91a653192a6b7507ba Mon Sep 17 00:00:00 2001 From: Riku Viitanen Date: Sat, 23 Dec 2023 19:02:10 +0200 -Subject: [PATCH 10/43] mb/hp: Add Compaq Elite 8300 CMT port +Subject: [PATCH 10/41] mb/hp: Add Compaq Elite 8300 CMT port Based on autoport and Z220 SuperIO code. diff --git a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch index 350122cd..41a5c4bb 100644 --- a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch +++ b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -1,7 +1,7 @@ -From 73dc0d08dc11f297681123f91754722dac35c293 Mon Sep 17 00:00:00 2001 +From 49c11dedc8c12c6868237109c49509729502cc45 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 2 Mar 2024 22:51:09 +0000 -Subject: [PATCH 11/43] nb/intel/haswell: make IOMMU a runtime option +Subject: [PATCH 11/41] nb/intel/haswell: make IOMMU a runtime option When I tested graphics cards on a coreboot port for Dell OptiPlex 9020 SFF, I could not use a graphics card unless diff --git a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch index a79e3068..3ebe0c7a 100644 --- a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch +++ b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -1,7 +1,7 @@ -From ceb1fbaadad7c6c814a5e95424c6def7fb8cad40 Mon Sep 17 00:00:00 2001 +From 49f11a79d59856b9dc2f81c436933ef22077adc6 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 2 Mar 2024 23:00:09 +0000 -Subject: [PATCH 12/43] dell/optiplex_9020: Disable IOMMU by default +Subject: [PATCH 12/41] dell/optiplex_9020: Disable IOMMU by default Needed to make graphics cards work. Turning it on is recommended if only using iGPU, otherwise leave it off diff --git a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch index 92172b25..e28e65c5 100644 --- a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch +++ b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -1,7 +1,7 @@ -From ba62bbca682e187487eea1709a80dd7f34007bbc Mon Sep 17 00:00:00 2001 +From bf2779aa7dc40c8b671d231ca041c3532381b723 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 6 Apr 2024 01:22:47 +0100 -Subject: [PATCH 13/43] nb/haswell: Fully disable iGPU when dGPU is used +Subject: [PATCH 13/41] nb/haswell: Fully disable iGPU when dGPU is used My earlier patch disabled decode *and* disabled the iGPU itself, but a subsequent revision disabled only VGA decode. Upon revisiting, I diff --git a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch index 65e7b0cd..fb00d0b5 100644 --- a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch +++ b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch @@ -1,7 +1,7 @@ -From 892b36c5f5a2004dafcd1af5662eb7f7062ee7b7 Mon Sep 17 00:00:00 2001 +From 44ad334748c8c979a42ece4d3425879d3eb9a2b7 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Fri, 3 May 2024 11:03:32 -0600 -Subject: [PATCH 14/43] ec/dell/mec5035: Add S3 suspend SMI handler +Subject: [PATCH 14/41] ec/dell/mec5035: Add S3 suspend SMI handler This is necessary for S3 resume to work on SNB and newer Dell Latitude laptops. If a command isn't sent, the EC cuts power to the DIMMs, diff --git a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch index 95e0360d..6f1792be 100644 --- a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch +++ b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch @@ -1,7 +1,7 @@ -From 1739b9892390ffda230b1ac8b88aa3e8e7b1527b Mon Sep 17 00:00:00 2001 +From c9b30b3c93acc42b3c4de4f782dd47d519f81a8d Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 4 May 2024 02:00:53 +0100 -Subject: [PATCH 15/43] nb/haswell: lock policy regs when disabling IOMMU +Subject: [PATCH 15/41] nb/haswell: lock policy regs when disabling IOMMU Angel Pons told me I should do it. See comments here: https://review.coreboot.org/c/coreboot/+/81016 diff --git a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch index c9c9a450..8b75181f 100644 --- a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch +++ b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch @@ -1,7 +1,7 @@ -From 2b0d5d00a405d96c59d525305673b18b98ea7e58 Mon Sep 17 00:00:00 2001 +From dc5084cfa9526d5ba4a450b4d30f7463d857ba5f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 10 May 2021 22:40:59 +0200 -Subject: [PATCH 16/43] nb/intel/gm45: Make DDR2 raminit work +Subject: [PATCH 16/41] nb/intel/gm45: Make DDR2 raminit work List of changes: - Update some timing and ODT values diff --git a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch index e745e5eb..61aa4bff 100644 --- a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch +++ b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch @@ -1,7 +1,7 @@ -From 4436acb74d92034f7b6ce73bf7cf2cc542cd4d49 Mon Sep 17 00:00:00 2001 +From 1afeaab1f511e0fac478560d8da2d378858e2ac9 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Tue, 6 Aug 2024 00:50:24 +0100 -Subject: [PATCH 17/43] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards +Subject: [PATCH 17/41] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards We add this patch: diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch index a03a4b19..863ae505 100644 --- a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch +++ b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch @@ -1,7 +1,7 @@ -From e3d766b05a58ba8db0f19d5a6f124e5a18373562 Mon Sep 17 00:00:00 2001 +From 12d29915dcd43053b7e3a17e778db3627fbbadfb Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Mon, 20 May 2024 10:24:16 -0600 -Subject: [PATCH 18/43] mb/dell/e6400: Use 100 MHz reference clock for display +Subject: [PATCH 18/41] mb/dell/e6400: Use 100 MHz reference clock for display The E6400 uses a 100 MHz reference clock for spread spectrum support on LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For diff --git a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch index e6e8ed8d..b75f269c 100644 --- a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch +++ b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch @@ -1,7 +1,7 @@ -From e046f1f9bc7bae66262ea36178a123c8bf2a7387 Mon Sep 17 00:00:00 2001 +From 25af68c921f62046ea6e939cbe9c7c7936497e96 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 12 Aug 2024 02:15:24 +0100 -Subject: [PATCH 19/43] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ +Subject: [PATCH 19/41] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ set it to 96MHz. fixes the following build error when building for x4x boards e.g. gigabyte ga-g41m-es2l: diff --git a/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch b/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch index 71d60c71..6f45ba44 100644 --- a/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch +++ b/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch @@ -1,7 +1,7 @@ -From 4554a398dab2f1b5e04153103e34378f4ee2f172 Mon Sep 17 00:00:00 2001 +From 6421e20fe009e981d6bc28cfd79e79ae2097c80d Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Thu, 26 Sep 2024 19:48:26 -0600 -Subject: [PATCH 20/43] mb/dell: Convert E6400 into a variant +Subject: [PATCH 20/41] mb/dell: Convert E6400 into a variant All the GM45 Dell Latitudes should be nearly identical, so convert the E6400 port into a variant so that future ports for the other systems can diff --git a/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch index 6ffa1c0d..557c00f6 100644 --- a/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch +++ b/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch @@ -1,7 +1,7 @@ -From 6fc8dd1d0d4fc369bd98b9305f81f7f1362dad58 Mon Sep 17 00:00:00 2001 +From 0b5aa25828b0f91a5345c12dfabdc9a0f9b3765b Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Thu, 26 Sep 2024 19:51:25 -0600 -Subject: [PATCH 21/43] mb/dell/gm45_latitudes: Add E4300 variant +Subject: [PATCH 21/41] mb/dell/gm45_latitudes: Add E4300 variant Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2 Signed-off-by: Nicholas Chin diff --git a/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch index 976abf36..16544078 100644 --- a/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch +++ b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch @@ -1,7 +1,7 @@ -From 9f38902761ca84c873d5f141c318e26c51a482ec Mon Sep 17 00:00:00 2001 +From 2f07e367c9c5488722619a6a2efd5aa2fb634a05 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Fri, 3 May 2024 16:31:12 -0600 -Subject: [PATCH 22/43] mb/dell: Add S3 SMI handler for Dell Latitudes +Subject: [PATCH 22/41] mb/dell: Add S3 SMI handler for Dell Latitudes Integrate the previously added mec5035_smi_sleep() function into mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240. diff --git a/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch b/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch index f8a1883e..d4d3444a 100644 --- a/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch +++ b/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch @@ -1,7 +1,7 @@ -From 5fc350208fff941734d267d9521c54b7f76cf081 Mon Sep 17 00:00:00 2001 +From ed8e485c5f719fbd0da34d2e883d002945134796 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Tue, 18 Jun 2024 21:31:08 -0600 -Subject: [PATCH 23/43] ec/dell/mec5035: Route power button event to host +Subject: [PATCH 23/41] ec/dell/mec5035: Route power button event to host If command 0x3e with an argument of 1 isn't sent to the EC, pressing the power button results in the EC powering off the system without letting diff --git a/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch index 5be3b97f..00de7f73 100644 --- a/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch +++ b/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch @@ -1,7 +1,7 @@ -From d7c6ec6e2d336f2e5e489bbfb306f858bcf0d46b Mon Sep 17 00:00:00 2001 +From 5d056590dd6f3899422546a16a59bec6402b96f6 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Tue, 31 Dec 2024 14:42:24 +0000 -Subject: [PATCH 24/43] Disable compression on refcode insertion +Subject: [PATCH 24/41] Disable compression on refcode insertion Compression is not reliably reproducible. In an lbmk release context, this means we cannot rely on vendorfile insertion. diff --git a/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch index 2fcf761a..935ad553 100644 --- a/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch +++ b/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch @@ -1,7 +1,7 @@ -From 5ac7b49b8fcb0ba21af96c72ab8827f2bef9d392 Mon Sep 17 00:00:00 2001 +From 0b4bce08857e886b15277099cb1a53fe31ddfece Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 21 Apr 2025 02:58:47 +0100 -Subject: [PATCH 25/43] nb/intel/*: Disable stack overflow debug options +Subject: [PATCH 25/41] nb/intel/*: Disable stack overflow debug options Signed-off-by: Leah Rowe --- diff --git a/config/coreboot/default/patches/0026-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0026-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch deleted file mode 100644 index 92b5532c..00000000 --- a/config/coreboot/default/patches/0026-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch +++ /dev/null @@ -1,708 +0,0 @@ -From 4442c2a69e01c7cf7deececa3ccf2edb06c31b82 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Mon, 30 Sep 2024 20:44:38 -0400 -Subject: [PATCH 26/43] mb/dell: Add Optiplex 780 MT (x4x/ICH10) - -Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/optiplex_780/Kconfig | 40 ++++ - src/mainboard/dell/optiplex_780/Kconfig.name | 4 + - src/mainboard/dell/optiplex_780/Makefile.mk | 10 + - src/mainboard/dell/optiplex_780/acpi/ec.asl | 5 + - .../dell/optiplex_780/acpi/ich10_pci_irqs.asl | 32 ++++ - .../dell/optiplex_780/acpi/superio.asl | 18 ++ - .../dell/optiplex_780/board_info.txt | 6 + - src/mainboard/dell/optiplex_780/cmos.default | 8 + - src/mainboard/dell/optiplex_780/cmos.layout | 72 ++++++++ - src/mainboard/dell/optiplex_780/cstates.c | 8 + - src/mainboard/dell/optiplex_780/devicetree.cb | 63 +++++++ - src/mainboard/dell/optiplex_780/dsdt.asl | 26 +++ - .../dell/optiplex_780/gma-mainboard.ads | 16 ++ - .../optiplex_780/variants/780_mt/data.vbt | Bin 0 -> 1917 bytes - .../optiplex_780/variants/780_mt/early_init.c | 12 ++ - .../dell/optiplex_780/variants/780_mt/gpio.c | 174 ++++++++++++++++++ - .../optiplex_780/variants/780_mt/hda_verb.c | 26 +++ - .../variants/780_mt/overridetree.cb | 10 + - 18 files changed, 530 insertions(+) - create mode 100644 src/mainboard/dell/optiplex_780/Kconfig - create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name - create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk - create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl - create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl - create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl - create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt - create mode 100644 src/mainboard/dell/optiplex_780/cmos.default - create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout - create mode 100644 src/mainboard/dell/optiplex_780/cstates.c - create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb - create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl - create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb - -diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig -new file mode 100644 -index 0000000000..2d06c75c9a ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/Kconfig -@@ -0,0 +1,40 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_DELL_OPTIPLEX_780_COMMON -+ def_bool n -+ select BOARD_ROMSIZE_KB_8192 -+ select CPU_INTEL_SOCKET_LGA775 -+ select DRIVERS_I2C_CK505 -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ select INTEL_GMA_HAVE_VBT -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_USES_IFD_GBE_REGION -+ select NORTHBRIDGE_INTEL_X4X -+ select PCIEXP_ASPM -+ select PCIEXP_CLK_PM -+ select SOUTHBRIDGE_INTEL_I82801JX -+ -+config BOARD_DELL_OPTIPLEX_780_MT -+ select BOARD_DELL_OPTIPLEX_780_COMMON -+ -+if BOARD_DELL_OPTIPLEX_780_COMMON -+ -+config VGA_BIOS_ID -+ default "8086,2e22" -+ -+config MAINBOARD_DIR -+ default "dell/optiplex_780" -+ -+config MAINBOARD_PART_NUMBER -+ default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT -+ -+config OVERRIDE_DEVICETREE -+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -+ -+config VARIANT_DIR -+ default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT -+ -+endif # BOARD_DELL_OPTIPLEX_780_COMMON -diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name -new file mode 100644 -index 0000000000..db7f2e8fe3 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/Kconfig.name -@@ -0,0 +1,4 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_DELL_OPTIPLEX_780_MT -+ bool "OptiPlex 780 MT" -diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk -new file mode 100644 -index 0000000000..d462995d75 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/Makefile.mk -@@ -0,0 +1,10 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+ramstage-y += cstates.c -+romstage-y += variants/$(VARIANT_DIR)/gpio.c -+ -+bootblock-y += variants/$(VARIANT_DIR)/early_init.c -+romstage-y += variants/$(VARIANT_DIR)/early_init.c -+ -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c -diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl -new file mode 100644 -index 0000000000..479296cb76 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl -@@ -0,0 +1,5 @@ -+/* SPDX-License-Identifier: CC-PDDC */ -+ -+/* Please update the license if adding licensable material. */ -+ -+/* dummy */ -diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl -new file mode 100644 -index 0000000000..b7588dcc41 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl -@@ -0,0 +1,32 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+/* This is board specific information: -+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 -+ */ -+ -+If (PICM) { -+ Return (Package() { -+ /* PCI slot */ -+ Package() { 0x0001ffff, 0, 0, 0x14}, -+ Package() { 0x0001ffff, 1, 0, 0x15}, -+ Package() { 0x0001ffff, 2, 0, 0x16}, -+ Package() { 0x0001ffff, 3, 0, 0x17}, -+ -+ Package() { 0x0002ffff, 0, 0, 0x15}, -+ Package() { 0x0002ffff, 1, 0, 0x16}, -+ Package() { 0x0002ffff, 2, 0, 0x17}, -+ Package() { 0x0002ffff, 3, 0, 0x14}, -+ }) -+} Else { -+ Return (Package() { -+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, -+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, -+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, -+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, -+ -+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, -+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, -+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, -+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, -+ }) -+} -diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl -new file mode 100644 -index 0000000000..9f3900b86c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl -@@ -0,0 +1,18 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#undef SUPERIO_DEV -+#undef SUPERIO_PNP_BASE -+#undef IT8720F_SHOW_SP1 -+#undef IT8720F_SHOW_SP2 -+#undef IT8720F_SHOW_EC -+#undef IT8720F_SHOW_KBCK -+#undef IT8720F_SHOW_KBCM -+#undef IT8720F_SHOW_GPIO -+#undef IT8720F_SHOW_CIR -+#define SUPERIO_DEV SIO0 -+#define SUPERIO_PNP_BASE 0x2e -+#define IT8720F_SHOW_EC 1 -+#define IT8720F_SHOW_KBCK 1 -+#define IT8720F_SHOW_KBCM 1 -+#define IT8720F_SHOW_GPIO 1 -+#include -diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt -new file mode 100644 -index 0000000000..aaf657b583 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/board_info.txt -@@ -0,0 +1,6 @@ -+Category: desktop -+Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1 -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default -new file mode 100644 -index 0000000000..23f0e55f3e ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/cmos.default -@@ -0,0 +1,8 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -+nmi=Enable -+sata_mode=AHCI -+gfx_uma_size=64M -diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout -new file mode 100644 -index 0000000000..9f5012adb4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/cmos.layout -@@ -0,0 +1,72 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+# coreboot config options: southbridge -+408 1 e 10 sata_mode -+409 2 e 7 power_on_after_fail -+411 1 e 1 nmi -+ -+# coreboot config options: cpu -+ -+# coreboot config options: northbridge -+432 4 e 11 gfx_uma_size -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+2 0 Enable -+2 1 Disable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+10 0 AHCI -+10 1 Compatible -+11 1 4M -+11 2 8M -+11 3 16M -+11 4 32M -+11 5 48M -+11 6 64M -+11 7 128M -+11 8 256M -+11 9 96M -+11 10 160M -+11 11 224M -+11 12 352M -+ -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 983 984 -diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c -new file mode 100644 -index 0000000000..4adf0edc63 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/cstates.c -@@ -0,0 +1,8 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+int get_cst_entries(const acpi_cstate_t **entries) -+{ -+ return 0; -+} -diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb -new file mode 100644 -index 0000000000..95e3bd517c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/devicetree.cb -@@ -0,0 +1,63 @@ -+# SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/x4x -+ device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster -+ device domain 0 on -+ ops x4x_pci_domain_ops # PCI domain -+ subsystemid 0x8086 0x0028 inherit -+ device pci 0.0 on end # Host Bridge -+ device pci 1.0 on end # PCIe x16 2.0 slot -+ device pci 2.0 on end # Integrated graphics controller -+ device pci 2.1 on end # Integrated graphics controller 2 -+ device pci 3.0 off end # ME -+ device pci 3.1 off end # ME -+ chip southbridge/intel/i82801jx # ICH10 -+ register "gpe0_en" = "0x40" -+ -+ # Set AHCI mode. -+ register "sata_port_map" = "0x3f" -+ register "sata_clock_request" = "1" -+ -+ # Enable PCIe ports 0,1 as slots. -+ register "pcie_slot_implemented" = "0x3" -+ -+ device pci 19.0 on end # GBE -+ device pci 1a.0 on end # USB -+ device pci 1a.1 on end # USB -+ device pci 1a.2 on end # USB -+ device pci 1a.7 on end # USB -+ device pci 1b.0 on end # Audio -+ device pci 1c.0 off end # PCIe 1 -+ device pci 1c.1 off end # PCIe 2 -+ device pci 1c.2 off end # PCIe 3 -+ device pci 1c.3 off end # PCIe 4 -+ device pci 1c.4 off end # PCIe 5 -+ device pci 1c.5 off end # PCIe 6 -+ device pci 1d.0 on end # USB -+ device pci 1d.1 on end # USB -+ device pci 1d.2 on end # USB -+ device pci 1d.7 on end # USB -+ device pci 1e.0 on end # PCI bridge -+ device pci 1f.0 on end # LPC bridge -+ device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5) -+ device pci 1f.3 on # SMBus -+ chip drivers/i2c/ck505 # IDT CV194 -+ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff, 0xff, -+ 0xff, 0xff, 0xff }" -+ register "regs" = "{ 0x15, 0x82, 0xff, 0xff, -+ 0xff, 0x00, 0x00, 0x95, -+ 0x00, 0x65, 0x7d, 0x56, -+ 0x13, 0xc0, 0x00, 0x07, -+ 0x01, 0x0a, 0x64 }" -+ device i2c 69 on end -+ end -+ end -+ device pci 1f.4 off end -+ device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode) -+ device pci 1f.6 off end # Thermal Subsystem -+ end -+ end -+end -diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl -new file mode 100644 -index 0000000000..9ad70469de ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/dsdt.asl -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20090811 // OEM revision -+) -+{ -+ #include -+ -+ OSYS = 2002 -+ // global NVS and variables -+ #include -+ -+ Device (\_SB.PCI0) -+ { -+ #include -+ #include -+ } -+ -+ #include -+} -diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads -new file mode 100644 -index 0000000000..bc81cf4a40 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads -@@ -0,0 +1,16 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ (DP2, -+ Analog, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..fefda9d6f226b88ab67c5b044de30a707df22fbf -GIT binary patch -literal 1917 -zcmd6nO>7%Q6vzLwGv0Mv$FUpJ*ik4iQd_wnX*X`M0y3~p?8a$~>ZXxZMU`4dc9RGb -zTXq_i1Bwd~aNr{c4i)r(goF^M-nek+sY0sMa}Sk>xFFy_FTEfX^Y+7unt+OgkeJbX -zznS;`v-5V=o{ZwwmnN>gY?}>{`7^JBpP$l`EBIwbi0*k&aU)n@v)E -znI_A1T57efS5MGNN5_ut -zt=x`G)EjR#mlhURC^2!A3p33TcBg4-d8JyTiF&hfk}|a#&Dfe2%~V^}=4!QavNzBh -z0Pae^5`gfb?7Q)c(LsP)8 -zQy)2gwgG1S^>aw&0D}Z+-SCcJJF;s)yXJeQ|4N{SU?$I`#$HZa9dWBuxA$6X;VK;%W?Y>I;0P`|*vwAK$S(VB2JSq6g4n -z>oEf8XCt;_Y-iYBWz#3T9EmJ -z2x?*GPeN%?=Fj3+fv~4%I(nv~XF7VOqi5RsAt%13JtW>q=<<;0IkLPSUGL%_1h)2kjaZzuV;`43yCV;I=#Jcyyw@xKE8GGX39@am|0GKhH` -zawsKv^FvHqm+c8*FfFsu??w)Oed@;Mg~21%rCZ%d{x!>-zmv4AyWL1E -xfz+CGUnQ7Y^TD}&c_cQRYlBC+`?m?k6Nuw??s04gg4@4`<@FO{XEbO( -+ -+void mb_get_spd_map(u8 spd_map[4]) -+{ -+ // BTX form factor -+ spd_map[0] = 0x53; -+ spd_map[1] = 0x52; -+ spd_map[2] = 0x51; -+ spd_map[3] = 0x50; -+} -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c -new file mode 100644 -index 0000000000..9993f17c55 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c -@@ -0,0 +1,174 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_NATIVE, -+ .gpio1 = GPIO_MODE_NATIVE, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_GPIO, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_NATIVE, -+ .gpio8 = GPIO_MODE_NATIVE, -+ .gpio9 = GPIO_MODE_GPIO, -+ .gpio10 = GPIO_MODE_GPIO, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_NATIVE, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_NATIVE, -+ .gpio18 = GPIO_MODE_GPIO, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_GPIO, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_GPIO, -+ .gpio31 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio5 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio9 = GPIO_DIR_OUTPUT, -+ .gpio10 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio18 = GPIO_DIR_OUTPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio20 = GPIO_DIR_OUTPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_OUTPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+ .gpio30 = GPIO_DIR_INPUT, -+ .gpio31 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio9 = GPIO_LEVEL_HIGH, -+ .gpio18 = GPIO_LEVEL_HIGH, -+ .gpio20 = GPIO_LEVEL_HIGH, -+ .gpio28 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio13 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_GPIO, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_NATIVE, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_NATIVE, -+ .gpio52 = GPIO_MODE_NATIVE, -+ .gpio53 = GPIO_MODE_NATIVE, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_GPIO, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio32 = GPIO_DIR_INPUT, -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_INPUT, -+ .gpio35 = GPIO_DIR_OUTPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_OUTPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio56 = GPIO_DIR_OUTPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio35 = GPIO_LEVEL_LOW, -+ .gpio49 = GPIO_LEVEL_HIGH, -+ .gpio56 = GPIO_LEVEL_HIGH, -+ .gpio60 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio64 = GPIO_MODE_NATIVE, -+ .gpio65 = GPIO_MODE_NATIVE, -+ .gpio66 = GPIO_MODE_NATIVE, -+ .gpio67 = GPIO_MODE_NATIVE, -+ .gpio68 = GPIO_MODE_NATIVE, -+ .gpio69 = GPIO_MODE_NATIVE, -+ .gpio70 = GPIO_MODE_NATIVE, -+ .gpio71 = GPIO_MODE_NATIVE, -+ .gpio72 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio72 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ }, -+}; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c -new file mode 100644 -index 0000000000..4158bcf899 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ /* coreboot specific header */ -+ 0x11d4194a, /* Analog Devices AD1984A */ -+ 0xbfd40000, /* Subsystem ID */ -+ 10, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ AZALIA_PIN_CFG(0, 0x11, 0x032140f0), -+ AZALIA_PIN_CFG(0, 0x12, 0x21214010), -+ AZALIA_PIN_CFG(0, 0x13, 0x901701f0), -+ AZALIA_PIN_CFG(0, 0x14, 0x03a190f0), -+ AZALIA_PIN_CFG(0, 0x15, 0xb7a70121), -+ AZALIA_PIN_CFG(0, 0x16, 0x9933012e), -+ AZALIA_PIN_CFG(0, 0x17, 0x97a601f0), -+ AZALIA_PIN_CFG(0, 0x1a, 0x90f301f0), -+ AZALIA_PIN_CFG(0, 0x1b, 0x014510f0), -+ AZALIA_PIN_CFG(0, 0x1c, 0x21a19020), -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb -new file mode 100644 -index 0000000000..555b1c1f5c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb -@@ -0,0 +1,10 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/x4x -+ device domain 0 on -+ chip southbridge/intel/i82801jx -+ device pci 1c.0 on end # PCIe 1 -+ device pci 1c.1 on end # PCIe 2 -+ end -+ end -+end --- -2.39.5 - diff --git a/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch b/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch new file mode 100644 index 00000000..d77fb756 --- /dev/null +++ b/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch @@ -0,0 +1,94 @@ +From 0287b792fced5752eef4e14d7bc95a21b318e64d Mon Sep 17 00:00:00 2001 +From: Felix Singer +Date: Wed, 26 Jun 2024 04:24:31 +0200 +Subject: [PATCH 26/41] soc/intel/skylake: configure usb acpi + +Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d +Signed-off-by: Felix Singer +--- + src/soc/intel/skylake/Kconfig | 1 + + src/soc/intel/skylake/chipset.cb | 56 +++++++++++++++++++++++++++++++- + 2 files changed, 56 insertions(+), 1 deletion(-) + +diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig +index 4ad33496b2..9191ed0ff8 100644 +--- a/src/soc/intel/skylake/Kconfig ++++ b/src/soc/intel/skylake/Kconfig +@@ -10,6 +10,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE + select CPU_INTEL_COMMON + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION ++ select DRIVERS_USB_ACPI + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 + select FSP_COMPRESS_FSP_S_LZ4 + select FSP_M_XIP +diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb +index 6538a1475b..dfb81d496e 100644 +--- a/src/soc/intel/skylake/chipset.cb ++++ b/src/soc/intel/skylake/chipset.cb +@@ -13,7 +13,61 @@ chip soc/intel/skylake + device pci 07.0 alias chap off end + device pci 08.0 alias gmm off end # Gaussian Mixture Model + device pci 13.0 alias ish off end # SensorHub +- device pci 14.0 alias south_xhci off ops usb_xhci_ops end ++ device pci 14.0 alias south_xhci off ops usb_xhci_ops ++ chip drivers/usb/acpi ++ register "type" = "UPC_TYPE_HUB" ++ device usb 0.0 alias xhci_root_hub off ++ chip drivers/usb/acpi ++ device usb 2.0 alias usb2_port1 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.1 alias usb2_port2 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.2 alias usb2_port3 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.3 alias usb2_port4 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.4 alias usb2_port5 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.5 alias usb2_port6 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.6 alias usb2_port7 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.7 alias usb2_port8 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.8 alias usb2_port9 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.9 alias usb2_port10 off end ++ end ++ chip drivers/usb/acpi ++ device usb 3.0 alias usb3_port1 off end ++ end ++ chip drivers/usb/acpi ++ device usb 3.1 alias usb3_port2 off end ++ end ++ chip drivers/usb/acpi ++ device usb 3.2 alias usb3_port3 off end ++ end ++ chip drivers/usb/acpi ++ device usb 3.3 alias usb3_port4 off end ++ end ++ chip drivers/usb/acpi ++ device usb 3.4 alias usb3_port5 off end ++ end ++ chip drivers/usb/acpi ++ device usb 3.5 alias usb3_port6 off end ++ end ++ end ++ end ++ end + device pci 14.1 alias south_xdci off ops usb_xdci_ops end + device pci 14.2 alias thermal off end + device pci 14.3 alias cio off end +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0027-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0027-mb-dell-optiplex_780-Add-USFF-variant.patch deleted file mode 100644 index 26946123..00000000 --- a/config/coreboot/default/patches/0027-mb-dell-optiplex_780-Add-USFF-variant.patch +++ /dev/null @@ -1,326 +0,0 @@ -From c5b90e39909fc88bec811ab8a24f79a7fce5c4af Mon Sep 17 00:00:00 2001 -From: Nicholas Chin -Date: Wed, 30 Oct 2024 20:55:25 -0600 -Subject: [PATCH 27/43] mb/dell/optiplex_780: Add USFF variant - -Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 -Signed-off-by: Nicholas Chin ---- - src/mainboard/dell/optiplex_780/Kconfig | 5 + - src/mainboard/dell/optiplex_780/Kconfig.name | 3 + - .../optiplex_780/variants/780_usff/data.vbt | Bin 0 -> 1917 bytes - .../variants/780_usff/early_init.c | 9 + - .../optiplex_780/variants/780_usff/gpio.c | 166 ++++++++++++++++++ - .../optiplex_780/variants/780_usff/hda_verb.c | 26 +++ - .../variants/780_usff/overridetree.cb | 10 ++ - 7 files changed, 219 insertions(+) - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c - create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb - -diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig -index 2d06c75c9a..fc649e35d5 100644 ---- a/src/mainboard/dell/optiplex_780/Kconfig -+++ b/src/mainboard/dell/optiplex_780/Kconfig -@@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON - config BOARD_DELL_OPTIPLEX_780_MT - select BOARD_DELL_OPTIPLEX_780_COMMON - -+config BOARD_DELL_OPTIPLEX_780_USFF -+ select BOARD_DELL_OPTIPLEX_780_COMMON -+ - if BOARD_DELL_OPTIPLEX_780_COMMON - - config VGA_BIOS_ID -@@ -30,11 +33,13 @@ config MAINBOARD_DIR - - config MAINBOARD_PART_NUMBER - default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT -+ default "OptiPlex 780 USFF" if BOARD_DELL_OPTIPLEX_780_USFF - - config OVERRIDE_DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" - - config VARIANT_DIR - default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT -+ default "780_usff" if BOARD_DELL_OPTIPLEX_780_USFF - - endif # BOARD_DELL_OPTIPLEX_780_COMMON -diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name -index db7f2e8fe3..bc84c82a79 100644 ---- a/src/mainboard/dell/optiplex_780/Kconfig.name -+++ b/src/mainboard/dell/optiplex_780/Kconfig.name -@@ -2,3 +2,6 @@ - - config BOARD_DELL_OPTIPLEX_780_MT - bool "OptiPlex 780 MT" -+ -+config BOARD_DELL_OPTIPLEX_780_USFF -+ bool "OptiPlex 780 USFF" -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..dbd764f285ed18f7ee9c54bc777560138bd9b5f7 -GIT binary patch -literal 1917 -zcmd6nO>7%Q6vzLwGv3{}j$^l`v7@w1q*9sEq+2(b3K>`@c5#TSx@iP+W+B10OwbsGtX=N(gc4jSGjKDkP+yIUo^nsel8$^ny^9H?td8Ra=EiCEn=G -z@6DV4?!2AdojnUv^Rirgvs$heXUkGs9S+{Jc2WPhP0buTak^BTFP@&N9-E$(UtuSX -zS{r`=b+EX|Ig`2a*^5oDdG>8jE-1BBxs`*jgrf_sj_fP;%L|PwURRcCFBMCroNRQv -zmp$2TUhc}qJMB(u#jDG@x6(N85thC4%Z=8hiN}lj&zb2~``u3C;?lCrPQOTnInFqB -zhvdwqWv?lxTb=fVEH;~RPHDPw&g*&|s$pU7!7x2mLBtAF!g>K`zPnkx!DpPHuk6{_zc*0qi7)Aet$T -z1ks@8hWS#+6cI5)j1oD86{5PX8Zu2(^OC6M`xo)V)Ow=U6P12c -z=U0uNC9T9v{)-|#h(mSX*hSA8)ZeocL7l4J&!{RSO{6~oTtyn535j!RQh#GA*wTF8 -zvasRbO~d!?*FbM3K`W?lHx=v*(jiARIhWyh4^io|;n?@1H>uqJy>0sjV-Dt)_=%bE -zgNO3D@uE5m+7aqi?Y8b+inye%Z=HUmgBtaZ3Lc%OLt+bo+)5BjVwT<{mxT`nde$vb -zV99s{>`r76L#Hr6XW6r|>HT47I`**Q#Vu0QW!^VP-9S{xXzpq_zS#9k-;aXz?b+S!Ne$Kkk6dq&Hj-x+kx1W-4#E&beDT*S)=&NoSE?<-w!G@~aW()0ZN4O&=Q+nZa)p%Vd$k-_$a= -T#w3FFBiyj -+ -+void mb_get_spd_map(u8 spd_map[4]) -+{ -+ spd_map[0] = 0x50; -+ spd_map[2] = 0x52; -+} -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c -new file mode 100644 -index 0000000000..389f4077d7 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c -@@ -0,0 +1,166 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+static const struct pch_gpio_set1 pch_gpio_set1_mode = { -+ .gpio0 = GPIO_MODE_NATIVE, -+ .gpio1 = GPIO_MODE_NATIVE, -+ .gpio2 = GPIO_MODE_GPIO, -+ .gpio3 = GPIO_MODE_GPIO, -+ .gpio4 = GPIO_MODE_GPIO, -+ .gpio5 = GPIO_MODE_GPIO, -+ .gpio6 = GPIO_MODE_GPIO, -+ .gpio7 = GPIO_MODE_NATIVE, -+ .gpio8 = GPIO_MODE_NATIVE, -+ .gpio9 = GPIO_MODE_GPIO, -+ .gpio10 = GPIO_MODE_GPIO, -+ .gpio11 = GPIO_MODE_NATIVE, -+ .gpio12 = GPIO_MODE_NATIVE, -+ .gpio13 = GPIO_MODE_GPIO, -+ .gpio14 = GPIO_MODE_GPIO, -+ .gpio15 = GPIO_MODE_NATIVE, -+ .gpio16 = GPIO_MODE_GPIO, -+ .gpio17 = GPIO_MODE_NATIVE, -+ .gpio18 = GPIO_MODE_GPIO, -+ .gpio19 = GPIO_MODE_GPIO, -+ .gpio20 = GPIO_MODE_GPIO, -+ .gpio21 = GPIO_MODE_GPIO, -+ .gpio22 = GPIO_MODE_GPIO, -+ .gpio23 = GPIO_MODE_NATIVE, -+ .gpio24 = GPIO_MODE_GPIO, -+ .gpio25 = GPIO_MODE_NATIVE, -+ .gpio26 = GPIO_MODE_NATIVE, -+ .gpio27 = GPIO_MODE_GPIO, -+ .gpio28 = GPIO_MODE_GPIO, -+ .gpio29 = GPIO_MODE_GPIO, -+ .gpio30 = GPIO_MODE_GPIO, -+ .gpio31 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_direction = { -+ .gpio2 = GPIO_DIR_INPUT, -+ .gpio3 = GPIO_DIR_INPUT, -+ .gpio4 = GPIO_DIR_INPUT, -+ .gpio5 = GPIO_DIR_INPUT, -+ .gpio6 = GPIO_DIR_INPUT, -+ .gpio9 = GPIO_DIR_OUTPUT, -+ .gpio10 = GPIO_DIR_INPUT, -+ .gpio13 = GPIO_DIR_INPUT, -+ .gpio14 = GPIO_DIR_INPUT, -+ .gpio16 = GPIO_DIR_INPUT, -+ .gpio18 = GPIO_DIR_OUTPUT, -+ .gpio19 = GPIO_DIR_INPUT, -+ .gpio20 = GPIO_DIR_OUTPUT, -+ .gpio21 = GPIO_DIR_INPUT, -+ .gpio22 = GPIO_DIR_INPUT, -+ .gpio24 = GPIO_DIR_INPUT, -+ .gpio27 = GPIO_DIR_INPUT, -+ .gpio28 = GPIO_DIR_OUTPUT, -+ .gpio29 = GPIO_DIR_INPUT, -+ .gpio30 = GPIO_DIR_INPUT, -+ .gpio31 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_level = { -+ .gpio9 = GPIO_LEVEL_HIGH, -+ .gpio18 = GPIO_LEVEL_HIGH, -+ .gpio20 = GPIO_LEVEL_HIGH, -+ .gpio28 = GPIO_LEVEL_HIGH, -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_blink = { -+}; -+ -+static const struct pch_gpio_set1 pch_gpio_set1_invert = { -+ .gpio13 = GPIO_INVERT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_mode = { -+ .gpio32 = GPIO_MODE_GPIO, -+ .gpio33 = GPIO_MODE_GPIO, -+ .gpio34 = GPIO_MODE_GPIO, -+ .gpio35 = GPIO_MODE_GPIO, -+ .gpio36 = GPIO_MODE_GPIO, -+ .gpio37 = GPIO_MODE_GPIO, -+ .gpio38 = GPIO_MODE_GPIO, -+ .gpio39 = GPIO_MODE_GPIO, -+ .gpio40 = GPIO_MODE_NATIVE, -+ .gpio41 = GPIO_MODE_NATIVE, -+ .gpio42 = GPIO_MODE_NATIVE, -+ .gpio43 = GPIO_MODE_NATIVE, -+ .gpio44 = GPIO_MODE_NATIVE, -+ .gpio45 = GPIO_MODE_NATIVE, -+ .gpio46 = GPIO_MODE_NATIVE, -+ .gpio47 = GPIO_MODE_NATIVE, -+ .gpio48 = GPIO_MODE_GPIO, -+ .gpio49 = GPIO_MODE_GPIO, -+ .gpio50 = GPIO_MODE_NATIVE, -+ .gpio51 = GPIO_MODE_NATIVE, -+ .gpio52 = GPIO_MODE_NATIVE, -+ .gpio53 = GPIO_MODE_NATIVE, -+ .gpio54 = GPIO_MODE_GPIO, -+ .gpio55 = GPIO_MODE_NATIVE, -+ .gpio56 = GPIO_MODE_GPIO, -+ .gpio57 = GPIO_MODE_GPIO, -+ .gpio58 = GPIO_MODE_NATIVE, -+ .gpio59 = GPIO_MODE_NATIVE, -+ .gpio60 = GPIO_MODE_GPIO, -+ .gpio61 = GPIO_MODE_NATIVE, -+ .gpio62 = GPIO_MODE_NATIVE, -+ .gpio63 = GPIO_MODE_NATIVE, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_direction = { -+ .gpio32 = GPIO_DIR_INPUT, -+ .gpio33 = GPIO_DIR_INPUT, -+ .gpio34 = GPIO_DIR_INPUT, -+ .gpio35 = GPIO_DIR_OUTPUT, -+ .gpio36 = GPIO_DIR_INPUT, -+ .gpio37 = GPIO_DIR_INPUT, -+ .gpio38 = GPIO_DIR_INPUT, -+ .gpio39 = GPIO_DIR_INPUT, -+ .gpio48 = GPIO_DIR_INPUT, -+ .gpio49 = GPIO_DIR_OUTPUT, -+ .gpio54 = GPIO_DIR_INPUT, -+ .gpio56 = GPIO_DIR_OUTPUT, -+ .gpio57 = GPIO_DIR_INPUT, -+ .gpio60 = GPIO_DIR_OUTPUT, -+}; -+ -+static const struct pch_gpio_set2 pch_gpio_set2_level = { -+ .gpio35 = GPIO_LEVEL_LOW, -+ .gpio49 = GPIO_LEVEL_HIGH, -+ .gpio56 = GPIO_LEVEL_HIGH, -+ .gpio60 = GPIO_LEVEL_LOW, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_mode = { -+ .gpio72 = GPIO_MODE_GPIO, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_direction = { -+ .gpio72 = GPIO_DIR_INPUT, -+}; -+ -+static const struct pch_gpio_set3 pch_gpio_set3_level = { -+}; -+ -+const struct pch_gpio_map mainboard_gpio_map = { -+ .set1 = { -+ .mode = &pch_gpio_set1_mode, -+ .direction = &pch_gpio_set1_direction, -+ .level = &pch_gpio_set1_level, -+ .blink = &pch_gpio_set1_blink, -+ .invert = &pch_gpio_set1_invert, -+ }, -+ .set2 = { -+ .mode = &pch_gpio_set2_mode, -+ .direction = &pch_gpio_set2_direction, -+ .level = &pch_gpio_set2_level, -+ }, -+ .set3 = { -+ .mode = &pch_gpio_set3_mode, -+ .direction = &pch_gpio_set3_direction, -+ .level = &pch_gpio_set3_level, -+ }, -+}; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c -new file mode 100644 -index 0000000000..c94e06b156 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ /* coreboot specific header */ -+ 0x11d4194a, /* Analog Devices AD1984A */ -+ 0x10280420, /* Subsystem ID */ -+ 10, /* Number of entries */ -+ -+ /* Pin Widget Verb Table */ -+ AZALIA_PIN_CFG(0, 0x11, 0x02214040), -+ AZALIA_PIN_CFG(0, 0x12, 0x01014010), -+ AZALIA_PIN_CFG(0, 0x13, 0x991301f0), -+ AZALIA_PIN_CFG(0, 0x14, 0x02a19020), -+ AZALIA_PIN_CFG(0, 0x15, 0x01813030), -+ AZALIA_PIN_CFG(0, 0x16, 0x413301f0), -+ AZALIA_PIN_CFG(0, 0x17, 0x41a601f0), -+ AZALIA_PIN_CFG(0, 0x1a, 0x41f301f0), -+ AZALIA_PIN_CFG(0, 0x1b, 0x414501f0), -+ AZALIA_PIN_CFG(0, 0x1c, 0x413301f0), -+}; -+ -+const u32 pc_beep_verbs[0] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb -new file mode 100644 -index 0000000000..555b1c1f5c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb -@@ -0,0 +1,10 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/x4x -+ device domain 0 on -+ chip southbridge/intel/i82801jx -+ device pci 1c.0 on end # PCIe 1 -+ device pci 1c.1 on end # PCIe 2 -+ end -+ end -+end --- -2.39.5 - diff --git a/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch b/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch new file mode 100644 index 00000000..e090016e --- /dev/null +++ b/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch @@ -0,0 +1,30 @@ +From 6b623421531a04d0d615889b0710dd82a800c0bd Mon Sep 17 00:00:00 2001 +From: Mate Kukri +Date: Fri, 22 Nov 2024 21:26:48 +0000 +Subject: [PATCH 27/41] soc/intel/skylake: Enable 4E/4F PNP I/O ports in + bootblock + +Change-Id: I57c9d8a9513a268e2ca6a0abd1306cd038598173 +Signed-off-by: Mate Kukri +--- + src/soc/intel/skylake/bootblock/pch.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c +index df00bb85a9..beaece960b 100644 +--- a/src/soc/intel/skylake/bootblock/pch.c ++++ b/src/soc/intel/skylake/bootblock/pch.c +@@ -100,8 +100,8 @@ static void soc_config_pwrmbase(void) + + void pch_early_iorange_init(void) + { +- uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | +- LPC_IOE_EC_62_66; ++ uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F | ++ LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66; + + const config_t *config = config_of_soc(); + +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch b/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch new file mode 100644 index 00000000..3b40298f --- /dev/null +++ b/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch @@ -0,0 +1,2232 @@ +From a2f4492e8680d96f328846e3eba85d5aebec8d09 Mon Sep 17 00:00:00 2001 +From: Mate Kukri +Date: Tue, 31 Dec 2024 22:49:15 +0000 +Subject: [PATCH 28/41] mb/lenovo: Add ThinkPad T480 and ThinkPad T480s + +These machine have BootGuard fused and requires deguard to +boot coreboot. + +Known issues: +- Alpine Ridge Thunderbolt 3 controller does not work +- Some Fn+F{1-12} keys aren't handled correctly +- Nvidia dGPU is finicky + - Needs option ROM + - Power enable code is buggy + - Nouveau only works on linux 6.8-6.9 +- Headphone jack isn't detected as plugged in despite correct verbs + +Thanks to Leah Rowe for helping with the T480s. + +Signed-off-by: Mate Kukri +Change-Id: I19d421412c771c1f242f6ff39453f824fa866163 +--- + src/device/pci_rom.c | 4 +- + src/ec/lenovo/h8/acpi/ec.asl | 2 +- + src/ec/lenovo/h8/bluetooth.c | 6 +- + src/ec/lenovo/h8/wwan.c | 6 +- + src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 57 +++++ + .../lenovo/sklkbl_thinkpad/Kconfig.name | 7 + + .../lenovo/sklkbl_thinkpad/Makefile.mk | 73 +++++++ + .../lenovo/sklkbl_thinkpad/acpi/ec.asl | 12 ++ + .../lenovo/sklkbl_thinkpad/acpi/superio.asl | 3 + + .../lenovo/sklkbl_thinkpad/bootblock.c | 60 ++++++ + .../lenovo/sklkbl_thinkpad/devicetree.cb | 71 ++++++ + src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl | 33 +++ + src/mainboard/lenovo/sklkbl_thinkpad/ec.c | 153 +++++++++++++ + src/mainboard/lenovo/sklkbl_thinkpad/ec.h | 99 +++++++++ + src/mainboard/lenovo/sklkbl_thinkpad/gpio.h | 8 + + .../lenovo/sklkbl_thinkpad/ramstage.c | 105 +++++++++ + .../sklkbl_thinkpad/variants/t480/data.vbt | Bin 0 -> 4106 bytes + .../variants/t480/gma-mainboard.ads | 19 ++ + .../sklkbl_thinkpad/variants/t480/gpio.c | 203 ++++++++++++++++++ + .../sklkbl_thinkpad/variants/t480/hda_verb.c | 90 ++++++++ + .../variants/t480/memory_init_params.c | 20 ++ + .../variants/t480/overridetree.cb | 103 +++++++++ + .../sklkbl_thinkpad/variants/t480s/data.vbt | Bin 0 -> 4106 bytes + .../variants/t480s/gma-mainboard.ads | 19 ++ + .../sklkbl_thinkpad/variants/t480s/gpio.c | 199 +++++++++++++++++ + .../sklkbl_thinkpad/variants/t480s/hda_verb.c | 90 ++++++++ + .../variants/t480s/memory_init_params.c | 44 ++++ + .../variants/t480s/overridetree.cb | 103 +++++++++ + .../variants/t480s/spd/spd_0.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_1.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_10.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_11.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_12.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_13.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_14.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_15.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_16.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_17.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_18.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_19.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_2.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_20.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_3.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_4.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_5.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_6.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_7.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_8.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_9.bin | Bin 0 -> 512 bytes + 49 files changed, 1583 insertions(+), 6 deletions(-) + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.h + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/gpio.h + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_12.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_13.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_20.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_3.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_9.bin + +diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c +index dc41ef14ce..bba98d9dea 100644 +--- a/src/device/pci_rom.c ++++ b/src/device/pci_rom.c +@@ -396,14 +396,16 @@ void pci_rom_ssdt(const struct device *device) + rom = cbrom; + } + ++#if 0 + const char *scope = acpi_device_path(device); + if (!scope) { + printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(device)); + return; + } ++#endif + + /* write _ROM method */ +- acpigen_write_scope(scope); ++ acpigen_write_scope("\\_SB.PCI0.RP01.PEGP"); + acpigen_write_rom((void *)rom, rom->size * 512); + acpigen_pop_len(); /* pop scope */ + } +diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl +index bc54d3b422..8f4a8e1986 100644 +--- a/src/ec/lenovo/h8/acpi/ec.asl ++++ b/src/ec/lenovo/h8/acpi/ec.asl +@@ -331,7 +331,7 @@ Device(EC) + #include "sleepbutton.asl" + #include "lid.asl" + #include "beep.asl" +-#include "thermal.asl" ++//#include "thermal.asl" + #include "systemstatus.asl" + #include "thinkpad.asl" + } +diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c +index 16fc8dce39..be71a24ced 100644 +--- a/src/ec/lenovo/h8/bluetooth.c ++++ b/src/ec/lenovo/h8/bluetooth.c +@@ -1,6 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + +-#include ++// #include + #include + #include + #include +@@ -28,16 +28,18 @@ bool h8_has_bdc(const struct device *dev) + { + struct ec_lenovo_h8_config *conf = dev->chip_info; + +- if (!conf->has_bdc_detection) { ++ if (1 || !conf->has_bdc_detection) { + printk(BIOS_INFO, "H8: BDC detection not implemented. " + "Assuming BDC installed\n"); + return true; + } + ++#if 0 + if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) { + printk(BIOS_INFO, "H8: BDC installed\n"); + return true; + } ++#endif + + printk(BIOS_INFO, "H8: BDC not installed\n"); + return false; +diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c +index 685886fcce..5cdcf77406 100644 +--- a/src/ec/lenovo/h8/wwan.c ++++ b/src/ec/lenovo/h8/wwan.c +@@ -1,6 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + +-#include ++// #include + #include + #include + #include +@@ -26,16 +26,18 @@ bool h8_has_wwan(const struct device *dev) + { + struct ec_lenovo_h8_config *conf = dev->chip_info; + +- if (!conf->has_wwan_detection) { ++ if (1 || !conf->has_wwan_detection) { + printk(BIOS_INFO, "H8: WWAN detection not implemented. " + "Assuming WWAN installed\n"); + return true; + } + ++#if 0 + if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) { + printk(BIOS_INFO, "H8: WWAN installed\n"); + return true; + } ++#endif + + printk(BIOS_INFO, "H8: WWAN not installed\n"); + return false; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +new file mode 100644 +index 0000000000..4998672943 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +@@ -0,0 +1,57 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON ++ bool ++ select BOARD_ROMSIZE_KB_16384 ++ select EC_LENOVO_H8 ++ select EC_LENOVO_PMH7 ++ select H8_HAS_BAT_THRESHOLDS_IMPL ++ select H8_HAS_LEDLOGO ++ select H8_HAS_PRIMARY_FN_KEYS ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select INTEL_GMA_HAVE_VBT ++ select INTEL_INT15 ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_HAS_TPM2 ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select MEMORY_MAPPED_TPM ++ select SOC_INTEL_COMMON_BLOCK_HDA_VERB ++ select SOC_INTEL_KABYLAKE ++ select SPD_READ_BY_WORD ++ select SYSTEM_TYPE_LAPTOP ++ ++config BOARD_LENOVO_T480 ++ bool ++ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON ++ ++config BOARD_LENOVO_T480S ++ bool ++ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON ++ ++if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON ++ ++config MAINBOARD_DIR ++ default "lenovo/sklkbl_thinkpad" ++ ++config VARIANT_DIR ++ default "t480" if BOARD_LENOVO_T480 ++ default "t480s" if BOARD_LENOVO_T480S ++ ++config OVERRIDE_DEVICETREE ++ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" ++ ++config MAINBOARD_PART_NUMBER ++ default "T480" if BOARD_LENOVO_T480 ++ default "T480s" if BOARD_LENOVO_T480S ++ ++config CBFS_SIZE ++ default 0x900000 ++ ++config DIMM_MAX ++ default 2 ++ ++config DIMM_SPD_SIZE ++ default 512 # DDR4 ++ ++endif +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name +new file mode 100644 +index 0000000000..abc273f387 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name +@@ -0,0 +1,7 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_LENOVO_T480 ++ bool "ThinkPad T480" ++ ++config BOARD_LENOVO_T480S ++ bool "ThinkPad T480s" +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk +new file mode 100644 +index 0000000000..c308239177 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk +@@ -0,0 +1,73 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++bootblock-y += bootblock.c ec.c ++ ++romstage-y += variants/$(VARIANT_DIR)/memory_init_params.c ++ ++ramstage-y += ramstage.c ec.c ++ramstage-y += variants/$(VARIANT_DIR)/gpio.c variants/$(VARIANT_DIR)/hda_verb.c ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads ++ ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_0.bin ++spd_0.bin-file := variants/$(VARIANT_DIR)/spd/spd_0.bin ++spd_0.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_1.bin ++spd_1.bin-file := variants/$(VARIANT_DIR)/spd/spd_1.bin ++spd_1.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_2.bin ++spd_2.bin-file := variants/$(VARIANT_DIR)/spd/spd_2.bin ++spd_2.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_3.bin ++spd_3.bin-file := variants/$(VARIANT_DIR)/spd/spd_3.bin ++spd_3.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_4.bin ++spd_4.bin-file := variants/$(VARIANT_DIR)/spd/spd_4.bin ++spd_4.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_5.bin ++spd_5.bin-file := variants/$(VARIANT_DIR)/spd/spd_5.bin ++spd_5.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_6.bin ++spd_6.bin-file := variants/$(VARIANT_DIR)/spd/spd_6.bin ++spd_6.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_7.bin ++spd_7.bin-file := variants/$(VARIANT_DIR)/spd/spd_7.bin ++spd_7.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_8.bin ++spd_8.bin-file := variants/$(VARIANT_DIR)/spd/spd_8.bin ++spd_8.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_9.bin ++spd_9.bin-file := variants/$(VARIANT_DIR)/spd/spd_9.bin ++spd_9.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_10.bin ++spd_10.bin-file := variants/$(VARIANT_DIR)/spd/spd_10.bin ++spd_10.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_11.bin ++spd_11.bin-file := variants/$(VARIANT_DIR)/spd/spd_11.bin ++spd_11.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_12.bin ++spd_12.bin-file := variants/$(VARIANT_DIR)/spd/spd_12.bin ++spd_12.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_13.bin ++spd_13.bin-file := variants/$(VARIANT_DIR)/spd/spd_13.bin ++spd_13.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_14.bin ++spd_14.bin-file := variants/$(VARIANT_DIR)/spd/spd_14.bin ++spd_14.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_15.bin ++spd_15.bin-file := variants/$(VARIANT_DIR)/spd/spd_15.bin ++spd_15.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_16.bin ++spd_16.bin-file := variants/$(VARIANT_DIR)/spd/spd_16.bin ++spd_16.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_17.bin ++spd_17.bin-file := variants/$(VARIANT_DIR)/spd/spd_17.bin ++spd_17.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_18.bin ++spd_18.bin-file := variants/$(VARIANT_DIR)/spd/spd_18.bin ++spd_18.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_19.bin ++spd_19.bin-file := variants/$(VARIANT_DIR)/spd/spd_19.bin ++spd_19.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_20.bin ++spd_20.bin-file := variants/$(VARIANT_DIR)/spd/spd_20.bin ++spd_20.bin-type := raw +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl +new file mode 100644 +index 0000000000..3a949a2fca +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl +@@ -0,0 +1,12 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB ++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB ++#define THINKPAD_EC_GPE 22 ++ ++Name(\TCRT, 100) ++Name(\TPSV, 90) ++Name(\FLVL, 0) ++ ++#include ++#include +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl +new file mode 100644 +index 0000000000..55b1db5b11 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c +new file mode 100644 +index 0000000000..fb660dbdfa +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c +@@ -0,0 +1,60 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include "ec.h" ++ ++static void configure_uart(uint16_t port, uint16_t iobase, uint8_t irqno) ++{ ++ microchip_pnp_enter_conf_state(port); ++ ++ // Select LPC I/F LDN ++ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF); ++ // Write UART BAR ++ pnp_write_le32(port, LPCIF_BAR_UART, (uint32_t) iobase << 16 | 0x8707); ++ // Set SIRQ4 to UART ++ pnp_write(port, LPCIF_SIRQ(irqno), LDN_UART); ++ ++ // Configure UART LDN ++ pnp_write(port, PNP_LDN_SELECT, LDN_UART); ++ pnp_write(port, UART_ACTIVATE, 0x01); ++ pnp_write(port, UART_CONFIG_SELECT, 0x00); ++ ++ microchip_pnp_exit_conf_state(port); ++ ++#ifdef CONFIG_BOARD_LENOVO_T480 ++ // Supply debug unlock key ++ debug_write_key(DEBUG_RW_KEY_IDX, debug_rw_key); ++ ++ // Use debug writes to set UART_TX and UART_RX GPIOs ++ debug_write_dword(0xf0c400 + 0x110, 0x00001000); ++ debug_write_dword(0xf0c400 + 0x114, 0x00001000); ++#endif ++} ++ ++ ++#define UART_PORT 0x3f8 ++#define UART_IRQ 4 ++ ++void bootblock_mainboard_early_init(void) ++{ ++ // Tell EC via BIOS Debug Port 1 that the world isn't on fire ++ ++ // Let the EC know that BIOS code is running ++ outb(0x11, 0x86); ++ outb(0x6e, 0x86); ++ ++ // Enable accesses to EC1 interface ++ ec0_write(0, ec0_read(0) | 0x20); ++ ++ // Reset LEDs to power on state ++ // (Without this warm reboot leaves LEDs off) ++ ec0_write(0x0c, 0x80); ++ ec0_write(0x0c, 0x07); ++ ec0_write(0x0c, 0x8a); ++ ++ // Setup debug UART ++ configure_uart(EC_CFG_PORT, UART_PORT, UART_IRQ); ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb +new file mode 100644 +index 0000000000..c07d4d53ca +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb +@@ -0,0 +1,71 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++chip soc/intel/skylake ++ # IGD Displays ++ register "gfx" = "GMA_STATIC_DISPLAYS(0)" ++ ++ register "panel_cfg" = "{ ++ .up_delay_ms = 200, ++ .down_delay_ms = 50, ++ .cycle_delay_ms = 600, ++ .backlight_on_delay_ms = 1, ++ .backlight_off_delay_ms = 200, ++ .backlight_pwm_hz = 200, ++ }" ++ ++ # Power ++ register "PmConfigSlpS3MinAssert" = "2" # 50ms ++ register "PmConfigSlpS4MinAssert" = "1" # 1s ++ register "PmConfigSlpSusMinAssert" = "3" # 500ms ++ register "PmConfigSlpAMinAssert" = "3" # 2s ++ ++ device domain 0 on ++ device ref igpu on end ++ device ref sa_thermal on end ++ device ref thermal on end ++ device ref south_xhci on end ++ device ref lpc_espi on ++ register "serirq_mode" = "SERIRQ_CONTINUOUS" ++ ++ register "gen1_dec" = "0x007c1601" ++ register "gen2_dec" = "0x000c15e1" ++ ++ chip ec/lenovo/pmh7 ++ register "backlight_enable" = "true" ++ register "dock_event_enable" = "true" ++ device pnp ff.1 on end # dummy ++ end ++ ++ chip ec/lenovo/h8 ++ register "beepmask0" = "0x00" ++ register "beepmask1" = "0x86" ++ register "config0" = "0xa6" ++ register "config1" = "0x0d" ++ register "config2" = "0xa8" ++ register "config3" = "0xc4" ++ register "has_keyboard_backlight" = "1" ++ register "event2_enable" = "0xff" ++ register "event3_enable" = "0xff" ++ register "event4_enable" = "0xd0" ++ register "event5_enable" = "0x3c" ++ register "event7_enable" = "0x01" ++ register "event8_enable" = "0x7b" ++ register "event9_enable" = "0xff" ++ register "eventc_enable" = "0xff" ++ register "eventd_enable" = "0xff" ++ register "evente_enable" = "0x9d" ++ device pnp ff.2 on # dummy ++ io 0x60 = 0x62 ++ io 0x62 = 0x66 ++ io 0x64 = 0x1600 ++ io 0x66 = 0x1604 ++ end ++ end ++ ++ chip drivers/pc80/tpm ++ device pnp 0c31.0 on end ++ end ++ end ++ device ref hda on end ++ end ++end +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl +new file mode 100644 +index 0000000000..aa4d4de2a6 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl +@@ -0,0 +1,33 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20110725 ++) ++{ ++ #include ++ #include ++ #include ++ ++ Device (\_SB.PCI0) ++ { ++ #include ++ #include ++ #include ++ } ++ ++ Scope (\_SB.PCI0.RP01) ++ { ++ Device (PEGP) ++ { ++ Name (_ADR, Zero) ++ } ++ } ++ ++ #include ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ec.c b/src/mainboard/lenovo/sklkbl_thinkpad/ec.c +new file mode 100644 +index 0000000000..adb6a60324 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/ec.c +@@ -0,0 +1,153 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include "ec.h" ++ ++#define MICROCHIP_CONFIGURATION_ENTRY_KEY 0x55 ++#define MICROCHIP_CONFIGURATION_EXIT_KEY 0xaa ++ ++void microchip_pnp_enter_conf_state(uint16_t port) ++{ ++ outb(MICROCHIP_CONFIGURATION_ENTRY_KEY, port); ++} ++ ++void microchip_pnp_exit_conf_state(uint16_t port) ++{ ++ outb(MICROCHIP_CONFIGURATION_EXIT_KEY, port); ++} ++ ++uint8_t pnp_read(uint16_t port, uint8_t index) ++{ ++ outb(index, port); ++ return inb(port + 1); ++} ++ ++uint32_t pnp_read_le32(uint16_t port, uint8_t index) ++{ ++ return (uint32_t) pnp_read(port, index) | ++ (uint32_t) pnp_read(port, index + 1) << 8 | ++ (uint32_t) pnp_read(port, index + 2) << 16 | ++ (uint32_t) pnp_read(port, index + 3) << 24; ++} ++ ++void pnp_write(uint16_t port, uint8_t index, uint8_t value) ++{ ++ outb(index, port); ++ outb(value, port + 1); ++} ++ ++void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value) ++{ ++ pnp_write(port, index, value & 0xff); ++ pnp_write(port, index + 1, value >> 8 & 0xff); ++ pnp_write(port, index + 2, value >> 16 & 0xff); ++ pnp_write(port, index + 3, value >> 24 & 0xff); ++} ++ ++static void ecN_clear_out_queue(uint16_t cmd_port, uint16_t data_port) ++{ ++ while (inb(cmd_port) & EC_OBF) ++ inb(data_port); ++} ++ ++static void ecN_wait_to_send(uint16_t cmd_port, uint16_t data_port) ++{ ++ while (inb(cmd_port) & EC_IBF) ++ ; ++} ++ ++static void ecN_wait_to_recv(uint16_t cmd_port, uint16_t data_port) ++{ ++ while (!(inb(cmd_port) & EC_OBF)) ++ ; ++} ++ ++uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr) ++{ ++ ecN_clear_out_queue(cmd_port, data_port); ++ ecN_wait_to_send(cmd_port, data_port); ++ outb(EC_READ, cmd_port); ++ ecN_wait_to_send(cmd_port, data_port); ++ outb(addr, data_port); ++ ecN_wait_to_recv(cmd_port, data_port); ++ return inb(data_port); ++} ++ ++void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val) ++{ ++ ecN_clear_out_queue(cmd_port, data_port); ++ ecN_wait_to_send(cmd_port, data_port); ++ outb(EC_WRITE, cmd_port); ++ ecN_wait_to_send(cmd_port, data_port); ++ outb(addr, data_port); ++ ecN_wait_to_send(cmd_port, data_port); ++ outb(val, data_port); ++} ++ ++uint8_t eeprom_read(uint16_t addr) ++{ ++ ecN_clear_out_queue(EC2_CMD, EC2_DATA); ++ ecN_wait_to_send(EC2_CMD, EC2_DATA); ++ outl(1, EC2_CMD); ++ ecN_wait_to_send(EC2_CMD, EC2_DATA); ++ outl(addr, EC2_DATA); ++ ecN_wait_to_recv(EC2_CMD, EC2_DATA); ++ return inl(EC2_DATA); ++} ++ ++void eeprom_write(uint16_t addr, uint8_t val) ++{ ++ ecN_clear_out_queue(EC2_CMD, EC2_DATA); ++ ecN_wait_to_send(EC2_CMD, EC2_DATA); ++ outl(2, EC2_CMD); ++ ecN_wait_to_send(EC2_CMD, EC2_DATA); ++ outl((uint32_t) addr | (uint32_t) val << 16, EC2_DATA); ++ ecN_wait_to_recv(EC2_CMD, EC2_DATA); ++ inl(EC2_DATA); ++} ++ ++uint16_t debug_loaded_keys(void) ++{ ++ return (uint16_t) ec0_read(0x87) << 8 | (uint16_t) ec0_read(0x86); ++} ++ ++static void debug_cmd(uint8_t cmd) ++{ ++ ec0_write(EC_DEBUG_CMD, cmd); ++ while (ec0_read(EC_DEBUG_CMD) & 0x80) ++ ; ++} ++ ++void debug_read_key(uint8_t i, uint8_t *key) ++{ ++ debug_cmd(0x80 | (i & 0xf)); ++ for (int j = 0; j < 8; ++j) ++ key[j] = ec0_read(0x3e + j); ++} ++ ++void debug_write_key(uint8_t i, const uint8_t *key) ++{ ++ for (int j = 0; j < 8; ++j) ++ ec0_write(0x3e + j, key[j]); ++ debug_cmd(0xc0 | (i & 0xf)); ++} ++ ++uint32_t debug_read_dword(uint32_t addr) ++{ ++ ecN_clear_out_queue(EC3_CMD, EC3_DATA); ++ ecN_wait_to_send(EC3_CMD, EC3_DATA); ++ outl(addr << 8 | 0xE2, EC3_DATA); ++ ecN_wait_to_recv(EC3_CMD, EC3_DATA); ++ return inl(EC3_DATA); ++} ++ ++void debug_write_dword(uint32_t addr, uint32_t val) ++{ ++ ecN_clear_out_queue(EC3_CMD, EC3_DATA); ++ ecN_wait_to_send(EC3_CMD, EC3_DATA); ++ outl(addr << 8 | 0xEA, EC3_DATA); ++ ecN_wait_to_send(EC3_CMD, EC3_DATA); ++ outl(val, EC3_DATA); ++} ++ ++const uint8_t debug_rw_key[8] = { 0x7a, 0x41, 0xb1, 0x49, 0xfe, 0x21, 0x01, 0xcf }; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ec.h b/src/mainboard/lenovo/sklkbl_thinkpad/ec.h +new file mode 100644 +index 0000000000..d2963c8962 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/ec.h +@@ -0,0 +1,99 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef SKLKBL_THINKPAD_EC_H ++#define SKLKBL_THINKPAD_EC_H ++ ++// EC configuration base address ++#define EC_CFG_PORT 0x4e ++ ++// Chip global registers ++#define PNP_LDN_SELECT 0x07 ++# define LDN_UART 0x07 ++# define LDN_LPCIF 0x0c ++#define EC_DEVICE_ID 0x20 ++#define EC_DEVICE_REV 0x21 ++ ++// LPC I/F registers ++#define LPCIF_SIRQ(i) (0x40 + (i)) ++ ++#define LPCIF_BAR_CFG 0x60 ++#define LPCIF_BAR_MAILBOX 0x64 ++#define LPCIF_BAR_8042 0x68 ++#define LPCIF_BAR_ACPI_EC0 0x6c ++#define LPCIF_BAR_ACPI_EC1 0x70 ++#define LPCIF_BAR_ACPI_EC2 0x74 ++#define LPCIF_BAR_ACPI_EC3 0x78 ++#define LPCIF_BAR_ACPI_PM0 0x7c ++#define LPCIF_BAR_UART 0x80 ++#define LPCIF_BAR_FAST_KYBD 0x84 ++#define LPCIF_BAR_EMBED_FLASH 0x88 ++#define LPCIF_BAR_GP_SPI 0x8c ++#define LPCIF_BAR_EMI 0x90 ++#define LPCIF_BAR_PMH7 0x94 ++#define LPCIF_BAR_PORT80_DBG0 0x98 ++#define LPCIF_BAR_PORT80_DBG1 0x9c ++#define LPCIF_BAR_RTC 0xa0 ++ ++// UART registers ++#define UART_ACTIVATE 0x30 ++#define UART_CONFIG_SELECT 0xf0 ++ ++void microchip_pnp_enter_conf_state(uint16_t port); ++void microchip_pnp_exit_conf_state(uint16_t port); ++uint8_t pnp_read(uint16_t port, uint8_t index); ++uint32_t pnp_read_le32(uint16_t port, uint8_t index); ++void pnp_write(uint16_t port, uint8_t index, uint8_t value); ++void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value); ++ ++#define EC0_CMD 0x0066 ++#define EC0_DATA 0x0062 ++#define EC1_CMD 0x1604 ++#define EC1_DATA 0x1600 ++#define EC2_CMD 0x1634 ++#define EC2_DATA 0x1630 ++#define EC3_CMD 0x161c ++#define EC3_DATA 0x1618 ++ ++#define EC_OBF (1 << 0) ++#define EC_IBF (1 << 1) ++ ++#define EC_READ 0x80 ++#define EC_WRITE 0x81 ++ ++uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr); ++ ++void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val); ++ ++// EC0 and EC1 mostly are useful with the READ/WRITE commands ++#define ec0_read(addr) ecN_read(EC0_CMD, EC0_DATA, addr) ++#define ec0_write(addr, val) ecN_write(EC0_CMD, EC0_DATA, addr, val) ++#define ec1_read(addr) ecN_read(EC1_CMD, EC1_DATA, addr) ++#define ec1_write(addr, val) ecN_write(EC1_CMD, EC1_DATA, addr, val) ++ ++// Read from the emulated EEPROM ++uint8_t eeprom_read(uint16_t addr); ++ ++// Write to the emulated EEPROM ++void eeprom_write(uint16_t addr, uint8_t val); ++ ++// Read loaded debug key mask ++uint16_t debug_loaded_keys(void); ++ ++// The following location (via either EC0 or EC1) can be used to interact with the debug interface ++#define EC_DEBUG_CMD 0x3d ++ ++void debug_read_key(uint8_t i, uint8_t *key); ++ ++void debug_write_key(uint8_t i, const uint8_t *key); ++ ++uint32_t debug_read_dword(uint32_t addr); ++ ++void debug_write_dword(uint32_t addr, uint32_t val); ++ ++// RW unlock key index ++#define DEBUG_RW_KEY_IDX 1 ++ ++// RW unlock key for EC version N24HT37W ++extern const uint8_t debug_rw_key[8]; ++ ++#endif +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h +new file mode 100644 +index 0000000000..d89ed712d4 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h +@@ -0,0 +1,8 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef GPIO_H ++#define GPIO_H ++ ++void variant_config_gpios(void); ++ ++#endif +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c +new file mode 100644 +index 0000000000..44c8578852 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c +@@ -0,0 +1,105 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "ec.h" ++#include "gpio.h" ++ ++#define GPIO_GPU_RST GPP_E22 // active low ++#define GPIO_1R8VIDEO_AON_ON GPP_E23 ++ ++#define GPIO_DGFX_PWRGD GPP_F3 ++ ++#define GPIO_DISCRETE_PRESENCE GPP_D9 // active low ++#define GPIO_DGFX_VRAM_ID0 GPP_D11 ++#define GPIO_DGFX_VRAM_ID1 GPP_D12 ++ ++void mainboard_silicon_init_params(FSP_SIL_UPD *params) ++{ ++ static const char * const dgfx_vram_id_str[] = { "1GB", "2GB", "4GB", "N/A" }; ++ ++ int dgfx_vram_id; ++ ++ // Setup GPIOs ++ variant_config_gpios(); ++ ++ // Detect and enable dGPU ++ if (gpio_get(GPIO_DISCRETE_PRESENCE) == 0) { // active low ++ dgfx_vram_id = gpio_get(GPIO_DGFX_VRAM_ID0) | gpio_get(GPIO_DGFX_VRAM_ID1) << 1; ++ printk(BIOS_DEBUG, "Discrete GPU present with %s VRAM\n", dgfx_vram_id_str[dgfx_vram_id]); ++ ++ // NOTE: i pulled this GPU enable sequence from thin air ++ // it sometimes works but is buggy and the GPU disappears in some cases so disabling it by default. ++ // also unrelated to this enable sequence the nouveau driver only works on 6.8-6.9 kernels ++ if (get_uint_option("dgpu_enable", 0)) { ++ printk(BIOS_DEBUG, "Enabling discrete GPU\n"); ++ gpio_set(GPIO_1R8VIDEO_AON_ON, 1); // Enable GPU power rail ++ while (!gpio_get(GPIO_DGFX_PWRGD)) // Wait for power good signal from GPU ++ ; ++ gpio_set(GPIO_GPU_RST, 1); // Release GPU from reset ++ } else { ++ printk(BIOS_DEBUG, "Discrete GPU will remain disabled\n"); ++ } ++ ++ } else { ++ printk(BIOS_DEBUG, "Discrete GPU not present\n"); ++ } ++} ++ ++static void dump_ec_cfg(uint16_t port) ++{ ++ microchip_pnp_enter_conf_state(port); ++ ++ // Device info ++ printk(BIOS_DEBUG, "Device id %02x\n", pnp_read(port, EC_DEVICE_ID)); ++ printk(BIOS_DEBUG, "Device rev %02x\n", pnp_read(port, EC_DEVICE_REV)); ++ ++ // Switch to LPCIF LDN ++ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF); ++ ++ // Dump SIRQs ++ for (int i = 0; i <= 15; i += 1) ++ printk(BIOS_DEBUG, "SIRQ%d = %02x\n", i, pnp_read(port, LPCIF_SIRQ(i))); ++ ++ // Dump BARs ++ printk(BIOS_DEBUG, "BAR CFG = %08x\n", pnp_read_le32(port, LPCIF_BAR_CFG)); ++ printk(BIOS_DEBUG, "BAR MAILBOX = %08x\n", pnp_read_le32(port, LPCIF_BAR_MAILBOX)); ++ printk(BIOS_DEBUG, "BAR 8042 = %08x\n", pnp_read_le32(port, LPCIF_BAR_8042)); ++ printk(BIOS_DEBUG, "BAR ACPI_EC0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC0)); ++ printk(BIOS_DEBUG, "BAR ACPI_EC1 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC1)); ++ printk(BIOS_DEBUG, "BAR ACPI_EC2 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC2)); ++ printk(BIOS_DEBUG, "BAR ACPI_EC3 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC3)); ++ printk(BIOS_DEBUG, "BAR ACPI_PM0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_PM0)); ++ printk(BIOS_DEBUG, "BAR UART = %08x\n", pnp_read_le32(port, LPCIF_BAR_UART)); ++ printk(BIOS_DEBUG, "BAR FAST_KYBD = %08x\n", pnp_read_le32(port, LPCIF_BAR_FAST_KYBD)); ++ printk(BIOS_DEBUG, "BAR EMBED_FLASH = %08x\n", pnp_read_le32(port, LPCIF_BAR_EMBED_FLASH)); ++ printk(BIOS_DEBUG, "BAR GP_SPI = %08x\n", pnp_read_le32(port, LPCIF_BAR_GP_SPI)); ++ printk(BIOS_DEBUG, "BAR EMI = %08x\n", pnp_read_le32(port, LPCIF_BAR_EMI)); ++ printk(BIOS_DEBUG, "BAR PMH7 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PMH7)); ++ printk(BIOS_DEBUG, "BAR PORT80_DBG0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PORT80_DBG0)); ++ printk(BIOS_DEBUG, "BAR PORT80_DBG1 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PORT80_DBG1)); ++ printk(BIOS_DEBUG, "BAR RTC = %08x\n", pnp_read_le32(port, LPCIF_BAR_RTC)); ++ ++ microchip_pnp_exit_conf_state(port); ++} ++ ++static void mainboard_enable(struct device *dev) ++{ ++ if (CONFIG(VGA_ROM_RUN)) ++ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, ++ GMA_INT15_PANEL_FIT_DEFAULT, ++ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); ++} ++ ++static void mainboard_init(void *chip_info) ++{ ++ dump_ec_cfg(EC_CFG_PORT); ++} ++ ++struct chip_operations mainboard_ops = { ++ .enable_dev = mainboard_enable, ++ .init = mainboard_init, ++}; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..4db4202961d0be67b75f52b28f2111d5655595c3 +GIT binary patch +literal 4106 +zcmeHJU2GIp6h5=FKeKmc=rAo()>4l^U|XP_ZDGYy!|YE>mu}hZ4|PdQy1bV0gipVB&+pHzmFpc`=IXxii}qiqH*)7}PU+ +z?woV)x!<09?wNbfhQa6n_IK}3M!Gw&OgS)sY2Q$LJ4F+z{-JneATkt9refXr6+8sr +zR{e1eASVcGl#mf_O&p%I^1;3af=xDeN0ZnydT=;zHOH-q=O;(UFda)^LXW8| +z-Vsanq!Y==Kq9plQ+*gu^hf&pJ9?tY{h01cbtR&SfsVM!_*!D4W5>papLuo?gRur| +zF$`lX;f2t48Dpd4V@(*z=dq95OkkfiVU53N<(gE+=U)KHEdU4}@R=aMjTTTOcb8-a +zC9IXSxZB*|#u~SlHnpsY25L#Sxy6ljl16gI)H0f>for?qaszCX;ESpG=pqROFWR~Z +zTqQzcH(berra`9K(R~0OJ_eeA=> +z&R-)LYP^U3@%6h}+0)7m-mEOhOM92l32>zpvu-&@ZkPf<>~Bsv&Oy1O(`pbLUf3vt*0HIRk0U3EzI +zIeSaIE9*jps%6qP7$EQo8=K#f^K_mFpy5prkNNSOU;oI@KK0}Ge*G6eyWz+6OyADf +zE`}Db#-81u-uS=OJB*=`v}WPMs@ugdtLtbZo6OEUf}>!QL` +z1zQ!pLt!Zek0|;p3VTDrj}`q(g?+8yuZk|KY?X>TRlP@LPpbH`s-ITbSygS+Jq6cQ +zp|Em=T_#B53Y|R}mtw!K3mUyWRhytxx_wi^(}HurDkx@L%OlKIA%rq@7%bE{p{Wl~ +zJJ%lV6&>fxBjnbA8G(&P?a8o%P#c~Wo$7|%1UE-$r;6jwt1uejOfMLwF-BDgC-Q+N +za!Hx;1S&$9!rlNCTsI*IMZ0#Y5aEO7sjIz#jb`S|q7OpRYx`h&=PK}_YnN#poNF=7 +z3yTO|pc0N&G3cozl21Q6c)l0vjm~0uFL)%2_T5RYR1$~dO~u)4px!jFycZNnchPVA +z!0+Vc_afL{m>rv2PY8{Cma`W{yG~JNJu?;L!#fSLmwRW{8R@gD7Z5~{xvZGpN)U`j +z^I~=;XVmtVzgSv@Na@HC?lC8A1l2+CU Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c +new file mode 100644 +index 0000000000..f7c29e1f39 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c +@@ -0,0 +1,203 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include "../../gpio.h" ++ ++/* FIXME: There are multiple GPIOs here that should be locked to prevent "TPM GPIO fail" style ++ * attacks. Unfortunately SKL/KBL GPIO locking *does not* work currently. */ ++ ++static const struct pad_config gpio_table[] = { ++ ++ /* ------- GPIO Community 0 ------- */ ++ ++ /* ------- GPIO Group GPP_A ------- */ ++ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */ ++ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */ ++ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */ ++ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */ ++ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */ ++ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */ ++ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */ ++ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */ ++ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */ ++ PAD_CFG_NF(GPP_A9, NATIVE, DEEP, NF1), /* LPCCLK_EC_24M */ ++ PAD_CFG_NF(GPP_A10, NATIVE, DEEP, NF1), /* LPCCLK_DEBUG_24M */ ++ PAD_NC(GPP_A11, NONE), ++ PAD_NC(GPP_A12, NONE), ++ PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */ ++ PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */ ++ PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSWARN */ ++ PAD_NC(GPP_A16, NONE), ++ PAD_NC(GPP_A17, NONE), ++ PAD_NC(GPP_A18, NONE), ++ PAD_NC(GPP_A19, NONE), ++ PAD_NC(GPP_A20, NONE), ++ PAD_NC(GPP_A21, NONE), ++ PAD_NC(GPP_A22, NONE), ++ PAD_NC(GPP_A23, NONE), ++ ++ /* ------- GPIO Group GPP_B ------- */ ++ PAD_NC(GPP_B0, NONE), ++ PAD_NC(GPP_B1, NONE), ++ PAD_NC(GPP_B2, NONE), ++ PAD_NC(GPP_B3, NONE), ++ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */ ++ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 */ ++ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 */ ++ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 */ ++ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 */ ++ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 */ ++ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE10 */ ++ PAD_NC(GPP_B11, NONE), ++ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */ ++ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */ ++ PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */ ++ PAD_CFG_GPO(GPP_B15, 1, DEEP), /* NFC_DLREQ */ ++ PAD_NC(GPP_B16, NONE), ++ PAD_NC(GPP_B17, NONE), ++ PAD_NC(GPP_B18, NONE), ++ PAD_NC(GPP_B19, NONE), ++ PAD_NC(GPP_B20, NONE), ++ PAD_NC(GPP_B21, NONE), ++ PAD_NC(GPP_B22, NONE), ++ PAD_NC(GPP_B23, NONE), ++ ++ /* ------- GPIO Community 1 ------- */ ++ ++ /* ------- GPIO Group GPP_C ------- */ ++ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ ++ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ ++ PAD_NC(GPP_C2, NONE), ++ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */ ++ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ ++ PAD_NC(GPP_C5, NONE), ++ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */ ++ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */ ++ PAD_NC(GPP_C8, NONE), ++ PAD_NC(GPP_C9, NONE), ++ PAD_NC(GPP_C10, NONE), ++ PAD_NC(GPP_C11, NONE), ++ PAD_NC(GPP_C12, NONE), ++ PAD_NC(GPP_C13, NONE), ++ PAD_NC(GPP_C14, NONE), ++ PAD_NC(GPP_C15, NONE), ++ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */ ++ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */ ++ PAD_NC(GPP_C18, NONE), ++ PAD_NC(GPP_C19, NONE), ++ PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ ++ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ ++ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ ++ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ ++ ++ /* ------- GPIO Group GPP_D ------- */ ++ PAD_NC(GPP_D0, NONE), ++ PAD_NC(GPP_D1, NONE), ++ PAD_NC(GPP_D2, NONE), ++ PAD_NC(GPP_D3, NONE), ++ PAD_NC(GPP_D4, NONE), ++ PAD_NC(GPP_D5, NONE), ++ PAD_NC(GPP_D6, NONE), ++ PAD_NC(GPP_D7, NONE), ++ PAD_NC(GPP_D8, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */ ++ PAD_NC(GPP_D10, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */ ++ PAD_NC(GPP_D13, NONE), ++ PAD_NC(GPP_D14, NONE), ++ PAD_NC(GPP_D15, NONE), ++ PAD_NC(GPP_D16, NONE), ++ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY1 */ ++ PAD_NC(GPP_D18, NONE), ++ PAD_NC(GPP_D19, NONE), ++ PAD_NC(GPP_D20, NONE), ++ PAD_NC(GPP_D21, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */ ++ PAD_NC(GPP_D23, NONE), ++ ++ /* ------- GPIO Group GPP_E ------- */ ++ PAD_NC(GPP_E0, NONE), ++ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -WWAN_SATA_DTCT (always HIGH) */ ++ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -PE_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */ ++ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */ ++ PAD_NC(GPP_E5, NONE), ++ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */ ++ PAD_NC(GPP_E7, NONE), ++ PAD_NC(GPP_E8, NONE), ++ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 (AON port) */ ++ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 (regular port) */ ++ PAD_NC(GPP_E11, NONE), ++ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */ ++ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */ ++ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */ ++ PAD_NC(GPP_E15, NONE), ++ PAD_NC(GPP_E16, NONE), ++ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ ++ PAD_NC(GPP_E18, NONE), ++ PAD_NC(GPP_E19, NONE), ++ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */ ++ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */ ++ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */ ++ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */ ++ ++ /* ------- GPIO Community 2 ------- */ ++ ++ /* -------- GPIO Group GPD -------- */ ++ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */ ++ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */ ++ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */ ++ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */ ++ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */ ++ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */ ++ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */ ++ PAD_NC(GPD7, NONE), ++ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */ ++ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */ ++ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */ ++ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ ++ ++ /* ------- GPIO Community 3 ------- */ ++ ++ /* ------- GPIO Group GPP_F ------- */ ++ PAD_NC(GPP_F0, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */ ++ PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, ACPI), /* DGFX_PWRGD */ ++ PAD_CFG_GPO(GPP_F4, 1, DEEP), /* -WWAN_RESET */ ++ PAD_NC(GPP_F5, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */ ++ PAD_NC(GPP_F16, NONE), ++ PAD_NC(GPP_F17, NONE), ++ PAD_NC(GPP_F18, NONE), ++ PAD_NC(GPP_F19, NONE), ++ PAD_NC(GPP_F20, NONE), ++ PAD_NC(GPP_F21, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -INTRUDER_PCH */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */ ++ ++ /* ------- GPIO Group GPP_G ------- */ ++ PAD_NC(GPP_G0, NONE), ++ PAD_NC(GPP_G1, NONE), ++ PAD_NC(GPP_G2, NONE), ++ PAD_NC(GPP_G3, NONE), ++ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ ++ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ ++ PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ ++ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ ++}; ++ ++void variant_config_gpios(void) ++{ ++ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c +new file mode 100644 +index 0000000000..3a951ce0da +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c +@@ -0,0 +1,90 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ 0x10ec0257, // Vendor/Device ID: Realtek ALC257 ++ 0x17aa225d, // Subsystem ID ++ 11, ++ AZALIA_SUBVENDOR(0, 0x17aa225d), ++ ++ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_MIC_IN, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_MIC_IN, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 3, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_HP_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 15 ++ )), ++ ++ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI ++ 0x80860101, // Subsystem ID ++ 4, ++ AZALIA_SUBVENDOR(2, 0x80860101), ++ ++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 3, 0 ++ )), ++}; ++ ++const u32 pc_beep_verbs[] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c +new file mode 100644 +index 0000000000..5252a402f9 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c +@@ -0,0 +1,20 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_memory_init_params(FSPM_UPD *mupd) ++{ ++ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; ++ mem_cfg->DqPinsInterleaved = true; /* DDR_DQ in interleave mode */ ++ mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */ ++ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; ++ ++ /* Get SPD for memory slots */ ++ struct spd_block blk = { .addr_map = { 0x50, 0x51, } }; ++ get_spd_smbus(&blk); ++ dump_spd_info(&blk); ++ ++ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; ++ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb +new file mode 100644 +index 0000000000..bf66bd3a69 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb +@@ -0,0 +1,103 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++chip soc/intel/skylake ++ device domain 0 on ++ device ref south_xhci on ++ register "usb2_ports" = "{ ++ [0] = USB2_PORT_MID(OC1), // USB-A ++ [1] = USB2_PORT_MID(OC0), // USB-A (always on) ++ [2] = USB2_PORT_MID(OC_SKIP), // JSC-1 (smartcard slot) ++ [3] = USB2_PORT_MID(OC_SKIP), // USB-C (charging port) ++ [4] = USB2_PORT_MID(OC_SKIP), // JCAM1 (IR camera) ++ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN1 (M.2 WWAN USB) ++ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN1 (M.2 WLAN USB) ++ [7] = USB2_PORT_MID(OC_SKIP), // JCAM1 (webcam) ++ [8] = USB2_PORT_MID(OC_SKIP), // JFPR1 (fingerprint reader) ++ [9] = USB2_PORT_MID(OC_SKIP), // JLCD1 (touch panel) ++ }" ++ register "usb3_ports" = "{ ++ [0] = USB3_PORT_DEFAULT(OC1), // USB-A ++ [1] = USB3_PORT_DEFAULT(OC0), // USB-A (always on) ++ [2] = USB3_PORT_DEFAULT(OC_SKIP), // RTS5344S (SD card reader) ++ [3] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C (charging port) ++ }" ++ end ++ ++ device ref sata on ++ # SATA_2 - JHDD1 SATA SSD ++ register "SataPortsEnable[2]" = "1" ++ register "SataPortsDevSlp[2]" = "1" ++ end ++ ++ # PCIe controller 1 - 1x4 ++ # PCIE 1-4 - RP1 - dGPU - CLKOUT0 - CLKREQ0 ++ # ++ # PCIe controller 2 - 2x1+1x2 (lane reversal) ++ # PCIE 5 - GBE - GBE - CLKOUT1 - CLKREQ1 (clobbers RP8) ++ # PCIE 6 - RP7 - WLAN - CLKOUT2 - CLKREQ2 ++ # PCIE 7-8 - RP5 - WWAN - CLKOUT3 - CLKREQ3 ++ # ++ # PCIe controller 3 - 2x2 ++ # PCIE 9-10 - RP9 - TB3 - CLKOUT4 - CLKREQ4 ++ # PCIE 11-12 - RP11 - SSD - CLKOUT5 - CLKREQ5 ++ ++ # dGPU - x4 ++ device ref pcie_rp1 on ++ register "PcieRpEnable[0]" = "1" ++ register "PcieRpClkReqSupport[0]" = "1" ++ register "PcieRpClkReqNumber[0]" = "0" ++ register "PcieRpClkSrcNumber[0]" = "0" ++ register "PcieRpAdvancedErrorReporting[0]" = "1" ++ register "PcieRpLtrEnable[0]" = "1" ++ end ++ ++ # Ethernet (clobbers RP8) ++ device ref gbe on ++ register "LanClkReqSupported" = "1" ++ register "LanClkReqNumber" = "1" ++ register "EnableLanLtr" = "1" ++ register "EnableLanK1Off" = "1" ++ end ++ ++ # M.2 WLAN - x1 ++ device ref pcie_rp7 on ++ register "PcieRpEnable[6]" = "1" ++ register "PcieRpClkReqSupport[6]" = "1" ++ register "PcieRpClkReqNumber[6]" = "2" ++ register "PcieRpClkSrcNumber[6]" = "2" ++ register "PcieRpAdvancedErrorReporting[6]" = "1" ++ register "PcieRpLtrEnable[6]" = "1" ++ end ++ ++ # M.2 WWAN - x2 ++ device ref pcie_rp5 on ++ register "PcieRpEnable[4]" = "1" ++ register "PcieRpClkReqSupport[4]" = "1" ++ register "PcieRpClkReqNumber[4]" = "3" ++ register "PcieRpClkSrcNumber[4]" = "3" ++ register "PcieRpAdvancedErrorReporting[4]" = "1" ++ register "PcieRpLtrEnable[4]" = "1" ++ end ++ ++ # TB3 (Alpine Ridge LP) - x2 ++ device ref pcie_rp9 on ++ register "PcieRpEnable[8]" = "1" ++ register "PcieRpClkReqSupport[8]" = "1" ++ register "PcieRpClkReqNumber[8]" = "4" ++ register "PcieRpClkSrcNumber[8]" = "4" ++ register "PcieRpAdvancedErrorReporting[8]" = "1" ++ register "PcieRpLtrEnable[8]" = "1" ++ register "PcieRpHotPlug[8]" = "1" ++ end ++ ++ # M.2 2280 caddy - x2 ++ device ref pcie_rp11 on ++ register "PcieRpEnable[10]" = "1" ++ register "PcieRpClkReqSupport[10]" = "1" ++ register "PcieRpClkReqNumber[10]" = "5" ++ register "PcieRpClkSrcNumber[10]" = "5" ++ register "PcieRpAdvancedErrorReporting[10]" = "1" ++ register "PcieRpLtrEnable[10]" = "1" ++ end ++ end ++end +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..47732e37d5b2bad4e674fd10eafa605d26f97840 +GIT binary patch +literal 4106 +zcmeHJUu+a*5TCu>yW9JAmoD2P9tqx`iFWXCLD09RaS&4j$?kY0KGYdgn6;MZ*!anbk!PNr!a%eU +zTXkLEL3ly5L&oUX#CS7?b2%Kad?s-#@;mhg8>>>#S&)d2I +zmP&-g0$k02szSQj(Y*j}YYtQnDH0;2ui{mPhI!flfFgv9nqI4Wr~5_?s`k0kALiCvcP +zCrRUFrpVYPYn?Jn%6MGXUXj_GGJYa!U&-tn8Gn&ANnz_0+@olH3VTw)mlf@-!p8{!e#p0ct5}M(h16D>p?OGjSz6v3juERjS +z#z{?mXvVqrXs_rvUmYR40gNzg(QD6y9E94?4DWO|6eb83LI-smcVC6x1n2reH}rAp +zLM);f=tWDCr``UF5T>!;PYu^H1g>EBP8A}2*fM>s-@nC3pDV|}6+CtfhG(II7`pcw +z`jLfJ!?;*R@Bp=Nw2EPOC7FEs(cugIP_K6tN_$~tvS8nx6iOv|IMrO3&-m*N9ZP#b +znG^~>I|l1cUVSeD9r^k3h0TP}WWD9=MZxY<Z3B2yU!k71#YRpThOJtVheMDA50rV#s@U +z+nKbA{O(olYR}icuzQD*-cjBQ9;%!eMDVP>7mWsF@=%>o)wSgq=n%DHNOYwRr4Ao6 +zbNdgEn*RdDS>Rud+fIY0N8JkP3q6;>8o%R(CE2n3?Xg%qP+U%~6|{XFyxv7Y#;J2Z +XK$lk*wsY^m4}9|iz?mg_AjCfat$CyH + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads +new file mode 100644 +index 0000000000..fcfbd75a92 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads +@@ -0,0 +1,19 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (eDP, ++ DP1, ++ DP2, ++ HDMI1, ++ HDMI2, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c +new file mode 100644 +index 0000000000..a98dd2bc4e +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c +@@ -0,0 +1,199 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include "../../gpio.h" ++ ++static const struct pad_config gpio_table[] = { ++ /* ------- GPIO Community 0 ------- */ ++ ++ /* ------- GPIO Group GPP_A ------- */ ++ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */ ++ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */ ++ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */ ++ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */ ++ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */ ++ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */ ++ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */ ++ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */ ++ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */ ++ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */ ++ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */ ++ PAD_NC(GPP_A11, NONE), ++ PAD_NC(GPP_A12, NONE), ++ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* -SUSWARN */ ++ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* -SUS_STAT */ ++ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), /* -SUSWARN */ ++ PAD_NC(GPP_A16, NONE), ++ PAD_NC(GPP_A17, NONE), ++ PAD_NC(GPP_A18, NONE), ++ PAD_NC(GPP_A19, NONE), ++ PAD_NC(GPP_A20, NONE), ++ PAD_NC(GPP_A21, NONE), ++ PAD_NC(GPP_A22, NONE), ++ PAD_NC(GPP_A23, NONE), ++ ++ /* ------- GPIO Group GPP_B ------- */ ++ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), ++ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), ++ PAD_NC(GPP_B2, NONE), ++ PAD_NC(GPP_B3, NONE), ++ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */ ++ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (dGPU) */ ++ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (WWAN) */ ++ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 (GBE) */ ++ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WLAN) */ ++ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 (TB3) */ ++ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 (SSD) */ ++ PAD_NC(GPP_B11, NONE), ++ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */ ++ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */ ++ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* PCH_SPKR */ ++ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */ ++ PAD_NC(GPP_B16, NONE), ++ PAD_NC(GPP_B17, NONE), ++ PAD_NC(GPP_B18, NONE), ++ PAD_NC(GPP_B19, NONE), ++ PAD_NC(GPP_B20, NONE), ++ PAD_NC(GPP_B21, NONE), ++ PAD_NC(GPP_B22, NONE), ++ PAD_NC(GPP_B23, NONE), ++ ++ /* ------- GPIO Community 1 ------- */ ++ ++ /* ------- GPIO Group GPP_C ------- */ ++ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ ++ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ ++ PAD_CFG_GPO(GPP_C2, 1, DEEP), ++ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */ ++ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ ++ PAD_NC(GPP_C5, NONE), ++ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */ ++ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */ ++ PAD_NC(GPP_C8, NONE), ++ PAD_NC(GPP_C9, NONE), ++ PAD_NC(GPP_C10, NONE), ++ PAD_NC(GPP_C11, NONE), ++ PAD_NC(GPP_C12, NONE), ++ PAD_NC(GPP_C13, NONE), ++ PAD_NC(GPP_C14, NONE), ++ PAD_NC(GPP_C15, NONE), ++ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */ ++ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */ ++ PAD_NC(GPP_C18, NONE), ++ PAD_NC(GPP_C19, NONE), ++ PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ ++ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ ++ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ ++ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ ++ ++ /* ------- GPIO Group GPP_D ------- */ ++ PAD_NC(GPP_D0, NONE), ++ PAD_NC(GPP_D1, NONE), ++ PAD_NC(GPP_D2, NONE), ++ PAD_NC(GPP_D3, NONE), ++ PAD_NC(GPP_D4, NONE), ++ PAD_NC(GPP_D5, NONE), ++ PAD_NC(GPP_D6, NONE), ++ PAD_NC(GPP_D7, NONE), ++ PAD_NC(GPP_D8, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */ ++ PAD_NC(GPP_D10, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */ ++ PAD_NC(GPP_D13, NONE), ++ PAD_NC(GPP_D14, NONE), ++ PAD_NC(GPP_D15, NONE), ++ PAD_NC(GPP_D16, NONE), ++ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */ ++ PAD_NC(GPP_D18, NONE), ++ PAD_NC(GPP_D19, NONE), ++ PAD_NC(GPP_D20, NONE), ++ PAD_NC(GPP_D21, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */ ++ PAD_NC(GPP_D23, NONE), ++ ++ /* ------- GPIO Group GPP_E ------- */ ++ PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */ ++ PAD_NC(GPP_E1, NONE), ++ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -SATA2_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */ ++ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */ ++ PAD_NC(GPP_E5, NONE), ++ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */ ++ PAD_NC(GPP_E7, NONE), ++ PAD_NC(GPP_E8, NONE), ++ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */ ++ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */ ++ PAD_NC(GPP_E11, NONE), ++ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */ ++ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */ ++ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */ ++ PAD_NC(GPP_E15, NONE), ++ PAD_NC(GPP_E16, NONE), ++ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ ++ PAD_NC(GPP_E18, NONE), ++ PAD_CFG_GPO(GPP_E19, 0, DEEP), ++ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */ ++ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */ ++ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */ ++ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */ ++ ++ /* ------- GPIO Community 2 ------- */ ++ ++ /* -------- GPIO Group GPD -------- */ ++ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */ ++ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */ ++ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */ ++ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */ ++ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */ ++ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */ ++ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */ ++ PAD_NC(GPD7, NONE), ++ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */ ++ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */ ++ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */ ++ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ ++ ++ /* ------- GPIO Community 3 ------- */ ++ ++ /* ------- GPIO Group GPP_F ------- */ ++ PAD_CFG_GPO(GPP_F0, 0, DEEP), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */ ++ PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI), /* DGFX_PWRGD */ ++ PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */ ++ PAD_NC(GPP_F5, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R37 to GND) */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */ ++ PAD_NC(GPP_F21, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -TAMPER_SW_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */ ++ ++ /* ------- GPIO Group GPP_G ------- */ ++ PAD_NC(GPP_G0, NONE), ++ PAD_NC(GPP_G1, NONE), ++ PAD_NC(GPP_G2, NONE), ++ PAD_NC(GPP_G3, NONE), ++ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ ++ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ ++ PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ ++ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ ++}; ++ ++void variant_config_gpios(void) ++{ ++ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c +new file mode 100644 +index 0000000000..b1d96c5a76 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c +@@ -0,0 +1,90 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ 0x10ec0257, // Vendor/Device ID: Realtek ALC257 ++ 0x17aa2258, // Subsystem ID ++ 11, ++ AZALIA_SUBVENDOR(0, 0x17aa2258), ++ ++ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_MIC_IN, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_MIC_IN, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 3, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_HP_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 15 ++ )), ++ ++ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI ++ 0x80860101, // Subsystem ID ++ 4, ++ AZALIA_SUBVENDOR(2, 0x80860101), ++ ++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++}; ++ ++const u32 pc_beep_verbs[] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c +new file mode 100644 +index 0000000000..001e934b3a +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c +@@ -0,0 +1,44 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static const struct pad_config memory_id_gpio_table[] = { ++ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */ ++}; ++ ++void mainboard_memory_init_params(FSPM_UPD *mupd) ++{ ++ int spd_idx; ++ char spd_name[20]; ++ size_t spd_size; ++ ++ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; ++ mem_cfg->DqPinsInterleaved = true; /* DDR_DQ in interleave mode */ ++ mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */ ++ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; ++ ++ /* Get SPD for soldered RAM SPD (CH A) */ ++ gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table)); ++ ++ spd_idx = gpio_get(GPP_F16) | gpio_get(GPP_F17) << 1 | gpio_get(GPP_F18) << 2 | ++ gpio_get(GPP_F19) << 3 | gpio_get(GPP_F20) << 4; ++ printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx); ++ snprintf(spd_name, sizeof(spd_name), "spd_%d.bin", spd_idx); ++ mem_cfg->MemorySpdPtr00 = (uintptr_t)cbfs_map(spd_name, &spd_size); ++ ++ /* Get SPD for memory slot (CH B) */ ++ struct spd_block blk = { .addr_map = { [1] = 0x51, } }; ++ get_spd_smbus(&blk); ++ dump_spd_info(&blk); ++ ++ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb +new file mode 100644 +index 0000000000..d4afca20c4 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb +@@ -0,0 +1,103 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++chip soc/intel/skylake ++ device domain 0 on ++ device ref south_xhci on ++ register "usb2_ports" = "{ ++ [0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on) ++ [1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A) ++ [2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot) ++ [3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB-C) ++ [4] = USB2_PORT_MID(OC_SKIP), // JCAM (IR camera) ++ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB) ++ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB) ++ [7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam) ++ [8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader) ++ [9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel) ++ }" ++ register "usb3_ports" = "{ ++ [0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on) ++ [1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A) ++ [2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader) ++ [3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSBC (USB-C) ++ }" ++ end ++ ++ device ref sata on ++ # SATA_2 - Main M.2 SATA SSD ++ register "SataPortsEnable[2]" = "1" ++ register "SataPortsDevSlp[2]" = "1" ++ end ++ ++ # PCIe controller 1 - 1x2+2x1 ++ # PCIE 1-2 - RP1 - dGPU - CLKOUT0 - CLKREQ0 ++ # PCIE 4 - RP4 - WWAN - CLKOUT1 - CLKREQ1 ++ # ++ # PCIe controller 2 - 2x1+1x2 (lane reversal) ++ # PCIE 5 - GBE - GBE - CLKOUT2 - CLKREQ2 (clobbers RP8) ++ # PCIE 6 - RP7 - WLAN - CLKOUT3 - CLKREQ3 ++ # PCIE 7-8 - RP5 - TB3 - CLKOUT4 - CLKREQ4 ++ # ++ # PCIe controller 3 - 1x4 (lane reversal) ++ # PCIE 9-12 - RP9 - SSD - CLKOUT5 - CLKREQ5 ++ ++ # dGPU - x2 ++ device ref pcie_rp1 on ++ register "PcieRpEnable[0]" = "1" ++ register "PcieRpClkReqSupport[0]" = "1" ++ register "PcieRpClkReqNumber[0]" = "0" ++ register "PcieRpClkSrcNumber[0]" = "0" ++ register "PcieRpAdvancedErrorReporting[0]" = "1" ++ register "PcieRpLtrEnable[0]" = "1" ++ end ++ ++ # M.2 WWAN - x1 ++ device ref pcie_rp4 on ++ register "PcieRpEnable[3]" = "1" ++ register "PcieRpClkReqSupport[3]" = "1" ++ register "PcieRpClkReqNumber[3]" = "1" ++ register "PcieRpClkSrcNumber[3]" = "1" ++ register "PcieRpAdvancedErrorReporting[3]" = "1" ++ register "PcieRpLtrEnable[3]" = "1" ++ end ++ ++ # Ethernet (clobbers RP8) ++ device ref gbe on ++ register "LanClkReqSupported" = "1" ++ register "LanClkReqNumber" = "2" ++ register "EnableLanLtr" = "1" ++ register "EnableLanK1Off" = "1" ++ end ++ ++ # M.2 WLAN - x1 ++ device ref pcie_rp7 on ++ register "PcieRpEnable[6]" = "1" ++ register "PcieRpClkReqSupport[6]" = "1" ++ register "PcieRpClkReqNumber[6]" = "3" ++ register "PcieRpClkSrcNumber[6]" = "3" ++ register "PcieRpAdvancedErrorReporting[6]" = "1" ++ register "PcieRpLtrEnable[6]" = "1" ++ end ++ ++ # TB3 (Alpine Ridge LP) - x2 ++ device ref pcie_rp5 on ++ register "PcieRpEnable[4]" = "1" ++ register "PcieRpClkReqSupport[4]" = "1" ++ register "PcieRpClkReqNumber[4]" = "4" ++ register "PcieRpClkSrcNumber[4]" = "4" ++ register "PcieRpAdvancedErrorReporting[4]" = "1" ++ register "PcieRpLtrEnable[4]" = "1" ++ register "PcieRpHotPlug[4]" = "1" ++ end ++ ++ # M.2 2280 SSD - x2 ++ device ref pcie_rp9 on ++ register "PcieRpEnable[8]" = "1" ++ register "PcieRpClkReqSupport[8]" = "1" ++ register "PcieRpClkReqNumber[8]" = "5" ++ register "PcieRpClkSrcNumber[8]" = "5" ++ register "PcieRpAdvancedErrorReporting[8]" = "1" ++ register "PcieRpLtrEnable[8]" = "1" ++ end ++ end ++end +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..86f39ddb55ea9fb58d5e5699637636ef597c734e +GIT binary patch +literal 512 +zcmY!u;9+)EWZ+<6U|?oq29gXMJYRrxPEL*>N67~+1r7#Qh7a1t+8`-(puhlu3{YAD +YT>%dM8_BI;nL`dsaHtp+rc($20I8n}l>h($ + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin 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0000000000000000000000000000000000000000..940f1e3cd8e5bd9ea32a82a14edcdcbc8132d8c7 +GIT binary patch +literal 512 +zcmY!u<-XH%N8S?V-1R3%^a4B#wurjQW(9mG0U=XnZ$x{Q& +z0UPq1A)%L_QJxwGl4(Y*BAFWD+8T7AOcTeDU_*B^6OSleBX=`bLy)jxgN`d)<=|uh +E020*^DF6Tf + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..30c84410d417ef7afa8705c93cdb64a9f4e915a0 +GIT binary patch +literal 512 +zcmY!uW!enxp}7)YiWinU~FgllWifig`TLxK(6%}hL^bdB7N9Ss$Lz^FmT39fQ* +FG5`?&65ap+ + +literal 0 +HcmV?d00001 + +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0028-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/coreboot/default/patches/0028-src-intel-x4x-Disable-stack-overflow-debug.patch deleted file mode 100644 index dd5f49b1..00000000 --- a/config/coreboot/default/patches/0028-src-intel-x4x-Disable-stack-overflow-debug.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 67b679f676c239ef904cdfdfc11d34f5ffe47b74 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 6 Jan 2025 01:53:53 +0000 -Subject: [PATCH 28/43] src/intel/x4x: Disable stack overflow debug - -Signed-off-by: Leah Rowe ---- - src/northbridge/intel/x4x/Kconfig | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 1803ef5733..7129aabf72 100644 ---- a/src/northbridge/intel/x4x/Kconfig -+++ b/src/northbridge/intel/x4x/Kconfig -@@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER - int - default 256 - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - # This number must be equal or lower than what's reported in ACPI PCI _CRS - config DOMAIN_RESOURCE_32BIT_LIMIT - default 0xfec00000 --- -2.39.5 - diff --git a/config/coreboot/default/patches/0029-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/coreboot/default/patches/0029-hp-8300cmt-remove-xhci_overcurrent_mapping.patch deleted file mode 100644 index 48255a87..00000000 --- a/config/coreboot/default/patches/0029-hp-8300cmt-remove-xhci_overcurrent_mapping.patch +++ /dev/null @@ -1,42 +0,0 @@ -From b738fe8af0132d6d0def055dbe25fa8bb3a797d0 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 22 Apr 2025 10:21:59 +0100 -Subject: [PATCH 29/43] hp/8300cmt: remove xhci_overcurrent_mapping - -No longer needed, as per the following commit: - -commit a3d1e6c4806e6c0e2e744be3a03fce12f21778d1 -Author: Keith Hui -Date: Tue Dec 31 18:19:31 2024 -0500 - - sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping - -Removing this from the devicetree also allows the -board to compile, otherwise an error is thrown: - -build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:10: error: 'const struct southbridge_intel_bd82x6x_config' has no member named 'xhci_overcurrent_mapping' - 147 | .xhci_overcurrent_mapping = 0x00000c03, - | ^~~~~~~~~~~~~~~~~~~~~~~~ -build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:37: error: excess elements in struct initializer [-Werror] - 147 | .xhci_overcurrent_mapping = 0x00000c03, - -Signed-off-by: Leah Rowe ---- - src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -index 3d21739b72..3a0b6d5c59 100644 ---- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -@@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - register "superspeed_capable_ports" = "0x0000000f" -- register "xhci_overcurrent_mapping" = "0x00000c03" - register "xhci_switchable_ports" = "0x0000000f" - register "usb_port_config" = "{ - { 1, 0, 0 }, --- -2.39.5 - diff --git a/config/coreboot/default/patches/0029-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0029-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch new file mode 100644 index 00000000..bb1dc948 --- /dev/null +++ b/config/coreboot/default/patches/0029-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch @@ -0,0 +1,708 @@ +From 3505474eebdb54c566dfff79286689f1ba4fbb67 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Mon, 30 Sep 2024 20:44:38 -0400 +Subject: [PATCH 29/41] mb/dell: Add Optiplex 780 MT (x4x/ICH10) + +Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/optiplex_780/Kconfig | 40 ++++ + src/mainboard/dell/optiplex_780/Kconfig.name | 4 + + src/mainboard/dell/optiplex_780/Makefile.mk | 10 + + src/mainboard/dell/optiplex_780/acpi/ec.asl | 5 + + .../dell/optiplex_780/acpi/ich10_pci_irqs.asl | 32 ++++ + .../dell/optiplex_780/acpi/superio.asl | 18 ++ + .../dell/optiplex_780/board_info.txt | 6 + + src/mainboard/dell/optiplex_780/cmos.default | 8 + + src/mainboard/dell/optiplex_780/cmos.layout | 72 ++++++++ + src/mainboard/dell/optiplex_780/cstates.c | 8 + + src/mainboard/dell/optiplex_780/devicetree.cb | 63 +++++++ + src/mainboard/dell/optiplex_780/dsdt.asl | 26 +++ + .../dell/optiplex_780/gma-mainboard.ads | 16 ++ + .../optiplex_780/variants/780_mt/data.vbt | Bin 0 -> 1917 bytes + .../optiplex_780/variants/780_mt/early_init.c | 12 ++ + .../dell/optiplex_780/variants/780_mt/gpio.c | 174 ++++++++++++++++++ + .../optiplex_780/variants/780_mt/hda_verb.c | 26 +++ + .../variants/780_mt/overridetree.cb | 10 + + 18 files changed, 530 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_780/Kconfig + create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name + create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk + create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl + create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl + create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl + create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt + create mode 100644 src/mainboard/dell/optiplex_780/cmos.default + create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout + create mode 100644 src/mainboard/dell/optiplex_780/cstates.c + create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb + create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl + create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb + +diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig +new file mode 100644 +index 0000000000..2d06c75c9a +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/Kconfig +@@ -0,0 +1,40 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_DELL_OPTIPLEX_780_COMMON ++ def_bool n ++ select BOARD_ROMSIZE_KB_8192 ++ select CPU_INTEL_SOCKET_LGA775 ++ select DRIVERS_I2C_CK505 ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ select INTEL_GMA_HAVE_VBT ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select NORTHBRIDGE_INTEL_X4X ++ select PCIEXP_ASPM ++ select PCIEXP_CLK_PM ++ select SOUTHBRIDGE_INTEL_I82801JX ++ ++config BOARD_DELL_OPTIPLEX_780_MT ++ select BOARD_DELL_OPTIPLEX_780_COMMON ++ ++if BOARD_DELL_OPTIPLEX_780_COMMON ++ ++config VGA_BIOS_ID ++ default "8086,2e22" ++ ++config MAINBOARD_DIR ++ default "dell/optiplex_780" ++ ++config MAINBOARD_PART_NUMBER ++ default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT ++ ++config OVERRIDE_DEVICETREE ++ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" ++ ++config VARIANT_DIR ++ default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT ++ ++endif # BOARD_DELL_OPTIPLEX_780_COMMON +diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name +new file mode 100644 +index 0000000000..db7f2e8fe3 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/Kconfig.name +@@ -0,0 +1,4 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_DELL_OPTIPLEX_780_MT ++ bool "OptiPlex 780 MT" +diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk +new file mode 100644 +index 0000000000..d462995d75 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/Makefile.mk +@@ -0,0 +1,10 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++ramstage-y += cstates.c ++romstage-y += variants/$(VARIANT_DIR)/gpio.c ++ ++bootblock-y += variants/$(VARIANT_DIR)/early_init.c ++romstage-y += variants/$(VARIANT_DIR)/early_init.c ++ ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads ++ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl +new file mode 100644 +index 0000000000..479296cb76 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl +@@ -0,0 +1,5 @@ ++/* SPDX-License-Identifier: CC-PDDC */ ++ ++/* Please update the license if adding licensable material. */ ++ ++/* dummy */ +diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl +new file mode 100644 +index 0000000000..b7588dcc41 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* This is board specific information: ++ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 ++ */ ++ ++If (PICM) { ++ Return (Package() { ++ /* PCI slot */ ++ Package() { 0x0001ffff, 0, 0, 0x14}, ++ Package() { 0x0001ffff, 1, 0, 0x15}, ++ Package() { 0x0001ffff, 2, 0, 0x16}, ++ Package() { 0x0001ffff, 3, 0, 0x17}, ++ ++ Package() { 0x0002ffff, 0, 0, 0x15}, ++ Package() { 0x0002ffff, 1, 0, 0x16}, ++ Package() { 0x0002ffff, 2, 0, 0x17}, ++ Package() { 0x0002ffff, 3, 0, 0x14}, ++ }) ++} Else { ++ Return (Package() { ++ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, ++ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, ++ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, ++ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, ++ ++ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, ++ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, ++ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, ++ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, ++ }) ++} +diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl +new file mode 100644 +index 0000000000..9f3900b86c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl +@@ -0,0 +1,18 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#undef SUPERIO_DEV ++#undef SUPERIO_PNP_BASE ++#undef IT8720F_SHOW_SP1 ++#undef IT8720F_SHOW_SP2 ++#undef IT8720F_SHOW_EC ++#undef IT8720F_SHOW_KBCK ++#undef IT8720F_SHOW_KBCM ++#undef IT8720F_SHOW_GPIO ++#undef IT8720F_SHOW_CIR ++#define SUPERIO_DEV SIO0 ++#define SUPERIO_PNP_BASE 0x2e ++#define IT8720F_SHOW_EC 1 ++#define IT8720F_SHOW_KBCK 1 ++#define IT8720F_SHOW_KBCM 1 ++#define IT8720F_SHOW_GPIO 1 ++#include +diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt +new file mode 100644 +index 0000000000..aaf657b583 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/board_info.txt +@@ -0,0 +1,6 @@ ++Category: desktop ++Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1 ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y +diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default +new file mode 100644 +index 0000000000..23f0e55f3e +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/cmos.default +@@ -0,0 +1,8 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Disable ++nmi=Enable ++sata_mode=AHCI ++gfx_uma_size=64M +diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout +new file mode 100644 +index 0000000000..9f5012adb4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/cmos.layout +@@ -0,0 +1,72 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++ ++# coreboot config options: southbridge ++408 1 e 10 sata_mode ++409 2 e 7 power_on_after_fail ++411 1 e 1 nmi ++ ++# coreboot config options: cpu ++ ++# coreboot config options: northbridge ++432 4 e 11 gfx_uma_size ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++2 0 Enable ++2 1 Disable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++10 0 AHCI ++10 1 Compatible ++11 1 4M ++11 2 8M ++11 3 16M ++11 4 32M ++11 5 48M ++11 6 64M ++11 7 128M ++11 8 256M ++11 9 96M ++11 10 160M ++11 11 224M ++11 12 352M ++ ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 983 984 +diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c +new file mode 100644 +index 0000000000..4adf0edc63 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/cstates.c +@@ -0,0 +1,8 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++int get_cst_entries(const acpi_cstate_t **entries) ++{ ++ return 0; ++} +diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb +new file mode 100644 +index 0000000000..95e3bd517c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/devicetree.cb +@@ -0,0 +1,63 @@ ++# SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster ++ device domain 0 on ++ ops x4x_pci_domain_ops # PCI domain ++ subsystemid 0x8086 0x0028 inherit ++ device pci 0.0 on end # Host Bridge ++ device pci 1.0 on end # PCIe x16 2.0 slot ++ device pci 2.0 on end # Integrated graphics controller ++ device pci 2.1 on end # Integrated graphics controller 2 ++ device pci 3.0 off end # ME ++ device pci 3.1 off end # ME ++ chip southbridge/intel/i82801jx # ICH10 ++ register "gpe0_en" = "0x40" ++ ++ # Set AHCI mode. ++ register "sata_port_map" = "0x3f" ++ register "sata_clock_request" = "1" ++ ++ # Enable PCIe ports 0,1 as slots. ++ register "pcie_slot_implemented" = "0x3" ++ ++ device pci 19.0 on end # GBE ++ device pci 1a.0 on end # USB ++ device pci 1a.1 on end # USB ++ device pci 1a.2 on end # USB ++ device pci 1a.7 on end # USB ++ device pci 1b.0 on end # Audio ++ device pci 1c.0 off end # PCIe 1 ++ device pci 1c.1 off end # PCIe 2 ++ device pci 1c.2 off end # PCIe 3 ++ device pci 1c.3 off end # PCIe 4 ++ device pci 1c.4 off end # PCIe 5 ++ device pci 1c.5 off end # PCIe 6 ++ device pci 1d.0 on end # USB ++ device pci 1d.1 on end # USB ++ device pci 1d.2 on end # USB ++ device pci 1d.7 on end # USB ++ device pci 1e.0 on end # PCI bridge ++ device pci 1f.0 on end # LPC bridge ++ device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5) ++ device pci 1f.3 on # SMBus ++ chip drivers/i2c/ck505 # IDT CV194 ++ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff }" ++ register "regs" = "{ 0x15, 0x82, 0xff, 0xff, ++ 0xff, 0x00, 0x00, 0x95, ++ 0x00, 0x65, 0x7d, 0x56, ++ 0x13, 0xc0, 0x00, 0x07, ++ 0x01, 0x0a, 0x64 }" ++ device i2c 69 on end ++ end ++ end ++ device pci 1f.4 off end ++ device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode) ++ device pci 1f.6 off end # Thermal Subsystem ++ end ++ end ++end +diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl +new file mode 100644 +index 0000000000..9ad70469de +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/dsdt.asl +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20090811 // OEM revision ++) ++{ ++ #include ++ ++ OSYS = 2002 ++ // global NVS and variables ++ #include ++ ++ Device (\_SB.PCI0) ++ { ++ #include ++ #include ++ } ++ ++ #include ++} +diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads +new file mode 100644 +index 0000000000..bc81cf4a40 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads +@@ -0,0 +1,16 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (DP2, ++ Analog, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..fefda9d6f226b88ab67c5b044de30a707df22fbf +GIT binary patch +literal 1917 +zcmd6nO>7%Q6vzLwGv0Mv$FUpJ*ik4iQd_wnX*X`M0y3~p?8a$~>ZXxZMU`4dc9RGb +zTXq_i1Bwd~aNr{c4i)r(goF^M-nek+sY0sMa}Sk>xFFy_FTEfX^Y+7unt+OgkeJbX +zznS;`v-5V=o{ZwwmnN>gY?}>{`7^JBpP$l`EBIwbi0*k&aU)n@v)E +znI_A1T57efS5MGNN5_ut +zt=x`G)EjR#mlhURC^2!A3p33TcBg4-d8JyTiF&hfk}|a#&Dfe2%~V^}=4!QavNzBh +z0Pae^5`gfb?7Q)c(LsP)8 +zQy)2gwgG1S^>aw&0D}Z+-SCcJJF;s)yXJeQ|4N{SU?$I`#$HZa9dWBuxA$6X;VK;%W?Y>I;0P`|*vwAK$S(VB2JSq6g4n +z>oEf8XCt;_Y-iYBWz#3T9EmJ +z2x?*GPeN%?=Fj3+fv~4%I(nv~XF7VOqi5RsAt%13JtW>q=<<;0IkLPSUGL%_1h)2kjaZzuV;`43yCV;I=#Jcyyw@xKE8GGX39@am|0GKhH` +zawsKv^FvHqm+c8*FfFsu??w)Oed@;Mg~21%rCZ%d{x!>-zmv4AyWL1E +xfz+CGUnQ7Y^TD}&c_cQRYlBC+`?m?k6Nuw??s04gg4@4`<@FO{XEbO( ++ ++void mb_get_spd_map(u8 spd_map[4]) ++{ ++ // BTX form factor ++ spd_map[0] = 0x53; ++ spd_map[1] = 0x52; ++ spd_map[2] = 0x51; ++ spd_map[3] = 0x50; ++} +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c +new file mode 100644 +index 0000000000..9993f17c55 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c +@@ -0,0 +1,174 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_NATIVE, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_GPIO, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_NATIVE, ++ .gpio8 = GPIO_MODE_NATIVE, ++ .gpio9 = GPIO_MODE_GPIO, ++ .gpio10 = GPIO_MODE_GPIO, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_NATIVE, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_NATIVE, ++ .gpio18 = GPIO_MODE_GPIO, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_GPIO, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio5 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio9 = GPIO_DIR_OUTPUT, ++ .gpio10 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio18 = GPIO_DIR_OUTPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio20 = GPIO_DIR_OUTPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_INPUT, ++ .gpio31 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio9 = GPIO_LEVEL_HIGH, ++ .gpio18 = GPIO_LEVEL_HIGH, ++ .gpio20 = GPIO_LEVEL_HIGH, ++ .gpio28 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio13 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_GPIO, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_NATIVE, ++ .gpio52 = GPIO_MODE_NATIVE, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio32 = GPIO_DIR_INPUT, ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio35 = GPIO_DIR_OUTPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio56 = GPIO_DIR_OUTPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio35 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_HIGH, ++ .gpio56 = GPIO_LEVEL_HIGH, ++ .gpio60 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_NATIVE, ++ .gpio69 = GPIO_MODE_NATIVE, ++ .gpio70 = GPIO_MODE_NATIVE, ++ .gpio71 = GPIO_MODE_NATIVE, ++ .gpio72 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio72 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ }, ++}; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c +new file mode 100644 +index 0000000000..4158bcf899 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header */ ++ 0x11d4194a, /* Analog Devices AD1984A */ ++ 0xbfd40000, /* Subsystem ID */ ++ 10, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ AZALIA_PIN_CFG(0, 0x11, 0x032140f0), ++ AZALIA_PIN_CFG(0, 0x12, 0x21214010), ++ AZALIA_PIN_CFG(0, 0x13, 0x901701f0), ++ AZALIA_PIN_CFG(0, 0x14, 0x03a190f0), ++ AZALIA_PIN_CFG(0, 0x15, 0xb7a70121), ++ AZALIA_PIN_CFG(0, 0x16, 0x9933012e), ++ AZALIA_PIN_CFG(0, 0x17, 0x97a601f0), ++ AZALIA_PIN_CFG(0, 0x1a, 0x90f301f0), ++ AZALIA_PIN_CFG(0, 0x1b, 0x014510f0), ++ AZALIA_PIN_CFG(0, 0x1c, 0x21a19020), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb +new file mode 100644 +index 0000000000..555b1c1f5c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb +@@ -0,0 +1,10 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device domain 0 on ++ chip southbridge/intel/i82801jx ++ device pci 1c.0 on end # PCIe 1 ++ device pci 1c.1 on end # PCIe 2 ++ end ++ end ++end +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0030-dell-3050micro-disable-nvme-hotplug.patch b/config/coreboot/default/patches/0030-dell-3050micro-disable-nvme-hotplug.patch deleted file mode 100644 index 6fbfa632..00000000 --- a/config/coreboot/default/patches/0030-dell-3050micro-disable-nvme-hotplug.patch +++ /dev/null @@ -1,49 +0,0 @@ -From a9a8ed5895dcb3af2bb57ca1492ddc5e9432b2b7 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Wed, 11 Dec 2024 01:06:01 +0000 -Subject: [PATCH 30/43] dell/3050micro: disable nvme hotplug - -in my testing, when running my 3050micro for a few days, -the nvme would sometimes randomly rename. - -e.g. nvme0n1 renamed to nvme0n2 - -this might cause crashes in linux, if booting only from the -nvme. in my case, i was booting from mdraid (sata+nvme) and -every few days, the nvme would rename at least once, causing -my RAID to become unsynced. since i'm using RAID1, this was -OK and I could simply re-sync the array, but this is quite -precarious indeed. if you're using raid0, that will potentially -corrupt your RAID array indefinitely. - -this same issue manifested on the T480/T480 thinkpads, and -S3 resume would break because of that, when booting from nvme, -because the nvme would be "unplugged" and appear to linux as a -new device (the one that you booted from). - -the fix there was to disable hotplugging on that pci-e slot -for the nvme, so apply the same fix here for 3050 micro - -Signed-off-by: Leah Rowe ---- - src/mainboard/dell/optiplex_3050/devicetree.cb | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb -index 0d2adff74a..829acacab3 100644 ---- a/src/mainboard/dell/optiplex_3050/devicetree.cb -+++ b/src/mainboard/dell/optiplex_3050/devicetree.cb -@@ -44,7 +44,9 @@ chip soc/intel/skylake - register "PcieRpAdvancedErrorReporting[20]" = "1" - register "PcieRpLtrEnable[20]" = "true" - register "PcieRpClkSrcNumber[20]" = "3" -- register "PcieRpHotPlug[20]" = "1" -+# disable hotplug on nvme to prevent renaming e.g. nvme0n1 rename to nvme0n2, -+# which could cause crashes in linux if booting from nvme -+ register "PcieRpHotPlug[20]" = "0" - end - - # Realtek LAN --- -2.39.5 - diff --git a/config/coreboot/default/patches/0030-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0030-mb-dell-optiplex_780-Add-USFF-variant.patch new file mode 100644 index 00000000..68bf39e9 --- /dev/null +++ b/config/coreboot/default/patches/0030-mb-dell-optiplex_780-Add-USFF-variant.patch @@ -0,0 +1,326 @@ +From 77f7b454580edf756c22b38dd78a855fa5b0977f Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Wed, 30 Oct 2024 20:55:25 -0600 +Subject: [PATCH 30/41] mb/dell/optiplex_780: Add USFF variant + +Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/optiplex_780/Kconfig | 5 + + src/mainboard/dell/optiplex_780/Kconfig.name | 3 + + .../optiplex_780/variants/780_usff/data.vbt | Bin 0 -> 1917 bytes + .../variants/780_usff/early_init.c | 9 + + .../optiplex_780/variants/780_usff/gpio.c | 166 ++++++++++++++++++ + .../optiplex_780/variants/780_usff/hda_verb.c | 26 +++ + .../variants/780_usff/overridetree.cb | 10 ++ + 7 files changed, 219 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb + +diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig +index 2d06c75c9a..fc649e35d5 100644 +--- a/src/mainboard/dell/optiplex_780/Kconfig ++++ b/src/mainboard/dell/optiplex_780/Kconfig +@@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON + config BOARD_DELL_OPTIPLEX_780_MT + select BOARD_DELL_OPTIPLEX_780_COMMON + ++config BOARD_DELL_OPTIPLEX_780_USFF ++ select BOARD_DELL_OPTIPLEX_780_COMMON ++ + if BOARD_DELL_OPTIPLEX_780_COMMON + + config VGA_BIOS_ID +@@ -30,11 +33,13 @@ config MAINBOARD_DIR + + config MAINBOARD_PART_NUMBER + default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT ++ default "OptiPlex 780 USFF" if BOARD_DELL_OPTIPLEX_780_USFF + + config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + + config VARIANT_DIR + default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT ++ default "780_usff" if BOARD_DELL_OPTIPLEX_780_USFF + + endif # BOARD_DELL_OPTIPLEX_780_COMMON +diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name +index db7f2e8fe3..bc84c82a79 100644 +--- a/src/mainboard/dell/optiplex_780/Kconfig.name ++++ b/src/mainboard/dell/optiplex_780/Kconfig.name +@@ -2,3 +2,6 @@ + + config BOARD_DELL_OPTIPLEX_780_MT + bool "OptiPlex 780 MT" ++ ++config BOARD_DELL_OPTIPLEX_780_USFF ++ bool "OptiPlex 780 USFF" +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..dbd764f285ed18f7ee9c54bc777560138bd9b5f7 +GIT binary patch +literal 1917 +zcmd6nO>7%Q6vzLwGv3{}j$^l`v7@w1q*9sEq+2(b3K>`@c5#TSx@iP+W+B10OwbsGtX=N(gc4jSGjKDkP+yIUo^nsel8$^ny^9H?td8Ra=EiCEn=G +z@6DV4?!2AdojnUv^Rirgvs$heXUkGs9S+{Jc2WPhP0buTak^BTFP@&N9-E$(UtuSX +zS{r`=b+EX|Ig`2a*^5oDdG>8jE-1BBxs`*jgrf_sj_fP;%L|PwURRcCFBMCroNRQv +zmp$2TUhc}qJMB(u#jDG@x6(N85thC4%Z=8hiN}lj&zb2~``u3C;?lCrPQOTnInFqB +zhvdwqWv?lxTb=fVEH;~RPHDPw&g*&|s$pU7!7x2mLBtAF!g>K`zPnkx!DpPHuk6{_zc*0qi7)Aet$T +z1ks@8hWS#+6cI5)j1oD86{5PX8Zu2(^OC6M`xo)V)Ow=U6P12c +z=U0uNC9T9v{)-|#h(mSX*hSA8)ZeocL7l4J&!{RSO{6~oTtyn535j!RQh#GA*wTF8 +zvasRbO~d!?*FbM3K`W?lHx=v*(jiARIhWyh4^io|;n?@1H>uqJy>0sjV-Dt)_=%bE +zgNO3D@uE5m+7aqi?Y8b+inye%Z=HUmgBtaZ3Lc%OLt+bo+)5BjVwT<{mxT`nde$vb +zV99s{>`r76L#Hr6XW6r|>HT47I`**Q#Vu0QW!^VP-9S{xXzpq_zS#9k-;aXz?b+S!Ne$Kkk6dq&Hj-x+kx1W-4#E&beDT*S)=&NoSE?<-w!G@~aW()0ZN4O&=Q+nZa)p%Vd$k-_$a= +T#w3FFBiyj ++ ++void mb_get_spd_map(u8 spd_map[4]) ++{ ++ spd_map[0] = 0x50; ++ spd_map[2] = 0x52; ++} +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c +new file mode 100644 +index 0000000000..389f4077d7 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c +@@ -0,0 +1,166 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_NATIVE, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_GPIO, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_NATIVE, ++ .gpio8 = GPIO_MODE_NATIVE, ++ .gpio9 = GPIO_MODE_GPIO, ++ .gpio10 = GPIO_MODE_GPIO, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_NATIVE, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_NATIVE, ++ .gpio18 = GPIO_MODE_GPIO, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_GPIO, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio5 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio9 = GPIO_DIR_OUTPUT, ++ .gpio10 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio18 = GPIO_DIR_OUTPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio20 = GPIO_DIR_OUTPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_INPUT, ++ .gpio31 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio9 = GPIO_LEVEL_HIGH, ++ .gpio18 = GPIO_LEVEL_HIGH, ++ .gpio20 = GPIO_LEVEL_HIGH, ++ .gpio28 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio13 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_GPIO, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_NATIVE, ++ .gpio52 = GPIO_MODE_NATIVE, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio32 = GPIO_DIR_INPUT, ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio35 = GPIO_DIR_OUTPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio56 = GPIO_DIR_OUTPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio35 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_HIGH, ++ .gpio56 = GPIO_LEVEL_HIGH, ++ .gpio60 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio72 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio72 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ }, ++}; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c +new file mode 100644 +index 0000000000..c94e06b156 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header */ ++ 0x11d4194a, /* Analog Devices AD1984A */ ++ 0x10280420, /* Subsystem ID */ ++ 10, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ AZALIA_PIN_CFG(0, 0x11, 0x02214040), ++ AZALIA_PIN_CFG(0, 0x12, 0x01014010), ++ AZALIA_PIN_CFG(0, 0x13, 0x991301f0), ++ AZALIA_PIN_CFG(0, 0x14, 0x02a19020), ++ AZALIA_PIN_CFG(0, 0x15, 0x01813030), ++ AZALIA_PIN_CFG(0, 0x16, 0x413301f0), ++ AZALIA_PIN_CFG(0, 0x17, 0x41a601f0), ++ AZALIA_PIN_CFG(0, 0x1a, 0x41f301f0), ++ AZALIA_PIN_CFG(0, 0x1b, 0x414501f0), ++ AZALIA_PIN_CFG(0, 0x1c, 0x413301f0), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb +new file mode 100644 +index 0000000000..555b1c1f5c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb +@@ -0,0 +1,10 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device domain 0 on ++ chip southbridge/intel/i82801jx ++ device pci 1c.0 on end # PCIe 1 ++ device pci 1c.1 on end # PCIe 2 ++ end ++ end ++end +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0031-dell-3050micro-disable-nvme-hotplug.patch b/config/coreboot/default/patches/0031-dell-3050micro-disable-nvme-hotplug.patch new file mode 100644 index 00000000..66a36d35 --- /dev/null +++ b/config/coreboot/default/patches/0031-dell-3050micro-disable-nvme-hotplug.patch @@ -0,0 +1,49 @@ +From cf5f29a8cfed97bb7fb5dee2d7539e57b169661e Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Wed, 11 Dec 2024 01:06:01 +0000 +Subject: [PATCH 31/41] dell/3050micro: disable nvme hotplug + +in my testing, when running my 3050micro for a few days, +the nvme would sometimes randomly rename. + +e.g. nvme0n1 renamed to nvme0n2 + +this might cause crashes in linux, if booting only from the +nvme. in my case, i was booting from mdraid (sata+nvme) and +every few days, the nvme would rename at least once, causing +my RAID to become unsynced. since i'm using RAID1, this was +OK and I could simply re-sync the array, but this is quite +precarious indeed. if you're using raid0, that will potentially +corrupt your RAID array indefinitely. + +this same issue manifested on the T480/T480 thinkpads, and +S3 resume would break because of that, when booting from nvme, +because the nvme would be "unplugged" and appear to linux as a +new device (the one that you booted from). + +the fix there was to disable hotplugging on that pci-e slot +for the nvme, so apply the same fix here for 3050 micro + +Signed-off-by: Leah Rowe +--- + src/mainboard/dell/optiplex_3050/devicetree.cb | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb +index 0d2adff74a..829acacab3 100644 +--- a/src/mainboard/dell/optiplex_3050/devicetree.cb ++++ b/src/mainboard/dell/optiplex_3050/devicetree.cb +@@ -44,7 +44,9 @@ chip soc/intel/skylake + register "PcieRpAdvancedErrorReporting[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" + register "PcieRpClkSrcNumber[20]" = "3" +- register "PcieRpHotPlug[20]" = "1" ++# disable hotplug on nvme to prevent renaming e.g. nvme0n1 rename to nvme0n2, ++# which could cause crashes in linux if booting from nvme ++ register "PcieRpHotPlug[20]" = "0" + end + + # Realtek LAN +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0031-soc-intel-skylake-configure-usb-acpi.patch b/config/coreboot/default/patches/0031-soc-intel-skylake-configure-usb-acpi.patch deleted file mode 100644 index 34db0787..00000000 --- a/config/coreboot/default/patches/0031-soc-intel-skylake-configure-usb-acpi.patch +++ /dev/null @@ -1,94 +0,0 @@ -From 17cddce1253e9d71760a2ce066edffd3fc78c844 Mon Sep 17 00:00:00 2001 -From: Felix Singer -Date: Wed, 26 Jun 2024 04:24:31 +0200 -Subject: [PATCH 31/43] soc/intel/skylake: configure usb acpi - -Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d -Signed-off-by: Felix Singer ---- - src/soc/intel/skylake/Kconfig | 1 + - src/soc/intel/skylake/chipset.cb | 56 +++++++++++++++++++++++++++++++- - 2 files changed, 56 insertions(+), 1 deletion(-) - -diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 4ad33496b2..9191ed0ff8 100644 ---- a/src/soc/intel/skylake/Kconfig -+++ b/src/soc/intel/skylake/Kconfig -@@ -10,6 +10,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE - select CPU_INTEL_COMMON - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select CPU_SUPPORTS_PM_TIMER_EMULATION -+ select DRIVERS_USB_ACPI - select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 - select FSP_COMPRESS_FSP_S_LZ4 - select FSP_M_XIP -diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb -index 6538a1475b..dfb81d496e 100644 ---- a/src/soc/intel/skylake/chipset.cb -+++ b/src/soc/intel/skylake/chipset.cb -@@ -13,7 +13,61 @@ chip soc/intel/skylake - device pci 07.0 alias chap off end - device pci 08.0 alias gmm off end # Gaussian Mixture Model - device pci 13.0 alias ish off end # SensorHub -- device pci 14.0 alias south_xhci off ops usb_xhci_ops end -+ device pci 14.0 alias south_xhci off ops usb_xhci_ops -+ chip drivers/usb/acpi -+ register "type" = "UPC_TYPE_HUB" -+ device usb 0.0 alias xhci_root_hub off -+ chip drivers/usb/acpi -+ device usb 2.0 alias usb2_port1 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.1 alias usb2_port2 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.2 alias usb2_port3 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.3 alias usb2_port4 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.4 alias usb2_port5 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.5 alias usb2_port6 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.6 alias usb2_port7 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.7 alias usb2_port8 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.8 alias usb2_port9 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.9 alias usb2_port10 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.0 alias usb3_port1 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.1 alias usb3_port2 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.2 alias usb3_port3 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.3 alias usb3_port4 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.4 alias usb3_port5 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.5 alias usb3_port6 off end -+ end -+ end -+ end -+ end - device pci 14.1 alias south_xdci off ops usb_xdci_ops end - device pci 14.2 alias thermal off end - device pci 14.3 alias cio off end --- -2.39.5 - diff --git a/config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch new file mode 100644 index 00000000..dd566a37 --- /dev/null +++ b/config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch @@ -0,0 +1,78 @@ +From 17791a403c7887c9b48eab578e3bf977d9ba84a3 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Wed, 18 Dec 2024 02:06:18 +0000 +Subject: [PATCH 32/41] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN + +This is used by lbmk to know where a tb.bin file goes, +when extracting and padding TBT.bin from Lenovo ThunderBolt +firmware updates on T480/T480s and other machines, grabbing +Lenovo update files. + +Not used in any builds, so it's not relevant for ./mk inject + +However, the ThunderBolt firmware is now auto-downloaded on +T480/T480s. This is not inserted, because it doesn't go in +the main flash, but the resulting ROM image can be flashed +on the TB controller's separate flash chip. + +Locations are as follows: + +vendorfiles/t480s/tb.bin +vendorfiles/t480/tb.bin + +This can be used for other affected ThinkPads when they're +added to Libreboot, but note that Lenovo provides different +TB firmware files for each machine. + +Since I assume it's the same TB controller on all of those +machines, I have to wonder: what difference is there between +the various TBT.bin files provided by Lenovo, and how do they +differ in terms of actual flashed configuration? + +We simply flash the padded TBT.bin when updating the firmware, +flashing externally. That's what this patch is for, so that +lbmk can auto-download them. + +Signed-off-by: Leah Rowe +--- + src/mainboard/lenovo/Kconfig | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig +index 2ffbaab85f..512b326381 100644 +--- a/src/mainboard/lenovo/Kconfig ++++ b/src/mainboard/lenovo/Kconfig +@@ -18,4 +18,30 @@ config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + ++config LENOVO_TBFW_BIN ++ string "Lenovo ThunderBolt firmware bin file" ++ default "" ++ help ++ ThunderBolt firmware for certain ThinkPad models e.g. T480. ++ Not used in the actual build. Libreboot's build system uses this ++ along with config/vendor/*/pkg.cfg entries defining a URL to the ++ Lenovo download link and hash. The resulting file when processed by ++ lbmk can be flashed to the ThunderBolt firmware's 25XX NOR device. ++ Earlier versions of this firmware had debug commands enabled that ++ sent logs to said flash IC, and it would quickly fill up, bricking ++ the ThunderBolt controller. With these updates, flashed externally, ++ you can fix the issue if present or otherwise prevent it. The benefit ++ here is that you then don't need to use Windows or a boot disk. You ++ can flash the TB firmware while flashing Libreboot firmware. Easy! ++ Look for these variables in lbmk: ++ TBFW_url TBFW_url_bkup TBFW_hash and look at how it handles that and ++ CONFIG_LENOVO_TBFW_BIN, in lbmk's include/vendor.sh file. ++ The path set by CONFIG_LENOVO_TBFW_BIN is used by lbmk when extracting ++ the firmware, putting it at that desired location. In this way, lbmk ++ can auto-download such firmware. E.g. ./mk -d coreboot t480_fsp_16mb ++ and it appears at vendorfiles/t480/tb.bin fully padded and everything! ++ ++ Just leave this blank if you don't care about this option. It's not ++ useful for every ThinkPad, only certain models. ++ + endif # VENDOR_LENOVO +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0032-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0032-src-intel-skylake-Disable-stack-overflow-debug-optio.patch deleted file mode 100644 index 60dda558..00000000 --- a/config/coreboot/default/patches/0032-src-intel-skylake-Disable-stack-overflow-debug-optio.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 02d0bc457b15874a450d67045f98c869cbf7dd03 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 6 Jan 2025 01:36:23 +0000 -Subject: [PATCH 32/43] src/intel/skylake: Disable stack overflow debug options - -The option was appearing in T480/3050micro configs of lbmk, -after updating on the coreboot/next uprev for 20241206 rev8: - -CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y - -I did some digging. See coreboot commit: - -commit 51cc2bacb6b07279b97e9934d079060475481fb6 -Author: Subrata Banik -Date: Fri Dec 13 13:07:28 2024 +0530 - - soc/intel/pantherlake: Disable stack overflow debug options - -Well now: - -I'm disabling this behaviour on Skylake, for the same -behaviour, because I want as few behaviour changes in general, -as possible, for the rev8 release. - -According to Subrata's patch, which was for Pantherlake, -without this change, stack corruption can occur on verstage -and romstage early on. Please look at that coreboot patch, -referenced above, for clarity. - -I see no harm in disabling this option for Skylake, since -the behaviour that it otherwise enables was not present -before. - -Signed-off-by: Leah Rowe ---- - src/soc/intel/skylake/Kconfig | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 9191ed0ff8..493a2d835a 100644 ---- a/src/soc/intel/skylake/Kconfig -+++ b/src/soc/intel/skylake/Kconfig -@@ -129,6 +129,15 @@ config DCACHE_RAM_SIZE - The size of the cache-as-ram region required during bootblock - and/or romstage. - -+# Override DEBUG Kconfig to avoid false alarm about stack overflow. -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS -+ bool -+ default n -+ -+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES -+ bool -+ default n -+ - config DCACHE_BSP_STACK_SIZE - hex - default 0x20400 if FSP_USES_CB_STACK --- -2.39.5 - diff --git a/config/coreboot/default/patches/0033-soc-intel-skylake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0033-soc-intel-skylake-Don-t-compress-FSP-S.patch index 0d450229..f1defb5d 100644 --- a/config/coreboot/default/patches/0033-soc-intel-skylake-Don-t-compress-FSP-S.patch +++ b/config/coreboot/default/patches/0033-soc-intel-skylake-Don-t-compress-FSP-S.patch @@ -1,7 +1,7 @@ -From c52fff995041cc6370e43201873dd1e3dff4e90c Mon Sep 17 00:00:00 2001 +From 2c1616af49bbc353b0946bcedf077d69d79ba293 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 26 Dec 2024 19:45:20 +0000 -Subject: [PATCH 33/43] soc/intel/skylake: Don't compress FSP-S +Subject: [PATCH 33/41] soc/intel/skylake: Don't compress FSP-S Build systems like lbmk need to reproducibly insert certain vendor files on release images. @@ -19,7 +19,7 @@ Signed-off-by: Leah Rowe 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 493a2d835a..42af82a5d8 100644 +index 9191ed0ff8..d51ffaef7b 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -12,7 +12,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE diff --git a/config/coreboot/default/patches/0034-soc-intel-pmc-Hardcoded-poweroff-after-power-fail.patch b/config/coreboot/default/patches/0034-soc-intel-pmc-Hardcoded-poweroff-after-power-fail.patch index 950b5dec..215a95f1 100644 --- a/config/coreboot/default/patches/0034-soc-intel-pmc-Hardcoded-poweroff-after-power-fail.patch +++ b/config/coreboot/default/patches/0034-soc-intel-pmc-Hardcoded-poweroff-after-power-fail.patch @@ -1,7 +1,7 @@ -From c3210c2d3e8a4be7eaf8d005ec3c0595a0d39919 Mon Sep 17 00:00:00 2001 +From 4e269cb66361a5b102f582e41ce8c70a0df3f60f Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Tue, 31 Dec 2024 01:40:42 +0000 -Subject: [PATCH 34/43] soc/intel/pmc: Hardcoded poweroff after power fail +Subject: [PATCH 34/41] soc/intel/pmc: Hardcoded poweroff after power fail Coreboot can set the power state for power on after previous power failure, based on the option table. On the ThinkPad T480, diff --git a/config/coreboot/default/patches/0035-ec-lenovo-h8-Add-CFR-objects-for-existing-options.patch b/config/coreboot/default/patches/0035-ec-lenovo-h8-Add-CFR-objects-for-existing-options.patch deleted file mode 100644 index b8c9e0fa..00000000 --- a/config/coreboot/default/patches/0035-ec-lenovo-h8-Add-CFR-objects-for-existing-options.patch +++ /dev/null @@ -1,182 +0,0 @@ -From 9e74101196da1ee94be39e68b37ce7ede665529d Mon Sep 17 00:00:00 2001 -From: Matt DeVillier -Date: Fri, 11 Jul 2025 16:07:29 -0500 -Subject: [PATCH 35/43] ec/lenovo/h8: Add CFR objects for existing options - -Add a header with CFR objects for existing configuration options, -so that supported boards can make use of them without duplication. - -TEST=build/boot lenovo/t480 w/edk2 payload - -Change-Id: I198f569e69abd42071df4d5354cd2bb258749257 -Signed-off-by: Matt DeVillier ---- - src/ec/lenovo/h8/cfr.h | 156 +++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 156 insertions(+) - create mode 100644 src/ec/lenovo/h8/cfr.h - -diff --git a/src/ec/lenovo/h8/cfr.h b/src/ec/lenovo/h8/cfr.h -new file mode 100644 -index 0000000000..934a3e866b ---- /dev/null -+++ b/src/ec/lenovo/h8/cfr.h -@@ -0,0 +1,156 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+/* -+ * CFR enums and structs for Lenovo H8 EC -+ */ -+ -+#ifndef _LENOVO_H8_CFR_H_ -+#define _LENOVO_H8_CFR_H_ -+ -+#include -+ -+/* Bluetooth */ -+static const struct sm_object bluetooth = SM_DECLARE_ENUM({ -+ .opt_name = "bluetooth", -+ .ui_name = "Bluetooth", -+ .ui_helptext = "Enable or disable the bluetooth module", -+ .default_value = 1, -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}); -+ -+/* Keyboard Backlight */ -+static const struct sm_object backlight = SM_DECLARE_ENUM({ -+ .opt_name = "backlight", -+ .ui_name = "Keyboard Backlight", -+ .ui_helptext = "Enable or disable the keyboard backlight", -+ .default_value = 0, -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}); -+ -+/* USB Always-On */ -+static const struct sm_object usb_always_on = SM_DECLARE_ENUM({ -+ .opt_name = "usb_always_on", -+ .ui_name = "USB Always-on", -+ .ui_helptext = "Always keep USB ports powered", -+ .default_value = 0, -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}); -+ -+/* Ultrawideband */ -+static const struct sm_object uwb = SM_DECLARE_ENUM({ -+ .opt_name = "uwb", -+ .ui_name = "Ultrawideband", -+ .ui_helptext = "TBD", -+ .default_value = 1, -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}); -+ -+/* Volume control */ -+static const struct sm_object volume = SM_DECLARE_ENUM({ -+ .opt_name = "volume", -+ .ui_name = "Volume", -+ .ui_helptext = "TBD", -+ .default_value = 0, -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}); -+ -+/* WLAN */ -+static const struct sm_object wlan = SM_DECLARE_ENUM({ -+ .opt_name = "wlan", -+ .ui_name = "WLAN", -+ .ui_helptext = "Enable or disable the WLAN module", -+ .default_value = 1, -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}); -+ -+/* WWAN */ -+static const struct sm_object wwan = SM_DECLARE_ENUM({ -+ .opt_name = "wwan", -+ .ui_name = "WWAN", -+ .ui_helptext = "Enable or disable the WWAN module", -+ .default_value = 1, -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}); -+ -+/* Power Management Beeps */ -+static const struct sm_object pm_beeps = SM_DECLARE_ENUM({ -+ .opt_name = "power_management_beeps", -+ .ui_name = "Power Management Beeps", -+ .ui_helptext = "Enable or disable power management beeps", -+ .default_value = 1, -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}); -+ -+/* Low Battery Beep */ -+static const struct sm_object battery_beep = SM_DECLARE_ENUM({ -+ .opt_name = "low_battery_beep", -+ .ui_name = "Low Battery Beep", -+ .ui_helptext = "Enable or disable low battery beep", -+ .default_value = 1, -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}); -+ -+/* Fn-CTRL Swap */ -+static const struct sm_object fn_ctrl_swap = SM_DECLARE_ENUM({ -+ .opt_name = "fn_ctrl_swap", -+ .ui_name = "Swap Fn and CTRL", -+ .ui_helptext = "Swap the left Fn and CTRL keys", -+ .default_value = CONFIG(H8_FN_CTRL_SWAP), -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}); -+ -+/* Fn Lock */ -+static const struct sm_object sticky_fn = SM_DECLARE_ENUM({ -+ .opt_name = "sticky_fn", -+ .ui_name = "Sticky Fn key", -+ .ui_helptext = "Function key acts as a toggle", -+ .default_value = 0, -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}); -+ -+/* Function keys primary */ -+static const struct sm_object f1_to_f12_as_primary = SM_DECLARE_ENUM({ -+ .opt_name = "f1_to_f12_as_primary", -+ .ui_name = "Primary Function keys", -+ .ui_helptext = "F1-F12 default act as function keys", -+ .default_value = 1, -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}); -+ -+#endif /* _LENOVO_H8_CFR_H_ */ --- -2.39.5 - diff --git a/config/coreboot/default/patches/0035-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0035-src-intel-skylake-Disable-stack-overflow-debug-optio.patch new file mode 100644 index 00000000..70ea1b6d --- /dev/null +++ b/config/coreboot/default/patches/0035-src-intel-skylake-Disable-stack-overflow-debug-optio.patch @@ -0,0 +1,61 @@ +From 1f13ade55375d32a65eb5e9cf327f7060353a225 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 6 Jan 2025 01:36:23 +0000 +Subject: [PATCH 35/41] src/intel/skylake: Disable stack overflow debug options + +The option was appearing in T480/3050micro configs of lbmk, +after updating on the coreboot/next uprev for 20241206 rev8: + +CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y + +I did some digging. See coreboot commit: + +commit 51cc2bacb6b07279b97e9934d079060475481fb6 +Author: Subrata Banik +Date: Fri Dec 13 13:07:28 2024 +0530 + + soc/intel/pantherlake: Disable stack overflow debug options + +Well now: + +I'm disabling this behaviour on Skylake, for the same +behaviour, because I want as few behaviour changes in general, +as possible, for the rev8 release. + +According to Subrata's patch, which was for Pantherlake, +without this change, stack corruption can occur on verstage +and romstage early on. Please look at that coreboot patch, +referenced above, for clarity. + +I see no harm in disabling this option for Skylake, since +the behaviour that it otherwise enables was not present +before. + +Signed-off-by: Leah Rowe +--- + src/soc/intel/skylake/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig +index d51ffaef7b..42af82a5d8 100644 +--- a/src/soc/intel/skylake/Kconfig ++++ b/src/soc/intel/skylake/Kconfig +@@ -129,6 +129,15 @@ config DCACHE_RAM_SIZE + The size of the cache-as-ram region required during bootblock + and/or romstage. + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + config DCACHE_BSP_STACK_SIZE + hex + default 0x20400 if FSP_USES_CB_STACK +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0036-ec-lenovo-pmh7-Add-CFR-objects-for-existing-options.patch b/config/coreboot/default/patches/0036-ec-lenovo-pmh7-Add-CFR-objects-for-existing-options.patch deleted file mode 100644 index f010c7ae..00000000 --- a/config/coreboot/default/patches/0036-ec-lenovo-pmh7-Add-CFR-objects-for-existing-options.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 93e574a0a913b2d982d10aab50f372f59e41ba8c Mon Sep 17 00:00:00 2001 -From: Matt DeVillier -Date: Fri, 11 Jul 2025 16:09:08 -0500 -Subject: [PATCH 36/43] ec/lenovo/pmh7: Add CFR objects for existing options - -Add a header with CFR objects for existing configuration options, -so that supported boards can make use of them without duplication. - -TEST=build/boot lenovo/t480 w/edk2 payload - -Change-Id: I8f5c335a8b9d1697b77b3c3542bd96f98583dbf6 -Signed-off-by: Matt DeVillier ---- - src/ec/lenovo/pmh7/cfr.h | 36 ++++++++++++++++++++++++++++++++++++ - 1 file changed, 36 insertions(+) - create mode 100644 src/ec/lenovo/pmh7/cfr.h - -diff --git a/src/ec/lenovo/pmh7/cfr.h b/src/ec/lenovo/pmh7/cfr.h -new file mode 100644 -index 0000000000..329fb56a3e ---- /dev/null -+++ b/src/ec/lenovo/pmh7/cfr.h -@@ -0,0 +1,36 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+/* -+ * CFR enums and structs for Lenovo PMH7 EC -+ */ -+ -+#ifndef _LENOVO_PMH7_CFR_H_ -+#define _LENOVO_PMH7_CFR_H_ -+ -+#include -+ -+/* Touchpad */ -+static const struct sm_object touchpad = SM_DECLARE_ENUM({ -+ .opt_name = "touchpad", -+ .ui_name = "Touchpad", -+ .ui_helptext = "Enable or disable the touchpad", -+ .default_value = 1, -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}); -+ -+/* Trackpoint */ -+static const struct sm_object trackpoint = SM_DECLARE_ENUM({ -+ .opt_name = "trackpoint", -+ .ui_name = "Trackpoint", -+ .ui_helptext = "Enable or disable the trackpoint", -+ .default_value = 1, -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}); -+ -+#endif /* _LENOVO_PMH7_CFR_H_ */ --- -2.39.5 - diff --git a/config/coreboot/default/patches/0036-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/coreboot/default/patches/0036-src-intel-x4x-Disable-stack-overflow-debug.patch new file mode 100644 index 00000000..303955a4 --- /dev/null +++ b/config/coreboot/default/patches/0036-src-intel-x4x-Disable-stack-overflow-debug.patch @@ -0,0 +1,33 @@ +From 5f34838af23fd4b6dccbab1f60b931fca7762e01 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 6 Jan 2025 01:53:53 +0000 +Subject: [PATCH 36/41] src/intel/x4x: Disable stack overflow debug + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/x4x/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig +index 1803ef5733..7129aabf72 100644 +--- a/src/northbridge/intel/x4x/Kconfig ++++ b/src/northbridge/intel/x4x/Kconfig +@@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER + int + default 256 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + # This number must be equal or lower than what's reported in ACPI PCI _CRS + config DOMAIN_RESOURCE_32BIT_LIMIT + default 0xfec00000 +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0037-Conditional-TBFW-setting-for-T480-T480S.patch b/config/coreboot/default/patches/0037-Conditional-TBFW-setting-for-T480-T480S.patch new file mode 100644 index 00000000..fbe70b0d --- /dev/null +++ b/config/coreboot/default/patches/0037-Conditional-TBFW-setting-for-T480-T480S.patch @@ -0,0 +1,37 @@ +From 3b6c8e02eba287727b3abc96ffe5612f28c27df3 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 21 Apr 2025 05:14:45 +0100 +Subject: [PATCH 37/41] Conditional TBFW setting for T480/T480S + +Otherwise, other boards will define it, which +might trigger the vendor download script, and +lead to a non-zero exit. + +Signed-off-by: Leah Rowe +--- + src/mainboard/lenovo/Kconfig | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig +index 512b326381..3d3490b35d 100644 +--- a/src/mainboard/lenovo/Kconfig ++++ b/src/mainboard/lenovo/Kconfig +@@ -18,6 +18,8 @@ config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + ++if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S ++ + config LENOVO_TBFW_BIN + string "Lenovo ThunderBolt firmware bin file" + default "" +@@ -44,4 +46,6 @@ config LENOVO_TBFW_BIN + Just leave this blank if you don't care about this option. It's not + useful for every ThinkPad, only certain models. + ++endif # BOARD LENOVO_T480 || BOARD_LENOVO_T480S ++ + endif # VENDOR_LENOVO +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0037-ec-lenovo-h8-Replace-chip-regs-for-BT-WWAN-detect-wi.patch b/config/coreboot/default/patches/0037-ec-lenovo-h8-Replace-chip-regs-for-BT-WWAN-detect-wi.patch deleted file mode 100644 index 401f4d9a..00000000 --- a/config/coreboot/default/patches/0037-ec-lenovo-h8-Replace-chip-regs-for-BT-WWAN-detect-wi.patch +++ /dev/null @@ -1,512 +0,0 @@ -From 321fa80375cb1050a09ef8ae8e1d9fb7a1590c8b Mon Sep 17 00:00:00 2001 -From: Matt DeVillier -Date: Sat, 12 Jul 2025 14:48:33 -0500 -Subject: [PATCH 37/43] ec/lenovo/h8: Replace chip regs for BT/WWAN detect with - Kconfig options - -Using Kconfig options instead of chip registers allows for newer boards -which do not implement BT/WWAN detection to not compile in the GPIO- -related parts, which are only valid for older (pre-FSP) platforms. - -Change-Id: Ibfe738adfc75abfaf078c6b7ff5472a1424909f5 -Signed-off-by: Matt DeVillier ---- - src/ec/lenovo/h8/Kconfig | 8 ++++++++ - src/ec/lenovo/h8/bluetooth.c | 2 +- - src/ec/lenovo/h8/chip.h | 2 -- - src/ec/lenovo/h8/wwan.c | 2 +- - src/mainboard/lenovo/t400/Kconfig | 1 + - src/mainboard/lenovo/t400/devicetree.cb | 1 - - src/mainboard/lenovo/t420/Kconfig | 1 + - src/mainboard/lenovo/t420/devicetree.cb | 1 - - src/mainboard/lenovo/t420s/Kconfig | 1 + - src/mainboard/lenovo/t420s/devicetree.cb | 1 - - src/mainboard/lenovo/t430/Kconfig | 2 ++ - src/mainboard/lenovo/t430/devicetree.cb | 2 -- - src/mainboard/lenovo/t430s/Kconfig | 1 + - src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb | 1 - - src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb | 2 -- - src/mainboard/lenovo/t520/Kconfig | 2 ++ - src/mainboard/lenovo/t520/devicetree.cb | 1 - - src/mainboard/lenovo/t520/variants/t520/overridetree.cb | 1 - - src/mainboard/lenovo/t530/Kconfig | 2 ++ - src/mainboard/lenovo/t530/devicetree.cb | 1 - - src/mainboard/lenovo/t530/variants/t530/overridetree.cb | 1 - - src/mainboard/lenovo/t60/Kconfig | 1 + - src/mainboard/lenovo/t60/variants/t60/overridetree.cb | 1 - - src/mainboard/lenovo/x1_carbon_gen1/Kconfig | 2 ++ - src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb | 2 -- - src/mainboard/lenovo/x200/Kconfig | 1 + - src/mainboard/lenovo/x200/devicetree.cb | 1 - - src/mainboard/lenovo/x201/Kconfig | 1 + - src/mainboard/lenovo/x201/devicetree.cb | 1 - - src/mainboard/lenovo/x220/Kconfig | 1 + - src/mainboard/lenovo/x220/devicetree.cb | 2 -- - src/mainboard/lenovo/x230/Kconfig | 1 + - src/mainboard/lenovo/x230/devicetree.cb | 2 -- - src/mainboard/lenovo/x230/variants/x230s/overridetree.cb | 2 -- - src/mainboard/lenovo/x60/Kconfig | 1 + - src/mainboard/lenovo/x60/devicetree.cb | 1 - - 36 files changed, 28 insertions(+), 28 deletions(-) - -diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig -index b15657d21a..fbdca5f94a 100644 ---- a/src/ec/lenovo/h8/Kconfig -+++ b/src/ec/lenovo/h8/Kconfig -@@ -65,4 +65,12 @@ config THINKPADEC_HKEY_EISAID - Motherboards of newer thinkpad models can override the default to match - vendor drivers and quirks. - -+config H8_HAS_BDC_GPIO_DETECTION -+ bool -+ default n -+ -+config H8_HAS_WWAN_GPIO_DETECTION -+ bool -+ default n -+ - endif # EC_LENOVO_H8 -diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c -index 16fc8dce39..aa5fc5814f 100644 ---- a/src/ec/lenovo/h8/bluetooth.c -+++ b/src/ec/lenovo/h8/bluetooth.c -@@ -28,7 +28,7 @@ bool h8_has_bdc(const struct device *dev) - { - struct ec_lenovo_h8_config *conf = dev->chip_info; - -- if (!conf->has_bdc_detection) { -+ if (!CONFIG(H8_HAS_BDC_GPIO_DETECTION)) { - printk(BIOS_INFO, "H8: BDC detection not implemented. " - "Assuming BDC installed\n"); - return true; -diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h -index 440c2fc4dd..0e4b11e753 100644 ---- a/src/ec/lenovo/h8/chip.h -+++ b/src/ec/lenovo/h8/chip.h -@@ -32,8 +32,6 @@ struct ec_lenovo_h8_config { - u8 has_keyboard_backlight; - u8 has_power_management_beeps; - u8 has_uwb; -- u8 has_bdc_detection; -- u8 has_wwan_detection; - - u8 bdc_gpio_num; - u8 bdc_gpio_lvl; -diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c -index 685886fcce..3eea9541ec 100644 ---- a/src/ec/lenovo/h8/wwan.c -+++ b/src/ec/lenovo/h8/wwan.c -@@ -26,7 +26,7 @@ bool h8_has_wwan(const struct device *dev) - { - struct ec_lenovo_h8_config *conf = dev->chip_info; - -- if (!conf->has_wwan_detection) { -+ if (!CONFIG(H8_HAS_WWAN_GPIO_DETECTION)) { - printk(BIOS_INFO, "H8: WWAN detection not implemented. " - "Assuming WWAN installed\n"); - return true; -diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig -index 5afcde8b81..85e580e30e 100644 ---- a/src/mainboard/lenovo/t400/Kconfig -+++ b/src/mainboard/lenovo/t400/Kconfig -@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 - select H8_HAS_BAT_THRESHOLDS_IMPL -+ select H8_HAS_BDC_GPIO_DETECTION if !BOARD_LENOVO_R500 - select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500 - select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500 - select HAVE_ACPI_TABLES -diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb -index 3d007533a4..9361f330d2 100644 ---- a/src/mainboard/lenovo/t400/devicetree.cb -+++ b/src/mainboard/lenovo/t400/devicetree.cb -@@ -155,7 +155,6 @@ chip northbridge/intel/gm45 - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - -- register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "48" - register "bdc_gpio_lvl" = "0" - end -diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig -index e2137a3379..cbf07efab7 100644 ---- a/src/mainboard/lenovo/t420/Kconfig -+++ b/src/mainboard/lenovo/t420/Kconfig -@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 - select H8_HAS_BAT_THRESHOLDS_IMPL -+ select H8_HAS_BDC_GPIO_DETECTION - select NO_UART_ON_SUPERIO - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES -diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb -index f5272fc701..37ac884eb3 100644 ---- a/src/mainboard/lenovo/t420/devicetree.cb -+++ b/src/mainboard/lenovo/t420/devicetree.cb -@@ -149,7 +149,6 @@ chip northbridge/intel/sandybridge - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - -- register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - end -diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig -index 5ed1fdefe9..37b3993a1a 100644 ---- a/src/mainboard/lenovo/t420s/Kconfig -+++ b/src/mainboard/lenovo/t420s/Kconfig -@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS - select EC_LENOVO_PMH7 - select GFX_GMA_PANEL_1_ON_LVDS - select H8_HAS_BAT_THRESHOLDS_IMPL -+ select H8_HAS_BDC_GPIO_DETECTION - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select HAVE_CMOS_DEFAULT -diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb -index 840e520fbb..335e025c72 100644 ---- a/src/mainboard/lenovo/t420s/devicetree.cb -+++ b/src/mainboard/lenovo/t420s/devicetree.cb -@@ -141,7 +141,6 @@ chip northbridge/intel/sandybridge - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - -- register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - end -diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig -index e136871503..1baa94a4c8 100644 ---- a/src/mainboard/lenovo/t430/Kconfig -+++ b/src/mainboard/lenovo/t430/Kconfig -@@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS - select EC_LENOVO_PMH7 - select GFX_GMA_PANEL_1_ON_LVDS - select H8_HAS_BAT_THRESHOLDS_IMPL -+ select H8_HAS_BDC_GPIO_DETECTION -+ select H8_HAS_WWAN_GPIO_DETECTION - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select HAVE_CMOS_DEFAULT -diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb -index 9a0db4dd85..02a4c85344 100644 ---- a/src/mainboard/lenovo/t430/devicetree.cb -+++ b/src/mainboard/lenovo/t430/devicetree.cb -@@ -118,11 +118,9 @@ chip northbridge/intel/sandybridge - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - -- register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - -- register "has_wwan_detection" = "1" - register "wwan_gpio_num" = "70" - register "wwan_gpio_lvl" = "0" - end -diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig -index 9a7a91b512..3ab5d340bb 100644 ---- a/src/mainboard/lenovo/t430s/Kconfig -+++ b/src/mainboard/lenovo/t430s/Kconfig -@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 - select H8_HAS_BAT_THRESHOLDS_IMPL -+ select H8_HAS_BDC_GPIO_DETECTION if BOARD_LENOVO_T430S - select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_T431S - select NO_UART_ON_SUPERIO - select BOARD_ROMSIZE_KB_16384 -diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb -index a9da730815..bc947af287 100644 ---- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb -+++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb -@@ -24,7 +24,6 @@ chip northbridge/intel/sandybridge - device ref lpc on - chip ec/lenovo/h8 - device pnp ff.2 on end # dummy -- register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - end -diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb -index 15712f941d..dae8bc7a2d 100644 ---- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb -+++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb -@@ -55,8 +55,6 @@ chip northbridge/intel/sandybridge - register "config1" = "0x09" - register "config3" = "0xc0" - register "evente_enable" = "0x1d" -- # T431s only has BT on wlan card -- register "has_bdc_detection" = "0" - end - end - device ref thermal off end -diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig -index 663113b98f..384927989f 100644 ---- a/src/mainboard/lenovo/t520/Kconfig -+++ b/src/mainboard/lenovo/t520/Kconfig -@@ -9,6 +9,8 @@ config BOARD_LENOVO_BASEBOARD_T520 - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 - select H8_HAS_BAT_THRESHOLDS_IMPL -+ select H8_HAS_BDC_GPIO_DETECTION -+ select H8_HAS_WWAN_GPIO_DETECTION - select NO_UART_ON_SUPERIO - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES -diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb -index 7102df0b9d..74605ca081 100644 ---- a/src/mainboard/lenovo/t520/devicetree.cb -+++ b/src/mainboard/lenovo/t520/devicetree.cb -@@ -137,7 +137,6 @@ chip northbridge/intel/sandybridge - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - -- register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - end -diff --git a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb -index 52946d1b6e..48d8f34e8d 100644 ---- a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb -+++ b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb -@@ -5,7 +5,6 @@ chip northbridge/intel/sandybridge - device ref lpc on - chip ec/lenovo/h8 - device pnp ff.2 on end # dummy -- register "has_wwan_detection" = "1" - register "wwan_gpio_num" = "70" - register "wwan_gpio_lvl" = "0" - end -diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig -index a797656d71..9450fdddd7 100644 ---- a/src/mainboard/lenovo/t530/Kconfig -+++ b/src/mainboard/lenovo/t530/Kconfig -@@ -9,6 +9,8 @@ config BOARD_LENOVO_BASEBOARD_T530 - select EC_LENOVO_PMH7 - select GFX_GMA_PANEL_1_ON_LVDS - select H8_HAS_BAT_THRESHOLDS_IMPL -+ select H8_HAS_BDC_GPIO_DETECTION -+ select H8_HAS_WWAN_GPIO_DETECTION - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select HAVE_CMOS_DEFAULT -diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb -index 362e0a69e9..13c40d91d4 100644 ---- a/src/mainboard/lenovo/t530/devicetree.cb -+++ b/src/mainboard/lenovo/t530/devicetree.cb -@@ -117,7 +117,6 @@ chip northbridge/intel/sandybridge - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - -- register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - end -diff --git a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb -index 3f058e3854..9bd36488f6 100644 ---- a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb -+++ b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb -@@ -21,7 +21,6 @@ chip northbridge/intel/sandybridge - device ref lpc on - chip ec/lenovo/h8 - device pnp ff.2 on end # dummy -- register "has_wwan_detection" = "1" - register "wwan_gpio_num" = "70" - register "wwan_gpio_lvl" = "0" - end -diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig -index ec3a6e01bb..6d095943bd 100644 ---- a/src/mainboard/lenovo/t60/Kconfig -+++ b/src/mainboard/lenovo/t60/Kconfig -@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS - select HAVE_CMOS_DEFAULT - select I945_LVDS - select INTEL_GMA_HAVE_VBT -+ select H8_HAS_BDC_GPIO_DETECTION if BOARD_LENOVO_T60 || BOARD_LENOVO_R60 - - config MAINBOARD_DIR - default "lenovo/t60" -diff --git a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb -index c58884a4b5..42e07a648c 100644 ---- a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb -+++ b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb -@@ -26,7 +26,6 @@ chip northbridge/intel/i945 - end - device pci 1f.0 on # PCI-LPC bridge - chip ec/lenovo/h8 -- register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "7" - register "bdc_gpio_lvl" = "0" - device pnp ff.2 on end -diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig -index 4e4c58b246..f0dcb38ab4 100644 ---- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig -+++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig -@@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS - select EC_LENOVO_PMH7 - select GFX_GMA_PANEL_1_ON_LVDS - select H8_HAS_BAT_THRESHOLDS_IMPL -+ select H8_HAS_BDC_GPIO_DETECTION -+ select H8_HAS_WWAN_GPIO_DETECTION - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select HAVE_CMOS_DEFAULT -diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb -index 84611d0656..6f601e9521 100644 ---- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb -+++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb -@@ -127,11 +127,9 @@ chip northbridge/intel/sandybridge - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - -- register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - -- register "has_wwan_detection" = "1" - register "wwan_gpio_num" = "70" - register "wwan_gpio_lvl" = "0" - end -diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig -index 29e2f6ca91..4aa1e2ce1e 100644 ---- a/src/mainboard/lenovo/x200/Kconfig -+++ b/src/mainboard/lenovo/x200/Kconfig -@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 - select H8_HAS_BAT_THRESHOLDS_IMPL -+ select H8_HAS_BDC_GPIO_DETECTION if BOARD_LENOVO_X200 - select NO_UART_ON_SUPERIO - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES -diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb -index 7871cfd00d..2d6ea77214 100644 ---- a/src/mainboard/lenovo/x200/devicetree.cb -+++ b/src/mainboard/lenovo/x200/devicetree.cb -@@ -144,7 +144,6 @@ chip northbridge/intel/gm45 - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - -- register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "7" - register "bdc_gpio_lvl" = "0" - end -diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig -index 8517232d20..319f127ab6 100644 ---- a/src/mainboard/lenovo/x201/Kconfig -+++ b/src/mainboard/lenovo/x201/Kconfig -@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS - select INTEL_GMA_HAVE_VBT - select MAINBOARD_USES_IFD_GBE_REGION - select H8_HAS_BAT_THRESHOLDS_IMPL -+ select H8_HAS_BDC_GPIO_DETECTION - - config VBOOT - select VBOOT_VBNV_FLASH -diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb -index 0be8a3ba07..5b6746b718 100644 ---- a/src/mainboard/lenovo/x201/devicetree.cb -+++ b/src/mainboard/lenovo/x201/devicetree.cb -@@ -140,7 +140,6 @@ chip northbridge/intel/ironlake - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - -- register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "48" - register "bdc_gpio_lvl" = "0" - end -diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig -index e6a2e66209..a877546bb7 100644 ---- a/src/mainboard/lenovo/x220/Kconfig -+++ b/src/mainboard/lenovo/x220/Kconfig -@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS - select EC_LENOVO_PMH7 - select GFX_GMA_PANEL_1_ON_LVDS - select H8_HAS_BAT_THRESHOLDS_IMPL -+ select H8_HAS_WWAN_GPIO_DETECTION - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select HAVE_CMOS_DEFAULT -diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb -index aaeecc8246..0ca9bcc6a3 100644 ---- a/src/mainboard/lenovo/x220/devicetree.cb -+++ b/src/mainboard/lenovo/x220/devicetree.cb -@@ -141,9 +141,7 @@ chip northbridge/intel/sandybridge - # BDC shorts pin14 and pin1 - # BDC's connector pin14 is left floating - # BDC's connector pin1 is routed to SB GPIO 54 -- register "has_bdc_detection" = "0" - -- register "has_wwan_detection" = "1" - register "wwan_gpio_num" = "70" - register "wwan_gpio_lvl" = "0" - end -diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig -index 1d04af9bff..cb6395beb9 100644 ---- a/src/mainboard/lenovo/x230/Kconfig -+++ b/src/mainboard/lenovo/x230/Kconfig -@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS - select EC_LENOVO_H8 - select H8_HAS_BAT_THRESHOLDS_IMPL - select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S -+ select H8_HAS_WWAN_GPIO_DETECTION if !BOARD_LENOVO_X230S - select NO_UART_ON_SUPERIO - select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP - select BOARD_ROMSIZE_KB_16384 if BOARD_LENOVO_X230S -diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb -index 3067096f0d..735ce4d9d9 100644 ---- a/src/mainboard/lenovo/x230/devicetree.cb -+++ b/src/mainboard/lenovo/x230/devicetree.cb -@@ -123,9 +123,7 @@ chip northbridge/intel/sandybridge - # BDC shorts pin14 and pin1 - # BDC's connector pin14 is left floating - # BDC's connector pin1 is routed to SB GPIO 54 -- register "has_bdc_detection" = "0" - -- register "has_wwan_detection" = "1" - register "wwan_gpio_num" = "70" - register "wwan_gpio_lvl" = "0" - end -diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb -index a84b5f3bdd..86c2e16e7d 100644 ---- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb -+++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb -@@ -40,8 +40,6 @@ chip northbridge/intel/sandybridge - register "config3" = "0xc4" - register "event5_enable" = "0x3c" - register "evente_enable" = "0x1d" -- # X230s only has BT on wlan card -- register "has_bdc_detection" = "0" - device pnp ff.2 on end - end - end -diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig -index 0f12a9272e..33238ccbd8 100644 ---- a/src/mainboard/lenovo/x60/Kconfig -+++ b/src/mainboard/lenovo/x60/Kconfig -@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS - select EC_LENOVO_H8 - select DRIVERS_I2C_CK505 - select DRIVER_LENOVO_SERIALS -+ select H8_HAS_BDC_GPIO_DETECTION - select HAVE_OPTION_TABLE - select INTEL_INT15 - select HAVE_CMOS_DEFAULT -diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb -index 0e1e5fced5..7f28bbae49 100644 ---- a/src/mainboard/lenovo/x60/devicetree.cb -+++ b/src/mainboard/lenovo/x60/devicetree.cb -@@ -130,7 +130,6 @@ chip northbridge/intel/i945 - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - -- register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "7" - register "bdc_gpio_lvl" = "0" - end --- -2.39.5 - diff --git a/config/coreboot/default/patches/0038-do-not-break-building-other-thinkpads-with-the-hacks.patch b/config/coreboot/default/patches/0038-do-not-break-building-other-thinkpads-with-the-hacks.patch new file mode 100644 index 00000000..8447cfab --- /dev/null +++ b/config/coreboot/default/patches/0038-do-not-break-building-other-thinkpads-with-the-hacks.patch @@ -0,0 +1,153 @@ +From 99086eb3298b01aa9b3c68d78c399261866321d5 Mon Sep 17 00:00:00 2001 +From: gaspar-ilom +Date: Thu, 6 Mar 2025 23:00:00 +0000 +Subject: [PATCH 38/41] do not break building other thinkpads with the hacks + for the t480/s made Mate Kukri + +still not fixing things properly but at least it should now be possible to build older thinkpads without regressions. +prior, some code was just commented or unreachable. now we make this explicit with preprocessor directives. +heads should build all boards on this coreboot version from the same coreboot tree. + +Signed-off-by: gaspar-ilom +--- + src/device/pci_rom.c | 9 ++++++--- + src/ec/lenovo/h8/acpi/ec.asl | 4 +++- + src/ec/lenovo/h8/bluetooth.c | 14 ++++++++++---- + src/ec/lenovo/h8/wwan.c | 14 ++++++++++---- + 4 files changed, 29 insertions(+), 12 deletions(-) + +diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c +index bba98d9dea..db3dbbe2ce 100644 +--- a/src/device/pci_rom.c ++++ b/src/device/pci_rom.c +@@ -396,16 +396,19 @@ void pci_rom_ssdt(const struct device *device) + rom = cbrom; + } + +-#if 0 ++ ++ #if CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON) ++ const char *scope = "\\_SB.PCI0.RP01.PEGP"; ++ #else + const char *scope = acpi_device_path(device); ++ #endif + if (!scope) { + printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(device)); + return; + } +-#endif + + /* write _ROM method */ +- acpigen_write_scope("\\_SB.PCI0.RP01.PEGP"); ++ acpigen_write_scope(scope); + acpigen_write_rom((void *)rom, rom->size * 512); + acpigen_pop_len(); /* pop scope */ + } +diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl +index 8f4a8e1986..f80c15106c 100644 +--- a/src/ec/lenovo/h8/acpi/ec.asl ++++ b/src/ec/lenovo/h8/acpi/ec.asl +@@ -331,7 +331,9 @@ Device(EC) + #include "sleepbutton.asl" + #include "lid.asl" + #include "beep.asl" +-//#include "thermal.asl" ++#if !CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON) ++#include "thermal.asl" ++#endif + #include "systemstatus.asl" + #include "thinkpad.asl" + } +diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c +index be71a24ced..e60b6c088c 100644 +--- a/src/ec/lenovo/h8/bluetooth.c ++++ b/src/ec/lenovo/h8/bluetooth.c +@@ -1,6 +1,8 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + +-// #include ++#if !CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON) ++#include ++#endif + #include + #include + #include +@@ -26,23 +28,27 @@ void h8_bluetooth_enable(int on) + */ + bool h8_has_bdc(const struct device *dev) + { ++ #if CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON) ++ printk(BIOS_INFO, "H8: BDC detection not implemented. " ++ "Assuming BDC installed\n"); ++ return true; ++ #else + struct ec_lenovo_h8_config *conf = dev->chip_info; + +- if (1 || !conf->has_bdc_detection) { ++ if (!conf->has_bdc_detection) { + printk(BIOS_INFO, "H8: BDC detection not implemented. " + "Assuming BDC installed\n"); + return true; + } + +-#if 0 + if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) { + printk(BIOS_INFO, "H8: BDC installed\n"); + return true; + } +-#endif + + printk(BIOS_INFO, "H8: BDC not installed\n"); + return false; ++ #endif + } + + /* +diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c +index 5cdcf77406..b4f5787e01 100644 +--- a/src/ec/lenovo/h8/wwan.c ++++ b/src/ec/lenovo/h8/wwan.c +@@ -1,6 +1,8 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + +-// #include ++#if !CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON) ++#include ++#endif + #include + #include + #include +@@ -24,23 +26,27 @@ void h8_wwan_enable(int on) + */ + bool h8_has_wwan(const struct device *dev) + { ++ #if CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON) ++ printk(BIOS_INFO, "H8: WWAN detection not implemented. " ++ "Assuming WWAN installed\n"); ++ return true; ++ #else + struct ec_lenovo_h8_config *conf = dev->chip_info; + +- if (1 || !conf->has_wwan_detection) { ++ if (!conf->has_wwan_detection) { + printk(BIOS_INFO, "H8: WWAN detection not implemented. " + "Assuming WWAN installed\n"); + return true; + } + +-#if 0 + if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) { + printk(BIOS_INFO, "H8: WWAN installed\n"); + return true; + } +-#endif + + printk(BIOS_INFO, "H8: WWAN not installed\n"); + return false; ++ #endif + } + + /* +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0038-ec-lenovo-h8-Add-Kconfig-to-select-use-of-Thermal-Zo.patch b/config/coreboot/default/patches/0038-ec-lenovo-h8-Add-Kconfig-to-select-use-of-Thermal-Zo.patch deleted file mode 100644 index d393226c..00000000 --- a/config/coreboot/default/patches/0038-ec-lenovo-h8-Add-Kconfig-to-select-use-of-Thermal-Zo.patch +++ /dev/null @@ -1,137 +0,0 @@ -From 596f2d915a36ebd3347441d7486e4d11780fc48c Mon Sep 17 00:00:00 2001 -From: Matt DeVillier -Date: Sat, 12 Jul 2025 17:17:42 -0500 -Subject: [PATCH 38/43] ec/lenovo/h8: Add Kconfig to select use of Thermal Zone - 1 - -Looking at the ACPI dumps of many older Thinkpads, most do not have a -second thermal zone (zone 1), they only use zone 0. This doesn't seem -to be a problem for most boards in the tree currently, but newer boards -(such as the T480) are reporting critical temperature errors on zone 1, -due to differences in the EC RAM layout (ie, TMP1 is not valid). - -To mitigate this issue with the T480 (and likely other newer boards), -only include the ACPI code for thermal zone 1 for boards which need it. -Explicitly select it for those boards based on ACPI dump analysis and -model similarity. - -Change-Id: Ic022f2e14b2cae74656c0ac85ba8410d50cdc9de -Signed-off-by: Matt DeVillier ---- - src/ec/lenovo/h8/Kconfig | 4 ++++ - src/ec/lenovo/h8/acpi/thermal.asl | 3 ++- - src/mainboard/lenovo/t400/Kconfig | 1 + - src/mainboard/lenovo/t410/Kconfig | 1 + - src/mainboard/lenovo/t60/Kconfig | 1 + - src/mainboard/lenovo/x200/Kconfig | 1 + - src/mainboard/lenovo/x201/Kconfig | 1 + - src/mainboard/lenovo/x60/Kconfig | 1 + - 8 files changed, 12 insertions(+), 1 deletion(-) - -diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig -index fbdca5f94a..c8626cc75b 100644 ---- a/src/ec/lenovo/h8/Kconfig -+++ b/src/ec/lenovo/h8/Kconfig -@@ -73,4 +73,8 @@ config H8_HAS_WWAN_GPIO_DETECTION - bool - default n - -+config H8_HAS_2ND_THERMAL_ZONE -+ bool -+ default n -+ - endif # EC_LENOVO_H8 -diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl -index fa5a282f54..bf9b653e12 100644 ---- a/src/ec/lenovo/h8/acpi/thermal.asl -+++ b/src/ec/lenovo/h8/acpi/thermal.asl -@@ -130,7 +130,7 @@ External (\PPKG, MethodObj) - Name (_PR0, Package () { FPWR }) - } - } -- -+#if CONFIG(H8_HAS_2ND_THERMAL_ZONE) - ThermalZone(THM1) - { - /* Thermal zone polling frequency: 10 seconds */ -@@ -168,4 +168,5 @@ External (\PPKG, MethodObj) - Return (C2K(\_SB.PCI0.LPCB.EC.TMP1)) - } - } -+#endif - } -diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig -index 85e580e30e..12fbcbdee6 100644 ---- a/src/mainboard/lenovo/t400/Kconfig -+++ b/src/mainboard/lenovo/t400/Kconfig -@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS - select SOUTHBRIDGE_INTEL_I82801IX - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 -+ select H8_HAS_2ND_THERMAL_ZONE - select H8_HAS_BAT_THRESHOLDS_IMPL - select H8_HAS_BDC_GPIO_DETECTION if !BOARD_LENOVO_R500 - select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500 -diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig -index 9c78cb1741..6f18528824 100644 ---- a/src/mainboard/lenovo/t410/Kconfig -+++ b/src/mainboard/lenovo/t410/Kconfig -@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS - select DRIVERS_LENOVO_HYBRID_GRAPHICS - select INTEL_GMA_HAVE_VBT - select MAINBOARD_USES_IFD_GBE_REGION -+ select H8_HAS_2ND_THERMAL_ZONE - select H8_HAS_BAT_THRESHOLDS_IMPL - select MAINBOARD_HAS_LIBGFXINIT - select DRIVERS_RICOH_RCE822 -diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig -index 6d095943bd..f1221191da 100644 ---- a/src/mainboard/lenovo/t60/Kconfig -+++ b/src/mainboard/lenovo/t60/Kconfig -@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS - select HAVE_CMOS_DEFAULT - select I945_LVDS - select INTEL_GMA_HAVE_VBT -+ select H8_HAS_2ND_THERMAL_ZONE - select H8_HAS_BDC_GPIO_DETECTION if BOARD_LENOVO_T60 || BOARD_LENOVO_R60 - - config MAINBOARD_DIR -diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig -index 4aa1e2ce1e..148584ed5c 100644 ---- a/src/mainboard/lenovo/x200/Kconfig -+++ b/src/mainboard/lenovo/x200/Kconfig -@@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS - select SOUTHBRIDGE_INTEL_I82801IX - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 -+ select H8_HAS_2ND_THERMAL_ZONE if BOARD_LENOVO_X200 - select H8_HAS_BAT_THRESHOLDS_IMPL - select H8_HAS_BDC_GPIO_DETECTION if BOARD_LENOVO_X200 - select NO_UART_ON_SUPERIO -diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig -index 319f127ab6..e91ec3e642 100644 ---- a/src/mainboard/lenovo/x201/Kconfig -+++ b/src/mainboard/lenovo/x201/Kconfig -@@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS - select MAINBOARD_HAS_TPM1 - select INTEL_GMA_HAVE_VBT - select MAINBOARD_USES_IFD_GBE_REGION -+ select H8_HAS_2ND_THERMAL_ZONE - select H8_HAS_BAT_THRESHOLDS_IMPL - select H8_HAS_BDC_GPIO_DETECTION - -diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig -index 33238ccbd8..edacdcf234 100644 ---- a/src/mainboard/lenovo/x60/Kconfig -+++ b/src/mainboard/lenovo/x60/Kconfig -@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS - select EC_LENOVO_H8 - select DRIVERS_I2C_CK505 - select DRIVER_LENOVO_SERIALS -+ select H8_HAS_2ND_THERMAL_ZONE - select H8_HAS_BDC_GPIO_DETECTION - select HAVE_OPTION_TABLE - select INTEL_INT15 --- -2.39.5 - diff --git a/config/coreboot/default/patches/0039-ec-lenovo-h8-Rework-invalid-temperature-reporting.patch b/config/coreboot/default/patches/0039-ec-lenovo-h8-Rework-invalid-temperature-reporting.patch deleted file mode 100644 index 3e73a17d..00000000 --- a/config/coreboot/default/patches/0039-ec-lenovo-h8-Rework-invalid-temperature-reporting.patch +++ /dev/null @@ -1,488 +0,0 @@ -From aedef7382e27d1494768997a18e4d9351cb44cd6 Mon Sep 17 00:00:00 2001 -From: Matt DeVillier -Date: Sat, 12 Jul 2025 17:28:13 -0500 -Subject: [PATCH 39/43] ec/lenovo/h8: Rework invalid temperature reporting - -As far back as the x201, Lenovo's EC ACPI has treated 128 as an invalid -value, and returned a corrected value when it is reported/read from EC -RAM. Drop the ME workaround, which most H8-equipped boards select, in -favor of Lenovo's logic, since both accomplish the same result. - -Change-Id: Icdc91e439ec30c8263de5810a13e75f7595472a5 -Signed-off-by: Matt DeVillier ---- - src/ec/lenovo/h8/acpi/thermal.asl | 25 ++++++------------- - .../lenovo/haswell/acpi/platform.asl | 3 --- - src/mainboard/lenovo/haswell/dsdt.asl | 1 - - src/mainboard/lenovo/l520/acpi/platform.asl | 4 --- - src/mainboard/lenovo/l520/dsdt.asl | 1 - - src/mainboard/lenovo/s230u/dsdt.asl | 1 - - src/mainboard/lenovo/t400/dsdt.asl | 1 - - src/mainboard/lenovo/t410/dsdt.asl | 1 - - src/mainboard/lenovo/t420/acpi/platform.asl | 4 --- - src/mainboard/lenovo/t420/dsdt.asl | 1 - - src/mainboard/lenovo/t420s/acpi/platform.asl | 4 --- - src/mainboard/lenovo/t420s/dsdt.asl | 1 - - src/mainboard/lenovo/t430/acpi/platform.asl | 4 --- - src/mainboard/lenovo/t430/dsdt.asl | 1 - - src/mainboard/lenovo/t430s/acpi/platform.asl | 4 --- - src/mainboard/lenovo/t430s/dsdt.asl | 1 - - src/mainboard/lenovo/t520/acpi/platform.asl | 4 --- - src/mainboard/lenovo/t520/dsdt.asl | 1 - - src/mainboard/lenovo/t530/acpi/platform.asl | 4 --- - src/mainboard/lenovo/t530/dsdt.asl | 1 - - src/mainboard/lenovo/x131e/acpi/platform.asl | 4 --- - src/mainboard/lenovo/x131e/dsdt.asl | 1 - - .../lenovo/x1_carbon_gen1/acpi/platform.asl | 4 --- - src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl | 1 - - src/mainboard/lenovo/x201/acpi/platform.asl | 4 --- - src/mainboard/lenovo/x201/dsdt.asl | 1 - - src/mainboard/lenovo/x220/acpi/platform.asl | 4 --- - src/mainboard/lenovo/x220/dsdt.asl | 1 - - src/mainboard/lenovo/x230/acpi/platform.asl | 4 --- - src/mainboard/lenovo/x230/dsdt.asl | 1 - - 30 files changed, 8 insertions(+), 84 deletions(-) - -diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl -index bf9b653e12..54f4f922bd 100644 ---- a/src/ec/lenovo/h8/acpi/thermal.asl -+++ b/src/ec/lenovo/h8/acpi/thermal.asl -@@ -4,11 +4,6 @@ - - Scope(\_TZ) - { --#if defined(EC_LENOVO_H8_ME_WORKAROUND) -- Name (MEB1, 0) -- Name (MEB2, 0) --#endif -- - Method(C2K, 1, NotSerialized) - { - Local0 = Arg0 * 10 -@@ -71,14 +66,12 @@ External (\PPKG, MethodObj) - } - - Method(_TMP) { --#if defined(EC_LENOVO_H8_ME_WORKAROUND) -- /* Avoid tripping alarm if ME isn't booted at all yet */ -- If (!MEB1 && \_SB.PCI0.LPCB.EC.TMP0 == 128) { -+ Local0 = \_SB.PCI0.LPCB.EC.TMP0 -+ /* Avoid tripping alarm if invalid value reported */ -+ If (Local0 == 128) { - Return (C2K(40)) - } -- MEB1 = 1 --#endif -- Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) -+ Return (C2K(Local0)) - } - - Method (_AC0) { -@@ -158,14 +151,12 @@ External (\PPKG, MethodObj) - } - - Method(_TMP) { --#if defined(EC_LENOVO_H8_ME_WORKAROUND) -- /* Avoid tripping alarm if ME isn't booted at all yet */ -- If (!MEB2 && \_SB.PCI0.LPCB.EC.TMP1 == 128) { -+ Local0 = \_SB.PCI0.LPCB.EC.TMP1 -+ /* Avoid tripping alarm if invalid value reported */ -+ If (Local0 == 128) { - Return (C2K(40)) - } -- MEB2 = 1 --#endif -- Return (C2K(\_SB.PCI0.LPCB.EC.TMP1)) -+ Return (C2K(Local0)) - } - } - #endif -diff --git a/src/mainboard/lenovo/haswell/acpi/platform.asl b/src/mainboard/lenovo/haswell/acpi/platform.asl -index f5a4df75f4..42587fd78a 100644 ---- a/src/mainboard/lenovo/haswell/acpi/platform.asl -+++ b/src/mainboard/lenovo/haswell/acpi/platform.asl -@@ -2,9 +2,6 @@ - - Method(_WAK,1) - { -- /* ME may not be up yet. */ -- \_TZ.MEB1 = 0 -- \_TZ.MEB2 = 0 - Return(Package(){0,0}) - } - -diff --git a/src/mainboard/lenovo/haswell/dsdt.asl b/src/mainboard/lenovo/haswell/dsdt.asl -index a7afeee766..708f524b08 100644 ---- a/src/mainboard/lenovo/haswell/dsdt.asl -+++ b/src/mainboard/lenovo/haswell/dsdt.asl -@@ -2,7 +2,6 @@ - - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - #define THINKPAD_EC_GPE 17 - - #include -diff --git a/src/mainboard/lenovo/l520/acpi/platform.asl b/src/mainboard/lenovo/l520/acpi/platform.asl -index c4becafc2a..9dee90edc3 100644 ---- a/src/mainboard/lenovo/l520/acpi/platform.asl -+++ b/src/mainboard/lenovo/l520/acpi/platform.asl -@@ -15,10 +15,6 @@ Method(_PTS,1) - - Method(_WAK,1) - { -- /* ME may not be up yet. */ -- \_TZ.MEB1 = 0 -- \_TZ.MEB2 = 0 -- - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - -diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl -index 06cffcf8a2..18e9f25a9a 100644 ---- a/src/mainboard/lenovo/l520/dsdt.asl -+++ b/src/mainboard/lenovo/l520/dsdt.asl -@@ -3,7 +3,6 @@ - #define THINKPAD_EC_GPE 22 - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - - #include - DefinitionBlock( -diff --git a/src/mainboard/lenovo/s230u/dsdt.asl b/src/mainboard/lenovo/s230u/dsdt.asl -index 861309b8e9..47e91fdb30 100644 ---- a/src/mainboard/lenovo/s230u/dsdt.asl -+++ b/src/mainboard/lenovo/s230u/dsdt.asl -@@ -3,7 +3,6 @@ - #define THINKPAD_EC_GPE 23 - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - - #include - DefinitionBlock( -diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl -index f9c682f9dc..cb824e42da 100644 ---- a/src/mainboard/lenovo/t400/dsdt.asl -+++ b/src/mainboard/lenovo/t400/dsdt.asl -@@ -3,7 +3,6 @@ - #define THINKPAD_EC_GPE 17 - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - - #include - DefinitionBlock( -diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl -index 42a10e605c..e2571f60c7 100644 ---- a/src/mainboard/lenovo/t410/dsdt.asl -+++ b/src/mainboard/lenovo/t410/dsdt.asl -@@ -3,7 +3,6 @@ - #define THINKPAD_EC_GPE 17 - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - - #include - DefinitionBlock( -diff --git a/src/mainboard/lenovo/t420/acpi/platform.asl b/src/mainboard/lenovo/t420/acpi/platform.asl -index c4becafc2a..9dee90edc3 100644 ---- a/src/mainboard/lenovo/t420/acpi/platform.asl -+++ b/src/mainboard/lenovo/t420/acpi/platform.asl -@@ -15,10 +15,6 @@ Method(_PTS,1) - - Method(_WAK,1) - { -- /* ME may not be up yet. */ -- \_TZ.MEB1 = 0 -- \_TZ.MEB2 = 0 -- - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - -diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl -index 33b6f80b17..1134782675 100644 ---- a/src/mainboard/lenovo/t420/dsdt.asl -+++ b/src/mainboard/lenovo/t420/dsdt.asl -@@ -3,7 +3,6 @@ - #define THINKPAD_EC_GPE 17 - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - - #include - DefinitionBlock( -diff --git a/src/mainboard/lenovo/t420s/acpi/platform.asl b/src/mainboard/lenovo/t420s/acpi/platform.asl -index c4becafc2a..9dee90edc3 100644 ---- a/src/mainboard/lenovo/t420s/acpi/platform.asl -+++ b/src/mainboard/lenovo/t420s/acpi/platform.asl -@@ -15,10 +15,6 @@ Method(_PTS,1) - - Method(_WAK,1) - { -- /* ME may not be up yet. */ -- \_TZ.MEB1 = 0 -- \_TZ.MEB2 = 0 -- - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - -diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl -index 33b6f80b17..1134782675 100644 ---- a/src/mainboard/lenovo/t420s/dsdt.asl -+++ b/src/mainboard/lenovo/t420s/dsdt.asl -@@ -3,7 +3,6 @@ - #define THINKPAD_EC_GPE 17 - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - - #include - DefinitionBlock( -diff --git a/src/mainboard/lenovo/t430/acpi/platform.asl b/src/mainboard/lenovo/t430/acpi/platform.asl -index c4becafc2a..9dee90edc3 100644 ---- a/src/mainboard/lenovo/t430/acpi/platform.asl -+++ b/src/mainboard/lenovo/t430/acpi/platform.asl -@@ -15,10 +15,6 @@ Method(_PTS,1) - - Method(_WAK,1) - { -- /* ME may not be up yet. */ -- \_TZ.MEB1 = 0 -- \_TZ.MEB2 = 0 -- - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - -diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl -index c19e75ee82..795f9a1ee9 100644 ---- a/src/mainboard/lenovo/t430/dsdt.asl -+++ b/src/mainboard/lenovo/t430/dsdt.asl -@@ -3,7 +3,6 @@ - #define THINKPAD_EC_GPE 17 - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - - #include - DefinitionBlock( -diff --git a/src/mainboard/lenovo/t430s/acpi/platform.asl b/src/mainboard/lenovo/t430s/acpi/platform.asl -index c4becafc2a..9dee90edc3 100644 ---- a/src/mainboard/lenovo/t430s/acpi/platform.asl -+++ b/src/mainboard/lenovo/t430s/acpi/platform.asl -@@ -15,10 +15,6 @@ Method(_PTS,1) - - Method(_WAK,1) - { -- /* ME may not be up yet. */ -- \_TZ.MEB1 = 0 -- \_TZ.MEB2 = 0 -- - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - -diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl -index 33b6f80b17..1134782675 100644 ---- a/src/mainboard/lenovo/t430s/dsdt.asl -+++ b/src/mainboard/lenovo/t430s/dsdt.asl -@@ -3,7 +3,6 @@ - #define THINKPAD_EC_GPE 17 - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - - #include - DefinitionBlock( -diff --git a/src/mainboard/lenovo/t520/acpi/platform.asl b/src/mainboard/lenovo/t520/acpi/platform.asl -index c4becafc2a..9dee90edc3 100644 ---- a/src/mainboard/lenovo/t520/acpi/platform.asl -+++ b/src/mainboard/lenovo/t520/acpi/platform.asl -@@ -15,10 +15,6 @@ Method(_PTS,1) - - Method(_WAK,1) - { -- /* ME may not be up yet. */ -- \_TZ.MEB1 = 0 -- \_TZ.MEB2 = 0 -- - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - -diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl -index 33b6f80b17..1134782675 100644 ---- a/src/mainboard/lenovo/t520/dsdt.asl -+++ b/src/mainboard/lenovo/t520/dsdt.asl -@@ -3,7 +3,6 @@ - #define THINKPAD_EC_GPE 17 - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - - #include - DefinitionBlock( -diff --git a/src/mainboard/lenovo/t530/acpi/platform.asl b/src/mainboard/lenovo/t530/acpi/platform.asl -index c4becafc2a..9dee90edc3 100644 ---- a/src/mainboard/lenovo/t530/acpi/platform.asl -+++ b/src/mainboard/lenovo/t530/acpi/platform.asl -@@ -15,10 +15,6 @@ Method(_PTS,1) - - Method(_WAK,1) - { -- /* ME may not be up yet. */ -- \_TZ.MEB1 = 0 -- \_TZ.MEB2 = 0 -- - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - -diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl -index 33b6f80b17..1134782675 100644 ---- a/src/mainboard/lenovo/t530/dsdt.asl -+++ b/src/mainboard/lenovo/t530/dsdt.asl -@@ -3,7 +3,6 @@ - #define THINKPAD_EC_GPE 17 - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - - #include - DefinitionBlock( -diff --git a/src/mainboard/lenovo/x131e/acpi/platform.asl b/src/mainboard/lenovo/x131e/acpi/platform.asl -index c4becafc2a..9dee90edc3 100644 ---- a/src/mainboard/lenovo/x131e/acpi/platform.asl -+++ b/src/mainboard/lenovo/x131e/acpi/platform.asl -@@ -15,10 +15,6 @@ Method(_PTS,1) - - Method(_WAK,1) - { -- /* ME may not be up yet. */ -- \_TZ.MEB1 = 0 -- \_TZ.MEB2 = 0 -- - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - -diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl -index 34391416f3..dc9878030e 100644 ---- a/src/mainboard/lenovo/x131e/dsdt.asl -+++ b/src/mainboard/lenovo/x131e/dsdt.asl -@@ -3,7 +3,6 @@ - #define THINKPAD_EC_GPE 22 - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - - #include - DefinitionBlock( -diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl b/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl -index c4becafc2a..9dee90edc3 100644 ---- a/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl -+++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl -@@ -15,10 +15,6 @@ Method(_PTS,1) - - Method(_WAK,1) - { -- /* ME may not be up yet. */ -- \_TZ.MEB1 = 0 -- \_TZ.MEB2 = 0 -- - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - -diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl -index 6838b5e9a6..18a47960f4 100644 ---- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl -+++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl -@@ -3,7 +3,6 @@ - #define THINKPAD_EC_GPE 17 - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - #define EC_LENOVO_H8_ALT_FN_F2F3_LAYOUT 1 - - #include -diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl -index f17adafc88..a238248886 100644 ---- a/src/mainboard/lenovo/x201/acpi/platform.asl -+++ b/src/mainboard/lenovo/x201/acpi/platform.asl -@@ -15,10 +15,6 @@ Method(_PTS,1) - - Method(_WAK,1) - { -- /* ME may not be up yet. */ -- \_TZ.MEB1 = 0 -- \_TZ.MEB2 = 0 -- - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - -diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl -index 42a10e605c..e2571f60c7 100644 ---- a/src/mainboard/lenovo/x201/dsdt.asl -+++ b/src/mainboard/lenovo/x201/dsdt.asl -@@ -3,7 +3,6 @@ - #define THINKPAD_EC_GPE 17 - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - - #include - DefinitionBlock( -diff --git a/src/mainboard/lenovo/x220/acpi/platform.asl b/src/mainboard/lenovo/x220/acpi/platform.asl -index c4becafc2a..9dee90edc3 100644 ---- a/src/mainboard/lenovo/x220/acpi/platform.asl -+++ b/src/mainboard/lenovo/x220/acpi/platform.asl -@@ -15,10 +15,6 @@ Method(_PTS,1) - - Method(_WAK,1) - { -- /* ME may not be up yet. */ -- \_TZ.MEB1 = 0 -- \_TZ.MEB2 = 0 -- - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - -diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl -index 33b6f80b17..1134782675 100644 ---- a/src/mainboard/lenovo/x220/dsdt.asl -+++ b/src/mainboard/lenovo/x220/dsdt.asl -@@ -3,7 +3,6 @@ - #define THINKPAD_EC_GPE 17 - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - - #include - DefinitionBlock( -diff --git a/src/mainboard/lenovo/x230/acpi/platform.asl b/src/mainboard/lenovo/x230/acpi/platform.asl -index c4becafc2a..9dee90edc3 100644 ---- a/src/mainboard/lenovo/x230/acpi/platform.asl -+++ b/src/mainboard/lenovo/x230/acpi/platform.asl -@@ -15,10 +15,6 @@ Method(_PTS,1) - - Method(_WAK,1) - { -- /* ME may not be up yet. */ -- \_TZ.MEB1 = 0 -- \_TZ.MEB2 = 0 -- - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - -diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl -index 33b6f80b17..1134782675 100644 ---- a/src/mainboard/lenovo/x230/dsdt.asl -+++ b/src/mainboard/lenovo/x230/dsdt.asl -@@ -3,7 +3,6 @@ - #define THINKPAD_EC_GPE 17 - #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB - #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB --#define EC_LENOVO_H8_ME_WORKAROUND 1 - - #include - DefinitionBlock( --- -2.39.5 - diff --git a/config/coreboot/default/patches/0039-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/coreboot/default/patches/0039-hp-8300cmt-remove-xhci_overcurrent_mapping.patch new file mode 100644 index 00000000..4dc78bdc --- /dev/null +++ b/config/coreboot/default/patches/0039-hp-8300cmt-remove-xhci_overcurrent_mapping.patch @@ -0,0 +1,42 @@ +From 521518c2b9fe32f77937cbd4ff1942f148b1c0f3 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 22 Apr 2025 10:21:59 +0100 +Subject: [PATCH 39/41] hp/8300cmt: remove xhci_overcurrent_mapping + +No longer needed, as per the following commit: + +commit a3d1e6c4806e6c0e2e744be3a03fce12f21778d1 +Author: Keith Hui +Date: Tue Dec 31 18:19:31 2024 -0500 + + sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping + +Removing this from the devicetree also allows the +board to compile, otherwise an error is thrown: + +build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:10: error: 'const struct southbridge_intel_bd82x6x_config' has no member named 'xhci_overcurrent_mapping' + 147 | .xhci_overcurrent_mapping = 0x00000c03, + | ^~~~~~~~~~~~~~~~~~~~~~~~ +build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:37: error: excess elements in struct initializer [-Werror] + 147 | .xhci_overcurrent_mapping = 0x00000c03, + +Signed-off-by: Leah Rowe +--- + src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb +index 3d21739b72..3a0b6d5c59 100644 +--- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb +@@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" +- register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 0, 0 }, +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0040-ec-lenovo-Add-support-for-MEC1653-EC.patch b/config/coreboot/default/patches/0040-ec-lenovo-Add-support-for-MEC1653-EC.patch deleted file mode 100644 index 8972e90e..00000000 --- a/config/coreboot/default/patches/0040-ec-lenovo-Add-support-for-MEC1653-EC.patch +++ /dev/null @@ -1,371 +0,0 @@ -From c88b371cb56046f79710143866562e119a8318ca Mon Sep 17 00:00:00 2001 -From: Matt DeVillier -Date: Fri, 11 Jul 2025 16:11:47 -0500 -Subject: [PATCH 40/43] ec/lenovo: Add support for MEC1653 EC - -Add support for the MEC1653 EC as used by the Thinkpad T480/480s. - -Change-Id: If82a7d27eb3163f51565c0c6e60cab60753611a7 -Signed-off-by: Matt DeVillier ---- - src/ec/lenovo/mec1653/Kconfig | 11 ++ - src/ec/lenovo/mec1653/Makefile.mk | 8 ++ - src/ec/lenovo/mec1653/mec1653.c | 207 ++++++++++++++++++++++++++++++ - src/ec/lenovo/mec1653/mec1653.h | 98 ++++++++++++++ - 4 files changed, 324 insertions(+) - create mode 100644 src/ec/lenovo/mec1653/Kconfig - create mode 100644 src/ec/lenovo/mec1653/Makefile.mk - create mode 100644 src/ec/lenovo/mec1653/mec1653.c - create mode 100644 src/ec/lenovo/mec1653/mec1653.h - -diff --git a/src/ec/lenovo/mec1653/Kconfig b/src/ec/lenovo/mec1653/Kconfig -new file mode 100644 -index 0000000000..858f13897b ---- /dev/null -+++ b/src/ec/lenovo/mec1653/Kconfig -@@ -0,0 +1,11 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+config EC_LENOVO_MEC1653 -+ bool -+ -+if EC_LENOVO_MEC1653 -+ -+config MEC1653_SEND_DEBUG_UNLOCK -+ bool -+ -+endif -diff --git a/src/ec/lenovo/mec1653/Makefile.mk b/src/ec/lenovo/mec1653/Makefile.mk -new file mode 100644 -index 0000000000..4cb4b20cbb ---- /dev/null -+++ b/src/ec/lenovo/mec1653/Makefile.mk -@@ -0,0 +1,8 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+ifeq ($(CONFIG_EC_LENOVO_MEC1653),y) -+ -+bootblock-y += mec1653.c -+ramstage-y += mec1653.c -+ -+endif -diff --git a/src/ec/lenovo/mec1653/mec1653.c b/src/ec/lenovo/mec1653/mec1653.c -new file mode 100644 -index 0000000000..098ae47425 ---- /dev/null -+++ b/src/ec/lenovo/mec1653/mec1653.c -@@ -0,0 +1,207 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include "mec1653.h" -+ -+#define MICROCHIP_CONFIGURATION_ENTRY_KEY 0x55 -+#define MICROCHIP_CONFIGURATION_EXIT_KEY 0xaa -+ -+#define UART_PORT 0x3f8 -+#define UART_IRQ 4 -+ -+// RW unlock key for EC version N24HT37W -+const uint8_t debug_rw_key[8] = { 0x7a, 0x41, 0xb1, 0x49, 0xfe, 0x21, 0x01, 0xcf }; -+ -+void microchip_pnp_enter_conf_state(uint16_t port) -+{ -+ outb(MICROCHIP_CONFIGURATION_ENTRY_KEY, port); -+} -+ -+void microchip_pnp_exit_conf_state(uint16_t port) -+{ -+ outb(MICROCHIP_CONFIGURATION_EXIT_KEY, port); -+} -+ -+uint8_t pnp_read(uint16_t port, uint8_t index) -+{ -+ outb(index, port); -+ return inb(port + 1); -+} -+ -+uint32_t pnp_read_le32(uint16_t port, uint8_t index) -+{ -+ return (uint32_t) pnp_read(port, index) | -+ (uint32_t) pnp_read(port, index + 1) << 8 | -+ (uint32_t) pnp_read(port, index + 2) << 16 | -+ (uint32_t) pnp_read(port, index + 3) << 24; -+} -+ -+void pnp_write(uint16_t port, uint8_t index, uint8_t value) -+{ -+ outb(index, port); -+ outb(value, port + 1); -+} -+ -+void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value) -+{ -+ pnp_write(port, index, value & 0xff); -+ pnp_write(port, index + 1, value >> 8 & 0xff); -+ pnp_write(port, index + 2, value >> 16 & 0xff); -+ pnp_write(port, index + 3, value >> 24 & 0xff); -+} -+ -+static void ecN_clear_out_queue(uint16_t cmd_port, uint16_t data_port) -+{ -+ while (inb(cmd_port) & EC_OBF) -+ inb(data_port); -+} -+ -+static void ecN_wait_to_send(uint16_t cmd_port, uint16_t data_port) -+{ -+ while (inb(cmd_port) & EC_IBF) -+ ; -+} -+ -+static void ecN_wait_to_recv(uint16_t cmd_port, uint16_t data_port) -+{ -+ while (!(inb(cmd_port) & EC_OBF)) -+ ; -+} -+ -+uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr) -+{ -+ ecN_clear_out_queue(cmd_port, data_port); -+ ecN_wait_to_send(cmd_port, data_port); -+ outb(EC_READ, cmd_port); -+ ecN_wait_to_send(cmd_port, data_port); -+ outb(addr, data_port); -+ ecN_wait_to_recv(cmd_port, data_port); -+ return inb(data_port); -+} -+ -+void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val) -+{ -+ ecN_clear_out_queue(cmd_port, data_port); -+ ecN_wait_to_send(cmd_port, data_port); -+ outb(EC_WRITE, cmd_port); -+ ecN_wait_to_send(cmd_port, data_port); -+ outb(addr, data_port); -+ ecN_wait_to_send(cmd_port, data_port); -+ outb(val, data_port); -+} -+ -+uint8_t eeprom_read(uint16_t addr) -+{ -+ ecN_clear_out_queue(EC2_CMD, EC2_DATA); -+ ecN_wait_to_send(EC2_CMD, EC2_DATA); -+ outl(1, EC2_CMD); -+ ecN_wait_to_send(EC2_CMD, EC2_DATA); -+ outl(addr, EC2_DATA); -+ ecN_wait_to_recv(EC2_CMD, EC2_DATA); -+ return inl(EC2_DATA); -+} -+ -+void eeprom_write(uint16_t addr, uint8_t val) -+{ -+ ecN_clear_out_queue(EC2_CMD, EC2_DATA); -+ ecN_wait_to_send(EC2_CMD, EC2_DATA); -+ outl(2, EC2_CMD); -+ ecN_wait_to_send(EC2_CMD, EC2_DATA); -+ outl((uint32_t) addr | (uint32_t) val << 16, EC2_DATA); -+ ecN_wait_to_recv(EC2_CMD, EC2_DATA); -+ inl(EC2_DATA); -+} -+ -+uint16_t debug_loaded_keys(void) -+{ -+ return (uint16_t) ec0_read(0x87) << 8 | (uint16_t) ec0_read(0x86); -+} -+ -+static void debug_cmd(uint8_t cmd) -+{ -+ ec0_write(EC_DEBUG_CMD, cmd); -+ while (ec0_read(EC_DEBUG_CMD) & 0x80) -+ ; -+} -+ -+void debug_read_key(uint8_t i, uint8_t *key) -+{ -+ debug_cmd(0x80 | (i & 0xf)); -+ for (int j = 0; j < 8; ++j) -+ key[j] = ec0_read(0x3e + j); -+} -+ -+void debug_write_key(uint8_t i, const uint8_t *key) -+{ -+ for (int j = 0; j < 8; ++j) -+ ec0_write(0x3e + j, key[j]); -+ debug_cmd(0xc0 | (i & 0xf)); -+} -+ -+uint32_t debug_read_dword(uint32_t addr) -+{ -+ ecN_clear_out_queue(EC3_CMD, EC3_DATA); -+ ecN_wait_to_send(EC3_CMD, EC3_DATA); -+ outl(addr << 8 | 0xE2, EC3_DATA); -+ ecN_wait_to_recv(EC3_CMD, EC3_DATA); -+ return inl(EC3_DATA); -+} -+ -+void debug_write_dword(uint32_t addr, uint32_t val) -+{ -+ ecN_clear_out_queue(EC3_CMD, EC3_DATA); -+ ecN_wait_to_send(EC3_CMD, EC3_DATA); -+ outl(addr << 8 | 0xEA, EC3_DATA); -+ ecN_wait_to_send(EC3_CMD, EC3_DATA); -+ outl(val, EC3_DATA); -+} -+ -+static void configure_uart(uint16_t port, uint16_t iobase, uint8_t irqno) -+{ -+ microchip_pnp_enter_conf_state(port); -+ -+ // Select LPC I/F LDN -+ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF); -+ // Write UART BAR -+ pnp_write_le32(port, LPCIF_BAR_UART, (uint32_t) iobase << 16 | 0x8707); -+ // Set SIRQ4 to UART -+ pnp_write(port, LPCIF_SIRQ(irqno), LDN_UART); -+ -+ // Configure UART LDN -+ pnp_write(port, PNP_LDN_SELECT, LDN_UART); -+ pnp_write(port, UART_ACTIVATE, 0x01); -+ pnp_write(port, UART_CONFIG_SELECT, 0x00); -+ -+ microchip_pnp_exit_conf_state(port); -+ -+ if (CONFIG(MEC1653_SEND_DEBUG_UNLOCK)) { -+ // Supply debug unlock key -+ debug_write_key(DEBUG_RW_KEY_IDX, debug_rw_key); -+ -+ // Use debug writes to set UART_TX and UART_RX GPIOs -+ debug_write_dword(0xf0c400 + 0x110, 0x00001000); -+ debug_write_dword(0xf0c400 + 0x114, 0x00001000); -+ } -+} -+ -+void bootblock_ec_init(void) -+{ -+ // Tell EC via BIOS Debug Port 1 that the world isn't on fire -+ -+ // Let the EC know that BIOS code is running -+ outb(0x11, 0x86); -+ outb(0x6e, 0x86); -+ -+ // Enable accesses to EC1 interface -+ ec0_write(0, ec0_read(0) | 0x20); -+ -+ // Reset LEDs to power on state -+ // (Without this warm reboot leaves LEDs off) -+ ec0_write(0x0c, 0x80); -+ ec0_write(0x0c, 0x07); -+ ec0_write(0x0c, 0x8a); -+ -+ // Setup debug UART -+ if (CONFIG(CONSOLE_SERIAL)) -+ configure_uart(EC_CFG_PORT, UART_PORT, UART_IRQ); -+} -diff --git a/src/ec/lenovo/mec1653/mec1653.h b/src/ec/lenovo/mec1653/mec1653.h -new file mode 100644 -index 0000000000..7dc4c1f635 ---- /dev/null -+++ b/src/ec/lenovo/mec1653/mec1653.h -@@ -0,0 +1,98 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef EC_LENOVO_MEC1653_H -+#define EC_LENOVO_MEC1653_H -+ -+// EC configuration base address -+#define EC_CFG_PORT 0x4e -+ -+// Chip global registers -+#define PNP_LDN_SELECT 0x07 -+# define LDN_UART 0x07 -+# define LDN_LPCIF 0x0c -+#define EC_DEVICE_ID 0x20 -+#define EC_DEVICE_REV 0x21 -+ -+// LPC I/F registers -+#define LPCIF_SIRQ(i) (0x40 + (i)) -+ -+#define LPCIF_BAR_CFG 0x60 -+#define LPCIF_BAR_MAILBOX 0x64 -+#define LPCIF_BAR_8042 0x68 -+#define LPCIF_BAR_ACPI_EC0 0x6c -+#define LPCIF_BAR_ACPI_EC1 0x70 -+#define LPCIF_BAR_ACPI_EC2 0x74 -+#define LPCIF_BAR_ACPI_EC3 0x78 -+#define LPCIF_BAR_ACPI_PM0 0x7c -+#define LPCIF_BAR_UART 0x80 -+#define LPCIF_BAR_FAST_KYBD 0x84 -+#define LPCIF_BAR_EMBED_FLASH 0x88 -+#define LPCIF_BAR_GP_SPI 0x8c -+#define LPCIF_BAR_EMI 0x90 -+#define LPCIF_BAR_PMH7 0x94 -+#define LPCIF_BAR_PORT80_DBG0 0x98 -+#define LPCIF_BAR_PORT80_DBG1 0x9c -+#define LPCIF_BAR_RTC 0xa0 -+ -+// UART registers -+#define UART_ACTIVATE 0x30 -+#define UART_CONFIG_SELECT 0xf0 -+ -+void microchip_pnp_enter_conf_state(uint16_t port); -+void microchip_pnp_exit_conf_state(uint16_t port); -+uint8_t pnp_read(uint16_t port, uint8_t index); -+uint32_t pnp_read_le32(uint16_t port, uint8_t index); -+void pnp_write(uint16_t port, uint8_t index, uint8_t value); -+void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value); -+ -+#define EC0_CMD 0x0066 -+#define EC0_DATA 0x0062 -+#define EC1_CMD 0x1604 -+#define EC1_DATA 0x1600 -+#define EC2_CMD 0x1634 -+#define EC2_DATA 0x1630 -+#define EC3_CMD 0x161c -+#define EC3_DATA 0x1618 -+ -+#define EC_OBF (1 << 0) -+#define EC_IBF (1 << 1) -+ -+#define EC_READ 0x80 -+#define EC_WRITE 0x81 -+ -+uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr); -+ -+void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val); -+ -+// EC0 and EC1 mostly are useful with the READ/WRITE commands -+#define ec0_read(addr) ecN_read(EC0_CMD, EC0_DATA, addr) -+#define ec0_write(addr, val) ecN_write(EC0_CMD, EC0_DATA, addr, val) -+#define ec1_read(addr) ecN_read(EC1_CMD, EC1_DATA, addr) -+#define ec1_write(addr, val) ecN_write(EC1_CMD, EC1_DATA, addr, val) -+ -+// Read from the emulated EEPROM -+uint8_t eeprom_read(uint16_t addr); -+ -+// Write to the emulated EEPROM -+void eeprom_write(uint16_t addr, uint8_t val); -+ -+// Read loaded debug key mask -+uint16_t debug_loaded_keys(void); -+ -+// The following location (via either EC0 or EC1) can be used to interact with the debug interface -+#define EC_DEBUG_CMD 0x3d -+ -+void debug_read_key(uint8_t i, uint8_t *key); -+ -+void debug_write_key(uint8_t i, const uint8_t *key); -+ -+uint32_t debug_read_dword(uint32_t addr); -+ -+void debug_write_dword(uint32_t addr, uint32_t val); -+ -+// RW unlock key index -+#define DEBUG_RW_KEY_IDX 1 -+ -+void bootblock_ec_init(void); -+ -+#endif /* EC_LENOVO_MEC1653_H */ --- -2.39.5 - diff --git a/config/coreboot/default/patches/0040-lenovo-t480-Drop-redundant-PcieRpEnable.patch b/config/coreboot/default/patches/0040-lenovo-t480-Drop-redundant-PcieRpEnable.patch new file mode 100644 index 00000000..2223ec46 --- /dev/null +++ b/config/coreboot/default/patches/0040-lenovo-t480-Drop-redundant-PcieRpEnable.patch @@ -0,0 +1,113 @@ +From eb71b55d2dd7af6f6ddca5e462fc228bdb04af50 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 8 Jul 2025 17:54:57 +0100 +Subject: [PATCH 1/1] lenovo/t480: Drop redundant PcieRpEnable + +This is in line with another change from upstream, in +the recent revision update: + +commit ee30558c49c9c4622277785ee0cd54c32720e489 +Author: Nico Huber +Date: Fri Jan 12 16:22:19 2024 +0100 + + soc/intel/skylake: Drop redundant PcieRpEnable + +This change is necessary, to prevent a build error. + +Signed-off-by: Leah Rowe +--- + .../lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb | 5 ----- + .../lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb | 5 ----- + 2 files changed, 10 deletions(-) + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb +index bf66bd3a69..316dbcbe8a 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb +@@ -43,7 +43,6 @@ chip soc/intel/skylake + + # dGPU - x4 + device ref pcie_rp1 on +- register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" +@@ -61,7 +60,6 @@ chip soc/intel/skylake + + # M.2 WLAN - x1 + device ref pcie_rp7 on +- register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "2" + register "PcieRpClkSrcNumber[6]" = "2" +@@ -71,7 +69,6 @@ chip soc/intel/skylake + + # M.2 WWAN - x2 + device ref pcie_rp5 on +- register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" +@@ -81,7 +78,6 @@ chip soc/intel/skylake + + # TB3 (Alpine Ridge LP) - x2 + device ref pcie_rp9 on +- register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" + register "PcieRpClkSrcNumber[8]" = "4" +@@ -92,7 +88,6 @@ chip soc/intel/skylake + + # M.2 2280 caddy - x2 + device ref pcie_rp11 on +- register "PcieRpEnable[10]" = "1" + register "PcieRpClkReqSupport[10]" = "1" + register "PcieRpClkReqNumber[10]" = "5" + register "PcieRpClkSrcNumber[10]" = "5" +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb +index d4afca20c4..dcaf15fabf 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb +@@ -43,7 +43,6 @@ chip soc/intel/skylake + + # dGPU - x2 + device ref pcie_rp1 on +- register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" +@@ -53,7 +52,6 @@ chip soc/intel/skylake + + # M.2 WWAN - x1 + device ref pcie_rp4 on +- register "PcieRpEnable[3]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "1" +@@ -71,7 +69,6 @@ chip soc/intel/skylake + + # M.2 WLAN - x1 + device ref pcie_rp7 on +- register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "3" + register "PcieRpClkSrcNumber[6]" = "3" +@@ -81,7 +78,6 @@ chip soc/intel/skylake + + # TB3 (Alpine Ridge LP) - x2 + device ref pcie_rp5 on +- register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "4" + register "PcieRpClkSrcNumber[4]" = "4" +@@ -92,7 +88,6 @@ chip soc/intel/skylake + + # M.2 2280 SSD - x2 + device ref pcie_rp9 on +- register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + register "PcieRpClkSrcNumber[8]" = "5" +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0041-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch b/config/coreboot/default/patches/0041-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch deleted file mode 100644 index 8f9d1d97..00000000 --- a/config/coreboot/default/patches/0041-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch +++ /dev/null @@ -1,1859 +0,0 @@ -From 05d402ba24e80a164fc3f7332ef9086a4750d266 Mon Sep 17 00:00:00 2001 -From: Matt DeVillier -Date: Wed, 9 Jul 2025 12:28:48 -0500 -Subject: [PATCH 41/43] mb/lenovo: Add ThinkPad T480 and ThinkPad T480s - -These machine have BootGuard fused and requires deguard to -boot coreboot. - -Known issues: -- Alpine Ridge Thunderbolt 3 controller does not work -- Some Fn+F{1-12} keys aren't handled correctly -- Nvidia dGPU is finicky - - Needs option ROM - - Power enable code is buggy - - Nouveau only works on linux 6.8-6.9 -- Headphone jack isn't detected as plugged in despite correct verbs - -Thanks to Leah Rowe for helping with the T480s. - -Change-Id: I19d421412c771c1f242f6ff39453f824fa866163 -Signed-off-by: Mate Kukri -Signed-off-by: Matt DeVillier ---- - src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 84 ++++++++ - .../lenovo/sklkbl_thinkpad/Kconfig.name | 7 + - .../lenovo/sklkbl_thinkpad/Makefile.mk | 21 ++ - .../lenovo/sklkbl_thinkpad/acpi/ec.asl | 12 ++ - .../lenovo/sklkbl_thinkpad/acpi/superio.asl | 3 + - .../lenovo/sklkbl_thinkpad/board_info.txt | 6 + - .../lenovo/sklkbl_thinkpad/bootblock.c | 9 + - src/mainboard/lenovo/sklkbl_thinkpad/cfr.c | 82 +++++++ - .../lenovo/sklkbl_thinkpad/devicetree.cb | 78 +++++++ - src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl | 33 +++ - src/mainboard/lenovo/sklkbl_thinkpad/gpio.h | 8 + - .../lenovo/sklkbl_thinkpad/ramstage.c | 87 ++++++++ - .../sklkbl_thinkpad/variants/t480/data.vbt | Bin 0 -> 4106 bytes - .../variants/t480/gma-mainboard.ads | 19 ++ - .../sklkbl_thinkpad/variants/t480/gpio.c | 203 ++++++++++++++++++ - .../sklkbl_thinkpad/variants/t480/hda_verb.c | 90 ++++++++ - .../variants/t480/memory_init_params.c | 20 ++ - .../variants/t480/overridetree.cb | 93 ++++++++ - .../sklkbl_thinkpad/variants/t480s/data.vbt | Bin 0 -> 4106 bytes - .../variants/t480s/gma-mainboard.ads | 19 ++ - .../sklkbl_thinkpad/variants/t480s/gpio.c | 199 +++++++++++++++++ - .../sklkbl_thinkpad/variants/t480s/hda_verb.c | 90 ++++++++ - .../variants/t480s/memory_init_params.c | 44 ++++ - .../variants/t480s/overridetree.cb | 93 ++++++++ - .../variants/t480s/spd/spd_0.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_1.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_10.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_11.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_12.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_13.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_14.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_15.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_16.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_17.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_18.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_19.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_2.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_20.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_3.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_4.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_5.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_6.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_7.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_8.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_9.bin | Bin 0 -> 512 bytes - 45 files changed, 1300 insertions(+) - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/cfr.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/gpio.h - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_12.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_13.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_20.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_3.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_9.bin - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -new file mode 100644 -index 0000000000..ccf43ea5c0 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -@@ -0,0 +1,84 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON -+ bool -+ select BOARD_ROMSIZE_KB_16384 -+ select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE -+ select EC_LENOVO_H8 -+ select EC_LENOVO_MEC1653 -+ select EC_LENOVO_PMH7 -+ select H8_HAS_BAT_THRESHOLDS_IMPL -+ select H8_HAS_LEDLOGO -+ select H8_HAS_PRIMARY_FN_KEYS -+ select H8_SUPPORT_BT_ON_WIFI -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select INTEL_GMA_HAVE_VBT -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_HAS_TPM2 -+ select MAINBOARD_USES_IFD_GBE_REGION -+ select MEMORY_MAPPED_TPM -+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB -+ select SOC_INTEL_KABYLAKE -+ select SPD_READ_BY_WORD -+ select SYSTEM_TYPE_LAPTOP -+ -+config BOARD_LENOVO_T480 -+ bool -+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON -+ select MEC1653_SEND_DEBUG_UNLOCK -+ -+config BOARD_LENOVO_T480S -+ bool -+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON -+ -+if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON -+ -+config MAINBOARD_DIR -+ default "lenovo/sklkbl_thinkpad" -+ -+config VARIANT_DIR -+ default "t480" if BOARD_LENOVO_T480 -+ default "t480s" if BOARD_LENOVO_T480S -+ -+config OVERRIDE_DEVICETREE -+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -+ -+config MAINBOARD_PART_NUMBER -+ default "T480" if BOARD_LENOVO_T480 -+ default "T480s" if BOARD_LENOVO_T480S -+ -+config CBFS_SIZE -+ default 0x900000 -+ -+config DIMM_MAX -+ default 2 -+ -+config DIMM_SPD_SIZE -+ default 512 # DDR4 -+ -+config CONSOLE_SERIAL -+ default n -+ -+config NO_POST -+ default y -+ -+config EDK2_BOOT_MANAGER_ESCAPE -+ default y -+ -+config EDK2_FOLLOW_BGRT_SPEC -+ default y -+ -+config EDK2_FULL_SCREEN_SETUP -+ default n -+ -+config PS2K_EISAID -+ default "LEN0071" -+ -+config PS2M_EISAID -+ default "LEN0094" -+ -+config THINKPADEC_HKEY_EISAID -+ default "LEN0268" -+ -+endif -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name -new file mode 100644 -index 0000000000..abc273f387 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name -@@ -0,0 +1,7 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_LENOVO_T480 -+ bool "ThinkPad T480" -+ -+config BOARD_LENOVO_T480S -+ bool "ThinkPad T480s" -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk -new file mode 100644 -index 0000000000..7122a232b4 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk -@@ -0,0 +1,21 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+bootblock-y += bootblock.c -+ -+romstage-y += variants/$(VARIANT_DIR)/memory_init_params.c -+ -+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c -+ramstage-y += ramstage.c -+ramstage-y += variants/$(VARIANT_DIR)/gpio.c variants/$(VARIANT_DIR)/hda_verb.c -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads -+ -+# Add files spd_0.bin to spd_20.bin to the cbfs image -+ifeq ($(CONFIG_BOARD_LENOVO_T480S),y) -+SPD_BINS := $(shell seq 0 20) -+define SPD_template -+cbfs-files-y += spd_$(1).bin -+spd_$(1).bin-file := variants/$(VARIANT_DIR)/spd/spd_$(1).bin -+spd_$(1).bin-type := raw -+endef -+$(foreach n,$(SPD_BINS),$(eval $(call SPD_template,$(n)))) -+endif -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl -new file mode 100644 -index 0000000000..3a949a2fca ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl -@@ -0,0 +1,12 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -+#define THINKPAD_EC_GPE 22 -+ -+Name(\TCRT, 100) -+Name(\TPSV, 90) -+Name(\FLVL, 0) -+ -+#include -+#include -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl -new file mode 100644 -index 0000000000..55b1db5b11 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt b/src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt -new file mode 100644 -index 0000000000..07ab6a3cd0 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt -@@ -0,0 +1,6 @@ -+Category: laptop -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2016 -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c -new file mode 100644 -index 0000000000..e1fdf18add ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+ -+void bootblock_mainboard_early_init(void) -+{ -+ bootblock_ec_init(); -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c b/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c -new file mode 100644 -index 0000000000..45f344b939 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c -@@ -0,0 +1,82 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Hide the dGPU CFR entry if dGPU not present */ -+static void update_dgpu(const struct sm_object *obj, struct sm_object *new) -+{ -+ struct device *dgpu = DEV_PTR(dgpu); -+ if (!dgpu || !dgpu->enabled) { -+ new->sm_bool.flags = CFR_OPTFLAG_SUPPRESS; -+ } -+} -+ -+/* dGPU */ -+static const struct sm_object dgpu = SM_DECLARE_ENUM({ -+ .opt_name = "dgpu_enable", -+ .ui_name = "dGPU", -+ .ui_helptext = "Enable or disable the dGPU", -+ .default_value = 0, -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}, WITH_CALLBACK(update_dgpu)); -+ -+static struct sm_obj_form system = { -+ .ui_name = "System", -+ .obj_list = (const struct sm_object *[]) { -+ &dgpu, -+ &hyper_threading, -+ &igd_dvmt, -+ &igd_aperture, -+ &legacy_8254_timer, -+ &me_state, -+ &me_state_counter, -+ &pciexp_aspm, -+ &pciexp_clk_pm, -+ &pciexp_l1ss, -+ &pciexp_speed, -+ &s0ix_enable, -+ &vtd, -+ NULL -+ }, -+}; -+ -+static struct sm_obj_form ec = { -+ .ui_name = "Embedded Controller", -+ .obj_list = (const struct sm_object *[]) { -+ &bluetooth, -+ &backlight, -+ &uwb, -+ &usb_always_on, -+ &volume, -+ &wlan, -+ &wwan, -+ &pm_beeps, -+ &battery_beep, -+ &fn_ctrl_swap, -+ &sticky_fn, -+ &f1_to_f12_as_primary, -+ &touchpad, -+ &trackpoint, -+ NULL -+ }, -+}; -+ -+static struct sm_obj_form *sm_root[] = { -+ &ec, -+ &system, -+ NULL -+}; -+ -+void mb_cfr_setup_menu(struct lb_cfr *cfr_root) -+{ -+ cfr_write_setup_menu(cfr_root, sm_root); -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb -new file mode 100644 -index 0000000000..5ec7750025 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb -@@ -0,0 +1,78 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+chip soc/intel/skylake -+ -+ # Power -+ register "PmConfigSlpS3MinAssert" = "2" # 50ms -+ register "PmConfigSlpS4MinAssert" = "1" # 1s -+ register "PmConfigSlpSusMinAssert" = "3" # 500ms -+ register "PmConfigSlpAMinAssert" = "3" # 2s -+ -+ device domain 0 on -+ subsystemid 0x17aa 0x225d inherit -+ device ref igpu on -+ register "gfx" = "GMA_STATIC_DISPLAYS(0)" -+ register "panel_cfg" = "{ -+ .up_delay_ms = 200, -+ .down_delay_ms = 50, -+ .cycle_delay_ms = 600, -+ .backlight_on_delay_ms = 1, -+ .backlight_off_delay_ms = 200, -+ .backlight_pwm_hz = 200, -+ }" -+ end -+ device ref sa_thermal on end -+ device ref thermal on end -+ device ref south_xhci on end -+ device ref sata on -+ register "SataPortsEnable[2]" = "1" -+ register "SataPortsDevSlp[2]" = "1" -+ end -+ device ref lpc_espi on -+ register "serirq_mode" = "SERIRQ_CONTINUOUS" -+ -+ register "gen1_dec" = "0x007c1601" -+ register "gen2_dec" = "0x000c15e1" -+ register "lpc_ioe" = "LPC_IOE_EC_4E_4F | -+ LPC_IOE_EC_62_66 | -+ LPC_IOE_KBC_60_64" -+ -+ chip ec/lenovo/pmh7 -+ register "backlight_enable" = "true" -+ register "dock_event_enable" = "true" -+ device pnp ff.1 on end # dummy -+ end -+ -+ chip ec/lenovo/h8 -+ register "beepmask0" = "0x00" -+ register "beepmask1" = "0x86" -+ register "config0" = "0xa6" -+ register "config1" = "0x0d" -+ register "config2" = "0xa8" -+ register "config3" = "0xc4" -+ register "has_keyboard_backlight" = "1" -+ register "event2_enable" = "0xff" -+ register "event3_enable" = "0xff" -+ register "event4_enable" = "0xd0" -+ register "event5_enable" = "0x3c" -+ register "event7_enable" = "0x01" -+ register "event8_enable" = "0x7b" -+ register "event9_enable" = "0xff" -+ register "eventc_enable" = "0xff" -+ register "eventd_enable" = "0xff" -+ register "evente_enable" = "0x9d" -+ device pnp ff.2 on # dummy -+ io 0x60 = 0x62 -+ io 0x62 = 0x66 -+ io 0x64 = 0x1600 -+ io 0x66 = 0x1604 -+ end -+ end -+ -+ chip drivers/pc80/tpm -+ device pnp 0c31.0 on end -+ end -+ end -+ device ref hda on end -+ end -+end -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl -new file mode 100644 -index 0000000000..aa4d4de2a6 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl -@@ -0,0 +1,33 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20110725 -+) -+{ -+ #include -+ #include -+ #include -+ -+ Device (\_SB.PCI0) -+ { -+ #include -+ #include -+ #include -+ } -+ -+ Scope (\_SB.PCI0.RP01) -+ { -+ Device (PEGP) -+ { -+ Name (_ADR, Zero) -+ } -+ } -+ -+ #include -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h -new file mode 100644 -index 0000000000..d89ed712d4 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h -@@ -0,0 +1,8 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef GPIO_H -+#define GPIO_H -+ -+void variant_config_gpios(void); -+ -+#endif -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c -new file mode 100644 -index 0000000000..eb582a7948 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c -@@ -0,0 +1,87 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "gpio.h" -+ -+#define GPIO_GPU_RST GPP_E22 // active low -+#define GPIO_1R8VIDEO_AON_ON GPP_E23 -+ -+#define GPIO_DGFX_PWRGD GPP_F3 -+ -+#define GPIO_DISCRETE_PRESENCE GPP_D9 // active low -+#define GPIO_DGFX_VRAM_ID0 GPP_D11 -+#define GPIO_DGFX_VRAM_ID1 GPP_D12 -+ -+void mainboard_silicon_init_params(FSP_SIL_UPD *params) -+{ -+ // Setup GPIOs -+ variant_config_gpios(); -+} -+ -+static void mainboard_fill_ssdt(const struct device *dev) -+{ -+ struct rom_header *rom; -+ struct device *dgpu = DEV_PTR(dgpu); -+ -+ /* Add entry for dGPU if present/enabled */ -+ if (!dgpu || !dgpu->enabled) -+ return; -+ -+ /* ROM should be already loaded? */ -+ rom = dgpu->pci_vga_option_rom; -+ if (!rom) { -+ rom = pci_rom_probe(dgpu); -+ if (!pci_rom_load(dgpu, rom)) -+ return; -+ } -+ -+ acpigen_write_scope("\\_SB.PCI0.RP01.PEGP"); -+ acpigen_write_rom((void *)rom, rom->size * 512); -+ acpigen_pop_len(); -+} -+ -+static void dgpu_detect(void) -+{ -+ static const char * const dgfx_vram_id_str[] = { "1GB", "2GB", "4GB", "N/A" }; -+ -+ int dgfx_vram_id; -+ -+ // Detect and enable dGPU -+ if (gpio_get(GPIO_DISCRETE_PRESENCE) == 0) { // active low -+ dgfx_vram_id = gpio_get(GPIO_DGFX_VRAM_ID0) | gpio_get(GPIO_DGFX_VRAM_ID1) << 1; -+ printk(BIOS_DEBUG, "Discrete GPU present with %s VRAM\n", dgfx_vram_id_str[dgfx_vram_id]); -+ -+ // NOTE: i pulled this GPU enable sequence from thin air -+ // it sometimes works but is buggy and the GPU disappears in some cases so disabling it by default. -+ // also unrelated to this enable sequence the nouveau driver only works on 6.8-6.9 kernels -+ if (get_uint_option("dgpu_enable", 0)) { -+ printk(BIOS_DEBUG, "Enabling discrete GPU\n"); -+ gpio_set(GPIO_1R8VIDEO_AON_ON, 1); // Enable GPU power rail -+ while (!gpio_get(GPIO_DGFX_PWRGD)) // Wait for power good signal from GPU -+ ; -+ gpio_set(GPIO_GPU_RST, 1); // Release GPU from reset -+ } else { -+ printk(BIOS_DEBUG, "Discrete GPU will remain disabled\n"); -+ } -+ -+ } else { -+ printk(BIOS_DEBUG, "Discrete GPU not present\n"); -+ } -+} -+ -+static void mainboard_enable(struct device *dev) -+{ -+ dgpu_detect(); -+ -+ dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; -+} -+ -+struct chip_operations mainboard_ops = { -+ .enable_dev = mainboard_enable, -+}; -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..4db4202961d0be67b75f52b28f2111d5655595c3 -GIT binary patch -literal 4106 -zcmeHJU2GIp6h5=FKeKmc=rAo()>4l^U|XP_ZDGYy!|YE>mu}hZ4|PdQy1bV0gipVB&+pHzmFpc`=IXxii}qiqH*)7}PU+ -z?woV)x!<09?wNbfhQa6n_IK}3M!Gw&OgS)sY2Q$LJ4F+z{-JneATkt9refXr6+8sr -zR{e1eASVcGl#mf_O&p%I^1;3af=xDeN0ZnydT=;zHOH-q=O;(UFda)^LXW8| -z-Vsanq!Y==Kq9plQ+*gu^hf&pJ9?tY{h01cbtR&SfsVM!_*!D4W5>papLuo?gRur| -zF$`lX;f2t48Dpd4V@(*z=dq95OkkfiVU53N<(gE+=U)KHEdU4}@R=aMjTTTOcb8-a -zC9IXSxZB*|#u~SlHnpsY25L#Sxy6ljl16gI)H0f>for?qaszCX;ESpG=pqROFWR~Z -zTqQzcH(berra`9K(R~0OJ_eeA=> -z&R-)LYP^U3@%6h}+0)7m-mEOhOM92l32>zpvu-&@ZkPf<>~Bsv&Oy1O(`pbLUf3vt*0HIRk0U3EzI -zIeSaIE9*jps%6qP7$EQo8=K#f^K_mFpy5prkNNSOU;oI@KK0}Ge*G6eyWz+6OyADf -zE`}Db#-81u-uS=OJB*=`v}WPMs@ugdtLtbZo6OEUf}>!QL` -z1zQ!pLt!Zek0|;p3VTDrj}`q(g?+8yuZk|KY?X>TRlP@LPpbH`s-ITbSygS+Jq6cQ -zp|Em=T_#B53Y|R}mtw!K3mUyWRhytxx_wi^(}HurDkx@L%OlKIA%rq@7%bE{p{Wl~ -zJJ%lV6&>fxBjnbA8G(&P?a8o%P#c~Wo$7|%1UE-$r;6jwt1uejOfMLwF-BDgC-Q+N -za!Hx;1S&$9!rlNCTsI*IMZ0#Y5aEO7sjIz#jb`S|q7OpRYx`h&=PK}_YnN#poNF=7 -z3yTO|pc0N&G3cozl21Q6c)l0vjm~0uFL)%2_T5RYR1$~dO~u)4px!jFycZNnchPVA -z!0+Vc_afL{m>rv2PY8{Cma`W{yG~JNJu?;L!#fSLmwRW{8R@gD7Z5~{xvZGpN)U`j -z^I~=;XVmtVzgSv@Na@HC?lC8A1l2+CU Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c -new file mode 100644 -index 0000000000..f7c29e1f39 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c -@@ -0,0 +1,203 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include "../../gpio.h" -+ -+/* FIXME: There are multiple GPIOs here that should be locked to prevent "TPM GPIO fail" style -+ * attacks. Unfortunately SKL/KBL GPIO locking *does not* work currently. */ -+ -+static const struct pad_config gpio_table[] = { -+ -+ /* ------- GPIO Community 0 ------- */ -+ -+ /* ------- GPIO Group GPP_A ------- */ -+ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */ -+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */ -+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */ -+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */ -+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */ -+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */ -+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */ -+ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */ -+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */ -+ PAD_CFG_NF(GPP_A9, NATIVE, DEEP, NF1), /* LPCCLK_EC_24M */ -+ PAD_CFG_NF(GPP_A10, NATIVE, DEEP, NF1), /* LPCCLK_DEBUG_24M */ -+ PAD_NC(GPP_A11, NONE), -+ PAD_NC(GPP_A12, NONE), -+ PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */ -+ PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */ -+ PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSWARN */ -+ PAD_NC(GPP_A16, NONE), -+ PAD_NC(GPP_A17, NONE), -+ PAD_NC(GPP_A18, NONE), -+ PAD_NC(GPP_A19, NONE), -+ PAD_NC(GPP_A20, NONE), -+ PAD_NC(GPP_A21, NONE), -+ PAD_NC(GPP_A22, NONE), -+ PAD_NC(GPP_A23, NONE), -+ -+ /* ------- GPIO Group GPP_B ------- */ -+ PAD_NC(GPP_B0, NONE), -+ PAD_NC(GPP_B1, NONE), -+ PAD_NC(GPP_B2, NONE), -+ PAD_NC(GPP_B3, NONE), -+ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */ -+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 */ -+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 */ -+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 */ -+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 */ -+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 */ -+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE10 */ -+ PAD_NC(GPP_B11, NONE), -+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */ -+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */ -+ PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */ -+ PAD_CFG_GPO(GPP_B15, 1, DEEP), /* NFC_DLREQ */ -+ PAD_NC(GPP_B16, NONE), -+ PAD_NC(GPP_B17, NONE), -+ PAD_NC(GPP_B18, NONE), -+ PAD_NC(GPP_B19, NONE), -+ PAD_NC(GPP_B20, NONE), -+ PAD_NC(GPP_B21, NONE), -+ PAD_NC(GPP_B22, NONE), -+ PAD_NC(GPP_B23, NONE), -+ -+ /* ------- GPIO Community 1 ------- */ -+ -+ /* ------- GPIO Group GPP_C ------- */ -+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ -+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ -+ PAD_NC(GPP_C2, NONE), -+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */ -+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ -+ PAD_NC(GPP_C5, NONE), -+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */ -+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */ -+ PAD_NC(GPP_C8, NONE), -+ PAD_NC(GPP_C9, NONE), -+ PAD_NC(GPP_C10, NONE), -+ PAD_NC(GPP_C11, NONE), -+ PAD_NC(GPP_C12, NONE), -+ PAD_NC(GPP_C13, NONE), -+ PAD_NC(GPP_C14, NONE), -+ PAD_NC(GPP_C15, NONE), -+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */ -+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */ -+ PAD_NC(GPP_C18, NONE), -+ PAD_NC(GPP_C19, NONE), -+ PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ -+ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ -+ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ -+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ -+ -+ /* ------- GPIO Group GPP_D ------- */ -+ PAD_NC(GPP_D0, NONE), -+ PAD_NC(GPP_D1, NONE), -+ PAD_NC(GPP_D2, NONE), -+ PAD_NC(GPP_D3, NONE), -+ PAD_NC(GPP_D4, NONE), -+ PAD_NC(GPP_D5, NONE), -+ PAD_NC(GPP_D6, NONE), -+ PAD_NC(GPP_D7, NONE), -+ PAD_NC(GPP_D8, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */ -+ PAD_NC(GPP_D10, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */ -+ PAD_NC(GPP_D13, NONE), -+ PAD_NC(GPP_D14, NONE), -+ PAD_NC(GPP_D15, NONE), -+ PAD_NC(GPP_D16, NONE), -+ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY1 */ -+ PAD_NC(GPP_D18, NONE), -+ PAD_NC(GPP_D19, NONE), -+ PAD_NC(GPP_D20, NONE), -+ PAD_NC(GPP_D21, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */ -+ PAD_NC(GPP_D23, NONE), -+ -+ /* ------- GPIO Group GPP_E ------- */ -+ PAD_NC(GPP_E0, NONE), -+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -WWAN_SATA_DTCT (always HIGH) */ -+ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -PE_DTCT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */ -+ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */ -+ PAD_NC(GPP_E5, NONE), -+ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */ -+ PAD_NC(GPP_E7, NONE), -+ PAD_NC(GPP_E8, NONE), -+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 (AON port) */ -+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 (regular port) */ -+ PAD_NC(GPP_E11, NONE), -+ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */ -+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */ -+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */ -+ PAD_NC(GPP_E15, NONE), -+ PAD_NC(GPP_E16, NONE), -+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ -+ PAD_NC(GPP_E18, NONE), -+ PAD_NC(GPP_E19, NONE), -+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */ -+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */ -+ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */ -+ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */ -+ -+ /* ------- GPIO Community 2 ------- */ -+ -+ /* -------- GPIO Group GPD -------- */ -+ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */ -+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */ -+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */ -+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */ -+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */ -+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */ -+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */ -+ PAD_NC(GPD7, NONE), -+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */ -+ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */ -+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */ -+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ -+ -+ /* ------- GPIO Community 3 ------- */ -+ -+ /* ------- GPIO Group GPP_F ------- */ -+ PAD_NC(GPP_F0, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */ -+ PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, ACPI), /* DGFX_PWRGD */ -+ PAD_CFG_GPO(GPP_F4, 1, DEEP), /* -WWAN_RESET */ -+ PAD_NC(GPP_F5, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */ -+ PAD_NC(GPP_F16, NONE), -+ PAD_NC(GPP_F17, NONE), -+ PAD_NC(GPP_F18, NONE), -+ PAD_NC(GPP_F19, NONE), -+ PAD_NC(GPP_F20, NONE), -+ PAD_NC(GPP_F21, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -INTRUDER_PCH */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */ -+ -+ /* ------- GPIO Group GPP_G ------- */ -+ PAD_NC(GPP_G0, NONE), -+ PAD_NC(GPP_G1, NONE), -+ PAD_NC(GPP_G2, NONE), -+ PAD_NC(GPP_G3, NONE), -+ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ -+ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ -+ PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ -+ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ -+}; -+ -+void variant_config_gpios(void) -+{ -+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c -new file mode 100644 -index 0000000000..3a951ce0da ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c -@@ -0,0 +1,90 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ 0x10ec0257, // Vendor/Device ID: Realtek ALC257 -+ 0x17aa225d, // Subsystem ID -+ 11, -+ AZALIA_SUBVENDOR(0, 0x17aa225d), -+ -+ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( -+ AZALIA_INTEGRATED, -+ AZALIA_INTERNAL, -+ AZALIA_MIC_IN, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_NO_JACK_PRESENCE_DETECT, -+ 2, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( -+ AZALIA_INTEGRATED, -+ AZALIA_INTERNAL, -+ AZALIA_SPEAKER, -+ AZALIA_OTHER_ANALOG, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_NO_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_MIC_IN, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 3, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_HP_OUT, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 15 -+ )), -+ -+ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI -+ 0x80860101, // Subsystem ID -+ 4, -+ AZALIA_SUBVENDOR(2, 0x80860101), -+ -+ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 2, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 3, 0 -+ )), -+}; -+ -+const u32 pc_beep_verbs[] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c -new file mode 100644 -index 0000000000..5252a402f9 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c -@@ -0,0 +1,20 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+ -+void mainboard_memory_init_params(FSPM_UPD *mupd) -+{ -+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; -+ mem_cfg->DqPinsInterleaved = true; /* DDR_DQ in interleave mode */ -+ mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */ -+ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; -+ -+ /* Get SPD for memory slots */ -+ struct spd_block blk = { .addr_map = { 0x50, 0x51, } }; -+ get_spd_smbus(&blk); -+ dump_spd_info(&blk); -+ -+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; -+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb -new file mode 100644 -index 0000000000..9acb823c10 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb -@@ -0,0 +1,93 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+chip soc/intel/skylake -+ device domain 0 on -+ device ref south_xhci on -+ register "usb2_ports" = "{ -+ [0] = USB2_PORT_MID(OC1), // USB-A -+ [1] = USB2_PORT_MID(OC0), // USB-A (always on) -+ [2] = USB2_PORT_MID(OC_SKIP), // JSC-1 (smartcard slot) -+ [3] = USB2_PORT_MID(OC_SKIP), // USB-C (charging port) -+ [4] = USB2_PORT_MID(OC_SKIP), // JCAM1 (IR camera) -+ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN1 (M.2 WWAN USB) -+ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN1 (M.2 WLAN USB) -+ [7] = USB2_PORT_MID(OC_SKIP), // JCAM1 (webcam) -+ [8] = USB2_PORT_MID(OC_SKIP), // JFPR1 (fingerprint reader) -+ [9] = USB2_PORT_MID(OC_SKIP), // JLCD1 (touch panel) -+ }" -+ register "usb3_ports" = "{ -+ [0] = USB3_PORT_DEFAULT(OC1), // USB-A -+ [1] = USB3_PORT_DEFAULT(OC0), // USB-A (always on) -+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // RTS5344S (SD card reader) -+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C (charging port) -+ }" -+ end -+ -+ # PCIe controller 1 - 1x4 -+ # PCIE 1-4 - RP1 - dGPU - CLKOUT0 - CLKREQ0 -+ # -+ # PCIe controller 2 - 2x1+1x2 (lane reversal) -+ # PCIE 5 - GBE - GBE - CLKOUT1 - CLKREQ1 (clobbers RP8) -+ # PCIE 6 - RP7 - WLAN - CLKOUT2 - CLKREQ2 -+ # PCIE 7-8 - RP5 - WWAN - CLKOUT3 - CLKREQ3 -+ # -+ # PCIe controller 3 - 2x2 -+ # PCIE 9-10 - RP9 - TB3 - CLKOUT4 - CLKREQ4 -+ # PCIE 11-12 - RP11 - SSD - CLKOUT5 - CLKREQ5 -+ -+ # dGPU - x4 -+ device ref pcie_rp1 on -+ register "PcieRpClkReqSupport[0]" = "1" -+ register "PcieRpClkReqNumber[0]" = "0" -+ register "PcieRpClkSrcNumber[0]" = "0" -+ register "PcieRpAdvancedErrorReporting[0]" = "1" -+ register "PcieRpLtrEnable[0]" = "1" -+ device generic 0 alias dgpu on end -+ end -+ -+ # Ethernet (clobbers RP8) -+ device ref gbe on -+ register "LanClkReqSupported" = "1" -+ register "LanClkReqNumber" = "1" -+ register "EnableLanLtr" = "1" -+ register "EnableLanK1Off" = "1" -+ end -+ -+ # M.2 WLAN - x1 -+ device ref pcie_rp7 on -+ register "PcieRpClkReqSupport[6]" = "1" -+ register "PcieRpClkReqNumber[6]" = "2" -+ register "PcieRpClkSrcNumber[6]" = "2" -+ register "PcieRpAdvancedErrorReporting[6]" = "1" -+ register "PcieRpLtrEnable[6]" = "1" -+ end -+ -+ # M.2 WWAN - x2 -+ device ref pcie_rp5 on -+ register "PcieRpClkReqSupport[4]" = "1" -+ register "PcieRpClkReqNumber[4]" = "3" -+ register "PcieRpClkSrcNumber[4]" = "3" -+ register "PcieRpAdvancedErrorReporting[4]" = "1" -+ register "PcieRpLtrEnable[4]" = "1" -+ end -+ -+ # TB3 (Alpine Ridge LP) - x2 -+ device ref pcie_rp9 on -+ register "PcieRpClkReqSupport[8]" = "1" -+ register "PcieRpClkReqNumber[8]" = "4" -+ register "PcieRpClkSrcNumber[8]" = "4" -+ register "PcieRpAdvancedErrorReporting[8]" = "1" -+ register "PcieRpLtrEnable[8]" = "1" -+ register "PcieRpHotPlug[8]" = "1" -+ end -+ -+ # M.2 2280 caddy - x2 -+ device ref pcie_rp11 on -+ register "PcieRpClkReqSupport[10]" = "1" -+ register "PcieRpClkReqNumber[10]" = "5" -+ register "PcieRpClkSrcNumber[10]" = "5" -+ register "PcieRpAdvancedErrorReporting[10]" = "1" -+ register "PcieRpLtrEnable[10]" = "1" -+ end -+ end -+end -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..47732e37d5b2bad4e674fd10eafa605d26f97840 -GIT binary patch -literal 4106 -zcmeHJUu+a*5TCu>yW9JAmoD2P9tqx`iFWXCLD09RaS&4j$?kY0KGYdgn6;MZ*!anbk!PNr!a%eU -zTXkLEL3ly5L&oUX#CS7?b2%Kad?s-#@;mhg8>>>#S&)d2I -zmP&-g0$k02szSQj(Y*j}YYtQnDH0;2ui{mPhI!flfFgv9nqI4Wr~5_?s`k0kALiCvcP -zCrRUFrpVYPYn?Jn%6MGXUXj_GGJYa!U&-tn8Gn&ANnz_0+@olH3VTw)mlf@-!p8{!e#p0ct5}M(h16D>p?OGjSz6v3juERjS -z#z{?mXvVqrXs_rvUmYR40gNzg(QD6y9E94?4DWO|6eb83LI-smcVC6x1n2reH}rAp -zLM);f=tWDCr``UF5T>!;PYu^H1g>EBP8A}2*fM>s-@nC3pDV|}6+CtfhG(II7`pcw -z`jLfJ!?;*R@Bp=Nw2EPOC7FEs(cugIP_K6tN_$~tvS8nx6iOv|IMrO3&-m*N9ZP#b -znG^~>I|l1cUVSeD9r^k3h0TP}WWD9=MZxY<Z3B2yU!k71#YRpThOJtVheMDA50rV#s@U -z+nKbA{O(olYR}icuzQD*-cjBQ9;%!eMDVP>7mWsF@=%>o)wSgq=n%DHNOYwRr4Ao6 -zbNdgEn*RdDS>Rud+fIY0N8JkP3q6;>8o%R(CE2n3?Xg%qP+U%~6|{XFyxv7Y#;J2Z -XK$lk*wsY^m4}9|iz?mg_AjCfat$CyH - -literal 0 -HcmV?d00001 - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads -new file mode 100644 -index 0000000000..fcfbd75a92 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads -@@ -0,0 +1,19 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ (eDP, -+ DP1, -+ DP2, -+ HDMI1, -+ HDMI2, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c -new file mode 100644 -index 0000000000..a98dd2bc4e ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c -@@ -0,0 +1,199 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include "../../gpio.h" -+ -+static const struct pad_config gpio_table[] = { -+ /* ------- GPIO Community 0 ------- */ -+ -+ /* ------- GPIO Group GPP_A ------- */ -+ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */ -+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */ -+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */ -+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */ -+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */ -+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */ -+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */ -+ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */ -+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */ -+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */ -+ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */ -+ PAD_NC(GPP_A11, NONE), -+ PAD_NC(GPP_A12, NONE), -+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* -SUSWARN */ -+ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* -SUS_STAT */ -+ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), /* -SUSWARN */ -+ PAD_NC(GPP_A16, NONE), -+ PAD_NC(GPP_A17, NONE), -+ PAD_NC(GPP_A18, NONE), -+ PAD_NC(GPP_A19, NONE), -+ PAD_NC(GPP_A20, NONE), -+ PAD_NC(GPP_A21, NONE), -+ PAD_NC(GPP_A22, NONE), -+ PAD_NC(GPP_A23, NONE), -+ -+ /* ------- GPIO Group GPP_B ------- */ -+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), -+ PAD_NC(GPP_B2, NONE), -+ PAD_NC(GPP_B3, NONE), -+ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */ -+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (dGPU) */ -+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (WWAN) */ -+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 (GBE) */ -+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WLAN) */ -+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 (TB3) */ -+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 (SSD) */ -+ PAD_NC(GPP_B11, NONE), -+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */ -+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */ -+ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* PCH_SPKR */ -+ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */ -+ PAD_NC(GPP_B16, NONE), -+ PAD_NC(GPP_B17, NONE), -+ PAD_NC(GPP_B18, NONE), -+ PAD_NC(GPP_B19, NONE), -+ PAD_NC(GPP_B20, NONE), -+ PAD_NC(GPP_B21, NONE), -+ PAD_NC(GPP_B22, NONE), -+ PAD_NC(GPP_B23, NONE), -+ -+ /* ------- GPIO Community 1 ------- */ -+ -+ /* ------- GPIO Group GPP_C ------- */ -+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ -+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ -+ PAD_CFG_GPO(GPP_C2, 1, DEEP), -+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */ -+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ -+ PAD_NC(GPP_C5, NONE), -+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */ -+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */ -+ PAD_NC(GPP_C8, NONE), -+ PAD_NC(GPP_C9, NONE), -+ PAD_NC(GPP_C10, NONE), -+ PAD_NC(GPP_C11, NONE), -+ PAD_NC(GPP_C12, NONE), -+ PAD_NC(GPP_C13, NONE), -+ PAD_NC(GPP_C14, NONE), -+ PAD_NC(GPP_C15, NONE), -+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */ -+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */ -+ PAD_NC(GPP_C18, NONE), -+ PAD_NC(GPP_C19, NONE), -+ PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ -+ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ -+ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ -+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ -+ -+ /* ------- GPIO Group GPP_D ------- */ -+ PAD_NC(GPP_D0, NONE), -+ PAD_NC(GPP_D1, NONE), -+ PAD_NC(GPP_D2, NONE), -+ PAD_NC(GPP_D3, NONE), -+ PAD_NC(GPP_D4, NONE), -+ PAD_NC(GPP_D5, NONE), -+ PAD_NC(GPP_D6, NONE), -+ PAD_NC(GPP_D7, NONE), -+ PAD_NC(GPP_D8, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */ -+ PAD_NC(GPP_D10, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */ -+ PAD_NC(GPP_D13, NONE), -+ PAD_NC(GPP_D14, NONE), -+ PAD_NC(GPP_D15, NONE), -+ PAD_NC(GPP_D16, NONE), -+ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */ -+ PAD_NC(GPP_D18, NONE), -+ PAD_NC(GPP_D19, NONE), -+ PAD_NC(GPP_D20, NONE), -+ PAD_NC(GPP_D21, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */ -+ PAD_NC(GPP_D23, NONE), -+ -+ /* ------- GPIO Group GPP_E ------- */ -+ PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */ -+ PAD_NC(GPP_E1, NONE), -+ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -SATA2_DTCT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */ -+ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */ -+ PAD_NC(GPP_E5, NONE), -+ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */ -+ PAD_NC(GPP_E7, NONE), -+ PAD_NC(GPP_E8, NONE), -+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */ -+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */ -+ PAD_NC(GPP_E11, NONE), -+ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */ -+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */ -+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */ -+ PAD_NC(GPP_E15, NONE), -+ PAD_NC(GPP_E16, NONE), -+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ -+ PAD_NC(GPP_E18, NONE), -+ PAD_CFG_GPO(GPP_E19, 0, DEEP), -+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */ -+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */ -+ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */ -+ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */ -+ -+ /* ------- GPIO Community 2 ------- */ -+ -+ /* -------- GPIO Group GPD -------- */ -+ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */ -+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */ -+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */ -+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */ -+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */ -+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */ -+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */ -+ PAD_NC(GPD7, NONE), -+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */ -+ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */ -+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */ -+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ -+ -+ /* ------- GPIO Community 3 ------- */ -+ -+ /* ------- GPIO Group GPP_F ------- */ -+ PAD_CFG_GPO(GPP_F0, 0, DEEP), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */ -+ PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI), /* DGFX_PWRGD */ -+ PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */ -+ PAD_NC(GPP_F5, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R37 to GND) */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */ -+ PAD_NC(GPP_F21, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -TAMPER_SW_DTCT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */ -+ -+ /* ------- GPIO Group GPP_G ------- */ -+ PAD_NC(GPP_G0, NONE), -+ PAD_NC(GPP_G1, NONE), -+ PAD_NC(GPP_G2, NONE), -+ PAD_NC(GPP_G3, NONE), -+ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ -+ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ -+ PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ -+ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ -+}; -+ -+void variant_config_gpios(void) -+{ -+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c -new file mode 100644 -index 0000000000..b1d96c5a76 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c -@@ -0,0 +1,90 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+ -+const u32 cim_verb_data[] = { -+ 0x10ec0257, // Vendor/Device ID: Realtek ALC257 -+ 0x17aa2258, // Subsystem ID -+ 11, -+ AZALIA_SUBVENDOR(0, 0x17aa2258), -+ -+ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( -+ AZALIA_INTEGRATED, -+ AZALIA_INTERNAL, -+ AZALIA_MIC_IN, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_NO_JACK_PRESENCE_DETECT, -+ 2, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( -+ AZALIA_INTEGRATED, -+ AZALIA_INTERNAL, -+ AZALIA_SPEAKER, -+ AZALIA_OTHER_ANALOG, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_NO_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_MIC_IN, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 3, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_HP_OUT, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 15 -+ )), -+ -+ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI -+ 0x80860101, // Subsystem ID -+ 4, -+ AZALIA_SUBVENDOR(2, 0x80860101), -+ -+ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+}; -+ -+const u32 pc_beep_verbs[] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c -new file mode 100644 -index 0000000000..001e934b3a ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c -@@ -0,0 +1,44 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static const struct pad_config memory_id_gpio_table[] = { -+ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */ -+}; -+ -+void mainboard_memory_init_params(FSPM_UPD *mupd) -+{ -+ int spd_idx; -+ char spd_name[20]; -+ size_t spd_size; -+ -+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; -+ mem_cfg->DqPinsInterleaved = true; /* DDR_DQ in interleave mode */ -+ mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */ -+ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; -+ -+ /* Get SPD for soldered RAM SPD (CH A) */ -+ gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table)); -+ -+ spd_idx = gpio_get(GPP_F16) | gpio_get(GPP_F17) << 1 | gpio_get(GPP_F18) << 2 | -+ gpio_get(GPP_F19) << 3 | gpio_get(GPP_F20) << 4; -+ printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx); -+ snprintf(spd_name, sizeof(spd_name), "spd_%d.bin", spd_idx); -+ mem_cfg->MemorySpdPtr00 = (uintptr_t)cbfs_map(spd_name, &spd_size); -+ -+ /* Get SPD for memory slot (CH B) */ -+ struct spd_block blk = { .addr_map = { [1] = 0x51, } }; -+ get_spd_smbus(&blk); -+ dump_spd_info(&blk); -+ -+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb -new file mode 100644 -index 0000000000..14fcf371c7 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb -@@ -0,0 +1,93 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+chip soc/intel/skylake -+ device domain 0 on -+ device ref south_xhci on -+ register "usb2_ports" = "{ -+ [0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on) -+ [1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A) -+ [2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot) -+ [3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB-C) -+ [4] = USB2_PORT_MID(OC_SKIP), // JCAM (IR camera) -+ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB) -+ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB) -+ [7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam) -+ [8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader) -+ [9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel) -+ }" -+ register "usb3_ports" = "{ -+ [0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on) -+ [1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A) -+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader) -+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSBC (USB-C) -+ }" -+ end -+ -+ # PCIe controller 1 - 1x2+2x1 -+ # PCIE 1-2 - RP1 - dGPU - CLKOUT0 - CLKREQ0 -+ # PCIE 4 - RP4 - WWAN - CLKOUT1 - CLKREQ1 -+ # -+ # PCIe controller 2 - 2x1+1x2 (lane reversal) -+ # PCIE 5 - GBE - GBE - CLKOUT2 - CLKREQ2 (clobbers RP8) -+ # PCIE 6 - RP7 - WLAN - CLKOUT3 - CLKREQ3 -+ # PCIE 7-8 - RP5 - TB3 - CLKOUT4 - CLKREQ4 -+ # -+ # PCIe controller 3 - 1x4 (lane reversal) -+ # PCIE 9-12 - RP9 - SSD - CLKOUT5 - CLKREQ5 -+ -+ # dGPU - x2 -+ device ref pcie_rp1 on -+ register "PcieRpClkReqSupport[0]" = "1" -+ register "PcieRpClkReqNumber[0]" = "0" -+ register "PcieRpClkSrcNumber[0]" = "0" -+ register "PcieRpAdvancedErrorReporting[0]" = "1" -+ register "PcieRpLtrEnable[0]" = "1" -+ device generic 0 alias dgpu on end -+ end -+ -+ # M.2 WWAN - x1 -+ device ref pcie_rp4 on -+ register "PcieRpClkReqSupport[3]" = "1" -+ register "PcieRpClkReqNumber[3]" = "1" -+ register "PcieRpClkSrcNumber[3]" = "1" -+ register "PcieRpAdvancedErrorReporting[3]" = "1" -+ register "PcieRpLtrEnable[3]" = "1" -+ end -+ -+ # Ethernet (clobbers RP8) -+ device ref gbe on -+ register "LanClkReqSupported" = "1" -+ register "LanClkReqNumber" = "2" -+ register "EnableLanLtr" = "1" -+ register "EnableLanK1Off" = "1" -+ end -+ -+ # M.2 WLAN - x1 -+ device ref pcie_rp7 on -+ register "PcieRpClkReqSupport[6]" = "1" -+ register "PcieRpClkReqNumber[6]" = "3" -+ register "PcieRpClkSrcNumber[6]" = "3" -+ register "PcieRpAdvancedErrorReporting[6]" = "1" -+ register "PcieRpLtrEnable[6]" = "1" -+ end -+ -+ # TB3 (Alpine Ridge LP) - x2 -+ device ref pcie_rp5 on -+ register "PcieRpClkReqSupport[4]" = "1" -+ register "PcieRpClkReqNumber[4]" = "4" -+ register "PcieRpClkSrcNumber[4]" = "4" -+ register "PcieRpAdvancedErrorReporting[4]" = "1" -+ register "PcieRpLtrEnable[4]" = "1" -+ register "PcieRpHotPlug[4]" = "1" -+ end -+ -+ # M.2 2280 SSD - x2 -+ device ref pcie_rp9 on -+ register "PcieRpClkReqSupport[8]" = "1" -+ register "PcieRpClkReqNumber[8]" = "5" -+ register "PcieRpClkSrcNumber[8]" = "5" -+ register "PcieRpAdvancedErrorReporting[8]" = "1" -+ register "PcieRpLtrEnable[8]" = "1" -+ end -+ end -+end -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin 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512 -zcmY!uW!enxp}7)YiWinU~FgllWifig`TLxK(6%}hL^bdB7N9Ss$Lz^FmT39fQ* -FG5`?&65ap+ - -literal 0 -HcmV?d00001 - --- -2.39.5 - diff --git a/config/coreboot/default/patches/0042-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/coreboot/default/patches/0042-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch deleted file mode 100644 index 2d6c13b0..00000000 --- a/config/coreboot/default/patches/0042-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 8109392f8998878939c942f2608cf8c7ece5847a Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Wed, 18 Dec 2024 02:06:18 +0000 -Subject: [PATCH 42/43] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN - -This is used by lbmk to know where a tb.bin file goes, -when extracting and padding TBT.bin from Lenovo ThunderBolt -firmware updates on T480/T480s and other machines, grabbing -Lenovo update files. - -Not used in any builds, so it's not relevant for ./mk inject - -However, the ThunderBolt firmware is now auto-downloaded on -T480/T480s. This is not inserted, because it doesn't go in -the main flash, but the resulting ROM image can be flashed -on the TB controller's separate flash chip. - -Locations are as follows: - -vendorfiles/t480s/tb.bin -vendorfiles/t480/tb.bin - -This can be used for other affected ThinkPads when they're -added to Libreboot, but note that Lenovo provides different -TB firmware files for each machine. - -Since I assume it's the same TB controller on all of those -machines, I have to wonder: what difference is there between -the various TBT.bin files provided by Lenovo, and how do they -differ in terms of actual flashed configuration? - -We simply flash the padded TBT.bin when updating the firmware, -flashing externally. That's what this patch is for, so that -lbmk can auto-download them. - -Signed-off-by: Leah Rowe ---- - src/mainboard/lenovo/Kconfig | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig -index 2ffbaab85f..512b326381 100644 ---- a/src/mainboard/lenovo/Kconfig -+++ b/src/mainboard/lenovo/Kconfig -@@ -18,4 +18,30 @@ config MAINBOARD_FAMILY - string - default MAINBOARD_PART_NUMBER - -+config LENOVO_TBFW_BIN -+ string "Lenovo ThunderBolt firmware bin file" -+ default "" -+ help -+ ThunderBolt firmware for certain ThinkPad models e.g. T480. -+ Not used in the actual build. Libreboot's build system uses this -+ along with config/vendor/*/pkg.cfg entries defining a URL to the -+ Lenovo download link and hash. The resulting file when processed by -+ lbmk can be flashed to the ThunderBolt firmware's 25XX NOR device. -+ Earlier versions of this firmware had debug commands enabled that -+ sent logs to said flash IC, and it would quickly fill up, bricking -+ the ThunderBolt controller. With these updates, flashed externally, -+ you can fix the issue if present or otherwise prevent it. The benefit -+ here is that you then don't need to use Windows or a boot disk. You -+ can flash the TB firmware while flashing Libreboot firmware. Easy! -+ Look for these variables in lbmk: -+ TBFW_url TBFW_url_bkup TBFW_hash and look at how it handles that and -+ CONFIG_LENOVO_TBFW_BIN, in lbmk's include/vendor.sh file. -+ The path set by CONFIG_LENOVO_TBFW_BIN is used by lbmk when extracting -+ the firmware, putting it at that desired location. In this way, lbmk -+ can auto-download such firmware. E.g. ./mk -d coreboot t480_fsp_16mb -+ and it appears at vendorfiles/t480/tb.bin fully padded and everything! -+ -+ Just leave this blank if you don't care about this option. It's not -+ useful for every ThinkPad, only certain models. -+ - endif # VENDOR_LENOVO --- -2.39.5 - diff --git a/config/coreboot/default/patches/0043-Conditional-TBFW-setting-for-T480-T480S.patch b/config/coreboot/default/patches/0043-Conditional-TBFW-setting-for-T480-T480S.patch deleted file mode 100644 index bf2d7637..00000000 --- a/config/coreboot/default/patches/0043-Conditional-TBFW-setting-for-T480-T480S.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 951040d7f9193c90e707988a2e7a043a2ba942e7 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Mon, 21 Apr 2025 05:14:45 +0100 -Subject: [PATCH 43/43] Conditional TBFW setting for T480/T480S - -Otherwise, other boards will define it, which -might trigger the vendor download script, and -lead to a non-zero exit. - -Signed-off-by: Leah Rowe ---- - src/mainboard/lenovo/Kconfig | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig -index 512b326381..3d3490b35d 100644 ---- a/src/mainboard/lenovo/Kconfig -+++ b/src/mainboard/lenovo/Kconfig -@@ -18,6 +18,8 @@ config MAINBOARD_FAMILY - string - default MAINBOARD_PART_NUMBER - -+if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S -+ - config LENOVO_TBFW_BIN - string "Lenovo ThunderBolt firmware bin file" - default "" -@@ -44,4 +46,6 @@ config LENOVO_TBFW_BIN - Just leave this blank if you don't care about this option. It's not - useful for every ThinkPad, only certain models. - -+endif # BOARD LENOVO_T480 || BOARD_LENOVO_T480S -+ - endif # VENDOR_LENOVO --- -2.39.5 - diff --git a/config/coreboot/default/target.cfg b/config/coreboot/default/target.cfg index 7c6bf44e..c84cd896 100644 --- a/config/coreboot/default/target.cfg +++ b/config/coreboot/default/target.cfg @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-3.0-or-later tree="default" -rev="8b52167a9f7d31a009b123e152c5c62dcf0a5202" +rev="812d0e2f626dfea7e7deb960a8dc08ff0e026bc1" diff --git a/config/coreboot/hp2170p_16mb/config/libgfxinit_corebootfb b/config/coreboot/hp2170p_16mb/config/libgfxinit_corebootfb index e734dadb..fcd29012 100644 --- a/config/coreboot/hp2170p_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp2170p_16mb/config/libgfxinit_corebootfb @@ -173,7 +173,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp2170p_16mb/config/libgfxinit_txtmode b/config/coreboot/hp2170p_16mb/config/libgfxinit_txtmode index 517ad32d..009b7345 100644 --- a/config/coreboot/hp2170p_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp2170p_16mb/config/libgfxinit_txtmode @@ -171,7 +171,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp2560p_8mb/config/libgfxinit_corebootfb b/config/coreboot/hp2560p_8mb/config/libgfxinit_corebootfb index 7b953cff..8f767a60 100644 --- a/config/coreboot/hp2560p_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp2560p_8mb/config/libgfxinit_corebootfb @@ -171,7 +171,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp2560p_8mb/config/libgfxinit_txtmode b/config/coreboot/hp2560p_8mb/config/libgfxinit_txtmode index d9be7fdf..d2d0e504 100644 --- a/config/coreboot/hp2560p_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp2560p_8mb/config/libgfxinit_txtmode @@ -169,7 +169,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp2570p_16mb/config/libgfxinit_corebootfb b/config/coreboot/hp2570p_16mb/config/libgfxinit_corebootfb index ef2bd843..fe8f0fa2 100644 --- a/config/coreboot/hp2570p_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp2570p_16mb/config/libgfxinit_corebootfb @@ -170,7 +170,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp2570p_16mb/config/libgfxinit_txtmode b/config/coreboot/hp2570p_16mb/config/libgfxinit_txtmode index 0df99d3c..92515c07 100644 --- a/config/coreboot/hp2570p_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp2570p_16mb/config/libgfxinit_txtmode @@ -168,7 +168,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8200sff_4mb/config/libgfxinit_corebootfb b/config/coreboot/hp8200sff_4mb/config/libgfxinit_corebootfb index ef110ae5..90d25c44 100644 --- a/config/coreboot/hp8200sff_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp8200sff_4mb/config/libgfxinit_corebootfb @@ -173,7 +173,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8200sff_4mb/config/libgfxinit_txtmode b/config/coreboot/hp8200sff_4mb/config/libgfxinit_txtmode index 0df68553..88435fa2 100644 --- a/config/coreboot/hp8200sff_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp8200sff_4mb/config/libgfxinit_txtmode @@ -171,7 +171,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8200sff_8mb/config/libgfxinit_corebootfb b/config/coreboot/hp8200sff_8mb/config/libgfxinit_corebootfb index 4a46ba5b..e1ef6986 100644 --- a/config/coreboot/hp8200sff_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp8200sff_8mb/config/libgfxinit_corebootfb @@ -173,7 +173,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8200sff_8mb/config/libgfxinit_txtmode b/config/coreboot/hp8200sff_8mb/config/libgfxinit_txtmode index 6295a22b..0c9caa1c 100644 --- a/config/coreboot/hp8200sff_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp8200sff_8mb/config/libgfxinit_txtmode @@ -171,7 +171,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp820g2_12mb/config/libgfxinit_corebootfb b/config/coreboot/hp820g2_12mb/config/libgfxinit_corebootfb index bef0f52e..15569ec1 100644 --- a/config/coreboot/hp820g2_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp820g2_12mb/config/libgfxinit_corebootfb @@ -169,7 +169,6 @@ CONFIG_PCIEXP_AER=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set CONFIG_BOARD_HP_ELITEBOOK_820_G2=y diff --git a/config/coreboot/hp820g2_12mb/config/libgfxinit_txtmode b/config/coreboot/hp820g2_12mb/config/libgfxinit_txtmode index 9ddee822..69692fcd 100644 --- a/config/coreboot/hp820g2_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp820g2_12mb/config/libgfxinit_txtmode @@ -167,7 +167,6 @@ CONFIG_PCIEXP_AER=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set CONFIG_BOARD_HP_ELITEBOOK_820_G2=y diff --git a/config/coreboot/hp8300cmt_16mb/config/libgfxinit_corebootfb b/config/coreboot/hp8300cmt_16mb/config/libgfxinit_corebootfb index 3f83d6ab..d7a98a79 100644 --- a/config/coreboot/hp8300cmt_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp8300cmt_16mb/config/libgfxinit_corebootfb @@ -172,7 +172,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT=y # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8300cmt_16mb/config/libgfxinit_txtmode b/config/coreboot/hp8300cmt_16mb/config/libgfxinit_txtmode index 814275e7..931f9848 100644 --- a/config/coreboot/hp8300cmt_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp8300cmt_16mb/config/libgfxinit_txtmode @@ -170,7 +170,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT=y # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8300usdt_16mb/config/libgfxinit_corebootfb b/config/coreboot/hp8300usdt_16mb/config/libgfxinit_corebootfb index 64dc2901..970c7ab7 100644 --- a/config/coreboot/hp8300usdt_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp8300usdt_16mb/config/libgfxinit_corebootfb @@ -172,7 +172,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8300usdt_16mb/config/libgfxinit_txtmode b/config/coreboot/hp8300usdt_16mb/config/libgfxinit_txtmode index 9330e338..17bccd0e 100644 --- a/config/coreboot/hp8300usdt_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp8300usdt_16mb/config/libgfxinit_txtmode @@ -170,7 +170,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8460pintel_8mb/config/libgfxinit_corebootfb b/config/coreboot/hp8460pintel_8mb/config/libgfxinit_corebootfb index 31b9d737..6760785c 100644 --- a/config/coreboot/hp8460pintel_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp8460pintel_8mb/config/libgfxinit_corebootfb @@ -173,7 +173,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8460pintel_8mb/config/libgfxinit_txtmode b/config/coreboot/hp8460pintel_8mb/config/libgfxinit_txtmode index e24295f3..0104743b 100644 --- a/config/coreboot/hp8460pintel_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp8460pintel_8mb/config/libgfxinit_txtmode @@ -171,7 +171,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8470pintel_16mb/config/libgfxinit_corebootfb b/config/coreboot/hp8470pintel_16mb/config/libgfxinit_corebootfb index 5a472c2a..a380ee28 100644 --- a/config/coreboot/hp8470pintel_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp8470pintel_16mb/config/libgfxinit_corebootfb @@ -172,7 +172,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8470pintel_16mb/config/libgfxinit_txtmode b/config/coreboot/hp8470pintel_16mb/config/libgfxinit_txtmode index 19127844..257a7e7e 100644 --- a/config/coreboot/hp8470pintel_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp8470pintel_16mb/config/libgfxinit_txtmode @@ -170,7 +170,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8560w_8mb/config/normal b/config/coreboot/hp8560w_8mb/config/normal index 4c1cc1b9..7652a564 100644 --- a/config/coreboot/hp8560w_8mb/config/normal +++ b/config/coreboot/hp8560w_8mb/config/normal @@ -169,7 +169,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp9470m_16mb/config/libgfxinit_corebootfb b/config/coreboot/hp9470m_16mb/config/libgfxinit_corebootfb index e931b384..789633f0 100644 --- a/config/coreboot/hp9470m_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp9470m_16mb/config/libgfxinit_corebootfb @@ -171,7 +171,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp9470m_16mb/config/libgfxinit_txtmode b/config/coreboot/hp9470m_16mb/config/libgfxinit_txtmode index 5b5acc17..90c7d32d 100644 --- a/config/coreboot/hp9470m_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp9470m_16mb/config/libgfxinit_txtmode @@ -169,7 +169,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hppro3500series_8mb/config/libgfxinit_corebootfb b/config/coreboot/hppro3500series_8mb/config/libgfxinit_corebootfb index c6c8596c..e01a0f5d 100644 --- a/config/coreboot/hppro3500series_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hppro3500series_8mb/config/libgfxinit_corebootfb @@ -168,7 +168,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hppro3500series_8mb/config/libgfxinit_txtmode b/config/coreboot/hppro3500series_8mb/config/libgfxinit_txtmode index 6aaf9cfe..a9358a5e 100644 --- a/config/coreboot/hppro3500series_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/hppro3500series_8mb/config/libgfxinit_txtmode @@ -166,7 +166,6 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/r400_16mb/config/libgfxinit_corebootfb b/config/coreboot/r400_16mb/config/libgfxinit_corebootfb index f4dd091b..e4de2ae7 100644 --- a/config/coreboot/r400_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r400_16mb/config/libgfxinit_corebootfb @@ -379,8 +379,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/r400_16mb/config/libgfxinit_txtmode b/config/coreboot/r400_16mb/config/libgfxinit_txtmode index cefb2e7f..76f734e9 100644 --- a/config/coreboot/r400_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/r400_16mb/config/libgfxinit_txtmode @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/r400_4mb/config/libgfxinit_corebootfb b/config/coreboot/r400_4mb/config/libgfxinit_corebootfb index 3406c4f8..77201d6f 100644 --- a/config/coreboot/r400_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r400_4mb/config/libgfxinit_corebootfb @@ -379,8 +379,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/r400_4mb/config/libgfxinit_txtmode b/config/coreboot/r400_4mb/config/libgfxinit_txtmode index b0aecef9..bfe81488 100644 --- a/config/coreboot/r400_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/r400_4mb/config/libgfxinit_txtmode @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/r400_8mb/config/libgfxinit_corebootfb b/config/coreboot/r400_8mb/config/libgfxinit_corebootfb index 73ea948f..07f12819 100644 --- a/config/coreboot/r400_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r400_8mb/config/libgfxinit_corebootfb @@ -379,8 +379,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/r400_8mb/config/libgfxinit_txtmode b/config/coreboot/r400_8mb/config/libgfxinit_txtmode index 856780d3..ca9843c4 100644 --- a/config/coreboot/r400_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/r400_8mb/config/libgfxinit_txtmode @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/r500_4mb/config/libgfxinit_corebootfb b/config/coreboot/r500_4mb/config/libgfxinit_corebootfb index 5969b55b..ccb870a7 100644 --- a/config/coreboot/r500_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r500_4mb/config/libgfxinit_corebootfb @@ -378,7 +378,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/r500_4mb/config/libgfxinit_txtmode b/config/coreboot/r500_4mb/config/libgfxinit_txtmode index 5bae0f85..41cf6001 100644 --- a/config/coreboot/r500_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/r500_4mb/config/libgfxinit_txtmode @@ -376,7 +376,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t400_16mb/config/libgfxinit_corebootfb b/config/coreboot/t400_16mb/config/libgfxinit_corebootfb index b04c8531..5ea07cc3 100644 --- a/config/coreboot/t400_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t400_16mb/config/libgfxinit_corebootfb @@ -379,8 +379,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t400_16mb/config/libgfxinit_txtmode b/config/coreboot/t400_16mb/config/libgfxinit_txtmode index 61d4040b..f37428d4 100644 --- a/config/coreboot/t400_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/t400_16mb/config/libgfxinit_txtmode @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t400_4mb/config/libgfxinit_corebootfb b/config/coreboot/t400_4mb/config/libgfxinit_corebootfb index d6f80065..1f8c824f 100644 --- a/config/coreboot/t400_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t400_4mb/config/libgfxinit_corebootfb @@ -379,8 +379,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t400_4mb/config/libgfxinit_txtmode b/config/coreboot/t400_4mb/config/libgfxinit_txtmode index 2e878426..53641b72 100644 --- a/config/coreboot/t400_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/t400_4mb/config/libgfxinit_txtmode @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t400_8mb/config/libgfxinit_corebootfb b/config/coreboot/t400_8mb/config/libgfxinit_corebootfb index b3c9a4fc..d62c8a54 100644 --- a/config/coreboot/t400_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t400_8mb/config/libgfxinit_corebootfb @@ -379,8 +379,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t400_8mb/config/libgfxinit_txtmode b/config/coreboot/t400_8mb/config/libgfxinit_txtmode index d47db263..c9cd21d1 100644 --- a/config/coreboot/t400_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t400_8mb/config/libgfxinit_txtmode @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t420_8mb/config/libgfxinit_corebootfb b/config/coreboot/t420_8mb/config/libgfxinit_corebootfb index eeed98c6..a780deb7 100644 --- a/config/coreboot/t420_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t420_8mb/config/libgfxinit_corebootfb @@ -395,7 +395,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t420_8mb/config/libgfxinit_txtmode b/config/coreboot/t420_8mb/config/libgfxinit_txtmode index 46d361f3..44c4a8a4 100644 --- a/config/coreboot/t420_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t420_8mb/config/libgfxinit_txtmode @@ -393,7 +393,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t420s_8mb/config/libgfxinit_corebootfb b/config/coreboot/t420s_8mb/config/libgfxinit_corebootfb index ba181603..589c472f 100644 --- a/config/coreboot/t420s_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t420s_8mb/config/libgfxinit_corebootfb @@ -395,7 +395,6 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t420s_8mb/config/libgfxinit_txtmode b/config/coreboot/t420s_8mb/config/libgfxinit_txtmode index b3286dfb..ead84d30 100644 --- a/config/coreboot/t420s_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t420s_8mb/config/libgfxinit_txtmode @@ -393,7 +393,6 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t430_12mb/config/libgfxinit_corebootfb b/config/coreboot/t430_12mb/config/libgfxinit_corebootfb index 18be2432..ca288aa5 100644 --- a/config/coreboot/t430_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t430_12mb/config/libgfxinit_corebootfb @@ -395,8 +395,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t430_12mb/config/libgfxinit_txtmode b/config/coreboot/t430_12mb/config/libgfxinit_txtmode index e5753d98..f180cd85 100644 --- a/config/coreboot/t430_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t430_12mb/config/libgfxinit_txtmode @@ -393,8 +393,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t480_vfsp_16mb/config/libgfxinit_corebootfb b/config/coreboot/t480_vfsp_16mb/config/libgfxinit_corebootfb index af19a3c5..84d1ff80 100644 --- a/config/coreboot/t480_vfsp_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t480_vfsp_16mb/config/libgfxinit_corebootfb @@ -216,13 +216,11 @@ CONFIG_BOARD_LENOVO_T480=y # CONFIG_BOARD_LENOVO_X230S is not set # CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set -CONFIG_PS2K_EISAID="LEN0071" -CONFIG_PS2M_EISAID="LEN0094" -CONFIG_THINKPADEC_HKEY_EISAID="LEN0268" +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" CONFIG_BOARD_LENOVO_SKLKBL_THINKPAD_COMMON=y -CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y -CONFIG_EDK2_FOLLOW_BGRT_SPEC=y CONFIG_LENOVO_TBFW_BIN="../../../vendorfiles/t480/tb.bin" CONFIG_TTYS0_BAUD=115200 # CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set @@ -499,13 +497,11 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y -CONFIG_H8_SUPPORT_BT_ON_WIFI=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y CONFIG_H8_HAS_PRIMARY_FN_KEYS=y CONFIG_H8_HAS_LEDLOGO=y -CONFIG_EC_LENOVO_MEC1653=y -CONFIG_MEC1653_SEND_DEBUG_UNLOCK=y CONFIG_EC_LENOVO_PMH7=y # @@ -649,6 +645,7 @@ CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y # CONFIG_DISPLAY_FSP_TIMESTAMPS is not set # CONFIG_BUILDING_WITH_DEBUG_FSP is not set +CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_VBT_CBFS_COMPRESSION_LZMA=y # CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set diff --git a/config/coreboot/t480_vfsp_16mb/config/libgfxinit_txtmode b/config/coreboot/t480_vfsp_16mb/config/libgfxinit_txtmode index 25bc9357..123091c8 100644 --- a/config/coreboot/t480_vfsp_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/t480_vfsp_16mb/config/libgfxinit_txtmode @@ -214,13 +214,11 @@ CONFIG_BOARD_LENOVO_T480=y # CONFIG_BOARD_LENOVO_X230S is not set # CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set -CONFIG_PS2K_EISAID="LEN0071" -CONFIG_PS2M_EISAID="LEN0094" -CONFIG_THINKPADEC_HKEY_EISAID="LEN0268" +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" CONFIG_BOARD_LENOVO_SKLKBL_THINKPAD_COMMON=y -CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y -CONFIG_EDK2_FOLLOW_BGRT_SPEC=y CONFIG_LENOVO_TBFW_BIN="../../../vendorfiles/t480/tb.bin" CONFIG_TTYS0_BAUD=115200 # CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set @@ -497,13 +495,11 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y -CONFIG_H8_SUPPORT_BT_ON_WIFI=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y CONFIG_H8_HAS_PRIMARY_FN_KEYS=y CONFIG_H8_HAS_LEDLOGO=y -CONFIG_EC_LENOVO_MEC1653=y -CONFIG_MEC1653_SEND_DEBUG_UNLOCK=y CONFIG_EC_LENOVO_PMH7=y # @@ -641,6 +637,7 @@ CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y # CONFIG_DISPLAY_FSP_TIMESTAMPS is not set # CONFIG_BUILDING_WITH_DEBUG_FSP is not set +CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_VBT_CBFS_COMPRESSION_LZMA=y # CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set diff --git a/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_corebootfb b/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_corebootfb index cf41cb6d..60043754 100644 --- a/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_corebootfb @@ -216,13 +216,11 @@ CONFIG_BOARD_LENOVO_T480S=y # CONFIG_BOARD_LENOVO_X230S is not set # CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set -CONFIG_PS2K_EISAID="LEN0071" -CONFIG_PS2M_EISAID="LEN0094" -CONFIG_THINKPADEC_HKEY_EISAID="LEN0268" +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" CONFIG_BOARD_LENOVO_SKLKBL_THINKPAD_COMMON=y -CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y -CONFIG_EDK2_FOLLOW_BGRT_SPEC=y CONFIG_LENOVO_TBFW_BIN="../../../vendorfiles/t480s/tb.bin" CONFIG_TTYS0_BAUD=115200 # CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set @@ -499,12 +497,11 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y -CONFIG_H8_SUPPORT_BT_ON_WIFI=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y CONFIG_H8_HAS_PRIMARY_FN_KEYS=y CONFIG_H8_HAS_LEDLOGO=y -CONFIG_EC_LENOVO_MEC1653=y CONFIG_EC_LENOVO_PMH7=y # @@ -648,6 +645,7 @@ CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y # CONFIG_DISPLAY_FSP_TIMESTAMPS is not set # CONFIG_BUILDING_WITH_DEBUG_FSP is not set +CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_VBT_CBFS_COMPRESSION_LZMA=y # CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set diff --git a/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_txtmode b/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_txtmode index bba6087b..76de6ae2 100644 --- a/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_txtmode @@ -214,13 +214,11 @@ CONFIG_BOARD_LENOVO_T480S=y # CONFIG_BOARD_LENOVO_X230S is not set # CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set -CONFIG_PS2K_EISAID="LEN0071" -CONFIG_PS2M_EISAID="LEN0094" -CONFIG_THINKPADEC_HKEY_EISAID="LEN0268" +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" CONFIG_BOARD_LENOVO_SKLKBL_THINKPAD_COMMON=y -CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y -CONFIG_EDK2_FOLLOW_BGRT_SPEC=y CONFIG_LENOVO_TBFW_BIN="../../../vendorfiles/t480s/tb.bin" CONFIG_TTYS0_BAUD=115200 # CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set @@ -497,12 +495,11 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y -CONFIG_H8_SUPPORT_BT_ON_WIFI=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y CONFIG_H8_HAS_PRIMARY_FN_KEYS=y CONFIG_H8_HAS_LEDLOGO=y -CONFIG_EC_LENOVO_MEC1653=y CONFIG_EC_LENOVO_PMH7=y # @@ -640,6 +637,7 @@ CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y # CONFIG_DISPLAY_FSP_TIMESTAMPS is not set # CONFIG_BUILDING_WITH_DEBUG_FSP is not set +CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_VBT_CBFS_COMPRESSION_LZMA=y # CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set diff --git a/config/coreboot/t500_16mb/config/libgfxinit_corebootfb b/config/coreboot/t500_16mb/config/libgfxinit_corebootfb index 375b0b01..f6c37a55 100644 --- a/config/coreboot/t500_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t500_16mb/config/libgfxinit_corebootfb @@ -379,8 +379,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t500_16mb/config/libgfxinit_txtmode b/config/coreboot/t500_16mb/config/libgfxinit_txtmode index 3d797080..ab08ab0e 100644 --- a/config/coreboot/t500_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/t500_16mb/config/libgfxinit_txtmode @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t500_4mb/config/libgfxinit_corebootfb b/config/coreboot/t500_4mb/config/libgfxinit_corebootfb index 5e5d3ade..2acd637d 100644 --- a/config/coreboot/t500_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t500_4mb/config/libgfxinit_corebootfb @@ -379,8 +379,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t500_4mb/config/libgfxinit_txtmode b/config/coreboot/t500_4mb/config/libgfxinit_txtmode index 9a7e5617..be8a63fc 100644 --- a/config/coreboot/t500_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/t500_4mb/config/libgfxinit_txtmode @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t500_8mb/config/libgfxinit_corebootfb b/config/coreboot/t500_8mb/config/libgfxinit_corebootfb index c8732a48..a3f26365 100644 --- a/config/coreboot/t500_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t500_8mb/config/libgfxinit_corebootfb @@ -379,8 +379,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t500_8mb/config/libgfxinit_txtmode b/config/coreboot/t500_8mb/config/libgfxinit_txtmode index c4b3c004..df65012c 100644 --- a/config/coreboot/t500_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t500_8mb/config/libgfxinit_txtmode @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t520_8mb/config/libgfxinit_corebootfb b/config/coreboot/t520_8mb/config/libgfxinit_corebootfb index 95e50779..5d8c9a7c 100644 --- a/config/coreboot/t520_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t520_8mb/config/libgfxinit_corebootfb @@ -396,8 +396,6 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t520_8mb/config/libgfxinit_txtmode b/config/coreboot/t520_8mb/config/libgfxinit_txtmode index 5dfa0496..897bf5f4 100644 --- a/config/coreboot/t520_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t520_8mb/config/libgfxinit_txtmode @@ -394,8 +394,6 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t530_12mb/config/libgfxinit_corebootfb b/config/coreboot/t530_12mb/config/libgfxinit_corebootfb index 46986899..eb09038d 100644 --- a/config/coreboot/t530_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t530_12mb/config/libgfxinit_corebootfb @@ -396,8 +396,6 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t530_12mb/config/libgfxinit_txtmode b/config/coreboot/t530_12mb/config/libgfxinit_txtmode index 005437ca..3c01cd8f 100644 --- a/config/coreboot/t530_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t530_12mb/config/libgfxinit_txtmode @@ -394,8 +394,6 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb index 83e57e15..4a943565 100644 --- a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb +++ b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb @@ -375,8 +375,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y diff --git a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode index 0fecf0a1..095dd8ef 100644 --- a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode +++ b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode @@ -375,8 +375,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y diff --git a/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb b/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb index 635cc7d1..3eb06179 100644 --- a/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb +++ b/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb @@ -375,8 +375,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y diff --git a/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode b/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode index b11e0db9..dbe9b6c5 100644 --- a/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode +++ b/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode @@ -375,8 +375,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y diff --git a/config/coreboot/w500_16mb/config/libgfxinit_corebootfb b/config/coreboot/w500_16mb/config/libgfxinit_corebootfb index 91cea560..11054290 100644 --- a/config/coreboot/w500_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w500_16mb/config/libgfxinit_corebootfb @@ -379,8 +379,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/w500_16mb/config/libgfxinit_txtmode b/config/coreboot/w500_16mb/config/libgfxinit_txtmode index 59326aca..466a524b 100644 --- a/config/coreboot/w500_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/w500_16mb/config/libgfxinit_txtmode @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/w500_4mb/config/libgfxinit_corebootfb b/config/coreboot/w500_4mb/config/libgfxinit_corebootfb index be7c6931..c687a752 100644 --- a/config/coreboot/w500_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w500_4mb/config/libgfxinit_corebootfb @@ -379,8 +379,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/w500_4mb/config/libgfxinit_txtmode b/config/coreboot/w500_4mb/config/libgfxinit_txtmode index cc520d46..e02e254f 100644 --- a/config/coreboot/w500_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/w500_4mb/config/libgfxinit_txtmode @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/w500_8mb/config/libgfxinit_corebootfb b/config/coreboot/w500_8mb/config/libgfxinit_corebootfb index 8af6b5b5..8dff38ca 100644 --- a/config/coreboot/w500_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w500_8mb/config/libgfxinit_corebootfb @@ -379,8 +379,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/w500_8mb/config/libgfxinit_txtmode b/config/coreboot/w500_8mb/config/libgfxinit_txtmode index 19d473b2..e0d68412 100644 --- a/config/coreboot/w500_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/w500_8mb/config/libgfxinit_txtmode @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/w530_12mb/config/libgfxinit_corebootfb b/config/coreboot/w530_12mb/config/libgfxinit_corebootfb index 50141db1..69e8845c 100644 --- a/config/coreboot/w530_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w530_12mb/config/libgfxinit_corebootfb @@ -396,8 +396,6 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/w530_12mb/config/libgfxinit_txtmode b/config/coreboot/w530_12mb/config/libgfxinit_txtmode index 35e909a6..76de1779 100644 --- a/config/coreboot/w530_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/w530_12mb/config/libgfxinit_txtmode @@ -394,8 +394,6 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x200_16mb/config/libgfxinit_corebootfb b/config/coreboot/x200_16mb/config/libgfxinit_corebootfb index 20f5bbda..a6020ff5 100644 --- a/config/coreboot/x200_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x200_16mb/config/libgfxinit_corebootfb @@ -374,8 +374,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x200_16mb/config/libgfxinit_txtmode b/config/coreboot/x200_16mb/config/libgfxinit_txtmode index d1635db3..aeac6173 100644 --- a/config/coreboot/x200_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x200_16mb/config/libgfxinit_txtmode @@ -372,8 +372,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x200_4mb/config/libgfxinit_corebootfb b/config/coreboot/x200_4mb/config/libgfxinit_corebootfb index 63166703..73f0def5 100644 --- a/config/coreboot/x200_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x200_4mb/config/libgfxinit_corebootfb @@ -374,8 +374,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x200_4mb/config/libgfxinit_txtmode b/config/coreboot/x200_4mb/config/libgfxinit_txtmode index 197e4ea4..e4d8caa8 100644 --- a/config/coreboot/x200_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/x200_4mb/config/libgfxinit_txtmode @@ -372,8 +372,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x200_8mb/config/libgfxinit_corebootfb b/config/coreboot/x200_8mb/config/libgfxinit_corebootfb index ddaefa7a..8ecc6c43 100644 --- a/config/coreboot/x200_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x200_8mb/config/libgfxinit_corebootfb @@ -374,8 +374,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x200_8mb/config/libgfxinit_txtmode b/config/coreboot/x200_8mb/config/libgfxinit_txtmode index ccc5904d..357d6609 100644 --- a/config/coreboot/x200_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/x200_8mb/config/libgfxinit_txtmode @@ -372,8 +372,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x220_8mb/config/libgfxinit_corebootfb b/config/coreboot/x220_8mb/config/libgfxinit_corebootfb index e72892ff..6945cfa1 100644 --- a/config/coreboot/x220_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x220_8mb/config/libgfxinit_corebootfb @@ -396,7 +396,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x220_8mb/config/libgfxinit_txtmode b/config/coreboot/x220_8mb/config/libgfxinit_txtmode index e0072f13..316a4bd9 100644 --- a/config/coreboot/x220_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/x220_8mb/config/libgfxinit_txtmode @@ -394,7 +394,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230_12mb/config/libgfxinit_corebootfb b/config/coreboot/x230_12mb/config/libgfxinit_corebootfb index cba17129..54f491f3 100644 --- a/config/coreboot/x230_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x230_12mb/config/libgfxinit_corebootfb @@ -396,7 +396,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230_12mb/config/libgfxinit_txtmode b/config/coreboot/x230_12mb/config/libgfxinit_txtmode index 73fe0a42..42442f6d 100644 --- a/config/coreboot/x230_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/x230_12mb/config/libgfxinit_txtmode @@ -394,7 +394,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230_16mb/config/libgfxinit_corebootfb b/config/coreboot/x230_16mb/config/libgfxinit_corebootfb index f8348375..b4b8d280 100644 --- a/config/coreboot/x230_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x230_16mb/config/libgfxinit_corebootfb @@ -396,7 +396,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230_16mb/config/libgfxinit_txtmode b/config/coreboot/x230_16mb/config/libgfxinit_txtmode index c4dda6a9..59b9f22c 100644 --- a/config/coreboot/x230_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x230_16mb/config/libgfxinit_txtmode @@ -394,7 +394,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230t_12mb/config/libgfxinit_corebootfb b/config/coreboot/x230t_12mb/config/libgfxinit_corebootfb index c2ef35aa..7dffd236 100644 --- a/config/coreboot/x230t_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x230t_12mb/config/libgfxinit_corebootfb @@ -396,7 +396,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230t_12mb/config/libgfxinit_txtmode b/config/coreboot/x230t_12mb/config/libgfxinit_txtmode index b161f781..e774d160 100644 --- a/config/coreboot/x230t_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/x230t_12mb/config/libgfxinit_txtmode @@ -394,7 +394,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230t_16mb/config/libgfxinit_corebootfb b/config/coreboot/x230t_16mb/config/libgfxinit_corebootfb index 9a1dd06b..d38d447d 100644 --- a/config/coreboot/x230t_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x230t_16mb/config/libgfxinit_corebootfb @@ -396,7 +396,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230t_16mb/config/libgfxinit_txtmode b/config/coreboot/x230t_16mb/config/libgfxinit_txtmode index 5a213187..2f901f5d 100644 --- a/config/coreboot/x230t_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x230t_16mb/config/libgfxinit_txtmode @@ -394,7 +394,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x60/config/libgfxinit_corebootfb b/config/coreboot/x60/config/libgfxinit_corebootfb index e2c15f7e..3bfe9434 100644 --- a/config/coreboot/x60/config/libgfxinit_corebootfb +++ b/config/coreboot/x60/config/libgfxinit_corebootfb @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y diff --git a/config/coreboot/x60/config/libgfxinit_txtmode b/config/coreboot/x60/config/libgfxinit_txtmode index 3163fda6..48c20b09 100644 --- a/config/coreboot/x60/config/libgfxinit_txtmode +++ b/config/coreboot/x60/config/libgfxinit_txtmode @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y diff --git a/config/coreboot/x60_16mb/config/libgfxinit_corebootfb b/config/coreboot/x60_16mb/config/libgfxinit_corebootfb index 92a46efc..ada7ba5d 100644 --- a/config/coreboot/x60_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x60_16mb/config/libgfxinit_corebootfb @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y diff --git a/config/coreboot/x60_16mb/config/libgfxinit_txtmode b/config/coreboot/x60_16mb/config/libgfxinit_txtmode index c21c7ba5..d2132064 100644 --- a/config/coreboot/x60_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x60_16mb/config/libgfxinit_txtmode @@ -377,8 +377,6 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set -CONFIG_H8_HAS_BDC_GPIO_DETECTION=y -CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y -- cgit v1.2.1