lbmk.git/config/vendor/x2e_n150, branch master libreboot build system (LibreBoot MaKe) vendor.sh: handle me_cleaner -p separately 2026-02-22T17:15:24+00:00 Leah Rowe leah@libreboot.org 2026-02-22T17:12:32+00:00 a938309d35b01dfc88e8b126b28df0fec9046058 this is a special mode that skips FPTR checks, which is needed on the topton x2e_n150 we currently set this, when MEclean="n", but we may want to skip cleaning while still checking FPTR on some boards (in a future lbmk revision) Signed-off-by: Leah Rowe <leah@libreboot.org> 
this is a special mode that skips FPTR checks, which is
needed on the topton x2e_n150

we currently set this, when MEclean="n", but we may want to
skip cleaning while still checking FPTR on some boards (in
a future lbmk revision)

Signed-off-by: Leah Rowe <leah@libreboot.org>
fix up old comment in vendor/x2e_n150 2025-09-28T21:09:58+00:00 Leah Rowe leah@libreboot.org 2025-09-28T21:09:58+00:00 aa3ccf04330962f029bd7c0a6104b2285b6719c7 theu current comment is for an old version of the n150 patch, before it was actually merged. the comment has been adjusted, to match the actual implementation that was merged. Signed-off-by: Leah Rowe <leah@libreboot.org> 
theu current comment is for an old version of the n150
patch, before it was actually merged. the comment has
been adjusted, to match the actual implementation that
was merged.

Signed-off-by: Leah Rowe <leah@libreboot.org>
New mainboard: X2E_N150 2025-09-27T23:21:15+00:00 Riku Viitanen riku.viitanen@protonmail.com 2025-09-27T07:53:05+00:00 b4c3bafb0eb7de0cd836d66a1b675430645d8513 Patch in Gerrit: https://review.coreboot.org/c/coreboot/+/89281 Not working: USB3 ports only work at USB2 speeds. IFD: Modified the original by: - Removing Device Exp2 region (empty anyway) - Enlarging the BIOS region to use this freed space - Setting the HAP bit in PCHSTRP55 using a fork of me_cleaner: https://github.com/XutaxKamay/me_cleaner Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Signed-off-by: Leah Rowe <leah@libreboot.org> 
Patch in Gerrit: https://review.coreboot.org/c/coreboot/+/89281
Not working: USB3 ports only work at USB2 speeds.

IFD:
Modified the original by:
- Removing Device Exp2 region (empty anyway)
- Enlarging the BIOS region to use this freed space
- Setting the HAP bit in PCHSTRP55 using a fork of
  me_cleaner: https://github.com/XutaxKamay/me_cleaner

Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Signed-off-by: Leah Rowe <leah@libreboot.org>